From a5c0757e04456aadb5b96170f91f586608f1ae09 Mon Sep 17 00:00:00 2001 From: rtel Date: Tue, 22 Dec 2015 13:56:20 +0000 Subject: [PATCH] Add in the CORTEX_A53_64-bit_UltraScale_MPSoC demo application (a demo has been included in the Xilinx SDK download for some time already). Update a few demo application files to work with 64-bit data types. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2399 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../RTOSDemo_A53/.cproject | 193 + .../RTOSDemo_A53/.project | 249 + .../src/Blinky_Demo/main_blinky.c | 230 + .../RTOSDemo_A53/src/FreeRTOSConfig.h | 220 + .../RTOSDemo_A53/src/FreeRTOS_asm_vectors.S | 307 + .../RTOSDemo_A53/src/FreeRTOS_tick_config.c | 169 + .../src/Full_Demo/IntQueueTimer.c | 273 + .../src/Full_Demo/IntQueueTimer.h | 78 + .../RTOSDemo_A53/src/Full_Demo/main_full.c | 459 + .../RTOSDemo_A53/src/Full_Demo/reg_test.S | 605 + .../RTOSDemo_A53/src/ParTest.c | 105 + .../RTOSDemo_A53/src/lscript.ld | 330 + .../RTOSDemo_A53/src/main.c | 352 + .../RTOSDemo_A53/src/platform.c | 103 + .../RTOSDemo_A53/src/platform.h | 41 + .../RTOSDemo_A53/src/platform_config.h | 6 + .../RTOSDemo_A53_bsp/.cproject | 13 + .../RTOSDemo_A53_bsp/.project | 75 + .../RTOSDemo_A53_bsp/.sdkproject | 4 + .../RTOSDemo_A53_bsp/Makefile | 31 + .../psu_cortexa53_0/include/bspconfig.h | 40 + .../psu_cortexa53_0/include/sleep.h | 50 + .../psu_cortexa53_0/include/vectors.h | 81 + .../psu_cortexa53_0/include/xaxipmon.h | 931 + .../psu_cortexa53_0/include/xaxipmon_hw.h | 566 + .../psu_cortexa53_0/include/xbasic_types.h | 119 + .../psu_cortexa53_0/include/xcanps.h | 567 + .../psu_cortexa53_0/include/xcanps_hw.h | 366 + .../psu_cortexa53_0/include/xcpu_cortexa53.h | 39 + .../psu_cortexa53_0/include/xcsudma.h | 414 + .../psu_cortexa53_0/include/xcsudma_hw.h | 308 + .../psu_cortexa53_0/include/xddr_xmpu0_cfg.h | 1304 + .../psu_cortexa53_0/include/xddr_xmpu1_cfg.h | 1304 + .../psu_cortexa53_0/include/xddr_xmpu2_cfg.h | 1304 + .../psu_cortexa53_0/include/xddr_xmpu3_cfg.h | 1304 + .../psu_cortexa53_0/include/xddr_xmpu4_cfg.h | 1304 + .../psu_cortexa53_0/include/xddr_xmpu5_cfg.h | 1304 + .../psu_cortexa53_0/include/xdebug.h | 32 + .../psu_cortexa53_0/include/xemacps.h | 783 + .../psu_cortexa53_0/include/xemacps_bd.h | 799 + .../psu_cortexa53_0/include/xemacps_bdring.h | 235 + .../psu_cortexa53_0/include/xemacps_hw.h | 647 + .../psu_cortexa53_0/include/xenv.h | 187 + .../psu_cortexa53_0/include/xenv_standalone.h | 368 + .../psu_cortexa53_0/include/xfpd_slcr.h | 382 + .../include/xfpd_slcr_secure.h | 277 + .../psu_cortexa53_0/include/xfpd_xmpu_cfg.h | 1304 + .../psu_cortexa53_0/include/xfpd_xmpu_sink.h | 81 + .../psu_cortexa53_0/include/xgpiops.h | 277 + .../psu_cortexa53_0/include/xgpiops_hw.h | 161 + .../psu_cortexa53_0/include/xiicps.h | 416 + .../psu_cortexa53_0/include/xiicps_hw.h | 380 + .../psu_cortexa53_0/include/xil_assert.h | 189 + .../psu_cortexa53_0/include/xil_cache.h | 75 + .../include/xil_cache_vxworks.h | 93 + .../psu_cortexa53_0/include/xil_exception.h | 168 + .../psu_cortexa53_0/include/xil_hal.h | 61 + .../psu_cortexa53_0/include/xil_io.h | 240 + .../psu_cortexa53_0/include/xil_macroback.h | 1052 + .../psu_cortexa53_0/include/xil_mmu.h | 79 + .../psu_cortexa53_0/include/xil_printf.h | 44 + .../psu_cortexa53_0/include/xil_testcache.h | 63 + .../psu_cortexa53_0/include/xil_testio.h | 91 + .../psu_cortexa53_0/include/xil_testmem.h | 162 + .../psu_cortexa53_0/include/xil_types.h | 184 + .../include/xiou_secure_slcr.h | 174 + .../psu_cortexa53_0/include/xiou_slcr.h | 4029 ++ .../psu_cortexa53_0/include/xipipsu.h | 277 + .../psu_cortexa53_0/include/xipipsu_hw.h | 76 + .../psu_cortexa53_0/include/xlpd_slcr.h | 5667 +++ .../include/xlpd_slcr_secure.h | 141 + .../psu_cortexa53_0/include/xlpd_xppu.h | 858 + .../psu_cortexa53_0/include/xlpd_xppu_sink.h | 81 + .../psu_cortexa53_0/include/xnandpsu.h | 584 + .../psu_cortexa53_0/include/xnandpsu_bbm.h | 211 + .../psu_cortexa53_0/include/xnandpsu_hw.h | 504 + .../psu_cortexa53_0/include/xnandpsu_onfi.h | 340 + .../psu_cortexa53_0/include/xocm_xmpu_cfg.h | 1304 + .../psu_cortexa53_0/include/xparameters.h | 1458 + .../psu_cortexa53_0/include/xparameters_ps.h | 317 + .../psu_cortexa53_0/include/xplatform_info.h | 81 + .../psu_cortexa53_0/include/xpseudo_asm.h | 53 + .../psu_cortexa53_0/include/xpseudo_asm_gcc.h | 169 + .../psu_cortexa53_0/include/xqspipsu.h | 263 + .../psu_cortexa53_0/include/xqspipsu_hw.h | 837 + .../psu_cortexa53_0/include/xreg_cortexa53.h | 182 + .../psu_cortexa53_0/include/xscugic.h | 315 + .../psu_cortexa53_0/include/xscugic_hw.h | 637 + .../psu_cortexa53_0/include/xsdps.h | 208 + .../psu_cortexa53_0/include/xsdps_hw.h | 605 + .../psu_cortexa53_0/include/xspips.h | 691 + .../psu_cortexa53_0/include/xspips_hw.h | 310 + .../psu_cortexa53_0/include/xstatus.h | 430 + .../psu_cortexa53_0/include/xtime_l.h | 88 + .../psu_cortexa53_0/include/xttcps.h | 408 + .../psu_cortexa53_0/include/xttcps_hw.h | 209 + .../psu_cortexa53_0/include/xuartps.h | 509 + .../psu_cortexa53_0/include/xuartps_hw.h | 424 + .../psu_cortexa53_0/include/xusbpsu.h | 569 + .../psu_cortexa53_0/include/xusbpsu_hw.h | 457 + .../psu_cortexa53_0/include/xwdtps.h | 219 + .../psu_cortexa53_0/include/xwdtps_hw.h | 190 + .../psu_cortexa53_0/include/xzdma.h | 669 + .../psu_cortexa53_0/include/xzdma_hw.h | 380 + .../libsrc/axipmon_v6_2/src/Makefile | 27 + .../libsrc/axipmon_v6_2/src/xaxipmon.c | 2115 + .../libsrc/axipmon_v6_2/src/xaxipmon.h | 931 + .../libsrc/axipmon_v6_2/src/xaxipmon_g.c | 127 + .../libsrc/axipmon_v6_2/src/xaxipmon_hw.h | 566 + .../axipmon_v6_2/src/xaxipmon_selftest.c | 148 + .../libsrc/axipmon_v6_2/src/xaxipmon_sinit.c | 100 + .../libsrc/canps_v3_0/src/Makefile | 40 + .../libsrc/canps_v3_0/src/xcanps.c | 1202 + .../libsrc/canps_v3_0/src/xcanps.h | 567 + .../libsrc/canps_v3_0/src/xcanps_g.c | 59 + .../libsrc/canps_v3_0/src/xcanps_hw.c | 90 + .../libsrc/canps_v3_0/src/xcanps_hw.h | 366 + .../libsrc/canps_v3_0/src/xcanps_intr.c | 416 + .../libsrc/canps_v3_0/src/xcanps_selftest.c | 231 + .../libsrc/canps_v3_0/src/xcanps_sinit.c | 100 + .../libsrc/cpu_cortexa53_v1_0/src/Makefile | 22 + .../cpu_cortexa53_v1_0/src/xcpu_cortexa53.h | 39 + .../libsrc/csudma_v1_0/src/Makefile | 40 + .../libsrc/csudma_v1_0/src/xcsudma.c | 764 + .../libsrc/csudma_v1_0/src/xcsudma.h | 414 + .../libsrc/csudma_v1_0/src/xcsudma_g.c | 55 + .../libsrc/csudma_v1_0/src/xcsudma_hw.h | 308 + .../libsrc/csudma_v1_0/src/xcsudma_intr.c | 271 + .../libsrc/csudma_v1_0/src/xcsudma_selftest.c | 122 + .../libsrc/csudma_v1_0/src/xcsudma_sinit.c | 104 + .../libsrc/emacps_v3_0/src/Makefile | 40 + .../libsrc/emacps_v3_0/src/xemacps.c | 476 + .../libsrc/emacps_v3_0/src/xemacps.h | 783 + .../libsrc/emacps_v3_0/src/xemacps_bd.h | 799 + .../libsrc/emacps_v3_0/src/xemacps_bdring.c | 1072 + .../libsrc/emacps_v3_0/src/xemacps_bdring.h | 235 + .../libsrc/emacps_v3_0/src/xemacps_control.c | 1158 + .../libsrc/emacps_v3_0/src/xemacps_g.c | 67 + .../libsrc/emacps_v3_0/src/xemacps_hw.c | 120 + .../libsrc/emacps_v3_0/src/xemacps_hw.h | 647 + .../libsrc/emacps_v3_0/src/xemacps_intr.c | 260 + .../libsrc/emacps_v3_0/src/xemacps_sinit.c | 94 + .../libsrc/gpiops_v3_0/src/Makefile | 40 + .../libsrc/gpiops_v3_0/src/xgpiops.c | 620 + .../libsrc/gpiops_v3_0/src/xgpiops.h | 277 + .../libsrc/gpiops_v3_0/src/xgpiops_g.c | 55 + .../libsrc/gpiops_v3_0/src/xgpiops_hw.c | 175 + .../libsrc/gpiops_v3_0/src/xgpiops_hw.h | 161 + .../libsrc/gpiops_v3_0/src/xgpiops_intr.c | 745 + .../libsrc/gpiops_v3_0/src/xgpiops_selftest.c | 132 + .../libsrc/gpiops_v3_0/src/xgpiops_sinit.c | 98 + .../libsrc/iicps_v3_0/src/Makefile | 40 + .../libsrc/iicps_v3_0/src/xiicps.c | 329 + .../libsrc/iicps_v3_0/src/xiicps.h | 416 + .../libsrc/iicps_v3_0/src/xiicps_g.c | 61 + .../libsrc/iicps_v3_0/src/xiicps_hw.c | 108 + .../libsrc/iicps_v3_0/src/xiicps_hw.h | 380 + .../libsrc/iicps_v3_0/src/xiicps_intr.c | 98 + .../libsrc/iicps_v3_0/src/xiicps_master.c | 985 + .../libsrc/iicps_v3_0/src/xiicps_options.c | 493 + .../libsrc/iicps_v3_0/src/xiicps_selftest.c | 129 + .../libsrc/iicps_v3_0/src/xiicps_sinit.c | 99 + .../libsrc/iicps_v3_0/src/xiicps_slave.c | 587 + .../libsrc/ipipsu_v1_0/src/Makefile | 40 + .../libsrc/ipipsu_v1_0/src/xipipsu.c | 347 + .../libsrc/ipipsu_v1_0/src/xipipsu.h | 277 + .../libsrc/ipipsu_v1_0/src/xipipsu_g.c | 105 + .../libsrc/ipipsu_v1_0/src/xipipsu_hw.h | 76 + .../libsrc/ipipsu_v1_0/src/xipipsu_sinit.c | 87 + .../libsrc/nandpsu_v1_0/src/Makefile | 83 + .../libsrc/nandpsu_v1_0/src/xnandps_g.c | 55 + .../libsrc/nandpsu_v1_0/src/xnandpsu.c | 4195 ++ .../libsrc/nandpsu_v1_0/src/xnandpsu.h | 584 + .../libsrc/nandpsu_v1_0/src/xnandpsu_bbm.c | 1087 + .../libsrc/nandpsu_v1_0/src/xnandpsu_bbm.h | 211 + .../libsrc/nandpsu_v1_0/src/xnandpsu_g.c | 70 + .../libsrc/nandpsu_v1_0/src/xnandpsu_hw.h | 504 + .../libsrc/nandpsu_v1_0/src/xnandpsu_onfi.c | 112 + .../libsrc/nandpsu_v1_0/src/xnandpsu_onfi.h | 340 + .../libsrc/nandpsu_v1_0/src/xnandpsu_sinit.c | 93 + .../libsrc/qspipsu_v1_0/src/Makefile | 40 + .../libsrc/qspipsu_v1_0/src/xqspipsu.c | 1228 + .../libsrc/qspipsu_v1_0/src/xqspipsu.h | 263 + .../libsrc/qspipsu_v1_0/src/xqspipsu_g.c | 57 + .../libsrc/qspipsu_v1_0/src/xqspipsu_hw.h | 837 + .../qspipsu_v1_0/src/xqspipsu_options.c | 416 + .../libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c | 97 + .../libsrc/scugic_v3_0/src/Makefile | 40 + .../libsrc/scugic_v3_0/src/xscugic.c | 712 + .../libsrc/scugic_v3_0/src/xscugic.h | 315 + .../libsrc/scugic_v3_0/src/xscugic_g.c | 56 + .../libsrc/scugic_v3_0/src/xscugic_hw.c | 567 + .../libsrc/scugic_v3_0/src/xscugic_hw.h | 637 + .../libsrc/scugic_v3_0/src/xscugic_intr.c | 170 + .../libsrc/scugic_v3_0/src/xscugic_selftest.c | 112 + .../libsrc/scugic_v3_0/src/xscugic_sinit.c | 100 + .../libsrc/sdps_v2_4/src/Makefile | 40 + .../libsrc/sdps_v2_4/src/xsdps.c | 1118 + .../libsrc/sdps_v2_4/src/xsdps.h | 208 + .../libsrc/sdps_v2_4/src/xsdps_g.c | 65 + .../libsrc/sdps_v2_4/src/xsdps_hw.h | 605 + .../libsrc/sdps_v2_4/src/xsdps_options.c | 792 + .../libsrc/sdps_v2_4/src/xsdps_sinit.c | 95 + .../libsrc/spips_v3_0/src/Makefile | 40 + .../libsrc/spips_v3_0/src/xspips.c | 1126 + .../libsrc/spips_v3_0/src/xspips.h | 691 + .../libsrc/spips_v3_0/src/xspips_g.c | 61 + .../libsrc/spips_v3_0/src/xspips_hw.c | 129 + .../libsrc/spips_v3_0/src/xspips_hw.h | 310 + .../libsrc/spips_v3_0/src/xspips_options.c | 430 + .../libsrc/spips_v3_0/src/xspips_selftest.c | 156 + .../libsrc/spips_v3_0/src/xspips_sinit.c | 97 + .../libsrc/standalone_v5_0/src/Makefile | 75 + .../libsrc/standalone_v5_0/src/_exit.c | 45 + .../libsrc/standalone_v5_0/src/_open.c | 53 + .../libsrc/standalone_v5_0/src/_sbrk.c | 70 + .../libsrc/standalone_v5_0/src/abort.c | 42 + .../libsrc/standalone_v5_0/src/asm_vectors.S | 208 + .../libsrc/standalone_v5_0/src/boot.S | 266 + .../libsrc/standalone_v5_0/src/bspconfig.h | 40 + .../libsrc/standalone_v5_0/src/changelog.txt | 222 + .../libsrc/standalone_v5_0/src/close.c | 47 + .../libsrc/standalone_v5_0/src/config.make | 2 + .../libsrc/standalone_v5_0/src/errno.c | 51 + .../libsrc/standalone_v5_0/src/fcntl.c | 46 + .../libsrc/standalone_v5_0/src/fstat.c | 50 + .../libsrc/standalone_v5_0/src/getpid.c | 51 + .../libsrc/standalone_v5_0/src/inbyte.c | 14 + .../src/initialise_monitor_handles.c | 52 + .../libsrc/standalone_v5_0/src/isatty.c | 56 + .../libsrc/standalone_v5_0/src/kill.c | 60 + .../libsrc/standalone_v5_0/src/lseek.c | 61 + .../libsrc/standalone_v5_0/src/open.c | 52 + .../libsrc/standalone_v5_0/src/outbyte.c | 15 + .../libsrc/standalone_v5_0/src/print.c | 32 + .../libsrc/standalone_v5_0/src/putnum.c | 59 + .../libsrc/standalone_v5_0/src/read.c | 111 + .../libsrc/standalone_v5_0/src/sbrk.c | 65 + .../libsrc/standalone_v5_0/src/sleep.c | 86 + .../libsrc/standalone_v5_0/src/sleep.h | 50 + .../standalone_v5_0/src/translation_table.s | 170 + .../libsrc/standalone_v5_0/src/uart.c | 162 + .../libsrc/standalone_v5_0/src/unlink.c | 50 + .../libsrc/standalone_v5_0/src/usleep.c | 93 + .../libsrc/standalone_v5_0/src/vectors.c | 149 + .../libsrc/standalone_v5_0/src/vectors.h | 81 + .../libsrc/standalone_v5_0/src/write.c | 111 + .../libsrc/standalone_v5_0/src/xbasic_types.h | 119 + .../standalone_v5_0/src/xddr_xmpu0_cfg.h | 1304 + .../standalone_v5_0/src/xddr_xmpu1_cfg.h | 1304 + .../standalone_v5_0/src/xddr_xmpu2_cfg.h | 1304 + .../standalone_v5_0/src/xddr_xmpu3_cfg.h | 1304 + .../standalone_v5_0/src/xddr_xmpu4_cfg.h | 1304 + .../standalone_v5_0/src/xddr_xmpu5_cfg.h | 1304 + .../libsrc/standalone_v5_0/src/xdebug.h | 32 + .../libsrc/standalone_v5_0/src/xenv.h | 187 + .../standalone_v5_0/src/xenv_standalone.h | 368 + .../libsrc/standalone_v5_0/src/xfpd_slcr.h | 382 + .../standalone_v5_0/src/xfpd_slcr_secure.h | 277 + .../standalone_v5_0/src/xfpd_xmpu_cfg.h | 1304 + .../standalone_v5_0/src/xfpd_xmpu_sink.h | 81 + .../libsrc/standalone_v5_0/src/xil-crt0.S | 118 + .../libsrc/standalone_v5_0/src/xil_assert.c | 147 + .../libsrc/standalone_v5_0/src/xil_assert.h | 189 + .../libsrc/standalone_v5_0/src/xil_cache.c | 648 + .../libsrc/standalone_v5_0/src/xil_cache.h | 75 + .../standalone_v5_0/src/xil_cache_vxworks.h | 93 + .../standalone_v5_0/src/xil_exception.c | 214 + .../standalone_v5_0/src/xil_exception.h | 168 + .../libsrc/standalone_v5_0/src/xil_hal.h | 61 + .../libsrc/standalone_v5_0/src/xil_io.c | 381 + .../libsrc/standalone_v5_0/src/xil_io.h | 240 + .../standalone_v5_0/src/xil_macroback.h | 1052 + .../libsrc/standalone_v5_0/src/xil_mmu.c | 110 + .../libsrc/standalone_v5_0/src/xil_mmu.h | 79 + .../libsrc/standalone_v5_0/src/xil_printf.c | 329 + .../libsrc/standalone_v5_0/src/xil_printf.h | 44 + .../standalone_v5_0/src/xil_testcache.c | 366 + .../standalone_v5_0/src/xil_testcache.h | 63 + .../libsrc/standalone_v5_0/src/xil_testio.c | 301 + .../libsrc/standalone_v5_0/src/xil_testio.h | 91 + .../libsrc/standalone_v5_0/src/xil_testmem.c | 882 + .../libsrc/standalone_v5_0/src/xil_testmem.h | 162 + .../libsrc/standalone_v5_0/src/xil_types.h | 184 + .../standalone_v5_0/src/xiou_secure_slcr.h | 174 + .../libsrc/standalone_v5_0/src/xiou_slcr.h | 4029 ++ .../libsrc/standalone_v5_0/src/xlpd_slcr.h | 5667 +++ .../standalone_v5_0/src/xlpd_slcr_secure.h | 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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.tcl create mode 100644 FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.c create mode 100644 FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.h create mode 100644 FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_pmucfg.c create mode 100644 FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/system.hdf diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject new file mode 100644 index 000000000..68d971910 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project new file mode 100644 index 000000000..3edc8c8a8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project @@ -0,0 +1,249 @@ + + + RTOSDemo_A53 + Created by SDK v2015.1. RTOSDemo_A53_bsp - psu_cortexa53_0 + + RTOSDemo_A53_bsp + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1450692515382 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-event_groups.c + + + + 1450692515402 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-list.c + + + + 1450692515422 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-queue.c + + + + 1450692515432 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-tasks.c + + + + 1450692515452 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-timers.c + + + + 1450692515452 + src/FreeRTOS_Source + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-include + + + + 1450692515462 + src/FreeRTOS_Source + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-portable + + + + 1450692538900 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1450692538920 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1450693252106 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1450693252106 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1450693252116 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1450693252116 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1450693252126 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1450693252126 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1450693252136 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1450693252136 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1450693252146 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1450693252146 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1450693252146 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1450692572845 + src/FreeRTOS_Source/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARM_CA53_64_BIT + + + + 1450692711859 + src/FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + + + FREERTOS_ROOT + $%7BPARENT-4-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..13e81b11c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,230 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainSELECTED_APPLICATION setting in main.c is used to select between the + * two. See the notes on using mainSELECTED_APPLICATION in main.c. This file + * implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "partest.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200 ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* The LED toggled by the Rx task. */ +#define mainTASK_LED ( 0 ) + +/*-----------------------------------------------------------*/ + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const uint32_t ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +uint32_t ulReceivedValue; +const uint32_t ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but is + it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + vParTestToggleLED( mainTASK_LED ); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h new file mode 100644 index 000000000..a6b247335 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h @@ -0,0 +1,220 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "xparameters.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* + * The FreeRTOS Cortex-A port implements a full interrupt nesting model. + * + * Interrupts that are assigned a priority at or below + * configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM + * generic interrupt controller [GIC] means a priority that has a numerical + * value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API + * functions and will nest. + * + * Interrupts that are assigned a priority above + * configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical + * value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS + * API functions, will nest, and will not be masked by FreeRTOS critical + * sections (although it is necessary for interrupts to be globally disabled + * extremely briefly as the interrupt mask is updated in the GIC). + * + * FreeRTOS functions that can be called from an interrupt are those that end in + * "FromISR". FreeRTOS maintains a separate interrupt safe API to enable + * interrupt entry to be shorter, faster, simpler and smaller. + * + * For the purpose of setting configMAX_API_CALL_INTERRUPT_PRIORITY 255 + * represents the lowest priority. + */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY 18 + +#define configCPU_CLOCK_HZ 100000000UL +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configPERIPHERAL_CLOCK_HZ ( 33333000UL ) +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configMAX_PRIORITIES ( 8 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 ) +#define configTOTAL_HEAP_SIZE ( 124 * 1024 ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_eTaskGetState 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Run time stats are not generated. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS and +portGET_RUN_TIME_COUNTER_VALUE must be defined if configGENERATE_RUN_TIME_STATS +is set to 1. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#define portGET_RUN_TIME_COUNTER_VALUE() + +/* The size of the global output buffer that is available for use when there +are multiple command interpreters running at once (for example, one on a UART +and one on TCP/IP). This is done to prevent an output buffer being defined by +each implementation - which would waste RAM. In this case, there is only one +command interpreter running. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +void vAssertCalled( const char * pcFile, unsigned long ulLine ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ); + +/* If configTASK_RETURN_ADDRESS is not defined then a task that attempts to +return from its implementing function will end up in a "task exit error" +function - which contains a call to configASSERT(). However this can give GCC +some problems when it tries to unwind the stack, as the exit error function has +nothing to return to. To avoid this define configTASK_RETURN_ADDRESS to 0. */ +#define configTASK_RETURN_ADDRESS NULL + +/* Bump up the priority of recmuCONTROLLING_TASK_PRIORITY to prevent false +positive errors being reported considering the priority of other tasks in the +system. */ +#define recmuCONTROLLING_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/****** Hardware specific settings. *******************************************/ + +/* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. This file contains a function + * that is suitable for use on the Zynq MPU. FreeRTOS_Tick_Handler() must + * be installed as the peripheral's interrupt handler. + */ +void vConfigureTickInterrupt( void ); +#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt() + +void vClearTickInterrupt( void ); +#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt() + +/* The following constant describe the hardware, and are correct for the +Zynq MPU. */ +#define configINTERRUPT_CONTROLLER_BASE_ADDRESS ( XPAR_PSU_ACPU_GIC_DIST_BASEADDR ) +#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ( XPAR_PSU_ACPU_GIC_BASEADDR - XPAR_PSU_ACPU_GIC_DIST_BASEADDR ) +#define configUNIQUE_INTERRUPT_PRIORITIES 32 + +#define fabs( x ) __builtin_fabs( x ) + +#define configUSE_TRACE_FACILITY 0 + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_asm_vectors.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_asm_vectors.S new file mode 100644 index 000000000..da7065510 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_asm_vectors.S @@ -0,0 +1,307 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex A53 processor +* Currently NEON registers are not saved on stack if interrupt is taken. +* It will be implemented. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00	pkp	5/21/14 Initial version
+*
+* +* @note +* +* None. +* +******************************************************************************/ + + + +.org 0 +.text + +.globl _boot +.globl _vector_table +.globl _freertos_vector_table + +.globl FIQInterrupt +.globl IRQInterrupt +.globl SErrorInterrupt +.globl SynchronousInterrupt + + +.org 0 + +.section .vectors, "a" + +_vector_table: + +.set VBAR, _vector_table + +.org VBAR + b _boot + +.org (VBAR + 0x80) + b . + +.org (VBAR + 0x100) + b . + +.org (VBAR + 0x180) + b . + + +.org (VBAR + 0x200) + b . + +.org (VBAR + 0x280) + b . + +.org (VBAR + 0x300) + b . + +.org (VBAR + 0x380) + b . + + + +.org (VBAR + 0x400) + b . + +.org (VBAR + 0x480) + b . + +.org (VBAR + 0x500) + b . + +.org (VBAR + 0x580) + b . + +.org (VBAR + 0x600) + b . + +.org (VBAR + 0x680) + b . + +.org (VBAR + 0x700) + b . + +.org (VBAR + 0x780) + b . + + + +/****************************************************************************** + * Vector table to use when FreeRTOS is running. + *****************************************************************************/ +.set FREERTOS_VBAR, (VBAR+0x1000) + +.org(FREERTOS_VBAR) +_freertos_vector_table: + b FreeRTOS_SWI_Handler + +.org (FREERTOS_VBAR + 0x80) + b FreeRTOS_IRQ_Handler + +.org (FREERTOS_VBAR + 0x100) + b . + +.org (FREERTOS_VBAR + 0x180) + b . + +.org (FREERTOS_VBAR + 0x200) + b FreeRTOS_SWI_Handler + +.org (FREERTOS_VBAR + 0x280) + b FreeRTOS_IRQ_Handler + +.org (FREERTOS_VBAR + 0x300) + b . + +.org (FREERTOS_VBAR + 0x380) + b . + +.org (FREERTOS_VBAR + 0x400) + b . + +.org (FREERTOS_VBAR + 0x480) + b . + +.org (FREERTOS_VBAR + 0x500) + b . + +.org (FREERTOS_VBAR + 0x580) + b . + +.org (FREERTOS_VBAR + 0x600) + b . + +.org (FREERTOS_VBAR + 0x680) + b . + +.org (FREERTOS_VBAR + 0x700) + b . + +.org (FREERTOS_VBAR + 0x780) + b . + +.org (FREERTOS_VBAR + 0x800) + + + + +SynchronousInterruptHandler: + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl SynchronousInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +IRQInterruptHandler: + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl IRQInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +FIQInterruptHandler: + + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl FIQInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +SErrorInterruptHandler: + + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl SErrorInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +.end diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_tick_config.c new file mode 100644 index 000000000..d9db148e6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_tick_config.c @@ -0,0 +1,169 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Xilinx includes. */ +#include "platform.h" +#include "xttcps.h" +#include "xscugic.h" + +/* Timer used to generate the tick interrupt. */ +static XTtcPs xRTOSTickTimerInstance; + +/*-----------------------------------------------------------*/ + +void vConfigureTickInterrupt( void ) +{ +BaseType_t xStatus; +XTtcPs_Config *pxTimerConfiguration; +uint16_t usInterval; +uint8_t ucPrescale; +const uint8_t ucLevelSensitive = 1; +extern XScuGic xInterruptController; + + pxTimerConfiguration = XTtcPs_LookupConfig( XPAR_XTTCPS_3_DEVICE_ID ); + + /* Initialise the device. */ + xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress ); + + if( xStatus != XST_SUCCESS ) + { + /* Not sure how to do this before XTtcPs_CfgInitialize is called as + *xRTOSTickTimerInstance is set within XTtcPs_CfgInitialize(). */ + XTtcPs_Stop( &xRTOSTickTimerInstance ); + xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + } + + /* Set the options. */ + XTtcPs_SetOptions( &xRTOSTickTimerInstance, ( XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE ) ); + + /* Derive values from the tick rate. */ + XTtcPs_CalcIntervalFromFreq( &xRTOSTickTimerInstance, configTICK_RATE_HZ, &( usInterval ), &( ucPrescale ) ); + + /* Set the interval and prescale. */ + XTtcPs_SetInterval( &xRTOSTickTimerInstance, usInterval ); + XTtcPs_SetPrescaler( &xRTOSTickTimerInstance, ucPrescale ); + + /* The priority must be the lowest possible. */ + XScuGic_SetPriorityTriggerType( &xInterruptController, XPAR_XTTCPS_3_INTR, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive ); + + /* Connect to the interrupt controller. */ + xStatus = XScuGic_Connect( &xInterruptController, XPAR_XTTCPS_3_INTR, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, ( void * ) &xRTOSTickTimerInstance ); + configASSERT( xStatus == XST_SUCCESS); + + /* Enable the interrupt in the GIC. */ + XScuGic_Enable( &xInterruptController, XPAR_XTTCPS_3_INTR ); + + /* Enable the interrupts in the timer. */ + XTtcPs_EnableInterrupts( &xRTOSTickTimerInstance, XTTCPS_IXR_INTERVAL_MASK ); + + /* Start the timer. */ + XTtcPs_Start( &xRTOSTickTimerInstance ); +} +/*-----------------------------------------------------------*/ + +void vClearTickInterrupt( void ) +{ +volatile uint32_t ulInterruptStatus; + + /* Read the interrupt status, then write it back to clear the interrupt. */ + ulInterruptStatus = XTtcPs_GetInterruptStatus( &xRTOSTickTimerInstance ); + XTtcPs_ClearInterruptStatus( &xRTOSTickTimerInstance, ulInterruptStatus ); + __asm volatile( "DSB SY" ); + __asm volatile( "ISB SY" ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIRQHandler( uint32_t ulICCIAR ) +{ +extern const XScuGic_Config XScuGic_ConfigTable[]; +static const XScuGic_VectorTableEntry *pxVectorTable = XScuGic_ConfigTable[ XPAR_SCUGIC_SINGLE_DEVICE_ID ].HandlerTable; +uint32_t ulInterruptID; +const XScuGic_VectorTableEntry *pxVectorEntry; + + /* Interrupts cannot be re-enabled until the source of the interrupt is + cleared. The ID of the interrupt is obtained by bitwise ANDing the ICCIAR + value with 0x3FF. */ + ulInterruptID = ulICCIAR & 0x3FFUL; + if( ulInterruptID < XSCUGIC_MAX_NUM_INTR_INPUTS ) + { + /* Call the function installed in the array of installed handler + functions. */ + pxVectorEntry = &( pxVectorTable[ ulInterruptID ] ); + configASSERT( pxVectorEntry ); + pxVectorEntry->Handler( pxVectorEntry->CallBackRef ); + } +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..0af7ac313 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,273 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * NOTE: Currently only timer 1 and timer 2 are used - + * + * This file initialises two timers as follows: + * + * Timer 0 and Timer 1 provide the interrupts that are used with the IntQ + * standard demo tasks, which test interrupt nesting and using queues from + * interrupts. Both these interrupts operate below the maximum syscall + * interrupt priority. + * + * Timer 2 is a much higher frequency timer that tests the nesting of interrupts + * that execute above the maximum syscall interrupt priority. + * + * All the timers can nest with the tick interrupt - creating a maximum + * interrupt nesting depth of 4. + * + * For convenience, the high frequency timer is also used to provide the time + * base for the run time stats. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Xilinx includes. */ +#include "xttcps.h" +#include "xscugic.h" + +/* The frequencies at which the first two timers expire are slightly offset to +ensure they don't remain synchronised. The frequency of the interrupt that +operates above the max syscall interrupt priority is 10 times faster so really +hammers the interrupt entry and exit code. */ +#define tmrTIMERS_USED 3 +#define tmrTIMER_0_FREQUENCY ( 100UL ) +#define tmrTIMER_1_FREQUENCY ( 111UL ) +#define tmrTIMER_2_FREQUENCY ( 20000UL ) + +/*-----------------------------------------------------------*/ + +/* + * The single interrupt service routines that is used to service all three + * timers. + */ +static void prvTimerHandler( void *CallBackRef ); + +/*-----------------------------------------------------------*/ + +/* Hardware constants. */ +static const BaseType_t xDeviceIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_DEVICE_ID, XPAR_XTTCPS_1_DEVICE_ID, XPAR_XTTCPS_2_DEVICE_ID }; +static const BaseType_t xInterruptIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_INTR, XPAR_XTTCPS_1_INTR, XPAR_XTTCPS_2_INTR }; + +/* Timer configuration settings. */ +typedef struct +{ + uint32_t OutputHz; /* Output frequency. */ + uint16_t Interval; /* Interval value. */ + uint8_t Prescaler; /* Prescaler value. */ + uint16_t Options; /* Option settings. */ +} TmrCntrSetup; + +static TmrCntrSetup xTimerSettings[ tmrTIMERS_USED ] = +{ + { tmrTIMER_0_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }, + { tmrTIMER_1_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }, + { tmrTIMER_2_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE } +}; + +/* Lower priority number means higher logical priority, so +configMAX_API_CALL_INTERRUPT_PRIORITY - 1 is above the maximum system call +interrupt priority. */ +static const UBaseType_t uxInterruptPriorities[ tmrTIMERS_USED ] = +{ + configMAX_API_CALL_INTERRUPT_PRIORITY + 1, + configMAX_API_CALL_INTERRUPT_PRIORITY, + configMAX_API_CALL_INTERRUPT_PRIORITY - 1 +}; + +static XTtcPs xTimerInstances[ tmrTIMERS_USED ]; + +/* Used to provide a means of ensuring the intended interrupt nesting depth is +actually being reached. */ +extern uint64_t ullPortInterruptNesting; +static volatile uint32_t ulMaxRecordedNesting = 1; + +/* Used to ensure the high frequency timer is running at the expected +frequency. */ +static volatile uint32_t ulHighFrequencyTimerCounts = 0; + +/*-----------------------------------------------------------*/ + +void vInitialiseTimerForIntQueueTest( void ) +{ +BaseType_t xStatus; +TmrCntrSetup *pxTimerSettings; +extern XScuGic xInterruptController; +BaseType_t xTimer; +XTtcPs *pxTimerInstance; +XTtcPs_Config *pxTimerConfiguration; +const uint8_t ucRisingEdge = 3; + + /*_RB_ Currently only timer 1 and timer 2 are used. */ + for( xTimer = 0; xTimer < ( tmrTIMERS_USED - 1 ); xTimer++ ) + { + /* Look up the timer's configuration. */ + pxTimerInstance = &( xTimerInstances[ xTimer ] ); + pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] ); + configASSERT( pxTimerConfiguration ); + + pxTimerSettings = &( xTimerSettings[ xTimer ] ); + + /* Initialise the device. */ + xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress ); + if( xStatus != XST_SUCCESS ) + { + /* Not sure how to do this before XTtcPs_CfgInitialize is called + as pxTimerInstance is set within XTtcPs_CfgInitialize(). */ + XTtcPs_Stop( pxTimerInstance ); + xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + } + + /* Set the options. */ + XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options ); + + /* The timer frequency is preset in the pxTimerSettings structure. + Derive the values for the other structure members. */ + XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) ); + + /* Set the interval and prescale. */ + XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval ); + XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler ); + + /* The priority must be the lowest possible. */ + XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge ); + + /* Connect to the interrupt controller. */ + xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance ); + configASSERT( xStatus == XST_SUCCESS); + + /* Enable the interrupt in the GIC. */ + XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] ); + + /* Enable the interrupts in the timer. */ + XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK ); + + /* Start the timer. */ + XTtcPs_Start( pxTimerInstance ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTimerHandler( void *pvCallBackRef ) +{ +uint32_t ulInterruptStatus; +XTtcPs *pxTimer = ( XTtcPs * ) pvCallBackRef; +BaseType_t xYieldRequired; + + /* Read the interrupt status, then write it back to clear the interrupt. */ + ulInterruptStatus = XTtcPs_GetInterruptStatus( pxTimer ); + XTtcPs_ClearInterruptStatus( pxTimer, ulInterruptStatus ); + __asm volatile( "DSB SY" ); + __asm volatile( "ISB SY" ); + + + /* Now the interrupt has been cleared, interrupts can be re-enabled. */ + portENABLE_INTERRUPTS(); + + /* Only one interrupt event type is expected. */ + configASSERT( ( XTTCPS_IXR_INTERVAL_MASK & ulInterruptStatus ) != 0 ); + + /* Check the device ID to know which IntQueue demo to call. */ + if( pxTimer->Config.DeviceId == xDeviceIDs[ 0 ] ) + { + xYieldRequired = xFirstTimerHandler(); + } + else if( pxTimer->Config.DeviceId == xDeviceIDs[ 1 ] ) + { + xYieldRequired = xSecondTimerHandler(); + } + else + { + /* Used to check the timer is running at the expected frequency. */ + ulHighFrequencyTimerCounts++; + xYieldRequired = pdFALSE; + } + + /* Latch the highest interrupt nesting count detected. */ + if( ullPortInterruptNesting > ulMaxRecordedNesting ) + { + ulMaxRecordedNesting = ullPortInterruptNesting; + } + + /* If xYieldRequired is not pdFALSE then calling either xFirstTimerHandler() + or xSecondTimerHandler() resulted in a task leaving the blocked state and + the task that left the blocked state had a priority higher than the currently + running task (the task this interrupt interrupted) - so a context switch + should be performed so the interrupt returns directly to the higher priority + task. xYieldRequired is tested inside the following macro. */ + portYIELD_FROM_ISR( xYieldRequired ); +} + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..5c133ff23 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +BaseType_t xTimer0Handler( void ); +BaseType_t xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c new file mode 100644 index 000000000..3ec1e00c1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c @@ -0,0 +1,459 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainSELECTED_APPLICATION setting in main.c is used to select between the two. + * See the notes on using mainSELECTED_APPLICATION in main.c. This file + * implements the comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + * NOTE 3: The full demo includes a test that checks the floating point context + * is maintained correctly across task switches. The standard GCC libraries can + * use floating point registers and made this test fail (unless the tasks that + * use the library are given a floating point context as described on the + * documentation page for this demo). + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every five seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "partest.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 3 ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * ( UBaseType_t ) 3 ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - ( UBaseType_t ) 1 ) + +/* The LED used by the check timer. */ +#define mainCHECK_LED ( 0 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( ( TickType_t ) 0 ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( ( TickType_t ) 5000 ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( ( TickType_t ) ( 200 ) ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + + +/* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file, but the + * entry points are kept in the C file for the convenience of checking the task + * parameter. + */ +static void prvRegTestTaskEntry1( void *pvParameters ); +extern void vRegTest1Implementation( void ); +static void prvRegTestTaskEntry2( void *pvParameters ); +extern void vRegTest2Implementation( void ); + +/* + * Register commands that can be used with FreeRTOS+CLI. The commands are + * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively. + */ +extern void vRegisterSampleCLICommands( void ); + +/* + * The task that manages the FreeRTOS+CLI input and output. + */ +extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile uint64_t ullRegTest1LoopCounter = 0ULL, ullRegTest2LoopCounter = 0ULL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static uint64_t ullLastRegTest1Value = 0, ullLastRegTest2Value = 0; +uint64_t ullErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 0ULL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 1ULL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 2ULL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 4ULL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 5ULL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 6ULL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 8ULL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 10ULL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ullErrorFound |= 1ULL << 12ULL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 13ULL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 14ULL; + } + + /* Check that the register test 1 task is still running. */ + if( ullLastRegTest1Value == ullRegTest1LoopCounter ) + { + ullErrorFound |= 1ULL << 15ULL; + } + ullLastRegTest1Value = ullRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ullLastRegTest2Value == ullRegTest2LoopCounter ) + { + ullErrorFound |= 1ULL << 16ULL; + } + ullLastRegTest2Value = ullRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + if( ullErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + } + + configASSERT( ullErrorFound == pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry1( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + that use the floating point unit must call vPortTaskUsesFPU() before + any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check timer will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry2( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + that use the floating point unit must call vPortTaskUsesFPU() before + any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check timer will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint64_t ullMultiplier = 0x015a4e35ULL, ullIncrement = 1ULL, ullMinDelay = pdMS_TO_TICKS( 95 ); +volatile uint64_t ullNextRand = ( uint64_t ) &pvParameters, ullValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ullNextRand = ( ullMultiplier * ullNextRand ) + ullIncrement; + ullValue = ( ullNextRand >> 16ULL ) & 0xffULL; + + if( ullValue < ullMinDelay ) + { + ullValue = ullMinDelay; + } + + vTaskDelay( ullValue ); + + while( ullValue > 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + ullValue--; + } + } +} + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/reg_test.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/reg_test.S new file mode 100644 index 000000000..8c21ced9a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/reg_test.S @@ -0,0 +1,605 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + .global vRegTest1Implementation + .global vRegTest2Implementation + .extern ullRegTest1LoopCounter + .extern ullRegTest2LoopCounter + + .text + + /* This function is explained in the comments at the top of main-full.c. */ +.type vRegTest1Implementation, %function +vRegTest1Implementation: + + /* Fill each general purpose register with a known value. */ + mov x0, #0xff + mov x1, #0x01 + mov x2, #0x02 + mov x3, #0x03 + mov x4, #0x04 + mov x5, #0x05 + mov x6, #0x06 + mov x7, #0x07 + mov x8, #0x08 + mov x9, #0x09 + mov x10, #0x10 + mov x11, #0x11 + mov x12, #0x12 + mov x13, #0x13 + mov x14, #0x14 + mov x15, #0x15 + mov x16, #0x16 + mov x17, #0x17 + mov x18, #0x18 + mov x19, #0x19 + mov x20, #0x20 + mov x21, #0x21 + mov x22, #0x22 + mov x23, #0x23 + mov x24, #0x24 + mov x25, #0x25 + mov x26, #0x26 + mov x27, #0x27 + mov x28, #0x28 + mov x29, #0x29 + mov x30, #0x30 + + /* Fill each FPU register with a known value. */ + fmov v0.d[1], x0 + fmov d1, x1 + fmov d2, x2 + fmov d3, x3 + fmov d4, x4 + fmov d5, x5 + fmov d6, x6 + fmov d7, x7 + fmov d8, x8 + fmov d9, x9 + fmov d10, x10 + fmov d11, x11 + fmov d12, x12 + fmov d13, x13 + fmov d14, x14 + fmov d15, x15 + fmov d16, x16 + fmov d17, x17 + fmov d18, x18 + fmov d19, x19 + fmov d20, x20 + fmov d21, x21 + fmov d22, x22 + fmov d23, x23 + fmov d24, x24 + fmov d25, x25 + fmov d26, x26 + fmov d27, x27 + fmov d28, x28 + fmov d29, x29 + fmov v30.d[1], x30 + fmov d31, xzr + + /* Loop, checking each itteration that each register still contains the + expected value. */ +reg1_loop: + /* Yield to increase test coverage */ + SMC 0 + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg1_error_loop if any register contains + an unexpected value. */ + cmp x0, #0xFF + bne reg1_error_loop + cmp x1, #0x01 + bne reg1_error_loop + cmp x2, #0x02 + bne reg1_error_loop + cmp x3, #0x03 + bne reg1_error_loop + cmp x4, #0x04 + bne reg1_error_loop + cmp x5, #0x05 + bne reg1_error_loop + cmp x6, #0x06 + bne reg1_error_loop + cmp x7, #0x07 + bne reg1_error_loop + cmp x8, #0x08 + bne reg1_error_loop + cmp x9, #0x09 + bne reg1_error_loop + cmp x10, #0x10 + bne reg1_error_loop + cmp x11, #0x11 + bne reg1_error_loop + cmp x12, #0x12 + bne reg1_error_loop + cmp x13, #0x13 + bne reg1_error_loop + cmp x14, #0x14 + bne reg1_error_loop + cmp x15, #0x15 + bne reg1_error_loop + cmp x16, #0x16 + bne reg1_error_loop + cmp x17, #0x17 + bne reg1_error_loop + cmp x18, #0x18 + bne reg1_error_loop + cmp x19, #0x19 + bne reg1_error_loop + cmp x20, #0x20 + bne reg1_error_loop + cmp x21, #0x21 + bne reg1_error_loop + cmp x22, #0x22 + bne reg1_error_loop + cmp x23, #0x23 + bne reg1_error_loop + cmp x24, #0x24 + bne reg1_error_loop + cmp x25, #0x25 + bne reg1_error_loop + cmp x26, #0x26 + bne reg1_error_loop + cmp x27, #0x27 + bne reg1_error_loop + cmp x28, #0x28 + bne reg1_error_loop + cmp x29, #0x29 + bne reg1_error_loop + cmp x30, #0x30 + bne reg1_error_loop + + /* Check every floating point register to ensure it contains the expected + value. First save the registers clobbered by the test. */ + stp x0, x1, [sp,#-0x10]! + + fmov x0, v0.d[1] + cmp x0, 0xff + bne reg1_error_loop + fmov x0, d1 + cmp x0, 0x01 + bne reg1_error_loop + fmov x0, d2 + cmp x0, 0x02 + bne reg1_error_loop + fmov x0, d3 + cmp x0, 0x03 + bne reg1_error_loop + fmov x0, d4 + cmp x0, 0x04 + bne reg1_error_loop + fmov x0, d5 + cmp x0, 0x05 + bne reg1_error_loop + fmov x0, d6 + cmp x0, 0x06 + bne reg1_error_loop + fmov x0, d7 + cmp x0, 0x07 + bne reg1_error_loop + fmov x0, d8 + cmp x0, 0x08 + bne reg1_error_loop + fmov x0, d9 + cmp x0, 0x09 + bne reg1_error_loop + fmov x0, d10 + cmp x0, 0x10 + bne reg1_error_loop + fmov x0, d11 + cmp x0, 0x11 + bne reg1_error_loop + fmov x0, d12 + cmp x0, 0x12 + bne reg1_error_loop + fmov x0, d13 + cmp x0, 0x13 + bne reg1_error_loop + fmov x0, d14 + cmp x0, 0x14 + bne reg1_error_loop + fmov x0, d15 + cmp x0, 0x15 + bne reg1_error_loop + fmov x0, d16 + cmp x0, 0x16 + bne reg1_error_loop + fmov x0, d17 + cmp x0, 0x17 + bne reg1_error_loop + fmov x0, d18 + cmp x0, 0x18 + bne reg1_error_loop + fmov x0, d19 + cmp x0, 0x19 + bne reg1_error_loop + fmov x0, d20 + cmp x0, 0x20 + bne reg1_error_loop + fmov x0, d21 + cmp x0, 0x21 + bne reg1_error_loop + fmov x0, d22 + cmp x0, 0x22 + bne reg1_error_loop + fmov x0, d23 + cmp x0, 0x23 + bne reg1_error_loop + fmov x0, d24 + cmp x0, 0x24 + bne reg1_error_loop + fmov x0, d25 + cmp x0, 0x25 + bne reg1_error_loop + fmov x0, d26 + cmp x0, 0x26 + bne reg1_error_loop + fmov x0, d27 + cmp x0, 0x27 + bne reg1_error_loop + fmov x0, d28 + cmp x0, 0x28 + bne reg1_error_loop + fmov x0, d29 + cmp x0, 0x29 + bne reg1_error_loop + fmov x0, v30.d[1] + cmp x0, 0x30 + bne reg1_error_loop + fmov x0, d31 + cmp x0, 0x00 + bne reg1_error_loop + + /* Restore the registers clobbered by the test. */ + ldp x0, x1, [sp], #0x10 + + /* Everything passed, increment the loop counter. */ + stp x0, x1, [sp,#-0x10]! + ldr x0, =ullRegTest1LoopCounter + ldr x1, [x0] + adds x1, x1, #1 + str x1, [x0] + ldp x0, x1, [sp], #0x10 + + /* Start again. */ + b reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop + +/*-----------------------------------------------------------*/ + +.type vRegTest2Implementation, %function +vRegTest2Implementation: + + /* Fill each general purpose register with a known value. */ + mov x0, #0xff0 + mov x1, #0x010 + mov x2, #0x020 + mov x3, #0x030 + mov x4, #0x040 + mov x5, #0x050 + mov x6, #0x060 + mov x7, #0x070 + mov x8, #0x080 + mov x9, #0x090 + mov x10, #0x100 + mov x11, #0x110 + mov x12, #0x120 + mov x13, #0x130 + mov x14, #0x140 + mov x15, #0x150 + mov x16, #0x160 + mov x17, #0x170 + mov x18, #0x180 + mov x19, #0x190 + mov x20, #0x200 + mov x21, #0x210 + mov x22, #0x220 + mov x23, #0x230 + mov x24, #0x240 + mov x25, #0x250 + mov x26, #0x260 + mov x27, #0x270 + mov x28, #0x280 + mov x29, #0x290 + mov x30, #0x300 + + /* Fill each FPU register with a known value. */ + fmov d0, x0 + fmov d1, x1 + fmov d2, x2 + fmov d3, x3 + fmov d4, x4 + fmov d5, x5 + fmov d6, x6 + fmov d7, x7 + fmov d8, x8 + fmov d9, x9 + fmov v10.d[1], x10 + fmov d11, x11 + fmov d12, x12 + fmov d13, x13 + fmov d14, x14 + fmov d15, x15 + fmov d16, x16 + fmov d17, x17 + fmov d18, x18 + fmov d19, x19 + fmov d20, x20 + fmov d21, x21 + fmov d22, x22 + fmov d23, x23 + fmov d24, x24 + fmov d25, x25 + fmov d26, x26 + fmov v27.d[1], x27 + fmov d28, x28 + fmov d29, x29 + fmov d30, x30 + fmov d31, x0 + + /* Loop, checking each itteration that each register still contains the + expected value. */ +reg2_loop: + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg2_error_loop if any register contains + an unexpected value. */ + cmp x0, #0xFF0 + bne reg2_error_loop + cmp x1, #0x010 + bne reg2_error_loop + cmp x2, #0x020 + bne reg2_error_loop + cmp x3, #0x030 + bne reg2_error_loop + cmp x4, #0x040 + bne reg2_error_loop + cmp x5, #0x050 + bne reg2_error_loop + cmp x6, #0x060 + bne reg2_error_loop + cmp x7, #0x070 + bne reg2_error_loop + cmp x8, #0x080 + bne reg2_error_loop + cmp x9, #0x090 + bne reg2_error_loop + cmp x10, #0x100 + bne reg2_error_loop + cmp x11, #0x110 + bne reg2_error_loop + cmp x12, #0x120 + bne reg2_error_loop + cmp x13, #0x130 + bne reg2_error_loop + cmp x14, #0x140 + bne reg2_error_loop + cmp x15, #0x150 + bne reg2_error_loop + cmp x16, #0x160 + bne reg2_error_loop + cmp x17, #0x170 + bne reg2_error_loop + cmp x18, #0x180 + bne reg2_error_loop + cmp x19, #0x190 + bne reg2_error_loop + cmp x20, #0x200 + bne reg2_error_loop + cmp x21, #0x210 + bne reg2_error_loop + cmp x22, #0x220 + bne reg2_error_loop + cmp x23, #0x230 + bne reg2_error_loop + cmp x24, #0x240 + bne reg2_error_loop + cmp x25, #0x250 + bne reg2_error_loop + cmp x26, #0x260 + bne reg2_error_loop + cmp x27, #0x270 + bne reg2_error_loop + cmp x28, #0x280 + bne reg2_error_loop + cmp x29, #0x290 + bne reg2_error_loop + cmp x30, #0x300 + bne reg2_error_loop + + /* Check every floating point register to ensure it contains the expected + value. First save the registers clobbered by the test. */ + stp x0, x1, [sp,#-0x10]! + + fmov x0, d0 + cmp x0, 0xff0 + bne reg1_error_loop + fmov x0, d1 + cmp x0, 0x010 + bne reg1_error_loop + fmov x0, d2 + cmp x0, 0x020 + bne reg1_error_loop + fmov x0, d3 + cmp x0, 0x030 + bne reg1_error_loop + fmov x0, d4 + cmp x0, 0x040 + bne reg1_error_loop + fmov x0, d5 + cmp x0, 0x050 + bne reg1_error_loop + fmov x0, d6 + cmp x0, 0x060 + bne reg1_error_loop + fmov x0, d7 + cmp x0, 0x070 + bne reg1_error_loop + fmov x0, d8 + cmp x0, 0x080 + bne reg1_error_loop + fmov x0, d9 + cmp x0, 0x090 + bne reg1_error_loop + fmov x0, v10.d[1] + cmp x0, 0x100 + bne reg1_error_loop + fmov x0, d11 + cmp x0, 0x110 + bne reg1_error_loop + fmov x0, d12 + cmp x0, 0x120 + bne reg1_error_loop + fmov x0, d13 + cmp x0, 0x130 + bne reg1_error_loop + fmov x0, d14 + cmp x0, 0x140 + bne reg1_error_loop + fmov x0, d15 + cmp x0, 0x150 + bne reg1_error_loop + fmov x0, d16 + cmp x0, 0x160 + bne reg1_error_loop + fmov x0, d17 + cmp x0, 0x170 + bne reg1_error_loop + fmov x0, d18 + cmp x0, 0x180 + bne reg1_error_loop + fmov x0, d19 + cmp x0, 0x190 + bne reg1_error_loop + fmov x0, d20 + cmp x0, 0x200 + bne reg1_error_loop + fmov x0, d21 + cmp x0, 0x210 + bne reg1_error_loop + fmov x0, d22 + cmp x0, 0x220 + bne reg1_error_loop + fmov x0, d23 + cmp x0, 0x230 + bne reg1_error_loop + fmov x0, d24 + cmp x0, 0x240 + bne reg1_error_loop + fmov x0, d25 + cmp x0, 0x250 + bne reg1_error_loop + fmov x0, d26 + cmp x0, 0x260 + bne reg1_error_loop + fmov x0, v27.d[1] + cmp x0, 0x270 + bne reg1_error_loop + fmov x0, d28 + cmp x0, 0x280 + bne reg1_error_loop + fmov x0, d29 + cmp x0, 0x290 + bne reg1_error_loop + fmov x0, d30 + cmp x0, 0x300 + bne reg1_error_loop + fmov x0, d31 + cmp x0, 0xff0 + bne reg1_error_loop + + /* Restore the registers clobbered by the test. */ + ldp x0, x1, [sp], #0x10 + + /* Everything passed, increment the loop counter. */ + stp x0, x1, [sp,#-0x10]! + ldr x0, =ullRegTest2LoopCounter + ldr x1, [x0] + adds x1, x1, #1 + str x1, [x0] + ldp x0, x1, [sp], #0x10 + + /* Start again. */ + b reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg2_error_loop + nop + + .end + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/ParTest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/ParTest.c new file mode 100644 index 000000000..f5f72844c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/ParTest.c @@ -0,0 +1,105 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple IO routines to control the LEDs. + * This file is called ParTest.c for historic reasons. Originally it stood for + * PARallel port TEST. + *-----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + + +/* Don't have any real LEDs yet! */ +volatile uint64_t ullLEDToggles = 0; + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue ) +{ +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + ullLEDToggles++; +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld new file mode 100644 index 000000000..52c1e882b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld @@ -0,0 +1,330 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: */ +/* */ +/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : Cortex-A53 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000; + +_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024; +_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048; +_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000 + psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x10000000 + psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000 + psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000 + psu_ocm_xmpu_cfg_S_AXI_BASEADDR : ORIGIN = 0xFFA70000, LENGTH = 0x10000 + psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000 + psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000 + psu_r5_0_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE00000, LENGTH = 0x10000 + psu_r5_0_atcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE10000, LENGTH = 0x10000 + psu_r5_0_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFE20000, LENGTH = 0x10000 + psu_r5_0_btcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE30000, LENGTH = 0x10000 + psu_r5_1_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE90000, LENGTH = 0x10000 + psu_r5_1_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFEB0000, LENGTH = 0x10000 + psu_r5_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x7FF00000 +} + +/* Specify the default entry point to the program */ + +ENTRY(_vector_table) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.init (ALIGN(64)) : { + KEEP (*(.init)) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.fini (ALIGN(64)) : { + KEEP (*(.fini)) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.interp : { + KEEP (*(.interp)) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.note-ABI-tag : { + KEEP (*(.note-ABI-tag)) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.rodata : { + . = ALIGN(64); + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.rodata1 : { + . = ALIGN(64); + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.sdata2 : { + . = ALIGN(64); + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.sbss2 : { + . = ALIGN(64); + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.data : { + . = ALIGN(64); + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + __data_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.data1 : { + . = ALIGN(64); + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.got : { + *(.got) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.got1 : { + *(.got1) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.got2 : { + *(.got2) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.ctors : { + . = ALIGN(64); + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.dtors : { + . = ALIGN(64); + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.eh_frame : { + *(.eh_frame) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.gcc_except_table : { + *(.gcc_except_table) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.mmu_tbl0 (ALIGN(4096)) : { + __mmu_tbl0_start = .; + *(.mmu_tbl0) + __mmu_tbl0_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.mmu_tbl1 (ALIGN(4096)) : { + __mmu_tbl1_start = .; + *(.mmu_tbl1) + __mmu_tbl1_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.mmu_tbl2 (ALIGN(4096)) : { + __mmu_tbl2_start = .; + *(.mmu_tbl2) + __mmu_tbl2_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.preinit_array : { + . = ALIGN(64); + __preinit_array_start = .; + KEEP (*(SORT(.preinit_array.*))) + KEEP (*(.preinit_array)) + __preinit_array_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.init_array : { + . = ALIGN(64); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.fini_array : { + . = ALIGN(64); + __fini_array_start = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.ARM.attributes : { + __ARM.attributes_start = .; + *(.ARM.attributes) + __ARM.attributes_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.sdata : { + . = ALIGN(64); + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.sbss (NOLOAD) : { + . = ALIGN(64); + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + . = ALIGN(64); + __sbss_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.tdata : { + . = ALIGN(64); + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.tbss : { + . = ALIGN(64); + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.bss (NOLOAD) : { + . = ALIGN(64); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(64); + __bss_end__ = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(64); + _heap = .; + HeapBase = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; + HeapLimit = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.stack (NOLOAD) : { + . = ALIGN(64); + _el3_stack_end = .; + . += _STACK_SIZE; + __el3_stack = .; + _el2_stack_end = .; + . += _EL2_STACK_SIZE; + . = ALIGN(64); + __el2_stack = .; + _el1_stack_end = .; + . += _EL1_STACK_SIZE; + . = ALIGN(64); + __el1_stack = .; + _el0_stack_end = .; + . += _EL0_STACK_SIZE; + . = ALIGN(64); + __el0_stack = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +_end = .; +} + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c new file mode 100644 index 000000000..d13b2cfc9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c @@ -0,0 +1,352 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainSELECTED_APPLICATION setting (defined in this file) is used to select + * between the two. The simply blinky demo is implemented and described in + * main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup and FreeRTOS hook functions. + * + * !!! IMPORTANT NOTE !!! + * Some GCC libraries can make use of the floating point registers. To avoid + * this causing corruption it is necessary to avoid their use. For this reason + * main.c contains very basic C implementations of the standard C library + * functions memset(), memcpy() and memcmp(), which are are used by FreeRTOS + * itself. Defining these functions in the project prevents the linker pulling + * them in from the library. Any other standard C library functions that are + * used by the application must likewise be defined in C. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "partest.h" +#include "QueueOverwrite.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Xilinx includes. */ +#include "platform.h" +#include "xttcps.h" +#include "xscugic.h" + +/* mainSELECTED_APPLICATION is used to select between two demo applications, + * as described at the top of this file. + * + * When mainSELECTED_APPLICATION is set to 0 the simple blinky example will + * be run. + * + * When mainSELECTED_APPLICATION is set to 1 the comprehensive test and demo + * application will be run. + */ +#define mainSELECTED_APPLICATION 1 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * See the comments at the top of this file and above the + * mainSELECTED_APPLICATION definition. + */ +#if ( mainSELECTED_APPLICATION == 0 ) + extern void main_blinky( void ); +#elif ( mainSELECTED_APPLICATION == 1 ) + extern void main_full( void ); +#else + #error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. +#endif + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +/* The interrupt controller is initialised in this file, and made available to +other modules. */ +XScuGic xInterruptController; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainSELECTED_APPLICATION setting is described at the top + of this file. */ + #if( mainSELECTED_APPLICATION == 0 ) + { + main_blinky(); + } + #elif( mainSELECTED_APPLICATION == 1 ) + { + main_full(); + } + #endif + + /* Don't expect to reach here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +BaseType_t xStatus; +XScuGic_Config *pxGICConfig; + + /* Ensure no interrupts execute while the scheduler is in an inconsistent + state. Interrupts are automatically enabled when the scheduler is + started. */ + portDISABLE_INTERRUPTS(); + + /* Obtain the configuration of the GIC. */ + pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID ); + + /* Sanity check the FreeRTOSConfig.h settings are correct for the + hardware. */ + configASSERT( pxGICConfig ); + configASSERT( pxGICConfig->CpuBaseAddress == ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) ); + configASSERT( pxGICConfig->DistBaseAddress == configINTERRUPT_CONTROLLER_BASE_ADDRESS ); + + /* Install a default handler for each GIC interrupt. */ + xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( const char * pcFile, unsigned long ulLine ) +{ +volatile unsigned long ul = 0; + + ( void ) pcFile; + ( void ) ulLine; + + taskENTER_CRITICAL(); + { + #if( configUSE_TRACE_FACILITY == 1 ) + { + vTraceStop(); + } + #endif + + /* Set ul to a non-zero value using the debugger to step out of this + function. */ + while( ul == 0 ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if( mainSELECTED_APPLICATION == 1 ) + { + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); + } + #endif +} +/*-----------------------------------------------------------*/ + +void *memcpy( void *pvDest, const void *pvSource, size_t xBytes ) +{ +/* The compiler used during development seems to err unless these volatiles are +included at -O3 optimisation. */ +volatile unsigned char *pcDest = ( volatile unsigned char * ) pvDest, *pcSource = ( volatile unsigned char * ) pvSource; +size_t x; + + /* Extremely crude standard library implementations in lieu of having a C + library. */ + if( pvDest != pvSource ) + { + for( x = 0; x < xBytes; x++ ) + { + pcDest[ x ] = pcSource[ x ]; + } + } + + return pvDest; +} +/*-----------------------------------------------------------*/ + +void *memset( void *pvDest, int iValue, size_t xBytes ) +{ +/* The compiler used during development seems to err unless these volatiles are +included at -O3 optimisation. */ +volatile unsigned char * volatile pcDest = ( volatile unsigned char * volatile ) pvDest; +volatile size_t x; + + /* Extremely crude standard library implementations in lieu of having a C + library. */ + for( x = 0; x < xBytes; x++ ) + { + pcDest[ x ] = ( unsigned char ) iValue; + } + + return pvDest; +} +/*-----------------------------------------------------------*/ + +int memcmp( const void *pvMem1, const void *pvMem2, size_t xBytes ) +{ +const volatile unsigned char *pucMem1 = pvMem1, *pucMem2 = pvMem2; +volatile size_t x; + + /* Extremely crude standard library implementations in lieu of having a C + library. */ + for( x = 0; x < xBytes; x++ ) + { + if( pucMem1[ x ] != pucMem2[ x ] ) + { + break; + } + } + + return xBytes - x; +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.c new file mode 100644 index 000000000..1f49bf62d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.c @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xparameters.h" +#include "xil_cache.h" + +#include "platform_config.h" + +/* + * Uncomment the following line if ps7 init source files are added in the + * source directory for compiling example outside of SDK. + */ +/*#include "ps7_init.h"*/ + +#ifdef STDOUT_IS_16550 + #include "xuartns550_l.h" + + #define UART_BAUD 9600 +#endif + +void +enable_caches() +{ +#ifdef __PPC__ + Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK); + Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK); +#elif __MICROBLAZE__ +#ifdef XPAR_MICROBLAZE_USE_ICACHE + Xil_ICacheEnable(); +#endif +#ifdef XPAR_MICROBLAZE_USE_DCACHE + Xil_DCacheEnable(); +#endif +#endif +} + +void +disable_caches() +{ + Xil_DCacheDisable(); + Xil_ICacheDisable(); +} + +void +init_uart() +{ +#ifdef STDOUT_IS_16550 + XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD); + XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); +#endif +#ifdef STDOUT_IS_PS7_UART + /* Bootrom/BSP configures PS7 UART to 115200 bps */ +#endif +} + +void +init_platform() +{ + /* + * If you want to run this example outside of SDK, + * uncomment the following line and also #include "ps7_init.h" at the top. + * Make sure that the ps7_init.c and ps7_init.h files are included + * along with this example source files for compilation. + */ + /* ps7_init();*/ + enable_caches(); + init_uart(); +} + +void +cleanup_platform() +{ + disable_caches(); +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.h new file mode 100644 index 000000000..24152a29d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef __PLATFORM_H_ +#define __PLATFORM_H_ + +#include "platform_config.h" + +void init_platform(); +void cleanup_platform(); + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform_config.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform_config.h new file mode 100644 index 000000000..fea03914b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform_config.h @@ -0,0 +1,6 @@ +#ifndef __PLATFORM_CONFIG_H_ +#define __PLATFORM_CONFIG_H_ + +#define STDOUT_IS_PSU_UART +#define UART_DEVICE_ID 0 +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject new file mode 100644 index 000000000..52ff9756f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.project b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.project new file mode 100644 index 000000000..c43704810 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.project @@ -0,0 +1,75 @@ + + + RTOSDemo_A53_bsp + Created by SDK v2015.1 + + + + + org.eclipse.cdt.make.core.makeBuilder + + + org.eclipse.cdt.core.errorOutputParser + org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser; + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.build.arguments + + + + org.eclipse.cdt.make.core.build.command + make + + + org.eclipse.cdt.make.core.build.target.auto + all + + + org.eclipse.cdt.make.core.build.target.clean + clean + + + org.eclipse.cdt.make.core.build.target.inc + all + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.enabledIncrementalBuild + true + + + org.eclipse.cdt.make.core.environment + + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + + com.xilinx.sdk.sw.SwProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.make.core.makeNature + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.sdkproject b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.sdkproject new file mode 100644 index 000000000..c622ab61b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.sdkproject @@ -0,0 +1,4 @@ +THIRPARTY=false +HW_PROJECT_REFERENCE=ZynqMP_hw_platform +PROCESSOR=psu_cortexa53_0 +MSS_FILE=system.mss diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile new file mode 100644 index 000000000..6a5a092a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile @@ -0,0 +1,31 @@ +# Makefile generated by Xilinx. + +PROCESSOR = psu_cortexa53_0 +LIBRARIES = ${PROCESSOR}/lib/libxil.a +BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) +SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) + +ifneq (,$(findstring win,$(RDI_PLATFORM))) + SHELL = CMD +endif + +all: libs + @echo 'Finished building libraries' + +include: $(addsuffix /make.include,$(SUBDIRS)) + +libs: $(addsuffix /make.libs,$(SUBDIRS)) + +$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a + cp -f $< $@ + +%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) + @echo "Running Make include in $(subst /make.include,,$@)" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -O0" + +%/make.libs: include + @echo "Running Make libs in $(subst /make.libs,,$@)" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -O0" + +clean: + rm -f ${PROCESSOR}/lib/libxil.a diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/bspconfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/bspconfig.h new file mode 100644 index 000000000..68b572d09 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/bspconfig.h @@ -0,0 +1,40 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Configurations for Standalone BSP +* +*******************************************************************/ + +#define MICROBLAZE_PVR_NONE diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/sleep.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/sleep.h new file mode 100644 index 000000000..8497d2fe6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/sleep.h @@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +s32 usleep(u32 useconds); +s32 sleep(u32 seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/vectors.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/vectors.h new file mode 100644 index 000000000..8c508c3a2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/vectors.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex A53 core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +void FIQInterrupt(void); +void IRQInterrupt(void); +void SynchronousInterrupt(void); +void SErrorInterrupt(void); + + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xaxipmon.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xaxipmon.h new file mode 100644 index 000000000..e21397108 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xaxipmon.h @@ -0,0 +1,931 @@ +/****************************************************************************** +* +* Copyright (C) 2007 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xaxipmon.h +* +* The XAxiPmon driver supports the Xilinx AXI Performance Monitor device. +* +* The AXI Performance Monitor device provides following features: +* +* Configurable number of Metric Counters and Incrementers +* Computes performance metrics for Agents connected to +* monitor slots (Up to 8 slots) +* +* The following Metrics can be computed: +* +* Metrics computed for an AXI4 MM agent: +* Write Request Count: Total number of write requests by/to the agent. +* Read Request Count: Total number of read requests given by/to the +* agent. +* Read Latency: It is defined as the time from the start of read address +* transaction to the beginning of the read data service. +* Write Latency: It is defined as the period needed a master completes +* write data transaction, i.e. from write address +* transaction to write response from slave. +* Write Byte Count: Total number of bytes written by/to the agent. +* This metric is helpful when calculating the +* throughput of the system. +* Read Byte Count: Total number of bytes read from/by the agent. +* Average Write Latency: Average write latency seen by the agent. +* It can be derived from total write latency +* and the write request count. +* Average Read Latency: Average read latency seen by the agent. It can be +* derived from total read latency and the read +* request count. +* Master Write Idle Cycle Count: Number of idle cycles caused by the +* masters during write transactions to +* the slave. +* Slave Write Idle Cycle Count: Number of idle cycles caused by this slave +* during write transactions to the slave. +* Master Read Idle Cycle Count: Number of idle cycles caused by the +* master during read transactions to the +* slave. +* Slave Read Idle Cycle Count: Number of idle cycles caused by this slave +* during read transactions to the slave. +* +* Metrics computed for an AXI4-Stream agent: +* +* Transfer Cycle Count: Total number of writes by/to the agent. +* Data Byte Count: Total number of data bytes written by/to the agent. +* This metric helps in calculating the throughput +* of the system. +* Position Byte Count: Total number of position bytes transferred. +* Null Byte Count: Total number of null bytes transferred. +* Packet Count: Total number of packets transferred. +* +* There are three modes : Advanced, Profile and Trace. +* - Advanced mode has 10 Mertic Counters, Sampled Metric Counters, Incrementors +* and Sampled Incrementors. +* - Profile mode has only 47 Metric Counters and Sampled Metric Counters. +* - Trace mode has no Counters. +* User should refer to the hardware device specification for detailed +* information about the device. +* +* This header file contains the prototypes of driver functions that can +* be used to access the AXI Performance Monitor device. +* +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the AXI Performance Monitor device. +* +* XAxiPmon_CfgInitialize() API is used to initialize the AXI Performance Monitor +* device. The user needs to first call the XAxiPmon_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XAxiPmon_CfgInitialize() API. +* +* +* Interrupts +* +* The AXI Performance Monitor does not support Interrupts +* +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* +* Building the driver +* +* The XAxiPmon driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* Limitations of the driver +* +* +*

+* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    02/27/12 First release
+* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
+* 3.00a bss    09/03/12 To support v2_01_a version of IP:
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			added XAPM_FLAG_EVENT, XAPM_FLAG_EVNTSTAR,
+*			XAPM_FLAG_EVNTSTOP.
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
+*			in xaxipmon.c
+*			Deleted XAPM_AGENT_OFFSET Macro in xaxipmon_hw.h
+* 3.01a bss    10/25/12 To support new version of IP:
+*			Added XAPM_MCXLOGEN_OFFSET macros in xaxipmon_hw.h.
+*			Added XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
+*			Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
+*			(CR #683746) in xaxipmon.c
+*			Added XAxiPmon_EnableEventLog,
+*			XAxiPmon_DisableMetricsCounter,
+*			XAxiPmon_EnableMetricsCounter APIs in xaxipmon.c to
+*			replace macros in this file.
+*			Added XAPM_FLAG_XXX macros.
+*			Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
+*			APIs (CR #683799).
+*			Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
+*			APIs (CR #683801).
+*			Added XAxiPmon_GetMetricName API (CR #683803).
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent
+*			declarations (CR #677337)
+* 4.00a bss    01/17/13 To support new version of IP:
+*			Added XAPM_METRIC_SET_12 to XAPM_METRIC_SET_15 macros.
+*			Added XAxiPmon_SetLogEnableRanges,
+*	  		XAxiPmon_GetLogEnableRanges,
+*			XAxiPmon_EnableMetricCounterTrigger,
+*			XAxiPmon_DisableMetricCounterTrigger,
+*			XAxiPmon_EnableEventLogTrigger,
+*			XAxiPmon_DisableEventLogTrigger,
+*			XAxiPmon_SetWriteLatencyId,
+*			XAxiPmon_SetReadLatencyId,
+*			XAxiPmon_GetWriteLatencyId,
+*			XAxiPmon_GetReadLatencyId APIs and removed
+*			XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
+*			Added XAPM_LATENCYID_OFFSET,
+*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
+*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK in
+*			xaxipmon_hw.h
+* 5.00a bss   08/26/13  To support new version of IP:
+*			XAxiPmon_SampleMetrics Macro.
+*			Modified XAxiPmon_CfgInitialize, Assert functions
+*			Added XAxiPmon_GetMetricCounter,
+*			XAxiPmon_SetSampleInterval, XAxiPmon_GetSampleInterval,
+*			XAxiPmon_SetWrLatencyStart, XAxiPmon_SetWrLatencyEnd,
+*			XAxiPmon_SetRdLatencyStart, XAxiPmon_SetRdLatencyEnd,
+*			XAxiPmon_GetWrLatencyStart, XAxiPmon_GetWrLatencyEnd,
+*			XAxiPmon_GetRdLatencyStart, XAxiPmon_GetRdLatencyEnd,
+*			XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
+*			XAxiPmon_GetWriteIdMask and XAxiPmon_GetReadIdMask APIs
+*			Renamed :
+*			XAxiPmon_SetWriteLatencyId to
+*			XAxiPmon_SetWriteId, XAxiPmon_SetReadLatencyId to
+*			XAxiPmon_SetReadId, XAxiPmon_GetWriteLatencyId to
+*			XAxiPmon_GetWriteId and XAxiPmon_SetReadLatencyId to
+*			XAxiPmon_GetReadId. in xaxipmon.c
+*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
+*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET,
+*			XAPM_IDMASK_OFFSET, XAPM_CR_IDFILTER_ENABLE_MASK,
+*			XAPM_CR_WRLATENCY_START_MASK,
+*			XAPM_CR_WRLATENCY_END_MASK,
+*			XAPM_CR_RDLATENCY_START_MASK,
+*			XAPM_CR_RDLATENCY_END_MASK and
+*			XAPM_MAX_COUNTERS_PROFILE.
+*			Renamed:
+*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
+*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
+*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
+*			in xaxipmon_hw.h.
+*			Modified driver tcl to generate new parameters
+*			ScaleFactor, ModeProfile, ModeTrace and ModeAdvanced
+*			in Config structure.
+* 6.0   adk  19/12/13 Updated as per the New Tcl API's
+* 6.1   adk  16/04/14 Updated the driver tcl for the newly added parameters in
+* 		      The Axi pmon IP.
+* 6.2   bss  04/21/14   Updated XAxiPmon_CfgInitialize in xaxipmon.c to Reset
+*			counters and FIFOs based on Modes(CR#782671). And if
+*			both profile and trace modes are present set mode as
+*			Advanced.
+* 6.2	bss  03/02/15	To support Zynq MP APM:
+*						Added Is32BitFiltering in XAxiPmon_Config structure.
+*						Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
+*						XAxiPmon_GetWriteId, XAxiPmon_GetReadId
+*						XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask
+*						XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
+*						functions in xaxipmon.c.
+*						Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET in
+*						xaxipmon_hw.h
+*
+*
+* +*****************************************************************************/ +#ifndef XAXIPMON_H /* Prevent circular inclusions */ +#define XAXIPMON_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xaxipmon_hw.h" + +/************************** Constant Definitions ****************************/ + + +/** + * @name Macro for Maximum number of Counters + * + * @{ + */ +#define XAPM_MAX_COUNTERS 10 /**< Maximum number of Counters */ +#define XAPM_MAX_COUNTERS_PROFILE 48 /**< Maximum number of Counters */ + +/*@}*/ + + +/** + * @name Indices for Metric Counters and Sampled Metric Coounters used with + * XAxiPmon_GetMetricCounter and XAxiPmon_GetSampledMetricCounter APIs + * @{ + */ + +#define XAPM_METRIC_COUNTER_0 0 /**< Metric Counter 0 Register Index */ +#define XAPM_METRIC_COUNTER_1 1 /**< Metric Counter 1 Register Index */ +#define XAPM_METRIC_COUNTER_2 2 /**< Metric Counter 2 Register Index */ +#define XAPM_METRIC_COUNTER_3 3 /**< Metric Counter 3 Register Index */ +#define XAPM_METRIC_COUNTER_4 4 /**< Metric Counter 4 Register Index */ +#define XAPM_METRIC_COUNTER_5 5 /**< Metric Counter 5 Register Index */ +#define XAPM_METRIC_COUNTER_6 6 /**< Metric Counter 6 Register Index */ +#define XAPM_METRIC_COUNTER_7 7 /**< Metric Counter 7 Register Index */ +#define XAPM_METRIC_COUNTER_8 8 /**< Metric Counter 8 Register Index */ +#define XAPM_METRIC_COUNTER_9 9 /**< Metric Counter 9 Register Index */ + +/*@}*/ + +/** + * @name Indices for Incrementers and Sampled Incrementers used with + * XAxiPmon_GetIncrementer and XAxiPmon_GetSampledIncrementer APIs + * @{ + */ + +#define XAPM_INCREMENTER_0 0 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_1 1 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_2 2 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_3 3 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_4 4 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_5 5 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_6 6 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_7 7 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_8 8 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_9 9 /**< Metric Counter 0 Register Index */ + +/*@}*/ + +/** + * @name Macros for Metric Selector Settings + * @{ + */ + +#define XAPM_METRIC_SET_0 0 /**< Write Transaction Count */ +#define XAPM_METRIC_SET_1 1 /**< Read Transaction Count */ +#define XAPM_METRIC_SET_2 2 /**< Write Byte Count */ +#define XAPM_METRIC_SET_3 3 /**< Read Byte Count */ +#define XAPM_METRIC_SET_4 4 /**< Write Beat Count */ +#define XAPM_METRIC_SET_5 5 /**< Total Read Latency */ +#define XAPM_METRIC_SET_6 6 /**< Total Write Latency */ +#define XAPM_METRIC_SET_7 7 /**< Slv_Wr_Idle_Cnt */ +#define XAPM_METRIC_SET_8 8 /**< Mst_Rd_Idle_Cnt */ +#define XAPM_METRIC_SET_9 9 /**< Num_BValids */ +#define XAPM_METRIC_SET_10 10 /**< Num_WLasts */ +#define XAPM_METRIC_SET_11 11 /**< Num_RLasts */ +#define XAPM_METRIC_SET_12 12 /**< Minimum Write Latency */ +#define XAPM_METRIC_SET_13 13 /**< Maximum Write Latency */ +#define XAPM_METRIC_SET_14 14 /**< Minimum Read Latency */ +#define XAPM_METRIC_SET_15 15 /**< Maximum Read Latency */ +#define XAPM_METRIC_SET_16 16 /**< Transfer Cycle Count */ +#define XAPM_METRIC_SET_17 17 /**< Packet Count */ +#define XAPM_METRIC_SET_18 18 /**< Data Byte Count */ +#define XAPM_METRIC_SET_19 19 /**< Position Byte Count */ +#define XAPM_METRIC_SET_20 20 /**< Null Byte Count */ +#define XAPM_METRIC_SET_21 21 /**< Slv_Idle_Cnt */ +#define XAPM_METRIC_SET_22 22 /**< Mst_Idle_Cnt */ +#define XAPM_METRIC_SET_30 30 /**< External event count */ + + +/*@}*/ + + +/** + * @name Macros for Maximum number of Agents + * @{ + */ + +#define XAPM_MAX_AGENTS 8 /**< Maximum number of Agents */ + +/*@}*/ + +/** + * @name Macros for Flags in Flag Enable Control Register + * @{ + */ + +#define XAPM_FLAG_WRADDR 0x00000001 /**< Write Address Flag */ +#define XAPM_FLAG_FIRSTWR 0x00000002 /**< First Write Flag */ +#define XAPM_FLAG_LASTWR 0x00000004 /**< Last Write Flag */ +#define XAPM_FLAG_RESPONSE 0x00000008 /**< Response Flag */ +#define XAPM_FLAG_RDADDR 0x00000010 /**< Read Address Flag */ +#define XAPM_FLAG_FIRSTRD 0x00000020 /**< First Read Flag */ +#define XAPM_FLAG_LASTRD 0x00000040 /**< Last Read Flag */ +#define XAPM_FLAG_SWDATA 0x00010000 /**< Software-written Data Flag */ +#define XAPM_FLAG_EVENT 0x00020000 /**< Last Read Flag */ +#define XAPM_FLAG_EVNTSTOP 0x00040000 /**< Last Read Flag */ +#define XAPM_FLAG_EVNTSTART 0x00080000 /**< Last Read Flag */ +#define XAPM_FLAG_GCCOVF 0x00100000 /**< Global Clock Counter Overflow + * Flag */ +#define XAPM_FLAG_SCLAPSE 0x00200000 /**< Sample Counter Lapse Flag */ +#define XAPM_FLAG_MC0 0x00400000 /**< Metric Counter 0 Flag */ +#define XAPM_FLAG_MC1 0x00800000 /**< Metric Counter 1 Flag */ +#define XAPM_FLAG_MC2 0x01000000 /**< Metric Counter 2 Flag */ +#define XAPM_FLAG_MC3 0x02000000 /**< Metric Counter 3 Flag */ +#define XAPM_FLAG_MC4 0x04000000 /**< Metric Counter 4 Flag */ +#define XAPM_FLAG_MC5 0x08000000 /**< Metric Counter 5 Flag */ +#define XAPM_FLAG_MC6 0x10000000 /**< Metric Counter 6 Flag */ +#define XAPM_FLAG_MC7 0x20000000 /**< Metric Counter 7 Flag */ +#define XAPM_FLAG_MC8 0x40000000 /**< Metric Counter 8 Flag */ +#define XAPM_FLAG_MC9 0x80000000 /**< Metric Counter 9 Flag */ + +/*@}*/ + +/** + * @name Macros for Read/Write Latency Start and End points + * @{ + */ +#define XAPM_LATENCY_ADDR_ISSUE 0 /**< Address Issue as start + point for Latency calculation*/ +#define XAPM_LATENCY_ADDR_ACCEPT 1 /**< Address Acceptance as start + point for Latency calculation*/ +#define XAPM_LATENCY_LASTRD 0 /**< Last Read as end point for + Latency calculation */ +#define XAPM_LATENCY_LASTWR 0 /**< Last Write as end point for + Latency calculation */ +#define XAPM_LATENCY_FIRSTRD 1 /**< First Read as end point for + Latency calculation */ +#define XAPM_LATENCY_FIRSTWR 1 /**< First Write as end point for + Latency calculation */ + +/*@}*/ + +/** + * @name Macros for Modes of APM + * @{ + */ + +#define XAPM_MODE_TRACE 2 /**< APM in Trace mode */ + +#define XAPM_MODE_PROFILE 1 /**< APM in Profile mode */ + +#define XAPM_MODE_ADVANCED 0 /**< APM in Advanced mode */ + +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the AXI Performance + * Monitor device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Device base address */ + int GlobalClkCounterWidth; /**< Global Clock Counter Width */ + int MetricSampleCounterWidth ; /**< Metric Sample Counters Width */ + u8 IsEventCount; /**< Event Count Enabled 1 - enabled + 0 - not enabled */ + u8 NumberofSlots; /**< Number of Monitor Slots */ + u8 NumberofCounters; /**< Number of Counters */ + u8 HaveSampledCounters; /**< Have Sampled Counters 1 - present + 0 - Not present */ + u8 IsEventLog; /**< Event Logging Enabled 1 - enabled + 0 - Not enabled */ + u32 FifoDepth; /**< Event Log FIFO Depth */ + u32 FifoWidth; /**< Event Log FIFO Width */ + u32 TidWidth; /**< Streaming Interface TID Width */ + u8 ScaleFactor; /**< Event Count Scaling factor */ + u8 ModeAdvanced; /**< Advanced Mode */ + u8 ModeProfile; /**< Profile Mode */ + u8 ModeTrace; /**< Trace Mode */ + u8 Is32BitFiltering; /**< 32 bit filtering enabled */ +} XAxiPmon_Config; + + +/** + * The driver's instance data. The user is required to allocate a variable + * of this type for every AXI Performance Monitor device in system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XAxiPmon_Config Config; /**< XAxiPmon_Config of current device */ + u32 IsReady; /**< Device is initialized and ready */ + u8 Mode; /**< APM Mode */ +} XAxiPmon; + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/****************************************************************************/ +/** +* +* This routine enables the Global Interrupt. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrGlobalEnable(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_IntrGlobalEnable(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \ + XAPM_GIE_OFFSET, 1) + + +/****************************************************************************/ +/** +* +* This routine disables the Global Interrupt. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrGlobalDisable(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_IntrGlobalDisable(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \ + XAPM_GIE_OFFSET, 0) + + +/****************************************************************************/ +/** +* +* This routine enables interrupt(s). Use the XAPM_IXR_* constants defined in +* xaxipmon_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Mask is the mask to enable. Bit positions of 1 will be enabled. +* Bit positions of 0 will keep the previous setting. This mask is +* formed by OR'ing XAPM_IXR__* bits defined in xaxipmon_hw.h. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XAxiPmon_IntrEnable(InstancePtr, Mask) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IE_OFFSET) | Mask); + + +/****************************************************************************/ +/** +* +* This routine disable interrupt(s). Use the XAPM_IXR_* constants defined in +* xaxipmon_hw.h to create the bit-mask to disable interrupts. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Mask is the mask to disable. Bit positions of 1 will be +* disabled. Bit positions of 0 will keep the previous setting. +* This mask is formed by OR'ing XAPM_IXR_* bits defined in +* xaxipmon_hw.h. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XAxiPmon_IntrDisable(InstancePtr, Mask) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IE_OFFSET) | Mask); + +/****************************************************************************/ +/** +* +* This routine clears the specified interrupt(s). +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* This mask is formed by OR'ing XAPM_IXR_* bits defined in +* xaxipmon_hw.h. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XAxiPmon_IntrClear(InstancePtr, Mask) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IS_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IS_OFFSET) | Mask); + +/****************************************************************************/ +/** +* +* This routine returns the Interrupt Status Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Interrupt Status Register contents +* +* @note C-Style signature: +* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_IntrGetStatus(InstancePtr) \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IS_OFFSET); + +/****************************************************************************/ +/** +* +* This function enables the Global Clock Counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableGlobalClkCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK); + +/****************************************************************************/ +/** +* +* This function disbles the Global Clock Counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableGlobalClkCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK)); + +/****************************************************************************/ +/** +* +* This function enables the specified flag in Flag Control Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableFlag(InstancePtr, Flag) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_FEC_OFFSET) | Flag); + +/****************************************************************************/ +/** +* +* This function disables the specified flag in Flag Control Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableFlag(InstancePtr, Flag) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_FEC_OFFSET) & ~(Flag)); + +/****************************************************************************/ +/** +* +* This function loads the sample interval register value into the sample +* interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_LoadSampleIntervalCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \ + XAPM_SICR_LOAD_MASK); + + + +/****************************************************************************/ +/** +* +* This enables the down count of the sample interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableSampleIntervalCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\ + XAPM_SICR_ENABLE_MASK); + + +/****************************************************************************/ +/** +* +* This disables the down count of the sample interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableSampleIntervalCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK)); + +/****************************************************************************/ +/** +* +* This enables Reset of Metric Counters when Sample Interval Counter lapses. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableMetricCounterReset(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\ + XAPM_SICR_MCNTR_RST_MASK); + +/****************************************************************************/ +/** +* +* This disables the down count of the sample interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableMetricCounterReset(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK)); + +/****************************************************************************/ +/** +* +* This function enables the ID Filter Masking. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableIDFilter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK); + +/****************************************************************************/ +/** +* +* This function disbles the ID Filter masking. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableIDFilter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK)); + +/****************************************************************************/ +/** +* +* This function samples Metric Counters to Sampled Metric Counters by +* reading Sample Register and also returns interval. i.e. the number of +* clocks in between previous read to the current read of sample register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Interval. i.e. the number of clocks in between previous +* read to the current read of sample register. +* +* @note C-Style signature: +* u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_SampleMetrics(InstancePtr) \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, XAPM_SR_OFFSET); + + +/************************** Function Prototypes *****************************/ + +/** + * Functions in xaxipmon_sinit.c + */ +XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId); + +/** + * Functions in xaxipmon.c + */ +int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, + XAxiPmon_Config *ConfigPtr, u32 EffectiveAddr); + +int XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr); + +void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr); + +int XAxiPmon_ResetFifo(XAxiPmon *InstancePtr); + +void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 RangeUpper, u16 RangeLower); + +void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 *RangeUpper, u16 *RangeLower); + +void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval); + +void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval); + +int XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics, + u8 CounterNum); + +int XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics, + u8 *Slot); +void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue, + u32 *CntLowValue); + +u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum); + +u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum); + +u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum); + +u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum); + +void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData); + +u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr); + +int XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables); + +int XAxiPmon_StopEventLog(XAxiPmon *InstancePtr); + +int XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval); + +int XAxiPmon_StopCounters(XAxiPmon *InstancePtr); + +void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr); + +void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr); + +void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 RangeUpper, u16 RangeLower); + +void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 *RangeUpper, u16 *RangeLower); + +void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr); + +void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr); + +void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr); + +void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr); + +void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr); + +const char * XAxiPmon_GetMetricName(u8 Metrics); + +void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId); + +void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId); + +u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr); + +u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr); + +void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param); + +void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param); + +void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param); + +void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param); + +u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr); + +u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr); + +u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr); + +u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr); + +void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask); + +void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask); + +u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr); + +u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr); + + +/** + * Functions in xaxipmon_selftest.c + */ +int XAxiPmon_SelfTest(XAxiPmon *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xaxipmon_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xaxipmon_hw.h new file mode 100644 index 000000000..7fc4ae088 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xaxipmon_hw.h @@ -0,0 +1,566 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xaxipmon_hw.h +* +* This header file contains identifiers and basic driver functions (or +* macros) that can be used to access the AXI Performance Monitor. +* +* Refer to the device specification for more information about this driver. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    02/27/12 First release
+* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
+* 3.00a bss    09/03/12 Deleted XAPM_AGENT_OFFSET Macro to support
+*			v2_01a version of IP.
+* 3.01a bss    10/25/12 To support new version of IP:
+*			Added XAPM_MCXLOGEN_OFFSET and
+*			XAPM_CR_EXTERNAL_TRIGGER_MASK macros.
+* 4.00a bss    01/17/13 To support new version of IP:
+*			Added XAPM_LATENCYID_OFFSET,
+*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
+*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK
+* 5.00a bss   08/26/13  To support new version of IP:
+*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
+*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET.
+*			Added macro XAPM_IDMASK_OFFSET, XAPM_SR_OFFSET.
+*			Added XAPM_CR_IDFILTER_ENABLE_MASK,
+*			XAPM_CR_WRLATENCY_START_MASK,
+*			XAPM_CR_WRLATENCY_END_MASK,
+*			XAPM_CR_RDLATENCY_START_MASK,
+*			XAPM_CR_RDLATENCY_END_MASK, XAPM_MASKID_RID_MASK
+*			and XAPM_MASKID_WID_MASK macros.
+*			Renamed:
+*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
+*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
+*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
+*
+* 6.2  bss  03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
+*					 Zynq MP APM.
+*
+* +*****************************************************************************/ +#ifndef XAXIPMON_HW_H /* Prevent circular inclusions */ +#define XAXIPMON_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ + + +/**@name Register offsets of AXIMONITOR in the Device Config + * + * The following constants provide access to each of the registers of the + * AXI PERFORMANCE MONITOR device. + * @{ + */ + +#define XAPM_GCC_HIGH_OFFSET 0x0000 /**< Global Clock Counter + 32 to 63 bits */ +#define XAPM_GCC_LOW_OFFSET 0x0004 /**< Global Clock Counter Lower + 0-31 bits */ +#define XAPM_SI_HIGH_OFFSET 0x0020 /**< Sample Interval MSB */ +#define XAPM_SI_LOW_OFFSET 0x0024 /**< Sample Interval LSB */ +#define XAPM_SICR_OFFSET 0x0028 /**< Sample Interval Control + Register */ +#define XAPM_SR_OFFSET 0x002C /**< Sample Register */ +#define XAPM_GIE_OFFSET 0x0030 /**< Global Interrupt Enable + Register */ +#define XAPM_IE_OFFSET 0x0034 /**< Interrupt Enable Register */ +#define XAPM_IS_OFFSET 0x0038 /**< Interrupt Status Register */ + +#define XAPM_MSR0_OFFSET 0x0044 /**< Metric Selector 0 Register */ +#define XAPM_MSR1_OFFSET 0x0048 /**< Metric Selector 1 Register */ +#define XAPM_MSR2_OFFSET 0x004C /**< Metric Selector 2 Register */ + +#define XAPM_MC0_OFFSET 0x0100 /**< Metric Counter 0 Register */ +#define XAPM_INC0_OFFSET 0x0104 /**< Incrementer 0 Register */ +#define XAPM_RANGE0_OFFSET 0x0108 /**< Range 0 Register */ +#define XAPM_MC0LOGEN_OFFSET 0x010C /**< Metric Counter 0 + Log Enable Register */ +#define XAPM_MC1_OFFSET 0x0110 /**< Metric Counter 1 Register */ +#define XAPM_INC1_OFFSET 0x0114 /**< Incrementer 1 Register */ +#define XAPM_RANGE1_OFFSET 0x0118 /**< Range 1 Register */ +#define XAPM_MC1LOGEN_OFFSET 0x011C /**< Metric Counter 1 + Log Enable Register */ +#define XAPM_MC2_OFFSET 0x0120 /**< Metric Counter 2 Register */ +#define XAPM_INC2_OFFSET 0x0124 /**< Incrementer 2 Register */ +#define XAPM_RANGE2_OFFSET 0x0128 /**< Range 2 Register */ +#define XAPM_MC2LOGEN_OFFSET 0x012C /**< Metric Counter 2 + Log Enable Register */ +#define XAPM_MC3_OFFSET 0x0130 /**< Metric Counter 3 Register */ +#define XAPM_INC3_OFFSET 0x0134 /**< Incrementer 3 Register */ +#define XAPM_RANGE3_OFFSET 0x0138 /**< Range 3 Register */ +#define XAPM_MC3LOGEN_OFFSET 0x013C /**< Metric Counter 3 + Log Enable Register */ +#define XAPM_MC4_OFFSET 0x0140 /**< Metric Counter 4 Register */ +#define XAPM_INC4_OFFSET 0x0144 /**< Incrementer 4 Register */ +#define XAPM_RANGE4_OFFSET 0x0148 /**< Range 4 Register */ +#define XAPM_MC4LOGEN_OFFSET 0x014C /**< Metric Counter 4 + Log Enable Register */ +#define XAPM_MC5_OFFSET 0x0150 /**< Metric Counter 5 + Register */ +#define XAPM_INC5_OFFSET 0x0154 /**< Incrementer 5 Register */ +#define XAPM_RANGE5_OFFSET 0x0158 /**< Range 5 Register */ +#define XAPM_MC5LOGEN_OFFSET 0x015C /**< Metric Counter 5 + Log Enable Register */ +#define XAPM_MC6_OFFSET 0x0160 /**< Metric Counter 6 + Register */ +#define XAPM_INC6_OFFSET 0x0164 /**< Incrementer 6 Register */ +#define XAPM_RANGE6_OFFSET 0x0168 /**< Range 6 Register */ +#define XAPM_MC6LOGEN_OFFSET 0x016C /**< Metric Counter 6 + Log Enable Register */ +#define XAPM_MC7_OFFSET 0x0170 /**< Metric Counter 7 + Register */ +#define XAPM_INC7_OFFSET 0x0174 /**< Incrementer 7 Register */ +#define XAPM_RANGE7_OFFSET 0x0178 /**< Range 7 Register */ +#define XAPM_MC7LOGEN_OFFSET 0x017C /**< Metric Counter 7 + Log Enable Register */ +#define XAPM_MC8_OFFSET 0x0180 /**< Metric Counter 8 + Register */ +#define XAPM_INC8_OFFSET 0x0184 /**< Incrementer 8 Register */ +#define XAPM_RANGE8_OFFSET 0x0188 /**< Range 8 Register */ +#define XAPM_MC8LOGEN_OFFSET 0x018C /**< Metric Counter 8 + Log Enable Register */ +#define XAPM_MC9_OFFSET 0x0190 /**< Metric Counter 9 + Register */ +#define XAPM_INC9_OFFSET 0x0194 /**< Incrementer 9 Register */ +#define XAPM_RANGE9_OFFSET 0x0198 /**< Range 9 Register */ +#define XAPM_MC9LOGEN_OFFSET 0x019C /**< Metric Counter 9 + Log Enable Register */ +#define XAPM_SMC0_OFFSET 0x0200 /**< Sampled Metric Counter + 0 Register */ +#define XAPM_SINC0_OFFSET 0x0204 /**< Sampled Incrementer + 0 Register */ +#define XAPM_SMC1_OFFSET 0x0210 /**< Sampled Metric Counter + 1 Register */ +#define XAPM_SINC1_OFFSET 0x0214 /**< Sampled Incrementer + 1 Register */ +#define XAPM_SMC2_OFFSET 0x0220 /**< Sampled Metric Counter + 2 Register */ +#define XAPM_SINC2_OFFSET 0x0224 /**< Sampled Incrementer + 2 Register */ +#define XAPM_SMC3_OFFSET 0x0230 /**< Sampled Metric Counter + 3 Register */ +#define XAPM_SINC3_OFFSET 0x0234 /**< Sampled Incrementer + 3 Register */ +#define XAPM_SMC4_OFFSET 0x0240 /**< Sampled Metric Counter + 4 Register */ +#define XAPM_SINC4_OFFSET 0x0244 /**< Sampled Incrementer + 4 Register */ +#define XAPM_SMC5_OFFSET 0x0250 /**< Sampled Metric Counter + 5 Register */ +#define XAPM_SINC5_OFFSET 0x0254 /**< Sampled Incrementer + 5 Register */ +#define XAPM_SMC6_OFFSET 0x0260 /**< Sampled Metric Counter + 6 Register */ +#define XAPM_SINC6_OFFSET 0x0264 /**< Sampled Incrementer + 6 Register */ +#define XAPM_SMC7_OFFSET 0x0270 /**< Sampled Metric Counter + 7 Register */ +#define XAPM_SINC7_OFFSET 0x0274 /**< Sampled Incrementer + 7 Register */ +#define XAPM_SMC8_OFFSET 0x0280 /**< Sampled Metric Counter + 8 Register */ +#define XAPM_SINC8_OFFSET 0x0284 /**< Sampled Incrementer + 8 Register */ +#define XAPM_SMC9_OFFSET 0x0290 /**< Sampled Metric Counter + 9 Register */ +#define XAPM_SINC9_OFFSET 0x0294 /**< Sampled Incrementer + 9 Register */ + +#define XAPM_MC10_OFFSET 0x01A0 /**< Metric Counter 10 + Register */ +#define XAPM_MC11_OFFSET 0x01B0 /**< Metric Counter 11 + Register */ +#define XAPM_MC12_OFFSET 0x0500 /**< Metric Counter 12 + Register */ +#define XAPM_MC13_OFFSET 0x0510 /**< Metric Counter 13 + Register */ +#define XAPM_MC14_OFFSET 0x0520 /**< Metric Counter 14 + Register */ +#define XAPM_MC15_OFFSET 0x0530 /**< Metric Counter 15 + Register */ +#define XAPM_MC16_OFFSET 0x0540 /**< Metric Counter 16 + Register */ +#define XAPM_MC17_OFFSET 0x0550 /**< Metric Counter 17 + Register */ +#define XAPM_MC18_OFFSET 0x0560 /**< Metric Counter 18 + Register */ +#define XAPM_MC19_OFFSET 0x0570 /**< Metric Counter 19 + Register */ +#define XAPM_MC20_OFFSET 0x0580 /**< Metric Counter 20 + Register */ +#define XAPM_MC21_OFFSET 0x0590 /**< Metric Counter 21 + Register */ +#define XAPM_MC22_OFFSET 0x05A0 /**< Metric Counter 22 + Register */ +#define XAPM_MC23_OFFSET 0x05B0 /**< Metric Counter 23 + Register */ +#define XAPM_MC24_OFFSET 0x0700 /**< Metric Counter 24 + Register */ +#define XAPM_MC25_OFFSET 0x0710 /**< Metric Counter 25 + Register */ +#define XAPM_MC26_OFFSET 0x0720 /**< Metric Counter 26 + Register */ +#define XAPM_MC27_OFFSET 0x0730 /**< Metric Counter 27 + Register */ +#define XAPM_MC28_OFFSET 0x0740 /**< Metric Counter 28 + Register */ +#define XAPM_MC29_OFFSET 0x0750 /**< Metric Counter 29 + Register */ +#define XAPM_MC30_OFFSET 0x0760 /**< Metric Counter 30 + Register */ +#define XAPM_MC31_OFFSET 0x0770 /**< Metric Counter 31 + Register */ +#define XAPM_MC32_OFFSET 0x0780 /**< Metric Counter 32 + Register */ +#define XAPM_MC33_OFFSET 0x0790 /**< Metric Counter 33 + Register */ +#define XAPM_MC34_OFFSET 0x07A0 /**< Metric Counter 34 + Register */ +#define XAPM_MC35_OFFSET 0x07B0 /**< Metric Counter 35 + Register */ +#define XAPM_MC36_OFFSET 0x0900 /**< Metric Counter 36 + Register */ +#define XAPM_MC37_OFFSET 0x0910 /**< Metric Counter 37 + Register */ +#define XAPM_MC38_OFFSET 0x0920 /**< Metric Counter 38 + Register */ +#define XAPM_MC39_OFFSET 0x0930 /**< Metric Counter 39 + Register */ +#define XAPM_MC40_OFFSET 0x0940 /**< Metric Counter 40 + Register */ +#define XAPM_MC41_OFFSET 0x0950 /**< Metric Counter 41 + Register */ +#define XAPM_MC42_OFFSET 0x0960 /**< Metric Counter 42 + Register */ +#define XAPM_MC43_OFFSET 0x0970 /**< Metric Counter 43 + Register */ +#define XAPM_MC44_OFFSET 0x0980 /**< Metric Counter 44 + Register */ +#define XAPM_MC45_OFFSET 0x0990 /**< Metric Counter 45 + Register */ +#define XAPM_MC46_OFFSET 0x09A0 /**< Metric Counter 46 + Register */ +#define XAPM_MC47_OFFSET 0x09B0 /**< Metric Counter 47 + Register */ + +#define XAPM_SMC10_OFFSET 0x02A0 /**< Sampled Metric Counter + 10 Register */ +#define XAPM_SMC11_OFFSET 0x02B0 /**< Sampled Metric Counter + 11 Register */ +#define XAPM_SMC12_OFFSET 0x0600 /**< Sampled Metric Counter + 12 Register */ +#define XAPM_SMC13_OFFSET 0x0610 /**< Sampled Metric Counter + 13 Register */ +#define XAPM_SMC14_OFFSET 0x0620 /**< Sampled Metric Counter + 14 Register */ +#define XAPM_SMC15_OFFSET 0x0630 /**< Sampled Metric Counter + 15 Register */ +#define XAPM_SMC16_OFFSET 0x0640 /**< Sampled Metric Counter + 16 Register */ +#define XAPM_SMC17_OFFSET 0x0650 /**< Sampled Metric Counter + 17 Register */ +#define XAPM_SMC18_OFFSET 0x0660 /**< Sampled Metric Counter + 18 Register */ +#define XAPM_SMC19_OFFSET 0x0670 /**< Sampled Metric Counter + 19 Register */ +#define XAPM_SMC20_OFFSET 0x0680 /**< Sampled Metric Counter + 20 Register */ +#define XAPM_SMC21_OFFSET 0x0690 /**< Sampled Metric Counter + 21 Register */ +#define XAPM_SMC22_OFFSET 0x06A0 /**< Sampled Metric Counter + 22 Register */ +#define XAPM_SMC23_OFFSET 0x06B0 /**< Sampled Metric Counter + 23 Register */ +#define XAPM_SMC24_OFFSET 0x0800 /**< Sampled Metric Counter + 24 Register */ +#define XAPM_SMC25_OFFSET 0x0810 /**< Sampled Metric Counter + 25 Register */ +#define XAPM_SMC26_OFFSET 0x0820 /**< Sampled Metric Counter + 26 Register */ +#define XAPM_SMC27_OFFSET 0x0830 /**< Sampled Metric Counter + 27 Register */ +#define XAPM_SMC28_OFFSET 0x0840 /**< Sampled Metric Counter + 28 Register */ +#define XAPM_SMC29_OFFSET 0x0850 /**< Sampled Metric Counter + 29 Register */ +#define XAPM_SMC30_OFFSET 0x0860 /**< Sampled Metric Counter + 30 Register */ +#define XAPM_SMC31_OFFSET 0x0870 /**< Sampled Metric Counter + 31 Register */ +#define XAPM_SMC32_OFFSET 0x0880 /**< Sampled Metric Counter + 32 Register */ +#define XAPM_SMC33_OFFSET 0x0890 /**< Sampled Metric Counter + 33 Register */ +#define XAPM_SMC34_OFFSET 0x08A0 /**< Sampled Metric Counter + 34 Register */ +#define XAPM_SMC35_OFFSET 0x08B0 /**< Sampled Metric Counter + 35 Register */ +#define XAPM_SMC36_OFFSET 0x0A00 /**< Sampled Metric Counter + 36 Register */ +#define XAPM_SMC37_OFFSET 0x0A10 /**< Sampled Metric Counter + 37 Register */ +#define XAPM_SMC38_OFFSET 0x0A20 /**< Sampled Metric Counter + 38 Register */ +#define XAPM_SMC39_OFFSET 0x0A30 /**< Sampled Metric Counter + 39 Register */ +#define XAPM_SMC40_OFFSET 0x0A40 /**< Sampled Metric Counter + 40 Register */ +#define XAPM_SMC41_OFFSET 0x0A50 /**< Sampled Metric Counter + 41 Register */ +#define XAPM_SMC42_OFFSET 0x0A60 /**< Sampled Metric Counter + 42 Register */ +#define XAPM_SMC43_OFFSET 0x0A70 /**< Sampled Metric Counter + 43 Register */ +#define XAPM_SMC44_OFFSET 0x0A80 /**< Sampled Metric Counter + 44 Register */ +#define XAPM_SMC45_OFFSET 0x0A90 /**< Sampled Metric Counter + 45 Register */ +#define XAPM_SMC46_OFFSET 0x0AA0 /**< Sampled Metric Counter + 46 Register */ +#define XAPM_SMC47_OFFSET 0x0AB0 /**< Sampled Metric Counter + 47 Register */ + +#define XAPM_CTL_OFFSET 0x0300 /**< Control Register */ + +#define XAPM_ID_OFFSET 0x0304 /**< Latency ID Register */ + +#define XAPM_IDMASK_OFFSET 0x0308 /**< ID Mask Register */ + +#define XAPM_RID_OFFSET 0x030C /**< Latency Write ID Register */ + +#define XAPM_RIDMASK_OFFSET 0x0310 /**< Read ID Mask Register */ + +#define XAPM_FEC_OFFSET 0x0400 /**< Flag Enable + Control Register */ + +#define XAPM_SWD_OFFSET 0x0404 /**< Software-written + Data Register */ + +/* @} */ + +/** + * @name AXI Monitor Sample Interval Control Register mask(s) + * @{ + */ + +#define XAPM_SICR_MCNTR_RST_MASK 0x00000100 /**< Enable the Metric + Counter Reset */ +#define XAPM_SICR_LOAD_MASK 0x00000002 /**< Load the Sample Interval + * Register Value into the + * counter */ +#define XAPM_SICR_ENABLE_MASK 0x00000001 /**< Enable the downcounter */ + +/*@}*/ + + +/** @name Interrupt Status/Enable Register Bit Definitions and Masks + * @{ + */ + +#define XAPM_IXR_MC9_OVERFLOW_MASK 0x00001000 /**< Metric Counter 9 + * Overflow> */ +#define XAPM_IXR_MC8_OVERFLOW_MASK 0x00000800 /**< Metric Counter 8 + * Overflow> */ +#define XAPM_IXR_MC7_OVERFLOW_MASK 0x00000400 /**< Metric Counter 7 + * Overflow> */ +#define XAPM_IXR_MC6_OVERFLOW_MASK 0x00000200 /**< Metric Counter 6 + * Overflow> */ +#define XAPM_IXR_MC5_OVERFLOW_MASK 0x00000100 /**< Metric Counter 5 + * Overflow> */ +#define XAPM_IXR_MC4_OVERFLOW_MASK 0x00000080 /**< Metric Counter 4 + * Overflow> */ +#define XAPM_IXR_MC3_OVERFLOW_MASK 0x00000040 /**< Metric Counter 3 + * Overflow> */ +#define XAPM_IXR_MC2_OVERFLOW_MASK 0x00000020 /**< Metric Counter 2 + * Overflow> */ +#define XAPM_IXR_MC1_OVERFLOW_MASK 0x00000010 /**< Metric Counter 1 + * Overflow> */ +#define XAPM_IXR_MC0_OVERFLOW_MASK 0x00000008 /**< Metric Counter 0 + * Overflow> */ +#define XAPM_IXR_FIFO_FULL_MASK 0x00000004 /**< Event Log FIFO + * full> */ +#define XAPM_IXR_SIC_OVERFLOW_MASK 0x00000002 /**< Sample Interval + * Counter Overflow> */ +#define XAPM_IXR_GCC_OVERFLOW_MASK 0x00000001 /**< Global Clock Counter + * Overflow> */ +#define XAPM_IXR_ALL_MASK (XAPM_IXR_SIC_OVERFLOW_MASK | \ + XAPM_IXR_GCC_OVERFLOW_MASK | \ + XAPM_IXR_FIFO_FULL_MASK | \ + XAPM_IXR_MC0_OVERFLOW_MASK | \ + XAPM_IXR_MC1_OVERFLOW_MASK | \ + XAPM_IXR_MC2_OVERFLOW_MASK | \ + XAPM_IXR_MC3_OVERFLOW_MASK | \ + XAPM_IXR_MC4_OVERFLOW_MASK | \ + XAPM_IXR_MC5_OVERFLOW_MASK | \ + XAPM_IXR_MC6_OVERFLOW_MASK | \ + XAPM_IXR_MC7_OVERFLOW_MASK | \ + XAPM_IXR_MC8_OVERFLOW_MASK | \ + XAPM_IXR_MC9_OVERFLOW_MASK) +/* @} */ + +/** + * @name AXI Monitor Control Register mask(s) + * @{ + */ + +#define XAPM_CR_FIFO_RESET_MASK 0x02000000 + /**< FIFO Reset */ +#define XAPM_CR_GCC_RESET_MASK 0x00020000 + /**< Global Clk + Counter Reset */ +#define XAPM_CR_GCC_ENABLE_MASK 0x00010000 + /**< Global Clk + Counter Enable */ +#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK 0x00000200 + /**< Enable External trigger + to start event Log */ +#define XAPM_CR_EVENTLOG_ENABLE_MASK 0x00000100 + /**< Event Log Enable */ + +#define XAPM_CR_RDLATENCY_END_MASK 0x00000080 + /**< Write Latency + End point */ +#define XAPM_CR_RDLATENCY_START_MASK 0x00000040 + /**< Read Latency + Start point */ +#define XAPM_CR_WRLATENCY_END_MASK 0x00000020 + /**< Write Latency + End point */ +#define XAPM_CR_WRLATENCY_START_MASK 0x00000010 + /**< Write Latency + Start point */ +#define XAPM_CR_IDFILTER_ENABLE_MASK 0x00000008 + /**< ID Filter Enable */ + +#define XAPM_CR_MCNTR_EXTTRIGGER_MASK 0x00000004 + /**< Enable External + trigger to start + Metric Counters */ +#define XAPM_CR_MCNTR_RESET_MASK 0x00000002 + /**< Metrics Counter + Reset */ +#define XAPM_CR_MCNTR_ENABLE_MASK 0x00000001 + /**< Metrics Counter + Enable */ +/*@}*/ + +/** + * @name AXI Monitor ID Register mask(s) + * @{ + */ + +#define XAPM_ID_RID_MASK 0xFFFF0000 /**< Read ID */ + +#define XAPM_ID_WID_MASK 0x0000FFFF /**< Write ID */ + +/*@}*/ + +/** + * @name AXI Monitor ID Mask Register mask(s) + * @{ + */ + +#define XAPM_MASKID_RID_MASK 0xFFFF0000 /**< Read ID Mask */ + +#define XAPM_MASKID_WID_MASK 0x0000FFFF /**< Write ID Mask*/ + +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* Read a register of the AXI Performance Monitor device. This macro provides +* register access to all registers using the register offsets defined above. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XAxiPmon_ReadReg(u32 BaseAddress, u32 RegOffset); +* +******************************************************************************/ +#define XAxiPmon_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + +/*****************************************************************************/ +/** +* +* Write a register of the AXI Performance Monitor device. This macro provides +* register access to all registers using the register offsets defined above. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XAxiPmon_WriteReg(u32 BaseAddress, +* u32 RegOffset,u32 Data) +* +******************************************************************************/ +#define XAxiPmon_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32((BaseAddress) + (RegOffset), (Data))) + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xbasic_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xbasic_types.h new file mode 100644 index 000000000..07e3db39a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xbasic_types.h @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xbasic_types.h +* +* +* @note Dummy File for backwards compatibility +* + +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+*
+* +******************************************************************************/ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +/** @name Legacy types + * Deprecated legacy types. + * @{ + */ +typedef unsigned char Xuint8; /**< unsigned 8-bit */ +typedef char Xint8; /**< signed 8-bit */ +typedef unsigned short Xuint16; /**< unsigned 16-bit */ +typedef short Xint16; /**< signed 16-bit */ +typedef unsigned long Xuint32; /**< unsigned 32-bit */ +typedef long Xint32; /**< signed 32-bit */ +typedef float Xfloat32; /**< 32-bit floating point */ +typedef double Xfloat64; /**< 64-bit double precision FP */ +typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */ + +#if !defined __XUINT64__ +typedef struct +{ + Xuint32 Upper; + Xuint32 Lower; +} Xuint64; +#endif + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XIL_TYPES_H +typedef Xuint32 u32; +typedef Xuint16 u16; +typedef Xuint8 u8; +#endif +#else +#include +#endif + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +/* + * Xilinx NULL, TRUE and FALSE legacy support. Deprecated. + * Please use NULL, TRUE and FALSE + */ +#define XNULL NULL +#define XTRUE TRUE +#define XFALSE FALSE + +/* + * This file is deprecated and users + * should use xil_types.h and xil_assert.h\n\r + */ +#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert. +#warning Please refer the Standalone BSP UG647 for further details + + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcanps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcanps.h new file mode 100644 index 000000000..9c4c24211 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcanps.h @@ -0,0 +1,567 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.h +* +* The Xilinx CAN driver component. This component supports the Xilinx +* CAN Controller. +* +* The CAN Controller supports the following features: +* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards. +* - Supports both Standard (11 bit Identifier) and Extended (29 bit +* Identifier) frames. +* - Supports Bit Rates up to 1 Mbps. +* - Transmit message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Transmit prioritization through one TX High Priority Buffer. +* - Receive message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Watermark interrupts for Rx FIFO with configurable Watermark. +* - Acceptance filtering with 4 acceptance filters. +* - Sleep mode with automatic wake up. +* - Loop Back mode for diagnostic applications. +* - Snoop mode for diagnostic applications. +* - Maskable Error and Status Interrupts. +* - Readable Error Counters. +* - External PHY chip required. +* - Receive Timestamp. +* +* The device driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CAN. The driver handles transmission and reception of +* CAN frames, as well as configuration of the controller. The driver is simply a +* pass-through mechanism between a protocol stack and the CAN. A single device +* driver can support multiple CANs. +* +* Since the driver is a simple pass-through mechanism between a protocol stack +* and the CAN, no assembly or disassembly of CAN frames is done at the +* driver-level. This assumes that the protocol stack passes a correctly +* formatted CAN frame to the driver for transmission, and that the driver +* does not validate the contents of an incoming frame +* +* Operation Modes +* +* The CAN controller supports the following modes of operation: +* - Configuration Mode: In this mode the CAN timing parameters and +* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN +* controller loses synchronization with the CAN bus and drives a +* constant recessive bit on the bus line. The Error Counter Register are +* reset. The CAN controller does not receive or transmit any messages +* even if there are pending transmit requests from the TX FIFO or the TX +* High Priority Buffer. The Storage FIFOs and the CAN configuration +* registers are still accessible. +* - Normal Mode:In Normal Mode the CAN controller participates in bus +* communication, by transmitting and receiving messages. +* - Sleep Mode: In Sleep Mode the CAN Controller does not transmit any +* messages. However, if any other node transmits a message, then the CAN +* Controller receives the transmitted message and exits from Sleep Mode. +* If there are new transmission requests from either the TX FIFO or the +* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these +* requests are not serviced, and the CAN Controller continues to remain +* in Sleep Mode. Interrupts are generated when the CAN controller enters +* Sleep mode or Wakes up from Sleep mode. +* - Loop Back Mode: In Loop Back mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus. Any message that is transmitted +* is looped back to the �Rx� line and acknowledged. The CAN controller +* thus receives any message that it transmits. It does not participate in +* normal bus communication and does not receive any messages that are +* transmitted by other CAN nodes. This mode is used for diagnostic +* purposes. +* - Snoop Mode: In Snoop mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus and does not participate +* in normal bus communication but receives messages that are transmitted +* by other CAN nodes. This mode is used for diagnostic purposes. +* +* +* Buffer Alignment +* +* It is important to note that frame buffers passed to the driver must be +* 32-bit aligned. +* +* Receive Address Filtering +* +* The device can be set to accept frames whose Identifiers match any of the +* 4 filters set in the Acceptance Filter Mask/ID registers. +* +* The incoming Identifier is masked with the bits in the Acceptance Filter Mask +* Register. This value is compared with the result of masking the bits in the +* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If +* both these values are equal, the message will be stored in the RX FIFO. +* +* Acceptance Filtering is performed by each of the defined acceptance filters. +* If the incoming identifier passes through any acceptance filter then the +* frame is stored in the RX FIFO. +* +* If the Accpetance Filters are not set up then all the received messages are +* stroed in the RX FIFO. +* +* PHY Communication +* +* This driver does not provide any mechanism for directly programming PHY. +* +* Interrupts +* +* The driver has no dependencies on the interrupt controller. The driver +* provides an interrupt handler. User of this driver needs to provide +* callback functions. An interrupt handler example is available with +* the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Device Reset +* +* Bus Off interrupt that can occur in the device requires a device reset. +* The user is responsible for resetting the device and re-configuring it +* based on its needs (the driver does not save the current configuration). +* When integrating into an RTOS, these reset and re-configure obligations are +* taken care of by the OS adapter software if it exists for that RTOS. +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xcanps_g.c files. +* A table is defined where each entry contains configuration information +* for a CAN device. This information includes such things as the base address +* of the memory-mapped device. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCanPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+*			Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*			SDK claims a 40kbps baud rate but it's not.
+* 3.0 adk     09/12/14  Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ +#ifndef XCANPS_H /* prevent circular inclusions */ +#define XCANPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xcanps_hw.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +/** @name CAN operation modes + * @{ + */ +#define XCANPS_MODE_CONFIG 0x00000001U /**< Configuration mode */ +#define XCANPS_MODE_NORMAL 0x00000002U /**< Normal mode */ +#define XCANPS_MODE_LOOPBACK 0x00000004U /**< Loop Back mode */ +#define XCANPS_MODE_SLEEP 0x00000008U /**< Sleep mode */ +#define XCANPS_MODE_SNOOP 0x00000010U /**< Snoop mode */ +/* @} */ + +/** @name Callback identifiers used as parameters to XCanPs_SetHandler() + * @{ + */ +#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */ +#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/ +#define XCANPS_HANDLER_ERROR 3U /**< Handler type for error interrupt */ +#define XCANPS_HANDLER_EVENT 4U /**< Handler type for all other interrupts */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XCanPs_Config; + +/******************************************************************************/ +/** + * Callback type for frame sending and reception interrupts. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. +*******************************************************************************/ +typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef); + +/******************************************************************************/ +/** + * Callback type for error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param ErrorMask is a bit mask indicating the cause of the error. Its + * value equals 'OR'ing one or more XCANPS_ESR_* values defined in + * xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask); + +/******************************************************************************/ +/** + * Callback type for all kinds of interrupts except sending frame interrupt, + * receiving frame interrupt, and error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param Mask is a bit mask indicating the pending interrupts. Its value + * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask); + +/** + * The XCanPs driver instance data. The user is required to allocate a + * variable of this type for every CAN device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XCanPs_Config CanConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + + /** + * Callback and callback reference for TXOK interrupt. + */ + XCanPs_SendRecvHandler SendHandler; + void *SendRef; + + /** + * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts. + */ + XCanPs_SendRecvHandler RecvHandler; + void *RecvRef; + + /** + * Callback and callback reference for ERROR interrupt. + */ + XCanPs_ErrorHandler ErrorHandler; + void *ErrorRef; + + /** + * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/ + * Wakeup/Sleep/Bus off/ARBLST interrupts. + */ + XCanPs_EventHandler EventHandler; + void *EventRef; + +} XCanPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the transmission is complete. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the transmission is done. +* - FALSE if the transmission is not done. +* +* @note C-Style signature: +* int XCanPs_IsTxDone(XCanPs *InstancePtr) +* +*******************************************************************************/ +#define XCanPs_IsTxDone(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the transmission FIFO is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if TX FIFO is full. +* - FALSE if the TX FIFO is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsTxFifoFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the Transmission High Priority Buffer is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the TX High Priority Buffer is full. +* - FALSE if the TX High Priority Buffer is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsHighPriorityBufFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the receive FIFO is empty. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if RX FIFO is empty. +* - FALSE if the RX FIFO is NOT empty. +* +* @note C-Style signature: +* int XCanPs_IsRxEmpty(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsRxEmpty(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE) + + +/****************************************************************************/ +/** +* +* This macro checks if the CAN device is ready for the driver to change +* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask +* Registers (AFMR). +* +* AFIR and AFMR for a filter are changeable only after the filter is disabled +* and this routine returns FALSE. The filter can be disabled using the +* XCanPs_AcceptFilterDisable function. +* +* Use the XCanPs_Accept_* functions for configuring the acceptance filters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the device is busy and NOT ready to accept writes to +* AFIR and AFMR. +* - FALSE if the device is ready to accept writes to AFIR and +* AFMR. +* +* @note C-Style signature: +* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsAcceptFilterBusy(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro calculates CAN message identifier value given identifier field +* values. +* +* @param StandardId contains Standard Message ID value. +* @param SubRemoteTransReq contains Substitute Remote Transmission +* Request value. +* @param IdExtension contains Identifier Extension value. +* @param ExtendedId contains Extended Message ID value. +* @param RemoteTransReq contains Remote Transmission Request value. +* +* @return Message Identifier value. +* +* @note C-Style signature: +* u32 XCanPs_CreateIdValue(u32 StandardId, +* u32 SubRemoteTransReq, +* u32 IdExtension, u32 ExtendedId, +* u32 RemoteTransReq) +* +* Read the CAN specification for meaning of each parameter. +* +*****************************************************************************/ +#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \ + ExtendedId, RemoteTransReq) \ + ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \ + (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\ + (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \ + (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \ + ((RemoteTransReq) & XCANPS_IDR_RTR_MASK)) + + +/****************************************************************************/ +/** +* +* This macro calculates value for Data Length Code register given Data +* Length Code value. +* +* @param DataLengCode indicates Data Length Code value. +* +* @return Value that can be assigned to Data Length Code register. +* +* @note C-Style signature: +* u32 XCanPs_CreateDlcValue(u32 DataLengCode) +* +* Read the CAN specification for meaning of Data Length Code. +* +*****************************************************************************/ +#define XCanPs_CreateDlcValue(DataLengCode) \ + (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK) + + +/****************************************************************************/ +/** +* +* This macro clears the timestamp in the Timestamp Control Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XCanPs_ClearTimestamp(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_ClearTimestamp(InstancePtr) \ + XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \ + XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xcanps.c + */ +s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr); + +void XCanPs_Reset(XCanPs *InstancePtr); +u8 XCanPs_GetMode(XCanPs *InstancePtr); +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode); +u32 XCanPs_GetStatus(XCanPs *InstancePtr); +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount); +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr); +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask); +s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr); +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes); +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes); +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr); +s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue); +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue); + +s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler); +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr); +s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1); +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1); + +s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr); +s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr); + +/* + * Diagnostic functions in xcanps_selftest.c + */ +s32 XCanPs_SelfTest(XCanPs *InstancePtr); + +/* + * Functions in xcanps_intr.c + */ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask); +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr); +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr); +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrHandler(void *InstancePtr); +s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef); + +/* + * Functions in xcanps_sinit.c + */ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcanps_hw.h new file mode 100644 index 000000000..22f9b0725 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcanps_hw.h @@ -0,0 +1,366 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.h +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xcanps.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a sbs    12/27/11 Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET  to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET  to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk   08/08/13  Updated for inclding the function prototype
+* 3.00  kvn   02/13/15  Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +#ifndef XCANPS_HW_H /* prevent circular inclusions */ +#define XCANPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the CAN. Each register is 32 bits. + * @{ + */ +#define XCANPS_SRR_OFFSET 0x00000000U /**< Software Reset Register */ +#define XCANPS_MSR_OFFSET 0x00000004U /**< Mode Select Register */ +#define XCANPS_BRPR_OFFSET 0x00000008U /**< Baud Rate Prescaler */ +#define XCANPS_BTR_OFFSET 0x0000000CU /**< Bit Timing Register */ +#define XCANPS_ECR_OFFSET 0x00000010U /**< Error Counter Register */ +#define XCANPS_ESR_OFFSET 0x00000014U /**< Error Status Register */ +#define XCANPS_SR_OFFSET 0x00000018U /**< Status Register */ + +#define XCANPS_ISR_OFFSET 0x0000001CU /**< Interrupt Status Register */ +#define XCANPS_IER_OFFSET 0x00000020U /**< Interrupt Enable Register */ +#define XCANPS_ICR_OFFSET 0x00000024U /**< Interrupt Clear Register */ +#define XCANPS_TCR_OFFSET 0x00000028U /**< Timestamp Control Register */ +#define XCANPS_WIR_OFFSET 0x0000002CU /**< Watermark Interrupt Reg */ + +#define XCANPS_TXFIFO_ID_OFFSET 0x00000030U /**< TX FIFO ID */ +#define XCANPS_TXFIFO_DLC_OFFSET 0x00000034U /**< TX FIFO DLC */ +#define XCANPS_TXFIFO_DW1_OFFSET 0x00000038U /**< TX FIFO Data Word 1 */ +#define XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU /**< TX FIFO Data Word 2 */ + +#define XCANPS_TXHPB_ID_OFFSET 0x00000040U /**< TX High Priority Buffer ID */ +#define XCANPS_TXHPB_DLC_OFFSET 0x00000044U /**< TX High Priority Buffer DLC */ +#define XCANPS_TXHPB_DW1_OFFSET 0x00000048U /**< TX High Priority Buf Data 1 */ +#define XCANPS_TXHPB_DW2_OFFSET 0x0000004CU /**< TX High Priority Buf Data Word 2 */ + +#define XCANPS_RXFIFO_ID_OFFSET 0x00000050U /**< RX FIFO ID */ +#define XCANPS_RXFIFO_DLC_OFFSET 0x00000054U /**< RX FIFO DLC */ +#define XCANPS_RXFIFO_DW1_OFFSET 0x00000058U /**< RX FIFO Data Word 1 */ +#define XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU /**< RX FIFO Data Word 2 */ + +#define XCANPS_AFR_OFFSET 0x00000060U /**< Acceptance Filter Register */ +#define XCANPS_AFMR1_OFFSET 0x00000064U /**< Acceptance Filter Mask 1 */ +#define XCANPS_AFIR1_OFFSET 0x00000068U /**< Acceptance Filter ID 1 */ +#define XCANPS_AFMR2_OFFSET 0x0000006CU /**< Acceptance Filter Mask 2 */ +#define XCANPS_AFIR2_OFFSET 0x00000070U /**< Acceptance Filter ID 2 */ +#define XCANPS_AFMR3_OFFSET 0x00000074U /**< Acceptance Filter Mask 3 */ +#define XCANPS_AFIR3_OFFSET 0x00000078U /**< Acceptance Filter ID 3 */ +#define XCANPS_AFMR4_OFFSET 0x0000007CU /**< Acceptance Filter Mask 4 */ +#define XCANPS_AFIR4_OFFSET 0x00000080U /**< Acceptance Filter ID 4 */ +/* @} */ + +/** @name Software Reset Register (SRR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SRR_CEN_MASK 0x00000002U /**< Can Enable */ +#define XCANPS_SRR_SRST_MASK 0x00000001U /**< Reset */ +/* @} */ + +/** @name Mode Select Register (MSR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_MSR_SNOOP_MASK 0x00000004U /**< Snoop Mode Select */ +#define XCANPS_MSR_LBACK_MASK 0x00000002U /**< Loop Back Mode Select */ +#define XCANPS_MSR_SLEEP_MASK 0x00000001U /**< Sleep Mode Select */ +/* @} */ + +/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BRPR_BRP_MASK 0x000000FFU /**< Baud Rate Prescaler */ +/* @} */ + +/** @name Bit Timing Register (BTR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BTR_SJW_MASK 0x00000180U /**< Synchronization Jump Width */ +#define XCANPS_BTR_SJW_SHIFT 7U +#define XCANPS_BTR_TS2_MASK 0x00000070U /**< Time Segment 2 */ +#define XCANPS_BTR_TS2_SHIFT 4U +#define XCANPS_BTR_TS1_MASK 0x0000000FU /**< Time Segment 1 */ +/* @} */ + +/** @name Error Counter Register (ECR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ECR_REC_MASK 0x0000FF00U /**< Receive Error Counter */ +#define XCANPS_ECR_REC_SHIFT 8U +#define XCANPS_ECR_TEC_MASK 0x000000FFU /**< Transmit Error Counter */ +/* @} */ + +/** @name Error Status Register (ESR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ESR_ACKER_MASK 0x00000010U /**< ACK Error */ +#define XCANPS_ESR_BERR_MASK 0x00000008U /**< Bit Error */ +#define XCANPS_ESR_STER_MASK 0x00000004U /**< Stuff Error */ +#define XCANPS_ESR_FMER_MASK 0x00000002U /**< Form Error */ +#define XCANPS_ESR_CRCER_MASK 0x00000001U /**< CRC Error */ +/* @} */ + +/** @name Status Register (SR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SR_SNOOP_MASK 0x00001000U /**< Snoop Mask */ +#define XCANPS_SR_ACFBSY_MASK 0x00000800U /**< Acceptance Filter busy */ +#define XCANPS_SR_TXFLL_MASK 0x00000400U /**< TX FIFO is full */ +#define XCANPS_SR_TXBFLL_MASK 0x00000200U /**< TX High Priority Buffer full */ +#define XCANPS_SR_ESTAT_MASK 0x00000180U /**< Error Status */ +#define XCANPS_SR_ESTAT_SHIFT 7U +#define XCANPS_SR_ERRWRN_MASK 0x00000040U /**< Error Warning */ +#define XCANPS_SR_BBSY_MASK 0x00000020U /**< Bus Busy */ +#define XCANPS_SR_BIDLE_MASK 0x00000010U /**< Bus Idle */ +#define XCANPS_SR_NORMAL_MASK 0x00000008U /**< Normal Mode */ +#define XCANPS_SR_SLEEP_MASK 0x00000004U /**< Sleep Mode */ +#define XCANPS_SR_LBACK_MASK 0x00000002U /**< Loop Back Mode */ +#define XCANPS_SR_CONFIG_MASK 0x00000001U /**< Configuration Mode */ +/* @} */ + +/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks + * @{ + */ +#define XCANPS_IXR_TXFEMP_MASK 0x00004000U /**< Tx Fifo Empty Interrupt */ +#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */ +#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */ +#define XCANPS_IXR_WKUP_MASK 0x00000800U /**< Wake up Interrupt */ +#define XCANPS_IXR_SLP_MASK 0x00000400U /**< Sleep Interrupt */ +#define XCANPS_IXR_BSOFF_MASK 0x00000200U /**< Bus Off Interrupt */ +#define XCANPS_IXR_ERROR_MASK 0x00000100U /**< Error Interrupt */ +#define XCANPS_IXR_RXNEMP_MASK 0x00000080U /**< RX FIFO Not Empty Interrupt */ +#define XCANPS_IXR_RXOFLW_MASK 0x00000040U /**< RX FIFO Overflow Interrupt */ +#define XCANPS_IXR_RXUFLW_MASK 0x00000020U /**< RX FIFO Underflow Interrupt */ +#define XCANPS_IXR_RXOK_MASK 0x00000010U /**< New Message Received Intr */ +#define XCANPS_IXR_TXBFLL_MASK 0x00000008U /**< TX High Priority Buf Full */ +#define XCANPS_IXR_TXFLL_MASK 0x00000004U /**< TX FIFO Full Interrupt */ +#define XCANPS_IXR_TXOK_MASK 0x00000002U /**< TX Successful Interrupt */ +#define XCANPS_IXR_ARBLST_MASK 0x00000001U /**< Arbitration Lost Interrupt */ +#define XCANPS_IXR_ALL ((u32)XCANPS_IXR_RXFWMFLL_MASK | \ + (u32)XCANPS_IXR_WKUP_MASK | \ + (u32)XCANPS_IXR_SLP_MASK | \ + (u32)XCANPS_IXR_BSOFF_MASK | \ + (u32)XCANPS_IXR_ERROR_MASK | \ + (u32)XCANPS_IXR_RXNEMP_MASK | \ + (u32)XCANPS_IXR_RXOFLW_MASK | \ + (u32)XCANPS_IXR_RXUFLW_MASK | \ + (u32)XCANPS_IXR_RXOK_MASK | \ + (u32)XCANPS_IXR_TXBFLL_MASK | \ + (u32)XCANPS_IXR_TXFLL_MASK | \ + (u32)XCANPS_IXR_TXOK_MASK | \ + (u32)XCANPS_IXR_ARBLST_MASK) +/* @} */ + +/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_TCR_CTS_MASK 0x00000001U /**< Clear Timestamp counter mask */ +/* @} */ + +/** @name CAN Watermark Register (WIR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_WIR_FW_MASK 0x0000003FU /**< Rx Full Threshold mask */ +#define XCANPS_WIR_EW_MASK 0x00003F00U /**< Tx Empty Threshold mask */ +#define XCANPS_WIR_EW_SHIFT 0x00000008U /**< Tx Empty Threshold shift */ + +/* @} */ + +/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter + Mask/Acceptance Filter ID) + * @{ + */ +#define XCANPS_IDR_ID1_MASK 0xFFE00000U /**< Standard Messg Identifier */ +#define XCANPS_IDR_ID1_SHIFT 21U +#define XCANPS_IDR_SRR_MASK 0x00100000U /**< Substitute Remote TX Req */ +#define XCANPS_IDR_SRR_SHIFT 20U +#define XCANPS_IDR_IDE_MASK 0x00080000U /**< Identifier Extension */ +#define XCANPS_IDR_IDE_SHIFT 19U +#define XCANPS_IDR_ID2_MASK 0x0007FFFEU /**< Extended Message Ident */ +#define XCANPS_IDR_ID2_SHIFT 1U +#define XCANPS_IDR_RTR_MASK 0x00000001U /**< Remote TX Request */ +/* @} */ + +/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DLCR_DLC_MASK 0xF0000000U /**< Data Length Code */ +#define XCANPS_DLCR_DLC_SHIFT 28U +#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU /**< Timestamp Mask (Rx only) */ + +/* @} */ + +/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW1R_DB0_MASK 0xFF000000U /**< Data Byte 0 */ +#define XCANPS_DW1R_DB0_SHIFT 24U +#define XCANPS_DW1R_DB1_MASK 0x00FF0000U /**< Data Byte 1 */ +#define XCANPS_DW1R_DB1_SHIFT 16U +#define XCANPS_DW1R_DB2_MASK 0x0000FF00U /**< Data Byte 2 */ +#define XCANPS_DW1R_DB2_SHIFT 8U +#define XCANPS_DW1R_DB3_MASK 0x000000FFU /**< Data Byte 3 */ +/* @} */ + +/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW2R_DB4_MASK 0xFF000000U /**< Data Byte 4 */ +#define XCANPS_DW2R_DB4_SHIFT 24U +#define XCANPS_DW2R_DB5_MASK 0x00FF0000U /**< Data Byte 5 */ +#define XCANPS_DW2R_DB5_SHIFT 16U +#define XCANPS_DW2R_DB6_MASK 0x0000FF00U /**< Data Byte 6 */ +#define XCANPS_DW2R_DB6_SHIFT 8U +#define XCANPS_DW2R_DB7_MASK 0x000000FFU /**< Data Byte 7 */ +/* @} */ + +/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_AFR_UAF4_MASK 0x00000008U /**< Use Acceptance Filter No.4 */ +#define XCANPS_AFR_UAF3_MASK 0x00000004U /**< Use Acceptance Filter No.3 */ +#define XCANPS_AFR_UAF2_MASK 0x00000002U /**< Use Acceptance Filter No.2 */ +#define XCANPS_AFR_UAF1_MASK 0x00000001U /**< Use Acceptance Filter No.1 */ +#define XCANPS_AFR_UAF_ALL_MASK ((u32)XCANPS_AFR_UAF4_MASK | \ + (u32)XCANPS_AFR_UAF3_MASK | \ + (u32)XCANPS_AFR_UAF2_MASK | \ + (u32)XCANPS_AFR_UAF1_MASK) +/* @} */ + +/** @name CAN frame length constants + * @{ + */ +#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */ +/* @} */ + +/* For backwards compatibilty */ +#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET +#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET +#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET +#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET + +#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK +#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET +#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK + + + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the CanPs interface + */ +void XCanPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcpu_cortexa53.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcpu_cortexa53.h new file mode 100644 index 000000000..cbdfc1705 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcpu_cortexa53.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa53.h +* +* dummy file +* +******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcsudma.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcsudma.h new file mode 100644 index 000000000..831bcfccd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcsudma.h @@ -0,0 +1,414 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* The CSU_DMA is present inside CSU (Configuration Security Unit) module which +* is located within the Low-Power Subsystem (LPS) internal to the PS. +* CSU_DMA allows the CSU to move data efficiently between the memory (32 bit +* AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure +* Stream Switch (SSS). +* +* The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC +* (read) channel and DST (write) channel. The DMA is effectively able to +* transfer data: +* - From PS-side to the SSS-side (SRC DMA only) +* - From SSS-side to the PS-side (DST DMA only) +* - Simultaneous PS-side to SSS_side and SSS-side to the PS-side +* +* Initialization & Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CSU_DMA core. +* +* XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core. +* The user needs to first call the XCsuDma_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to the +* XCsuDma_CfgInitialize() API. +* +* Interrupts +* This driver will not support handling of interrupts user should write handler +* to handle the interrupts. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCsuDma driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* @file xcsudma.h +* +* This header file contains identifiers and register-level driver functions (or +* macros), range macros, structure typedefs that can be used to access the +* Xilinx CSU_DMA core instance. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +#ifndef XCSUDMA_H_ +#define XCSUDMA_H_ /**< Prevent circular inclusions + * by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xcsudma_hw.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xil_cache.h" + +/************************** Constant Definitions *****************************/ + +/** @name CSU_DMA Channels + * @{ + */ +typedef enum { + XCSUDMA_SRC_CHANNEL = 0U, /**< Source Channel of CSU_DMA */ + XCSUDMA_DST_CHANNEL /**< Destination Channel of CSU_DMA */ +}XCsuDma_Channel; +/*@}*/ + +/** @name CSU_DMA pause types + * @{ + */ +typedef enum { + XCSUDMA_PAUSE_MEMORY, /**< Pauses memory data transfer + * to/from CSU_DMA */ + XCSUDMA_PAUSE_STREAM, /**< Pauses stream data transfer + * to/from CSU_DMA */ +}XCsuDma_PauseType; + +/*@}*/ + + +/** @name Ranges of Size + * @{ + */ +#define XCSUDMA_SIZE_MAX 0x07FFFFFF /**< Maximum allowed no of words */ + +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* This function resets the CSU_DMA core. +* +* @param None. +* +* @return None. +* +* @note None. +* C-style signature: +* void XCsuDma_Reset() +* +******************************************************************************/ +#define XCsuDma_Reset() \ + Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \ + (u32)(XCSUDMA_RESET_SET_MASK)); \ + Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \ + (u32)(XCSUDMA_RESET_UNSET_MASK)); + +/*****************************************************************************/ +/** +* This function will be in busy while loop until the data transfer is +* completed. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return None. +* +* @note This function should be called after XCsuDma_Transfer in polled +* mode to wait until the data gets transfered completely. +* C-style signature: +* void XCsuDma_WaitForDone(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_WaitForDone(InstancePtr,Channel) \ + while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_I_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK)) + +/*****************************************************************************/ +/** +* +* This function returns the number of completed SRC/DST DMA transfers that +* have not been acknowledged by software based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Count is number of completed DMA transfers but not acknowledged +* (Range is 0 to 7). +* - 000 - All finished transfers have been acknowledged. +* - Count - Count number of finished transfers are still +* outstanding. +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetDoneCount(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \ + (u32)(XCSUDMA_STS_DONE_CNT_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the current SRC/DST FIFO level in 32 bit words of the +* selected channel +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return FIFO level. (Range is 0 to 128) +* - 0 Indicates empty +* - Any number 1 to 128 indicates the number of entries in FIFO. +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetFIFOLevel(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \ + (u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the current number of read(src)/write(dst) outstanding +* commands based on the type of channel selected. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Count of outstanding commands. (Range is 0 to 9). +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetWROutstandCount(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \ + (u32)(XCUSDMA_STS_OUTSTDG_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the status of Channel either it is busy or not. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Returns the current status of the core. +* - TRUE represents core is currently busy. +* - FALSE represents core is not involved in any transfers. +* +* @note None. +* C-style signature: +* s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +* +******************************************************************************/ + +#define XCsuDma_IsBusy(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \ + (TRUE) : (FALSE) + + +/**************************** Type Definitions *******************************/ + +/** +* This typedef contains configuration information for a CSU_DMA core. +* Each CSU_DMA core should have a configuration structure associated. +*/ +typedef struct { + u16 DeviceId; /**< DeviceId is the unique ID of the + * device */ + u32 BaseAddress; /**< BaseAddress is the physical base address + * of the device's registers */ +} XCsuDma_Config; + + +/******************************************************************************/ +/** +* +* The XCsuDma driver instance data structure. A pointer to an instance data +* structure is passed around by functions to refer to a specific driver +* instance. +*/ +typedef struct { + XCsuDma_Config Config; /**< Hardware configuration */ + u32 IsReady; /**< Device and the driver instance + * are initialized */ +}XCsuDma; + + +/******************************************************************************/ +/** +* This typedef contains all the configuration feilds which needs to be set +* before the start of the data transfer. All these feilds of CSU_DMA can be +* configured by using XCsuDma_SetConfig API. +*/ +typedef struct { + u8 SssFifoThesh; /**< SSS FIFO threshold value */ + u8 ApbErr; /**< ABP invalid access error */ + u8 EndianType; /**< Type of endianess */ + u8 AxiBurstType; /**< Type of AXI bus */ + u32 TimeoutValue; /**< Time out value */ + u8 FifoThresh; /**< FIFO threshold value */ + u8 Acache; /**< AXI CACHE selection */ + u8 RouteBit; /**< Selection of Route */ + u8 TimeoutEn; /**< Enable of time out counters */ + u16 TimeoutPre; /**< Pre scaler value */ + u8 MaxOutCmds; /**< Maximum number of outstanding + * commands */ +}XCsuDma_Configure; + +/*****************************************************************************/ + + +/************************** Function Prototypes ******************************/ + +XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId); + +s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, + u32 EffectiveAddr); +void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + UINTPTR Addr, u32 Size, u8 EnDataLast); +void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr, + u32 Size); +u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel); +u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); +s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); +void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); + +u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr); +void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr); + +void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues); +void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues); +void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value); +u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr); + +/* Interrupt related APIs */ +u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel); +void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +s32 XCsuDma_SelfTest(XCsuDma *InstancePtr); + +/******************************************************************************/ + +#ifdef __cplusplus +} + +#endif + +#endif /* End of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcsudma_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcsudma_hw.h new file mode 100644 index 000000000..76e401c2b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcsudma_hw.h @@ -0,0 +1,308 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcsudma_hw.h +* +* This header file contains identifiers and register-level driver functions (or +* macros) that can be used to access the Xilinx CSU_DMA core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vnsld  22/10/14 First release
+*
+* +******************************************************************************/ + +#ifndef XCSUDMA_HW_H_ +#define XCSUDMA_HW_H_ /**< Prevent circular inclusions + * by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Registers offsets + * @{ + */ +#define XCSUDMA_ADDR_OFFSET 0x000 /**< Address Register Offset */ +#define XCSUDMA_SIZE_OFFSET 0x004 /**< Size Register Offset */ +#define XCSUDMA_STS_OFFSET 0x008 /**< Status Register Offset */ +#define XCSUDMA_CTRL_OFFSET 0x00C /**< Control Register Offset */ +#define XCSUDMA_CRC_OFFSET 0x010 /**< CheckSum Register Offset */ +#define XCSUDMA_I_STS_OFFSET 0x014 /**< Interrupt Status Register + * Offset */ +#define XCSUDMA_I_EN_OFFSET 0x018 /**< Interrupt Enable Register + * Offset */ +#define XCSUDMA_I_DIS_OFFSET 0x01C /**< Interrupt Disable Register + * Offset */ +#define XCSUDMA_I_MASK_OFFSET 0x020 /**< Interrupt Mask Register Offset */ +#define XCSUDMA_CTRL2_OFFSET 0x024 /**< Interrupt Control Register 2 + * Offset */ +#define XCSUDMA_ADDR_MSB_OFFSET 0x028 /**< Address's MSB Register Offset */ +#define XCSUDMA_SAFETY_CHK_OFFSET 0xFF8 /**< Safety Check Field Offset */ +#define XCSUDMA_FUTURE_ECO_OFFSET 0xFFC /**< Future potential ECO Offset */ +/*@}*/ + +/** @name CSU Base address and CSU_DMA reset offset + * @{ + */ +#define XCSU_BASEADDRESS 0xFFCA0000 + /**< CSU Base Address */ +#define XCSU_DMA_RESET_OFFSET 0x0000000CU /**< CSU_DMA Reset offset */ +/*@}*/ + +/** @name CSU_DMA Reset register bit masks + * @{ + */ +#define XCSUDMA_RESET_SET_MASK 0x00000001U /**< Reset set mask */ +#define XCSUDMA_RESET_UNSET_MASK 0x00000000U /**< Reset unset mask*/ +/*@}*/ + +/** @name Offset difference for Source and destination + * @{ + */ +#define XCSUDMA_OFFSET_DIFF 0x00000800U /**< Offset difference for + * source and + * destination channels */ +/*@}*/ + +/** @name Address register bit masks + * @{ + */ +#define XCSUDMA_ADDR_MASK 0xFFFFFFFCU /**< Address mask */ +#define XCSUDMA_ADDR_LSB_MASK 0x00000003U /**< Address alignment check + * mask */ +/*@}*/ + +/** @name Size register bit masks and shifts + * @{ + */ +#define XCSUDMA_SIZE_MASK 0x1FFFFFFCU /**< Mask for size */ +#define XCSUDMA_LAST_WORD_MASK 0x00000001U /**< Last word check bit mask*/ +#define XCSUDMA_SIZE_SHIFT 2U /**< Shift for size */ +/*@}*/ + +/** @name Status register bit masks and shifts + * @{ + */ +#define XCSUDMA_STS_DONE_CNT_MASK 0x0000E000U /**< Count done mask */ +#define XCSUDMA_STS_FIFO_LEVEL_MASK 0x00001FE0U /**< FIFO level mask */ +#define XCUSDMA_STS_OUTSTDG_MASK 0x0000001EU /**< No.of outstanding + * read/write + * commands mask */ +#define XCSUDMA_STS_BUSY_MASK 0x00000001U /**< Busy mask */ +#define XCSUDMA_STS_DONE_CNT_SHIFT 13U /**< Shift for Count + * done */ +#define XCSUDMA_STS_FIFO_LEVEL_SHIFT 5U /**< Shift for FIFO + * level */ +#define XCUSDMA_STS_OUTSTDG_SHIFT 1U /**< Shift for No.of + * outstanding + * read/write + * commands */ +/*@}*/ + +/** @name Control register bit masks and shifts + * @{ + */ +#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U /**< SSS FIFO threshold + * value mask */ +#define XCSUDMA_CTRL_APB_ERR_MASK 0x01000000U /**< APB register + * access error + * mask */ +#define XCSUDMA_CTRL_ENDIAN_MASK 0x00800000U /**< Endianess mask */ +#define XCSUDMA_CTRL_BURST_MASK 0x00400000U /**< AXI burst type + * mask */ +#define XCSUDMA_CTRL_TIMEOUT_MASK 0x003FFC00U /**< Time out value + * mask */ +#define XCSUDMA_CTRL_FIFO_THRESH_MASK 0x000003FCU /**< FIFO threshold + * mask */ +#define XCSUDMA_CTRL_PAUSE_MEM_MASK 0x00000001U /**< Memory pause + * mask */ +#define XCSUDMA_CTRL_PAUSE_STRM_MASK 0x00000002U /**< Stream pause + * mask */ +#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U /**< SSS FIFO threshold + * shift */ +#define XCSUDMA_CTRL_APB_ERR_SHIFT 24U /**< APB error shift */ +#define XCSUDMA_CTRL_ENDIAN_SHIFT 23U /**< Endianess shift */ +#define XCSUDMA_CTRL_BURST_SHIFT 22U /**< AXI burst type + * shift */ +#define XCSUDMA_CTRL_TIMEOUT_SHIFT 10U /**< Time out value + * shift */ +#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT 2U /**< FIFO thresh + * shift */ +/*@}*/ + +/** @name CheckSum register bit masks + * @{ + */ +#define XCSUDMA_CRC_RESET_MASK 0x00000000U /**< Mask to reset + * value of + * check sum */ +/*@}*/ + +/** @name Interrupt Enable/Disable/Mask/Status registers bit masks + * @{ + */ +#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK 0x00000001U /**< FIFO overflow + * mask, it is valid + * only to Destination + * Channel */ +#define XCSUDMA_IXR_INVALID_APB_MASK 0x00000040U /**< Invalid APB access + * mask */ +#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK 0x00000020U /**< FIFO threshold hit + * indicator mask */ +#define XCSUDMA_IXR_TIMEOUT_MEM_MASK 0x00000010U /**< Time out counter + * expired to access + * memory mask */ +#define XCSUDMA_IXR_TIMEOUT_STRM_MASK 0x00000008U /**< Time out counter + * expired to access + * stream mask */ +#define XCSUDMA_IXR_AXI_WRERR_MASK 0x00000004U /**< AXI Read/Write + * error mask */ +#define XCSUDMA_IXR_DONE_MASK 0x00000002U /**< Done mask */ +#define XCSUDMA_IXR_MEM_DONE_MASK 0x00000001U /**< Memory done + * mask, it is valid + * only for source + * channel*/ +#define XCSUDMA_IXR_SRC_MASK 0x0000007FU + /**< ((XCSUDMA_IXR_INVALID_APB_MASK)| + (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | + (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | + (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | + (XCSUDMA_IXR_AXI_WRERR_MASK) | + (XCSUDMA_IXR_DONE_MASK) | + (XCSUDMA_IXR_MEM_DONE_MASK)) */ + /**< All interrupt mask + * for source */ +#define XCSUDMA_IXR_DST_MASK 0x000000FEU + /**< ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) | + (XCSUDMA_IXR_INVALID_APB_MASK) | + (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | + (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | + (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | + (XCSUDMA_IXR_AXI_WRERR_MASK) | + (XCSUDMA_IXR_DONE_MASK)) */ + /**< All interrupt mask + * for destination */ +/*@}*/ + +/** @name Control register 2 bit masks and shifts + * @{ + */ +#define XCSUDMA_CTRL2_RESERVED_MASK 0x083F0000U /**< Reserved bits + * mask */ +#define XCSUDMA_CTRL2_ACACHE_MASK 0X07000000U /**< AXI CACHE mask */ +#define XCSUDMA_CTRL2_ROUTE_MASK 0x00800000U /**< Route mask */ +#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK 0x00400000U /**< Time out counters + * enable mask */ +#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK 0x0000FFF0U /**< Time out pre + * mask */ +#define XCSUDMA_CTRL2_MAXCMDS_MASK 0x0000000FU /**< Maximum commands + * mask */ +#define XCSUDMA_CTRL2_RESET_MASK 0x0000FFF8U /**< Reset mask */ +#define XCSUDMA_CTRL2_ACACHE_SHIFT 24U /**< Shift for + * AXI R/W CACHE */ +#define XCSUDMA_CTRL2_ROUTE_SHIFT 23U /**< Shift for route */ +#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT 22U /**< Shift for Timeout + * enable feild */ +#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT 4U /**< Shift for Timeout + * pre feild */ +/*@}*/ + +/** @name MSB Address register bit masks and shifts + * @{ + */ +#define XCSUDMA_MSB_ADDR_MASK 0x0001FFFFU /**< MSB bits of address + * mask */ +#define XCSUDMA_MSB_ADDR_SHIFT 32U /**< Shift for MSB bits of + * address */ +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XCsuDma_In32 Xil_In32 /**< Input operation */ +#define XCsuDma_Out32 Xil_Out32 /**< Output operation */ + +/*****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the Xilinx base address of the CSU_DMA core. +* @param RegOffset is the register offset of the register. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset) +* +******************************************************************************/ +#define XCsuDma_ReadReg(BaseAddress, RegOffset) \ + XCsuDma_In32((BaseAddress) + (u32)(RegOffset)) + +/*****************************************************************************/ +/** +* +* This macro writes the value into the given register. +* +* @param BaseAddress is the Xilinx base address of the CSU_DMA core. +* @param RegOffset is the register offset of the register. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +******************************************************************************/ +#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data) \ + XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + + +#ifdef __cplusplus +} + +#endif + + +#endif /* End of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu0_cfg.h new file mode 100644 index 000000000..9029bead8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu0_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU0_CFG_H__ +#define __XDDR_XMPU0_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu0Cfg Base Address + */ +#define XDDR_XMPU0_CFG_BASEADDR 0xFD000000UL + +/** + * Register: XddrXmpu0CfgCtrl + */ +#define XDDR_XMPU0_CFG_CTRL ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU0_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu0CfgErrSts1 + */ +#define XDDR_XMPU0_CFG_ERR_STS1 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU0_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgErrSts2 + */ +#define XDDR_XMPU0_CFG_ERR_STS2 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU0_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgPoison + */ +#define XDDR_XMPU0_CFG_POISON ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU0_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU0_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU0_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU0_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgIsr + */ +#define XDDR_XMPU0_CFG_ISR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU0_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgImr + */ +#define XDDR_XMPU0_CFG_IMR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU0_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu0CfgIen + */ +#define XDDR_XMPU0_CFG_IEN ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU0_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgIds + */ +#define XDDR_XMPU0_CFG_IDS ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU0_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgLock + */ +#define XDDR_XMPU0_CFG_LOCK ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU0_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00Strt + */ +#define XDDR_XMPU0_CFG_R00_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU0_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00End + */ +#define XDDR_XMPU0_CFG_R00_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU0_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00Mstr + */ +#define XDDR_XMPU0_CFG_R00_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU0_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00 + */ +#define XDDR_XMPU0_CFG_R00 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU0_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01Strt + */ +#define XDDR_XMPU0_CFG_R01_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU0_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01End + */ +#define XDDR_XMPU0_CFG_R01_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU0_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01Mstr + */ +#define XDDR_XMPU0_CFG_R01_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU0_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01 + */ +#define XDDR_XMPU0_CFG_R01 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU0_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02Strt + */ +#define XDDR_XMPU0_CFG_R02_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU0_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02End + */ +#define XDDR_XMPU0_CFG_R02_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU0_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02Mstr + */ +#define XDDR_XMPU0_CFG_R02_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU0_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02 + */ +#define XDDR_XMPU0_CFG_R02 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU0_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03Strt + */ +#define XDDR_XMPU0_CFG_R03_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU0_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03End + */ +#define XDDR_XMPU0_CFG_R03_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU0_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03Mstr + */ +#define XDDR_XMPU0_CFG_R03_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU0_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03 + */ +#define XDDR_XMPU0_CFG_R03 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU0_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04Strt + */ +#define XDDR_XMPU0_CFG_R04_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU0_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04End + */ +#define XDDR_XMPU0_CFG_R04_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU0_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04Mstr + */ +#define XDDR_XMPU0_CFG_R04_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU0_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04 + */ +#define XDDR_XMPU0_CFG_R04 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU0_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05Strt + */ +#define XDDR_XMPU0_CFG_R05_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU0_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05End + */ +#define XDDR_XMPU0_CFG_R05_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU0_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05Mstr + */ +#define XDDR_XMPU0_CFG_R05_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU0_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05 + */ +#define XDDR_XMPU0_CFG_R05 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU0_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06Strt + */ +#define XDDR_XMPU0_CFG_R06_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU0_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06End + */ +#define XDDR_XMPU0_CFG_R06_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU0_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06Mstr + */ +#define XDDR_XMPU0_CFG_R06_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU0_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06 + */ +#define XDDR_XMPU0_CFG_R06 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU0_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07Strt + */ +#define XDDR_XMPU0_CFG_R07_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU0_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07End + */ +#define XDDR_XMPU0_CFG_R07_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU0_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07Mstr + */ +#define XDDR_XMPU0_CFG_R07_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU0_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07 + */ +#define XDDR_XMPU0_CFG_R07 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU0_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08Strt + */ +#define XDDR_XMPU0_CFG_R08_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU0_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08End + */ +#define XDDR_XMPU0_CFG_R08_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU0_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08Mstr + */ +#define XDDR_XMPU0_CFG_R08_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU0_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08 + */ +#define XDDR_XMPU0_CFG_R08 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU0_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09Strt + */ +#define XDDR_XMPU0_CFG_R09_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU0_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09End + */ +#define XDDR_XMPU0_CFG_R09_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU0_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09Mstr + */ +#define XDDR_XMPU0_CFG_R09_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU0_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09 + */ +#define XDDR_XMPU0_CFG_R09 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU0_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10Strt + */ +#define XDDR_XMPU0_CFG_R10_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU0_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10End + */ +#define XDDR_XMPU0_CFG_R10_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU0_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10Mstr + */ +#define XDDR_XMPU0_CFG_R10_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU0_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10 + */ +#define XDDR_XMPU0_CFG_R10 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU0_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11Strt + */ +#define XDDR_XMPU0_CFG_R11_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU0_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11End + */ +#define XDDR_XMPU0_CFG_R11_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU0_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11Mstr + */ +#define XDDR_XMPU0_CFG_R11_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU0_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11 + */ +#define XDDR_XMPU0_CFG_R11 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU0_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12Strt + */ +#define XDDR_XMPU0_CFG_R12_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU0_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12End + */ +#define XDDR_XMPU0_CFG_R12_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU0_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12Mstr + */ +#define XDDR_XMPU0_CFG_R12_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU0_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12 + */ +#define XDDR_XMPU0_CFG_R12 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU0_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13Strt + */ +#define XDDR_XMPU0_CFG_R13_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU0_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13End + */ +#define XDDR_XMPU0_CFG_R13_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU0_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13Mstr + */ +#define XDDR_XMPU0_CFG_R13_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU0_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13 + */ +#define XDDR_XMPU0_CFG_R13 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU0_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14Strt + */ +#define XDDR_XMPU0_CFG_R14_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU0_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14End + */ +#define XDDR_XMPU0_CFG_R14_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU0_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14Mstr + */ +#define XDDR_XMPU0_CFG_R14_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU0_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14 + */ +#define XDDR_XMPU0_CFG_R14 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU0_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15Strt + */ +#define XDDR_XMPU0_CFG_R15_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU0_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15End + */ +#define XDDR_XMPU0_CFG_R15_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU0_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15Mstr + */ +#define XDDR_XMPU0_CFG_R15_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU0_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15 + */ +#define XDDR_XMPU0_CFG_R15 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU0_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU0_CFG_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu1_cfg.h new file mode 100644 index 000000000..e2fa6d4aa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu1_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU1_CFG_H__ +#define __XDDR_XMPU1_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu1Cfg Base Address + */ +#define XDDR_XMPU1_CFG_BASEADDR 0xFD010000UL + +/** + * Register: XddrXmpu1CfgCtrl + */ +#define XDDR_XMPU1_CFG_CTRL ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU1_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu1CfgErrSts1 + */ +#define XDDR_XMPU1_CFG_ERR_STS1 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU1_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgErrSts2 + */ +#define XDDR_XMPU1_CFG_ERR_STS2 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU1_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgPoison + */ +#define XDDR_XMPU1_CFG_POISON ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU1_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU1_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU1_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU1_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgIsr + */ +#define XDDR_XMPU1_CFG_ISR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU1_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgImr + */ +#define XDDR_XMPU1_CFG_IMR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU1_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu1CfgIen + */ +#define XDDR_XMPU1_CFG_IEN ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU1_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgIds + */ +#define XDDR_XMPU1_CFG_IDS ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU1_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgLock + */ +#define XDDR_XMPU1_CFG_LOCK ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU1_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00Strt + */ +#define XDDR_XMPU1_CFG_R00_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU1_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00End + */ +#define XDDR_XMPU1_CFG_R00_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU1_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00Mstr + */ +#define XDDR_XMPU1_CFG_R00_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU1_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00 + */ +#define XDDR_XMPU1_CFG_R00 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU1_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01Strt + */ +#define XDDR_XMPU1_CFG_R01_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU1_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01End + */ +#define XDDR_XMPU1_CFG_R01_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU1_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01Mstr + */ +#define XDDR_XMPU1_CFG_R01_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU1_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01 + */ +#define XDDR_XMPU1_CFG_R01 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU1_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02Strt + */ +#define XDDR_XMPU1_CFG_R02_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU1_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02End + */ +#define XDDR_XMPU1_CFG_R02_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU1_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02Mstr + */ +#define XDDR_XMPU1_CFG_R02_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU1_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02 + */ +#define XDDR_XMPU1_CFG_R02 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU1_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03Strt + */ +#define XDDR_XMPU1_CFG_R03_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU1_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03End + */ +#define XDDR_XMPU1_CFG_R03_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU1_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03Mstr + */ +#define XDDR_XMPU1_CFG_R03_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU1_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03 + */ +#define XDDR_XMPU1_CFG_R03 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU1_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04Strt + */ +#define XDDR_XMPU1_CFG_R04_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU1_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04End + */ +#define XDDR_XMPU1_CFG_R04_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU1_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04Mstr + */ +#define XDDR_XMPU1_CFG_R04_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU1_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04 + */ +#define XDDR_XMPU1_CFG_R04 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU1_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05Strt + */ +#define XDDR_XMPU1_CFG_R05_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU1_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05End + */ +#define XDDR_XMPU1_CFG_R05_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU1_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05Mstr + */ +#define XDDR_XMPU1_CFG_R05_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU1_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05 + */ +#define XDDR_XMPU1_CFG_R05 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU1_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06Strt + */ +#define XDDR_XMPU1_CFG_R06_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU1_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06End + */ +#define XDDR_XMPU1_CFG_R06_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU1_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06Mstr + */ +#define XDDR_XMPU1_CFG_R06_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU1_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06 + */ +#define XDDR_XMPU1_CFG_R06 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU1_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07Strt + */ +#define XDDR_XMPU1_CFG_R07_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU1_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07End + */ +#define XDDR_XMPU1_CFG_R07_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU1_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07Mstr + */ +#define XDDR_XMPU1_CFG_R07_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU1_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07 + */ +#define XDDR_XMPU1_CFG_R07 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU1_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08Strt + */ +#define XDDR_XMPU1_CFG_R08_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU1_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08End + */ +#define XDDR_XMPU1_CFG_R08_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU1_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08Mstr + */ +#define XDDR_XMPU1_CFG_R08_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU1_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08 + */ +#define XDDR_XMPU1_CFG_R08 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU1_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09Strt + */ +#define XDDR_XMPU1_CFG_R09_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU1_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09End + */ +#define XDDR_XMPU1_CFG_R09_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU1_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09Mstr + */ +#define XDDR_XMPU1_CFG_R09_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU1_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09 + */ +#define XDDR_XMPU1_CFG_R09 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU1_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10Strt + */ +#define XDDR_XMPU1_CFG_R10_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU1_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10End + */ +#define XDDR_XMPU1_CFG_R10_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU1_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10Mstr + */ +#define XDDR_XMPU1_CFG_R10_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU1_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10 + */ +#define XDDR_XMPU1_CFG_R10 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU1_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11Strt + */ +#define XDDR_XMPU1_CFG_R11_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU1_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11End + */ +#define XDDR_XMPU1_CFG_R11_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU1_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11Mstr + */ +#define XDDR_XMPU1_CFG_R11_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU1_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11 + */ +#define XDDR_XMPU1_CFG_R11 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU1_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12Strt + */ +#define XDDR_XMPU1_CFG_R12_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU1_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12End + */ +#define XDDR_XMPU1_CFG_R12_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU1_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12Mstr + */ +#define XDDR_XMPU1_CFG_R12_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU1_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12 + */ +#define XDDR_XMPU1_CFG_R12 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU1_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13Strt + */ +#define XDDR_XMPU1_CFG_R13_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU1_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13End + */ +#define XDDR_XMPU1_CFG_R13_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU1_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13Mstr + */ +#define XDDR_XMPU1_CFG_R13_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU1_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13 + */ +#define XDDR_XMPU1_CFG_R13 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU1_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14Strt + */ +#define XDDR_XMPU1_CFG_R14_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU1_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14End + */ +#define XDDR_XMPU1_CFG_R14_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU1_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14Mstr + */ +#define XDDR_XMPU1_CFG_R14_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU1_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14 + */ +#define XDDR_XMPU1_CFG_R14 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU1_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15Strt + */ +#define XDDR_XMPU1_CFG_R15_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU1_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15End + */ +#define XDDR_XMPU1_CFG_R15_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU1_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15Mstr + */ +#define XDDR_XMPU1_CFG_R15_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU1_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15 + */ +#define XDDR_XMPU1_CFG_R15 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU1_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU1_CFG_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu2_cfg.h new file mode 100644 index 000000000..55ea2a7d3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu2_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU2_CFG_H__ +#define __XDDR_XMPU2_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu2Cfg Base Address + */ +#define XDDR_XMPU2_CFG_BASEADDR 0xFD020000UL + +/** + * Register: XddrXmpu2CfgCtrl + */ +#define XDDR_XMPU2_CFG_CTRL ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU2_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu2CfgErrSts1 + */ +#define XDDR_XMPU2_CFG_ERR_STS1 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU2_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgErrSts2 + */ +#define XDDR_XMPU2_CFG_ERR_STS2 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU2_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgPoison + */ +#define XDDR_XMPU2_CFG_POISON ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU2_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU2_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU2_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU2_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgIsr + */ +#define XDDR_XMPU2_CFG_ISR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU2_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgImr + */ +#define XDDR_XMPU2_CFG_IMR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU2_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu2CfgIen + */ +#define XDDR_XMPU2_CFG_IEN ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU2_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgIds + */ +#define XDDR_XMPU2_CFG_IDS ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU2_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgLock + */ +#define XDDR_XMPU2_CFG_LOCK ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU2_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00Strt + */ +#define XDDR_XMPU2_CFG_R00_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU2_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00End + */ +#define XDDR_XMPU2_CFG_R00_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU2_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00Mstr + */ +#define XDDR_XMPU2_CFG_R00_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU2_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00 + */ +#define XDDR_XMPU2_CFG_R00 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU2_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01Strt + */ +#define XDDR_XMPU2_CFG_R01_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU2_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01End + */ +#define XDDR_XMPU2_CFG_R01_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU2_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01Mstr + */ +#define XDDR_XMPU2_CFG_R01_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU2_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01 + */ +#define XDDR_XMPU2_CFG_R01 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU2_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02Strt + */ +#define XDDR_XMPU2_CFG_R02_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU2_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02End + */ +#define XDDR_XMPU2_CFG_R02_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU2_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02Mstr + */ +#define XDDR_XMPU2_CFG_R02_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU2_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02 + */ +#define XDDR_XMPU2_CFG_R02 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU2_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03Strt + */ +#define XDDR_XMPU2_CFG_R03_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU2_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03End + */ +#define XDDR_XMPU2_CFG_R03_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU2_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03Mstr + */ +#define XDDR_XMPU2_CFG_R03_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU2_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03 + */ +#define XDDR_XMPU2_CFG_R03 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU2_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04Strt + */ +#define XDDR_XMPU2_CFG_R04_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU2_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04End + */ +#define XDDR_XMPU2_CFG_R04_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU2_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04Mstr + */ +#define XDDR_XMPU2_CFG_R04_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU2_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04 + */ +#define XDDR_XMPU2_CFG_R04 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU2_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05Strt + */ +#define XDDR_XMPU2_CFG_R05_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU2_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05End + */ +#define XDDR_XMPU2_CFG_R05_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU2_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05Mstr + */ +#define XDDR_XMPU2_CFG_R05_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU2_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05 + */ +#define XDDR_XMPU2_CFG_R05 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU2_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06Strt + */ +#define XDDR_XMPU2_CFG_R06_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU2_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06End + */ +#define XDDR_XMPU2_CFG_R06_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU2_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06Mstr + */ +#define XDDR_XMPU2_CFG_R06_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU2_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06 + */ +#define XDDR_XMPU2_CFG_R06 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU2_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07Strt + */ +#define XDDR_XMPU2_CFG_R07_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU2_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07End + */ +#define XDDR_XMPU2_CFG_R07_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU2_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07Mstr + */ +#define XDDR_XMPU2_CFG_R07_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU2_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07 + */ +#define XDDR_XMPU2_CFG_R07 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU2_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08Strt + */ +#define XDDR_XMPU2_CFG_R08_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU2_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08End + */ +#define XDDR_XMPU2_CFG_R08_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU2_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08Mstr + */ +#define XDDR_XMPU2_CFG_R08_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU2_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08 + */ +#define XDDR_XMPU2_CFG_R08 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU2_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09Strt + */ +#define XDDR_XMPU2_CFG_R09_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU2_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09End + */ +#define XDDR_XMPU2_CFG_R09_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU2_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09Mstr + */ +#define XDDR_XMPU2_CFG_R09_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU2_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09 + */ +#define XDDR_XMPU2_CFG_R09 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU2_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10Strt + */ +#define XDDR_XMPU2_CFG_R10_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU2_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10End + */ +#define XDDR_XMPU2_CFG_R10_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU2_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10Mstr + */ +#define XDDR_XMPU2_CFG_R10_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU2_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10 + */ +#define XDDR_XMPU2_CFG_R10 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU2_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11Strt + */ +#define XDDR_XMPU2_CFG_R11_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU2_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11End + */ +#define XDDR_XMPU2_CFG_R11_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU2_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11Mstr + */ +#define XDDR_XMPU2_CFG_R11_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU2_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11 + */ +#define XDDR_XMPU2_CFG_R11 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU2_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12Strt + */ +#define XDDR_XMPU2_CFG_R12_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU2_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12End + */ +#define XDDR_XMPU2_CFG_R12_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU2_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12Mstr + */ +#define XDDR_XMPU2_CFG_R12_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU2_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12 + */ +#define XDDR_XMPU2_CFG_R12 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU2_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13Strt + */ +#define XDDR_XMPU2_CFG_R13_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU2_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13End + */ +#define XDDR_XMPU2_CFG_R13_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU2_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13Mstr + */ +#define XDDR_XMPU2_CFG_R13_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU2_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13 + */ +#define XDDR_XMPU2_CFG_R13 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU2_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14Strt + */ +#define XDDR_XMPU2_CFG_R14_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU2_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14End + */ +#define XDDR_XMPU2_CFG_R14_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU2_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14Mstr + */ +#define XDDR_XMPU2_CFG_R14_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU2_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14 + */ +#define XDDR_XMPU2_CFG_R14 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU2_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15Strt + */ +#define XDDR_XMPU2_CFG_R15_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU2_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15End + */ +#define XDDR_XMPU2_CFG_R15_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU2_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15Mstr + */ +#define XDDR_XMPU2_CFG_R15_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU2_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15 + */ +#define XDDR_XMPU2_CFG_R15 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU2_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU2_CFG_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu3_cfg.h new file mode 100644 index 000000000..416314967 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu3_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU3_CFG_H__ +#define __XDDR_XMPU3_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu3Cfg Base Address + */ +#define XDDR_XMPU3_CFG_BASEADDR 0xFD030000UL + +/** + * Register: XddrXmpu3CfgCtrl + */ +#define XDDR_XMPU3_CFG_CTRL ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU3_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu3CfgErrSts1 + */ +#define XDDR_XMPU3_CFG_ERR_STS1 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU3_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgErrSts2 + */ +#define XDDR_XMPU3_CFG_ERR_STS2 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU3_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgPoison + */ +#define XDDR_XMPU3_CFG_POISON ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU3_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU3_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU3_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU3_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgIsr + */ +#define XDDR_XMPU3_CFG_ISR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU3_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgImr + */ +#define XDDR_XMPU3_CFG_IMR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU3_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu3CfgIen + */ +#define XDDR_XMPU3_CFG_IEN ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU3_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgIds + */ +#define XDDR_XMPU3_CFG_IDS ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU3_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgLock + */ +#define XDDR_XMPU3_CFG_LOCK ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU3_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00Strt + */ +#define XDDR_XMPU3_CFG_R00_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU3_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00End + */ +#define XDDR_XMPU3_CFG_R00_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU3_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00Mstr + */ +#define XDDR_XMPU3_CFG_R00_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU3_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00 + */ +#define XDDR_XMPU3_CFG_R00 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU3_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01Strt + */ +#define XDDR_XMPU3_CFG_R01_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU3_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01End + */ +#define XDDR_XMPU3_CFG_R01_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU3_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01Mstr + */ +#define XDDR_XMPU3_CFG_R01_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU3_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01 + */ +#define XDDR_XMPU3_CFG_R01 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU3_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02Strt + */ +#define XDDR_XMPU3_CFG_R02_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU3_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02End + */ +#define XDDR_XMPU3_CFG_R02_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU3_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02Mstr + */ +#define XDDR_XMPU3_CFG_R02_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU3_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02 + */ +#define XDDR_XMPU3_CFG_R02 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU3_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03Strt + */ +#define XDDR_XMPU3_CFG_R03_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU3_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03End + */ +#define XDDR_XMPU3_CFG_R03_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU3_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03Mstr + */ +#define XDDR_XMPU3_CFG_R03_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU3_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03 + */ +#define XDDR_XMPU3_CFG_R03 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU3_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04Strt + */ +#define XDDR_XMPU3_CFG_R04_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU3_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04End + */ +#define XDDR_XMPU3_CFG_R04_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU3_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04Mstr + */ +#define XDDR_XMPU3_CFG_R04_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU3_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04 + */ +#define XDDR_XMPU3_CFG_R04 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU3_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05Strt + */ +#define XDDR_XMPU3_CFG_R05_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU3_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05End + */ +#define XDDR_XMPU3_CFG_R05_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU3_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05Mstr + */ +#define XDDR_XMPU3_CFG_R05_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU3_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05 + */ +#define XDDR_XMPU3_CFG_R05 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU3_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06Strt + */ +#define XDDR_XMPU3_CFG_R06_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU3_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06End + */ +#define XDDR_XMPU3_CFG_R06_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU3_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06Mstr + */ +#define XDDR_XMPU3_CFG_R06_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU3_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06 + */ +#define XDDR_XMPU3_CFG_R06 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU3_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07Strt + */ +#define XDDR_XMPU3_CFG_R07_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU3_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07End + */ +#define XDDR_XMPU3_CFG_R07_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU3_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07Mstr + */ +#define XDDR_XMPU3_CFG_R07_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU3_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07 + */ +#define XDDR_XMPU3_CFG_R07 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU3_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08Strt + */ +#define XDDR_XMPU3_CFG_R08_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU3_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08End + */ +#define XDDR_XMPU3_CFG_R08_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU3_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08Mstr + */ +#define XDDR_XMPU3_CFG_R08_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU3_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08 + */ +#define XDDR_XMPU3_CFG_R08 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU3_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09Strt + */ +#define XDDR_XMPU3_CFG_R09_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU3_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09End + */ +#define XDDR_XMPU3_CFG_R09_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU3_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09Mstr + */ +#define XDDR_XMPU3_CFG_R09_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU3_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09 + */ +#define XDDR_XMPU3_CFG_R09 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU3_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10Strt + */ +#define XDDR_XMPU3_CFG_R10_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU3_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10End + */ +#define XDDR_XMPU3_CFG_R10_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU3_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10Mstr + */ +#define XDDR_XMPU3_CFG_R10_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU3_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10 + */ +#define XDDR_XMPU3_CFG_R10 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU3_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11Strt + */ +#define XDDR_XMPU3_CFG_R11_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU3_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11End + */ +#define XDDR_XMPU3_CFG_R11_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU3_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11Mstr + */ +#define XDDR_XMPU3_CFG_R11_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU3_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11 + */ +#define XDDR_XMPU3_CFG_R11 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU3_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12Strt + */ +#define XDDR_XMPU3_CFG_R12_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU3_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12End + */ +#define XDDR_XMPU3_CFG_R12_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU3_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12Mstr + */ +#define XDDR_XMPU3_CFG_R12_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU3_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12 + */ +#define XDDR_XMPU3_CFG_R12 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU3_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13Strt + */ +#define XDDR_XMPU3_CFG_R13_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU3_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13End + */ +#define XDDR_XMPU3_CFG_R13_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU3_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13Mstr + */ +#define XDDR_XMPU3_CFG_R13_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU3_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13 + */ +#define XDDR_XMPU3_CFG_R13 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU3_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14Strt + */ +#define XDDR_XMPU3_CFG_R14_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU3_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14End + */ +#define XDDR_XMPU3_CFG_R14_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU3_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14Mstr + */ +#define XDDR_XMPU3_CFG_R14_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU3_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14 + */ +#define XDDR_XMPU3_CFG_R14 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU3_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15Strt + */ +#define XDDR_XMPU3_CFG_R15_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU3_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15End + */ +#define XDDR_XMPU3_CFG_R15_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU3_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15Mstr + */ +#define XDDR_XMPU3_CFG_R15_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU3_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15 + */ +#define XDDR_XMPU3_CFG_R15 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU3_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU3_CFG_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu4_cfg.h new file mode 100644 index 000000000..2df814419 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu4_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU4_CFG_H__ +#define __XDDR_XMPU4_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu4Cfg Base Address + */ +#define XDDR_XMPU4_CFG_BASEADDR 0xFD040000UL + +/** + * Register: XddrXmpu4CfgCtrl + */ +#define XDDR_XMPU4_CFG_CTRL ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU4_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu4CfgErrSts1 + */ +#define XDDR_XMPU4_CFG_ERR_STS1 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU4_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgErrSts2 + */ +#define XDDR_XMPU4_CFG_ERR_STS2 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU4_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgPoison + */ +#define XDDR_XMPU4_CFG_POISON ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU4_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU4_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU4_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU4_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgIsr + */ +#define XDDR_XMPU4_CFG_ISR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU4_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgImr + */ +#define XDDR_XMPU4_CFG_IMR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU4_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu4CfgIen + */ +#define XDDR_XMPU4_CFG_IEN ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU4_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgIds + */ +#define XDDR_XMPU4_CFG_IDS ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU4_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgLock + */ +#define XDDR_XMPU4_CFG_LOCK ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU4_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00Strt + */ +#define XDDR_XMPU4_CFG_R00_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU4_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00End + */ +#define XDDR_XMPU4_CFG_R00_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU4_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00Mstr + */ +#define XDDR_XMPU4_CFG_R00_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU4_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00 + */ +#define XDDR_XMPU4_CFG_R00 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU4_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01Strt + */ +#define XDDR_XMPU4_CFG_R01_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU4_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01End + */ +#define XDDR_XMPU4_CFG_R01_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU4_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01Mstr + */ +#define XDDR_XMPU4_CFG_R01_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU4_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01 + */ +#define XDDR_XMPU4_CFG_R01 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU4_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02Strt + */ +#define XDDR_XMPU4_CFG_R02_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU4_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02End + */ +#define XDDR_XMPU4_CFG_R02_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU4_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02Mstr + */ +#define XDDR_XMPU4_CFG_R02_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU4_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02 + */ +#define XDDR_XMPU4_CFG_R02 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU4_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03Strt + */ +#define XDDR_XMPU4_CFG_R03_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU4_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03End + */ +#define XDDR_XMPU4_CFG_R03_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU4_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03Mstr + */ +#define XDDR_XMPU4_CFG_R03_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU4_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03 + */ +#define XDDR_XMPU4_CFG_R03 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU4_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04Strt + */ +#define XDDR_XMPU4_CFG_R04_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU4_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04End + */ +#define XDDR_XMPU4_CFG_R04_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU4_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04Mstr + */ +#define XDDR_XMPU4_CFG_R04_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU4_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04 + */ +#define XDDR_XMPU4_CFG_R04 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU4_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05Strt + */ +#define XDDR_XMPU4_CFG_R05_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU4_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05End + */ +#define XDDR_XMPU4_CFG_R05_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU4_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05Mstr + */ +#define XDDR_XMPU4_CFG_R05_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU4_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05 + */ +#define XDDR_XMPU4_CFG_R05 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU4_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06Strt + */ +#define XDDR_XMPU4_CFG_R06_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU4_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06End + */ +#define XDDR_XMPU4_CFG_R06_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU4_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06Mstr + */ +#define XDDR_XMPU4_CFG_R06_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU4_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06 + */ +#define XDDR_XMPU4_CFG_R06 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU4_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07Strt + */ +#define XDDR_XMPU4_CFG_R07_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU4_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07End + */ +#define XDDR_XMPU4_CFG_R07_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU4_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07Mstr + */ +#define XDDR_XMPU4_CFG_R07_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU4_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07 + */ +#define XDDR_XMPU4_CFG_R07 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU4_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08Strt + */ +#define XDDR_XMPU4_CFG_R08_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU4_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08End + */ +#define XDDR_XMPU4_CFG_R08_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU4_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08Mstr + */ +#define XDDR_XMPU4_CFG_R08_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU4_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08 + */ +#define XDDR_XMPU4_CFG_R08 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU4_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09Strt + */ +#define XDDR_XMPU4_CFG_R09_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU4_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09End + */ +#define XDDR_XMPU4_CFG_R09_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU4_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09Mstr + */ +#define XDDR_XMPU4_CFG_R09_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU4_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09 + */ +#define XDDR_XMPU4_CFG_R09 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU4_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10Strt + */ +#define XDDR_XMPU4_CFG_R10_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU4_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10End + */ +#define XDDR_XMPU4_CFG_R10_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU4_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10Mstr + */ +#define XDDR_XMPU4_CFG_R10_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU4_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10 + */ +#define XDDR_XMPU4_CFG_R10 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU4_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11Strt + */ +#define XDDR_XMPU4_CFG_R11_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU4_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11End + */ +#define XDDR_XMPU4_CFG_R11_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU4_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11Mstr + */ +#define XDDR_XMPU4_CFG_R11_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU4_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11 + */ +#define XDDR_XMPU4_CFG_R11 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU4_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12Strt + */ +#define XDDR_XMPU4_CFG_R12_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU4_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12End + */ +#define XDDR_XMPU4_CFG_R12_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU4_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12Mstr + */ +#define XDDR_XMPU4_CFG_R12_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU4_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12 + */ +#define XDDR_XMPU4_CFG_R12 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU4_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13Strt + */ +#define XDDR_XMPU4_CFG_R13_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU4_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13End + */ +#define XDDR_XMPU4_CFG_R13_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU4_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13Mstr + */ +#define XDDR_XMPU4_CFG_R13_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU4_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13 + */ +#define XDDR_XMPU4_CFG_R13 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU4_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14Strt + */ +#define XDDR_XMPU4_CFG_R14_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU4_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14End + */ +#define XDDR_XMPU4_CFG_R14_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU4_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14Mstr + */ +#define XDDR_XMPU4_CFG_R14_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU4_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14 + */ +#define XDDR_XMPU4_CFG_R14 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU4_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15Strt + */ +#define XDDR_XMPU4_CFG_R15_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU4_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15End + */ +#define XDDR_XMPU4_CFG_R15_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU4_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15Mstr + */ +#define XDDR_XMPU4_CFG_R15_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU4_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15 + */ +#define XDDR_XMPU4_CFG_R15 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU4_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU4_CFG_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu5_cfg.h new file mode 100644 index 000000000..60811718d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xddr_xmpu5_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU5_CFG_H__ +#define __XDDR_XMPU5_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu5Cfg Base Address + */ +#define XDDR_XMPU5_CFG_BASEADDR 0xFD050000UL + +/** + * Register: XddrXmpu5CfgCtrl + */ +#define XDDR_XMPU5_CFG_CTRL ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU5_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu5CfgErrSts1 + */ +#define XDDR_XMPU5_CFG_ERR_STS1 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU5_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgErrSts2 + */ +#define XDDR_XMPU5_CFG_ERR_STS2 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU5_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgPoison + */ +#define XDDR_XMPU5_CFG_POISON ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU5_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU5_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU5_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU5_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgIsr + */ +#define XDDR_XMPU5_CFG_ISR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU5_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgImr + */ +#define XDDR_XMPU5_CFG_IMR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU5_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu5CfgIen + */ +#define XDDR_XMPU5_CFG_IEN ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU5_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgIds + */ +#define XDDR_XMPU5_CFG_IDS ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU5_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgLock + */ +#define XDDR_XMPU5_CFG_LOCK ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU5_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00Strt + */ +#define XDDR_XMPU5_CFG_R00_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU5_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00End + */ +#define XDDR_XMPU5_CFG_R00_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU5_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00Mstr + */ +#define XDDR_XMPU5_CFG_R00_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU5_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00 + */ +#define XDDR_XMPU5_CFG_R00 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU5_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01Strt + */ +#define XDDR_XMPU5_CFG_R01_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU5_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01End + */ +#define XDDR_XMPU5_CFG_R01_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU5_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01Mstr + */ +#define XDDR_XMPU5_CFG_R01_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU5_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01 + */ +#define XDDR_XMPU5_CFG_R01 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU5_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02Strt + */ +#define XDDR_XMPU5_CFG_R02_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU5_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02End + */ +#define XDDR_XMPU5_CFG_R02_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU5_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02Mstr + */ +#define XDDR_XMPU5_CFG_R02_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU5_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02 + */ +#define XDDR_XMPU5_CFG_R02 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU5_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03Strt + */ +#define XDDR_XMPU5_CFG_R03_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU5_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03End + */ +#define XDDR_XMPU5_CFG_R03_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU5_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03Mstr + */ +#define XDDR_XMPU5_CFG_R03_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU5_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03 + */ +#define XDDR_XMPU5_CFG_R03 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU5_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04Strt + */ +#define XDDR_XMPU5_CFG_R04_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU5_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04End + */ +#define XDDR_XMPU5_CFG_R04_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU5_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04Mstr + */ +#define XDDR_XMPU5_CFG_R04_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU5_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04 + */ +#define XDDR_XMPU5_CFG_R04 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU5_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05Strt + */ +#define XDDR_XMPU5_CFG_R05_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU5_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05End + */ +#define XDDR_XMPU5_CFG_R05_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU5_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05Mstr + */ +#define XDDR_XMPU5_CFG_R05_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU5_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05 + */ +#define XDDR_XMPU5_CFG_R05 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU5_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06Strt + */ +#define XDDR_XMPU5_CFG_R06_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU5_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06End + */ +#define XDDR_XMPU5_CFG_R06_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU5_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06Mstr + */ +#define XDDR_XMPU5_CFG_R06_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU5_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06 + */ +#define XDDR_XMPU5_CFG_R06 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU5_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07Strt + */ +#define XDDR_XMPU5_CFG_R07_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU5_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07End + */ +#define XDDR_XMPU5_CFG_R07_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU5_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07Mstr + */ +#define XDDR_XMPU5_CFG_R07_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU5_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07 + */ +#define XDDR_XMPU5_CFG_R07 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU5_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08Strt + */ +#define XDDR_XMPU5_CFG_R08_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU5_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08End + */ +#define XDDR_XMPU5_CFG_R08_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU5_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08Mstr + */ +#define XDDR_XMPU5_CFG_R08_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU5_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08 + */ +#define XDDR_XMPU5_CFG_R08 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU5_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09Strt + */ +#define XDDR_XMPU5_CFG_R09_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU5_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09End + */ +#define XDDR_XMPU5_CFG_R09_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU5_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09Mstr + */ +#define XDDR_XMPU5_CFG_R09_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU5_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09 + */ +#define XDDR_XMPU5_CFG_R09 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU5_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10Strt + */ +#define XDDR_XMPU5_CFG_R10_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU5_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10End + */ +#define XDDR_XMPU5_CFG_R10_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU5_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10Mstr + */ +#define XDDR_XMPU5_CFG_R10_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU5_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10 + */ +#define XDDR_XMPU5_CFG_R10 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU5_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11Strt + */ +#define XDDR_XMPU5_CFG_R11_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU5_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11End + */ +#define XDDR_XMPU5_CFG_R11_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU5_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11Mstr + */ +#define XDDR_XMPU5_CFG_R11_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU5_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11 + */ +#define XDDR_XMPU5_CFG_R11 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU5_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12Strt + */ +#define XDDR_XMPU5_CFG_R12_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU5_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12End + */ +#define XDDR_XMPU5_CFG_R12_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU5_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12Mstr + */ +#define XDDR_XMPU5_CFG_R12_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU5_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12 + */ +#define XDDR_XMPU5_CFG_R12 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU5_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13Strt + */ +#define XDDR_XMPU5_CFG_R13_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU5_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13End + */ +#define XDDR_XMPU5_CFG_R13_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU5_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13Mstr + */ +#define XDDR_XMPU5_CFG_R13_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU5_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13 + */ +#define XDDR_XMPU5_CFG_R13 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU5_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14Strt + */ +#define XDDR_XMPU5_CFG_R14_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU5_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14End + */ +#define XDDR_XMPU5_CFG_R14_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU5_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14Mstr + */ +#define XDDR_XMPU5_CFG_R14_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU5_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14 + */ +#define XDDR_XMPU5_CFG_R14 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU5_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15Strt + */ +#define XDDR_XMPU5_CFG_R15_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU5_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15End + */ +#define XDDR_XMPU5_CFG_R15_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU5_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15Mstr + */ +#define XDDR_XMPU5_CFG_R15_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU5_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15 + */ +#define XDDR_XMPU5_CFG_R15 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU5_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU5_CFG_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xdebug.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xdebug.h new file mode 100644 index 000000000..650946bd0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xdebug.h @@ -0,0 +1,32 @@ +#ifndef XDEBUG /* prevent circular inclusions */ +#define XDEBUG /* by using protection macros */ + +#if defined(DEBUG) && !defined(NDEBUG) + +#ifndef XDEBUG_WARNING +#define XDEBUG_WARNING +#warning DEBUG is enabled +#endif + +int printf(const char *format, ...); + +#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */ +#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */ +#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */ + +#define xdbg_current_types (XDBG_DEBUG_GENERAL) + +#define xdbg_stmnt(x) x + +#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) + + +#else /* defined(DEBUG) && !defined(NDEBUG) */ + +#define xdbg_stmnt(x) + +#define xdbg_printf(...) + +#endif /* defined(DEBUG) && !defined(NDEBUG) */ + +#endif /* XDEBUG */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps.h new file mode 100644 index 000000000..adb2f4b21 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps.h @@ -0,0 +1,783 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** + * + * @file xemacps.h + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not suppoted from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ *
+ * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001U +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002U +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004U +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020U +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040U +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400U +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800U +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U + +#define XEMACPS_DEFAULT_OPTIONS \ + ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ + (u32)XEMACPS_FCS_INSERT_OPTION | \ + (u32)XEMACPS_FCS_STRIP_OPTION | \ + (u32)XEMACPS_BROADCAST_OPTION | \ + (u32)XEMACPS_LENTYPE_ERR_OPTION | \ + (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ + (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1U +#define XEMACPS_HANDLER_DMARECV 2U +#define XEMACPS_HANDLER_ERROR 3U +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */ + +#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */ +#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ +#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 0x00000001 +#define XEMACPS_4BYTE_BURST 0x00000004 +#define XEMACPS_8BYTE_BURST 0x00000008 +#define XEMACPS_16BYTE_BURST 0x00000010 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * paramter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs_Instance { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + u32 Version; + u32 RxBufMask; + u32 MaxMtuSize; + u32 MaxFrameSize; + u32 MaxVlanFrameSize; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IER_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IDR_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/* + * Initialization functions in xemacps.c + */ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + UINTPTR EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction); + +/* + * Lookup configuration in xemacps_sinit.c + */ +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPointer, void *CallBackRef); +void XEmacPs_IntrHandler(void *XEmacPsPtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_bd.h new file mode 100644 index 000000000..41e0ab845 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_bd.h @@ -0,0 +1,799 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *
+ *
+ * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ +#ifdef __aarch64__ +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U +#else +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U +#endif + +/** + * The XEmacPs_Bd is the type for buffer descriptors (BDs). + */ +#define XEMACPS_BD_NUM_WORDS 2U +typedef UINTPTR XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * Zero out BD fields + * + * @param BdPtr is the BD pointer to operate on + * + * @return Nothing + * + * @note + * C-style signature: + * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClear(BdPtr) \ + memset((BdPtr), 0, sizeof(XEmacPs_Bd)) + +/****************************************************************************/ +/** +* +* Read the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to read +* @param Offset is the word offset to be read +* +* @return The 32-bit value of the field +* +* @note +* C-style signature: +* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset) +* +*****************************************************************************/ +#define XEmacPs_BdRead(BaseAddress, Offset) \ + (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset))) + +/****************************************************************************/ +/** +* +* Write the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to write +* @param Offset is the word offset to be written +* @param Data is the 32-bit value to write to the field +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data) +* +*****************************************************************************/ +#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ + (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data)) + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : + * + * C-style signature: + * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + (u32)((Addr) & ULONG64_LO_MASK)); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr)) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : Due to some bits are mixed within recevie BD's address field, + * read-modify-write is performed. + * + * C-style signature: + * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr))) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Status field (word 1). + * + * @param BdPtr is the BD pointer to operate on + * @param Data is the value to write to BD's status field. + * + * @note + * C-style signature: + * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data) + * + *****************************************************************************/ +#define XEmacPs_BdSetStatus(BdPtr, Data) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data)) + + +/*****************************************************************************/ +/** + * Retrieve the BD's Packet DMA transfer status word (word 1). + * + * @param BdPtr is the BD pointer to operate on + * + * @return Status word + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) + * + * Due to the BD bit layout differences in transmit and receive. User's + * caution is required. + *****************************************************************************/ +#define XEmacPs_BdGetStatus(BdPtr) \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) + + +/*****************************************************************************/ +/** + * Get the address (bits 0..31) of the BD's buffer address (word 0) + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U) +#else +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) +#endif + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + +/*****************************************************************************/ +/** + * Retrieve the BD length field. + * + * For Tx channels, the returned value is the same as that written with + * XEmacPs_BdSetLength(). + * + * For Rx channels, the returned value is the size of the received packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) + * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. + * + *****************************************************************************/ +#define XEmacPs_BdGetLength(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_LEN_MASK) + +/*****************************************************************************/ +/** + * Retrieve the RX frame size. + * + * The returned value is the size of the received packet. + * This API supports jumbo frame sizes if enabled. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr) + * RxBufMask is dependent on whether jumbo is enabled or not. + * + *****************************************************************************/ +#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + (InstancePtr)->RxBufMask) + +/*****************************************************************************/ +/** + * Test whether the given BD has been marked as the last BD of a packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsLast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the given transmit BD marks the end of the current + * packet to be processed. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the current packet does not end with the given + * BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Set this bit to mark the last descriptor in the receive buffer descriptor + * list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetRxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + XEMACPS_RXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the receive BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit to mark the last descriptor in the transmit buffer + * descriptor list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetTxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the transmit BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/* + * Must clear this bit to enable the MAC to write data to the receive + * buffer. Hardware sets this bit once it has successfully written a frame to + * memory. Once set, software has to clear the bit before the buffer can be + * used again. This macro clear the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearRxNew(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_NEW_MASK)) + + +/*****************************************************************************/ +/** + * Determine the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxNew(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Software sets this bit to disable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro sets this bit of transmit BD to avoid + * confusion. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Software clears this bit to enable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro clears this bit of transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Determine the used bit of the transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUsed(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to too many retries. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxRetry(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to data can not be + * feteched in time or buffers are exhausted. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUrun(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to buffer is exhausted + * mid-frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxExh(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit, no CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Clear this bit, CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Determine the broadcast bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxBcast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the multicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxMultiHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the unicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxUniHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame is a VLAN Tagged frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxVlan(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame has Type ID of 8100h and null VLAN + * identifier(Priority tag). + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxPri(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame's Concatenation Format Indicator (CFI) of + * the frames VLANTCI field was set. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxCFI(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the End Of Frame (EOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxEOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the Start Of Frame (SOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxSOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE) + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_bdring.h new file mode 100644 index 000000000..b678c5401 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_bdring.h @@ -0,0 +1,235 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_bdring.h +* +* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs +* DMA functionalities. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+* +******************************************************************************/ + +#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */ +#define XEMACPS_BDRING_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/**************************** Type Definitions *******************************/ + +/** This is an internal structure used to maintain the DMA list */ +typedef struct { + UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */ + UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */ + UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */ + u32 Length; /**< Total size of ring in bytes */ + u32 RunState; /**< Flag to indicate DMA is started */ + u32 Separation; /**< Number of bytes between the starting address + of adjacent BDs */ + XEmacPs_Bd *FreeHead; + /**< First BD in the free group */ + XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */ + XEmacPs_Bd *HwHead; /**< First BD in the work group */ + XEmacPs_Bd *HwTail; /**< Last BD in the work group */ + XEmacPs_Bd *PostHead; + /**< First BD in the post-work group */ + XEmacPs_Bd *BdaRestart; + /**< BDA to load when channel is started */ + + u32 HwCnt; /**< Number of BDs in work group */ + u32 PreCnt; /**< Number of BDs in pre-work group */ + u32 FreeCnt; /**< Number of allocatable BDs in the free group */ + u32 PostCnt; /**< Number of BDs in post-work group */ + u32 AllCnt; /**< Total Number of BDs for channel */ +} XEmacPs_BdRing; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many BDs will fit +* in a BD list within the given memory constraints. +* +* The results of this macro can be provided to XEmacPs_BdRingCreate(). +* +* @param Alignment specifies what byte alignment the BDs must fall on and +* must be a power of 2 to get an accurate calculation (32, 64, 128,...) +* @param Bytes is the number of bytes to be used to store BDs. +* +* @return Number of BDs that can fit in the given memory area +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes) +* +******************************************************************************/ +#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \ + (u32)((Bytes) / (sizeof(XEmacPs_Bd))) + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many bytes of memory +* is required to contain a given number of BDs at a given alignment. +* +* @param Alignment specifies what byte alignment the BDs must fall on. This +* parameter must be a power of 2 to get an accurate calculation (32, 64, +* 128,...) +* @param NumBd is the number of BDs to calculate memory size requirements for +* +* @return The number of bytes of memory required to create a BD list with the +* given memory constraints. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd) +* +******************************************************************************/ +#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \ + (u32)(sizeof(XEmacPs_Bd) * (NumBd)) + +/****************************************************************************/ +/** +* Return the total number of BDs allocated by this channel with +* XEmacPs_BdRingCreate(). +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The total number of BDs allocated for this channel. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt) + +/****************************************************************************/ +/** +* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre- +* processing. +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The number of BDs currently allocatable. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt) + +/****************************************************************************/ +/** +* Return the next BD from BdPtr in a list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on. +* +* @return The next BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingNext(RingPtr, BdPtr) \ + (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \ + (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \ + (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation)) + +/****************************************************************************/ +/** +* Return the previous BD from BdPtr in the list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on +* +* @return The previous BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \ + (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \ + (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \ + (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation)) + +/************************** Function Prototypes ******************************/ + +/* + * Scatter gather DMA related functions in xemacps_bdring.c + */ +LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, u32 BdCount); +LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction); +LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd ** BdSetPtr); +LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit, + XEmacPs_Bd ** BdSetPtr); +u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit, + XEmacPs_Bd ** BdSetPtr); +LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); + + +#ifdef __cplusplus +} +#endif + + +#endif /* end of protection macros */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_hw.h new file mode 100644 index 000000000..4b8f582ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_hw.h @@ -0,0 +1,647 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_hw.h +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device. +* High-level driver functions are defined in xemacps.h. +* +* @note +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+*
+* +******************************************************************************/ + +#ifndef XEMACPS_HW_H /* prevent circular inclusions */ +#define XEMACPS_HW_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address + supported */ +#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */ + +#ifdef __aarch64__ +#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment + on the local bus */ +#else + +#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment + on the local bus */ +#endif +#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using + options that impose alignment + restrictions on the buffer data on + the local bus */ + +/** @name Direction identifiers + * + * These are used by several functions and callbacks that need + * to specify whether an operation specifies a send or receive channel. + * @{ + */ +#define XEMACPS_SEND 1U /**< send direction */ +#define XEMACPS_RECV 2U /**< receive direction */ +/*@}*/ + +/** @name MDC clock division + * currently supporting 8, 16, 32, 48, 64, 96, 128, 224. + * @{ + */ +typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, + MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224 +} XEmacPs_MdcDiv; + +/*@}*/ + +#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in + bytes, 64, 128, ... 10240 */ +#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U + +#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a + unit, this is HW setup */ + +#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */ +#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */ + +#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */ + +/* Register offset definitions. Unless otherwise noted, register access is + * 32 bit. Names are self explained here. + */ + +#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */ +#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */ +#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */ + +#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */ +#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */ +#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */ +#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */ +#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */ + +#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */ +#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */ +#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */ +#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */ + +#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */ +#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */ +#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */ + +#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */ + +#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */ +#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */ + +#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */ +#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */ +#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */ +#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */ +#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */ +#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */ +#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */ +#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */ + +#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */ +#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */ +#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */ +#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */ + +#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */ + +#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low + reg */ +#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High + reg */ + +#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes + transmitted counter */ +#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast + Frames counter*/ +#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast + Frame counter */ +#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted + Counter */ +#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames + Transmitted counter */ +#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte + Frames Transmitted + counter */ +#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte + Frames Transmitted + counter*/ +#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte + Frames transmitted + counter */ +#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte + Frames transmitted + counter */ +#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte + Frames transmitted + counter */ +#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than + 1519 byte Frames + transmitted counter */ +#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error + counter */ + +#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame + Counter */ +#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame + Counter */ +#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame + Counter */ +#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame + Counter */ +#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission + Frame Counter */ +#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense + Error Counter */ + +#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register + Low */ +#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register + High */ + +#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames + Received Counter */ +#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast + Frames Received Counter */ +#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast + Frames Received Counter */ +#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames + Received Counter */ +#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames + Received Counter */ +#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte + Frames Received Counter */ +#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte + Frames Received Counter */ +#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte + Frames Received Counter */ +#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte + Frames Received Counter */ +#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte + Frames Received Counter */ +#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte + Frames Received Counter */ +#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received + Counter */ +#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received + Counter */ +#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received + Counter */ +#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence + Error Counter */ +#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error + Counter */ +#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */ +#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */ +#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error + Counter */ +#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */ +#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error + Counter */ +#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error + Counter */ +#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error + Counter */ +#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter + offset, for clearing */ + +#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */ +#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */ +#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond + adjustment counter */ +#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond + increment counter */ +#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second + counter */ +#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit + nanosecond counter */ +#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second + counter */ +#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive + nanosecond counter */ +#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit + second counter */ +#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit + nanosecond counter */ +#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive + second counter */ +#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive + nanosecond counter */ + +#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status + reg */ +#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address + reg */ +#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address + reg */ +#define XEMACPS_MSBBUF_QBASE_OFFSET 0x000004C8U /**< MSB Buffer Q Base + reg */ +#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable + reg */ +#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable + reg */ +#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask + reg */ + +/* Define some bit positions for registers. */ + +/** @name network control register bit definitions + * @{ + */ +#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from + Rx SRAM */ +#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum + pause frame */ +#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */ +#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission + after current frame */ +#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */ + +#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to + stat counters */ +#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic + registers */ +#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic + registers */ +#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */ +#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */ +#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */ +#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */ +/*@}*/ + +/** @name network configuration register bit definitions + * @{ + */ +#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of + non-standard preamble */ +#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */ +#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of + FCS error */ +#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */ +#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum + offload */ +#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause + Frames to memory */ +#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */ +#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */ +#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */ +#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from + received frames */ +#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U +/**< RX length error discard */ +#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */ +#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */ +#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */ +#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U +/**< External address match enable */ +#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */ +#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte + frames reception */ +#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash + frames */ +#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash + frames */ +#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive + broadcast frames */ +#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */ +#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */ +#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN + frames */ +#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */ +#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */ +#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */ +/*@}*/ + +/** @name network status register bit definitaions + * @{ + */ +#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */ +#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */ +/*@}*/ + + +/** @name MAC address register word 1 mask + * @{ + */ +#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32] + bit[31:0] are in BOTTOM */ +/*@}*/ + + +/** @name DMA control register bit definitions + * @{ + */ +#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */ +#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */ +#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */ +#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer + size */ +#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer + size */ +#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX + checksum offload */ +#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */ +#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */ +#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */ +#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */ +#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */ +#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */ +/*@}*/ + +/** @name transmit status register bit definitions + * @{ + */ +#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */ +#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */ +#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */ +#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted + mid frame */ +#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */ +#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */ +#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */ +#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */ + +#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \ + (u32)XEMACPS_TXSR_URUN_MASK | \ + (u32)XEMACPS_TXSR_BUFEXH_MASK | \ + (u32)XEMACPS_TXSR_RXOVR_MASK | \ + (u32)XEMACPS_TXSR_FRAMERX_MASK | \ + (u32)XEMACPS_TXSR_USEDREAD_MASK) +/*@}*/ + +/** + * @name receive status register bit definitions + * @{ + */ +#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */ +#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */ +#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */ +#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */ + +#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \ + (u32)XEMACPS_RXSR_RXOVR_MASK | \ + (u32)XEMACPS_RXSR_BUFFNA_MASK) +/*@}*/ + +/** + * @name Interrupt Q1 status register bit definitions + * @{ + */ +#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */ +#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */ + +#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \ + (u32)XEMACPS_INTQ1SR_TXERR_MASK) + +/*@}*/ + +/** + * @name interrupts bit definitions + * Bits definitions are same in XEMACPS_ISR_OFFSET, + * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET + * @{ + */ +#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */ +#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req + transmitted */ +#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */ +#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted + */ +#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */ +#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */ +#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */ +#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */ +#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */ +#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached + zero */ +#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */ +#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */ +#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */ +#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */ +#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or + no buffers*/ +#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */ +#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */ +#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */ +#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */ +#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */ +#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */ +#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */ + +#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \ + (u32)XEMACPS_IXR_RETRY_MASK | \ + (u32)XEMACPS_IXR_URUN_MASK) + + +#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \ + (u32)XEMACPS_IXR_RXUSED_MASK | \ + (u32)XEMACPS_IXR_RXOVR_MASK) + +/*@}*/ + +/** @name PHY Maintenance bit definitions + * @{ + */ +#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */ +#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */ +#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */ +#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */ +#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */ +#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */ +#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */ +#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */ +/*@}*/ + +/* Transmit buffer descriptor status words offset + * @{ + */ +#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */ +#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */ +#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */ + +/* + * @} + */ + +/* Transmit buffer descriptor status words bit positions. + * Transmit buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit address pointing to the location of + * the transmit data. + * The following register - word1, consists of various information to control + * the XEmacPs transmit process. After transmit, this is updated with status + * information, whether the frame was transmitted OK or why it had failed. + * @{ + */ +#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */ +#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */ +#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */ +#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */ +#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */ +#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */ +#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */ +#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */ +#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */ +/* + * @} + */ + +/* Receive buffer descriptor status words bit positions. + * Receive buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit word aligned address pointing to the + * address of the buffer. The lower two bits make up the wrap bit indicating + * the last descriptor and the ownership bit to indicate it has been used by + * the XEmacPs. + * The following register - word1, contains status information regarding why + * the frame was received (the filter match condition) as well as other + * useful info. + * @{ + */ +#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */ +#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */ +#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */ +#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */ +#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address + matched */ +#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */ +#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */ +#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */ +#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */ +#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */ +#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */ +#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */ +#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */ +#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */ +#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */ + +#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */ +#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */ +#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */ +/* + * @} + */ + +/* + * Define appropriate I/O access method to memory mapped I/O or other + * interface if necessary. + */ + +#define XEmacPs_In32 Xil_In32 +#define XEmacPs_Out32 Xil_Out32 + + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XEmacPs_ReadReg(BaseAddress, RegOffset) \ + XEmacPs_In32((BaseAddress) + (u32)(RegOffset)) + + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \ + XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the emacps interface + */ +void XEmacPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus + } +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xenv.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xenv.h new file mode 100644 index 000000000..c2f76ee26 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xenv.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv.h +* +* Defines common services that are typically found in a host operating. +* environment. This include file simply includes an OS specific file based +* on the compile-time constant BUILD_ENV_*, where * is the name of the target +* environment. +* +* All services are defined as macros. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+*
+* +******************************************************************************/ + +#ifndef XENV_H /* prevent circular inclusions */ +#define XENV_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Select which target environment we are operating under + */ + +/* VxWorks target environment */ +#if defined XENV_VXWORKS +#include "xenv_vxworks.h" + +/* Linux target environment */ +#elif defined XENV_LINUX +#include "xenv_linux.h" + +/* Unit test environment */ +#elif defined XENV_UNITTEST +#include "ut_xenv.h" + +/* Integration test environment */ +#elif defined XENV_INTTEST +#include "int_xenv.h" + +/* Standalone environment selected */ +#else +#include "xenv_standalone.h" +#endif + + +/* + * The following comments specify the types and macro wrappers that are + * expected to be defined by the target specific header files + */ + +/**************************** Type Definitions *******************************/ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP + * + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes) + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr is the destination address to copy data to. + * @param SrcPtr is the source address to copy data from. + * @param Bytes is the number of bytes to copy. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes) + * + * Fills an area of memory with constant data. + * + * @param DestPtr is the destination address to set. + * @param Data contains the value to set. + * @param Bytes is the number of bytes to set. + * + * @return None + */ +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + * + * Samples the processor's or external timer's time base counter. + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of microseconds. + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of milliseconds. + */ + +/*****************************************************************************//** + * + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. + * + * @param delay is the number of microseconds to delay. + * + * @return None + */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xenv_standalone.h new file mode 100644 index 000000000..edab9db71 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xenv_standalone.h @@ -0,0 +1,368 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv_standalone.h +* +* Defines common services specified by xenv.h. +* +* @note +* This file is not intended to be included directly by driver code. +* Instead, the generic xenv.h file is intended to be included by driver +* code. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+*
+* +* +******************************************************************************/ + +#ifndef XENV_STANDALONE_H +#define XENV_STANDALONE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +/****************************************************************************** + * + * Get the processor dependent includes + * + ******************************************************************************/ + +#include + +#if defined __MICROBLAZE__ +# include "mb_interface.h" +# include "xparameters.h" /* XPAR constants used below in MB section */ + +#elif defined __PPC__ +# include "sleep.h" +# include "xcache_l.h" /* also include xcache_l.h for caching macros */ +#endif + +/****************************************************************************** + * + * MEMCPY / MEMSET related macros. + * + * The following are straight forward implementations of memset and memcpy. + * + * NOTE: memcpy may not work if source and target memory area are overlapping. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param SrcPtr + * Source address to copy data from. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead. + * + * @note + * This implemention MAY BREAK work if source and target memory + * area are overlapping. + * + *****************************************************************************/ + +#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ + memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) + + + +/*****************************************************************************/ +/** + * + * Fills an area of memory with constant data. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param Data + * Value to set. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_FILL is deprecated. Use memset() instead. + * + *****************************************************************************/ + +#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ + memset((void *) DestPtr, (s32) Data, (size_t) Bytes) + + + +/****************************************************************************** + * + * TIME related macros + * + ******************************************************************************/ + +/** + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ +typedef s32 XENV_TIME_STAMP; + +/*****************************************************************************/ +/** + * + * Time is derived from the 64 bit PPC timebase register + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None. + * + * @note + * + * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + *

+ * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_GET(StampPtr) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. Not implemented without OS + * support. + * + * @param delay + * Number of microseconds to delay. + * + * @return None. + * + *****************************************************************************/ + +#ifdef __PPC__ +#define XENV_USLEEP(delay) usleep(delay) +#define udelay(delay) usleep(delay) +#else +#define XENV_USLEEP(delay) +#define udelay(delay) +#endif + + +/****************************************************************************** + * + * CACHE handling macros / mappings + * + ******************************************************************************/ +/****************************************************************************** + * + * Processor independent macros + * + ******************************************************************************/ + +#define XCACHE_ENABLE_CACHE() \ + { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } + +#define XCACHE_DISABLE_CACHE() \ + { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } + + +/****************************************************************************** + * + * MicroBlaze case + * + * NOTE: Currently the following macros will only work on systems that contain + * only ONE MicroBlaze processor. Also, the macros will only be enabled if the + * system is built using a xparameters.h file. + * + ******************************************************************************/ + +#if defined __MICROBLAZE__ + +/* Check if MicroBlaze data cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_DCACHE == 1) +# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache() +# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache() +# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() + +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) + +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_flush_dcache_range((s32)(Addr), (s32)(Len)) +#else +# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) +#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ + +#else +# define XCACHE_ENABLE_DCACHE() +# define XCACHE_DISABLE_DCACHE() +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) +#endif /*XPAR_MICROBLAZE_USE_DCACHE*/ + + +/* Check if MicroBlaze instruction cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_ICACHE == 1) +# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache() +# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache() + +# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() + +# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ + microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len)) + +#else +# define XCACHE_ENABLE_ICACHE() +# define XCACHE_DISABLE_ICACHE() +#endif /*XPAR_MICROBLAZE_USE_ICACHE*/ + + +/****************************************************************************** + * + * PowerPC case + * + * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a + * specific memory region (0x80000001). Each bit (0-30) in the regions + * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB + * range. + * + * regions --> cached address range + * ------------|-------------------------------------------------- + * 0x80000000 | [0, 0x7FFFFFF] + * 0x00000001 | [0xF8000000, 0xFFFFFFFF] + * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF] + * + ******************************************************************************/ + +#elif defined __PPC__ + +#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001) +#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache() +#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001) +#define XCACHE_DISABLE_ICACHE() XCache_DisableICache() + +#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + XCache_FlushDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() + + +/****************************************************************************** + * + * Unknown processor / architecture + * + ******************************************************************************/ + +#else +/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef XENV_STANDALONE_H */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_slcr.h new file mode 100644 index 000000000..b565b958a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_slcr.h @@ -0,0 +1,382 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_SLCR_H__ +#define __XFPD_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdSlcr Base Address + */ +#define XFPD_SLCR_BASEADDR 0xFD610000UL + +/** + * Register: XfpdSlcrWprot0 + */ +#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL ) +#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL + +#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL +#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL +#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL +#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrCtrl + */ +#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL ) +#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIsr + */ +#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL ) +#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrImr + */ +#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL + +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrIer + */ +#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL ) +#define XFPD_SLCR_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIdr + */ +#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL ) +#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrItr + */ +#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL ) +#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrWdtClkSel + */ +#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL ) +#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL +#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL +#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL +#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIntFpd + */ +#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL ) +#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL + +#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrGpu + */ +#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL ) +#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL + +#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL +#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL +#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL +#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL + +#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL +#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL +#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL +#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL + +#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL +#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL +#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL + +#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL +#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL +#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL + +#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL +#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL +#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrGdmaCfg + */ +#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL ) +#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL + +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL + +#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL + +/** + * Register: XfpdSlcrGdma + */ +#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL ) +#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL + +#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL + +#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL + +#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL + +/** + * Register: XfpdSlcrAfiFs + */ +#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL ) +#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL + +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL + +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL + +/** + * Register: XfpdSlcrErrAtbIsr + */ +#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL ) +#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrErrAtbImr + */ +#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL ) +#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrErrAtbIer + */ +#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL ) +#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrErrAtbIdr + */ +#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL ) +#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrAtbCmdstore + */ +#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL ) +#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrAtbRespEn + */ +#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL ) +#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrAtbResptype + */ +#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL ) +#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrAtbPrescale + */ +#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL ) +#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL + +#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL +#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL +#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL +#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL +#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL +#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL +#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_SLCR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_slcr_secure.h new file mode 100644 index 000000000..6541a4f1d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_slcr_secure.h @@ -0,0 +1,277 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_SLCR_SECURE_H__ +#define __XFPD_SLCR_SECURE_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdSlcrSecure Base Address + */ +#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL + +/** + * Register: XfpdSlcrSecCtrl + */ +#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) +#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecIsr + */ +#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) +#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecImr + */ +#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) +#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL + +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecIer + */ +#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) +#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecIdr + */ +#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) +#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecItr + */ +#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) +#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecSata + */ +#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) +#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecPcie + */ +#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) +#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecDpdma + */ +#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL ) +#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL + +#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL +#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL +#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL +#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecGdma + */ +#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL ) +#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL + +#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL +#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL +#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL +#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL + +/** + * Register: XfpdSlcrSecGic + */ +#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL ) +#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_SLCR_SECURE_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_xmpu_cfg.h new file mode 100644 index 000000000..75aef19f9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_xmpu_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_XMPU_CFG_H__ +#define __XFPD_XMPU_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdXmpuCfg Base Address + */ +#define XFPD_XMPU_CFG_BASEADDR 0xFD5D0000UL + +/** + * Register: XfpdXmpuCfgCtrl + */ +#define XFPD_XMPU_CFG_CTRL ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000000UL ) +#define XFPD_XMPU_CFG_CTRL_RSTVAL 0x00000003UL + +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuCfgErrSts1 + */ +#define XFPD_XMPU_CFG_ERR_STS1 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000004UL ) +#define XFPD_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgErrSts2 + */ +#define XFPD_XMPU_CFG_ERR_STS2 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000008UL ) +#define XFPD_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgPoison + */ +#define XFPD_XMPU_CFG_POISON ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) +#define XFPD_XMPU_CFG_POISON_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_POISON_BASE_SHIFT 0UL +#define XFPD_XMPU_CFG_POISON_BASE_WIDTH 20UL +#define XFPD_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL +#define XFPD_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgIsr + */ +#define XFPD_XMPU_CFG_ISR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000010UL ) +#define XFPD_XMPU_CFG_ISR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_ISR_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgImr + */ +#define XFPD_XMPU_CFG_IMR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000014UL ) +#define XFPD_XMPU_CFG_IMR_RSTVAL 0x0000000fUL + +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IMR_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuCfgIen + */ +#define XFPD_XMPU_CFG_IEN ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000018UL ) +#define XFPD_XMPU_CFG_IEN_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IEN_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgIds + */ +#define XFPD_XMPU_CFG_IDS ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) +#define XFPD_XMPU_CFG_IDS_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IDS_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgLock + */ +#define XFPD_XMPU_CFG_LOCK ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000020UL ) +#define XFPD_XMPU_CFG_LOCK_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00Strt + */ +#define XFPD_XMPU_CFG_R00_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000100UL ) +#define XFPD_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00End + */ +#define XFPD_XMPU_CFG_R00_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000104UL ) +#define XFPD_XMPU_CFG_R00_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00Mstr + */ +#define XFPD_XMPU_CFG_R00_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000108UL ) +#define XFPD_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00 + */ +#define XFPD_XMPU_CFG_R00 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) +#define XFPD_XMPU_CFG_R00_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R00_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R00_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R00_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R00_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01Strt + */ +#define XFPD_XMPU_CFG_R01_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000110UL ) +#define XFPD_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01End + */ +#define XFPD_XMPU_CFG_R01_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000114UL ) +#define XFPD_XMPU_CFG_R01_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01Mstr + */ +#define XFPD_XMPU_CFG_R01_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000118UL ) +#define XFPD_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01 + */ +#define XFPD_XMPU_CFG_R01 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) +#define XFPD_XMPU_CFG_R01_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R01_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R01_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R01_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R01_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02Strt + */ +#define XFPD_XMPU_CFG_R02_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000120UL ) +#define XFPD_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02End + */ +#define XFPD_XMPU_CFG_R02_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000124UL ) +#define XFPD_XMPU_CFG_R02_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02Mstr + */ +#define XFPD_XMPU_CFG_R02_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000128UL ) +#define XFPD_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02 + */ +#define XFPD_XMPU_CFG_R02 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) +#define XFPD_XMPU_CFG_R02_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R02_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R02_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R02_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R02_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03Strt + */ +#define XFPD_XMPU_CFG_R03_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000130UL ) +#define XFPD_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03End + */ +#define XFPD_XMPU_CFG_R03_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000134UL ) +#define XFPD_XMPU_CFG_R03_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03Mstr + */ +#define XFPD_XMPU_CFG_R03_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000138UL ) +#define XFPD_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03 + */ +#define XFPD_XMPU_CFG_R03 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) +#define XFPD_XMPU_CFG_R03_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R03_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R03_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R03_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R03_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04Strt + */ +#define XFPD_XMPU_CFG_R04_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000140UL ) +#define XFPD_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04End + */ +#define XFPD_XMPU_CFG_R04_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000144UL ) +#define XFPD_XMPU_CFG_R04_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04Mstr + */ +#define XFPD_XMPU_CFG_R04_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000148UL ) +#define XFPD_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04 + */ +#define XFPD_XMPU_CFG_R04 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) +#define XFPD_XMPU_CFG_R04_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R04_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R04_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R04_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R04_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05Strt + */ +#define XFPD_XMPU_CFG_R05_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000150UL ) +#define XFPD_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05End + */ +#define XFPD_XMPU_CFG_R05_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000154UL ) +#define XFPD_XMPU_CFG_R05_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05Mstr + */ +#define XFPD_XMPU_CFG_R05_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000158UL ) +#define XFPD_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05 + */ +#define XFPD_XMPU_CFG_R05 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) +#define XFPD_XMPU_CFG_R05_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R05_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R05_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R05_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R05_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06Strt + */ +#define XFPD_XMPU_CFG_R06_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000160UL ) +#define XFPD_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06End + */ +#define XFPD_XMPU_CFG_R06_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000164UL ) +#define XFPD_XMPU_CFG_R06_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06Mstr + */ +#define XFPD_XMPU_CFG_R06_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000168UL ) +#define XFPD_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06 + */ +#define XFPD_XMPU_CFG_R06 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) +#define XFPD_XMPU_CFG_R06_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R06_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R06_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R06_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R06_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07Strt + */ +#define XFPD_XMPU_CFG_R07_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000170UL ) +#define XFPD_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07End + */ +#define XFPD_XMPU_CFG_R07_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000174UL ) +#define XFPD_XMPU_CFG_R07_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07Mstr + */ +#define XFPD_XMPU_CFG_R07_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000178UL ) +#define XFPD_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07 + */ +#define XFPD_XMPU_CFG_R07 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) +#define XFPD_XMPU_CFG_R07_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R07_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R07_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R07_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R07_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08Strt + */ +#define XFPD_XMPU_CFG_R08_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000180UL ) +#define XFPD_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08End + */ +#define XFPD_XMPU_CFG_R08_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000184UL ) +#define XFPD_XMPU_CFG_R08_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08Mstr + */ +#define XFPD_XMPU_CFG_R08_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000188UL ) +#define XFPD_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08 + */ +#define XFPD_XMPU_CFG_R08 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) +#define XFPD_XMPU_CFG_R08_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R08_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R08_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R08_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R08_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09Strt + */ +#define XFPD_XMPU_CFG_R09_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000190UL ) +#define XFPD_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09End + */ +#define XFPD_XMPU_CFG_R09_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000194UL ) +#define XFPD_XMPU_CFG_R09_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09Mstr + */ +#define XFPD_XMPU_CFG_R09_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000198UL ) +#define XFPD_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09 + */ +#define XFPD_XMPU_CFG_R09 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) +#define XFPD_XMPU_CFG_R09_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R09_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R09_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R09_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R09_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10Strt + */ +#define XFPD_XMPU_CFG_R10_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) +#define XFPD_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10End + */ +#define XFPD_XMPU_CFG_R10_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) +#define XFPD_XMPU_CFG_R10_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10Mstr + */ +#define XFPD_XMPU_CFG_R10_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) +#define XFPD_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10 + */ +#define XFPD_XMPU_CFG_R10 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) +#define XFPD_XMPU_CFG_R10_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R10_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R10_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R10_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R10_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11Strt + */ +#define XFPD_XMPU_CFG_R11_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) +#define XFPD_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11End + */ +#define XFPD_XMPU_CFG_R11_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) +#define XFPD_XMPU_CFG_R11_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11Mstr + */ +#define XFPD_XMPU_CFG_R11_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) +#define XFPD_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11 + */ +#define XFPD_XMPU_CFG_R11 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) +#define XFPD_XMPU_CFG_R11_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R11_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R11_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R11_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R11_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12Strt + */ +#define XFPD_XMPU_CFG_R12_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) +#define XFPD_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12End + */ +#define XFPD_XMPU_CFG_R12_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) +#define XFPD_XMPU_CFG_R12_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12Mstr + */ +#define XFPD_XMPU_CFG_R12_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) +#define XFPD_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12 + */ +#define XFPD_XMPU_CFG_R12 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) +#define XFPD_XMPU_CFG_R12_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R12_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R12_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R12_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R12_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13Strt + */ +#define XFPD_XMPU_CFG_R13_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) +#define XFPD_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13End + */ +#define XFPD_XMPU_CFG_R13_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) +#define XFPD_XMPU_CFG_R13_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13Mstr + */ +#define XFPD_XMPU_CFG_R13_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) +#define XFPD_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13 + */ +#define XFPD_XMPU_CFG_R13 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) +#define XFPD_XMPU_CFG_R13_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R13_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R13_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R13_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R13_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14Strt + */ +#define XFPD_XMPU_CFG_R14_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) +#define XFPD_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14End + */ +#define XFPD_XMPU_CFG_R14_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) +#define XFPD_XMPU_CFG_R14_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14Mstr + */ +#define XFPD_XMPU_CFG_R14_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) +#define XFPD_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14 + */ +#define XFPD_XMPU_CFG_R14 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) +#define XFPD_XMPU_CFG_R14_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R14_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R14_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R14_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R14_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15Strt + */ +#define XFPD_XMPU_CFG_R15_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) +#define XFPD_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15End + */ +#define XFPD_XMPU_CFG_R15_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) +#define XFPD_XMPU_CFG_R15_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15Mstr + */ +#define XFPD_XMPU_CFG_R15_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) +#define XFPD_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15 + */ +#define XFPD_XMPU_CFG_R15 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) +#define XFPD_XMPU_CFG_R15_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R15_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R15_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R15_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R15_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_XMPU_CFG_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_xmpu_sink.h new file mode 100644 index 000000000..39172f1f4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_xmpu_sink.h @@ -0,0 +1,81 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_XMPU_SINK_H__ +#define __XFPD_XMPU_SINK_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdXmpuSink Base Address + */ +#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL + +/** + * Register: XfpdXmpuSinkErrSts + */ +#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL ) +#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL + +#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkIsr + */ +#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL ) +#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkImr + */ +#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL ) +#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL + +#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuSinkIer + */ +#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL ) +#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkIdr + */ +#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL ) +#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_XMPU_SINK_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xgpiops.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xgpiops.h new file mode 100644 index 000000000..ef9a7f05a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xgpiops.h @@ -0,0 +1,277 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xgpiops.h +* +* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO +* Controller. +* +* The GPIO Controller supports the following features: +* - 4 banks +* - Masked writes (There are no masked reads) +* - Bypass mode +* - Configurable Interrupts (Level/Edge) +* +* This driver is intended to be RTOS and processor independent. Any needs for +* dynamic memory management, threads or thread mutual exclusion, virtual +* memory, or cache control must be satisfied by the layer above this driver. + +* This driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the GPIO. +* +* Interrupts +* +* The driver provides interrupt management functions and an interrupt handler. +* Users of this driver need to provide callback functions. An interrupt handler +* example is available with the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XGpioPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+* +******************************************************************************/ +#ifndef XGPIOPS_H /* prevent circular inclusions */ +#define XGPIOPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xgpiops_hw.h" + +/************************** Constant Definitions *****************************/ + +/** @name Interrupt types + * @{ + * The following constants define the interrupt types that can be set for each + * GPIO pin. + */ +#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */ +#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */ +#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */ +/*@}*/ + +#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */ +#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */ +#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */ +#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */ + +#ifdef XPAR_PSU_GPIO_0_BASEADDR +#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */ +#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */ + +#define XGPIOPS_MAX_BANKS 0x06U /**< Max banks in a GPIO device */ +#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */ + +#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)174 /*< Max pins in the ZynqMP GPIO device + * 0 - 25, Bank 0 + * 26 - 51, Bank 1 + * 52 - 77, Bank 2 + * 78 - 109, Bank 3 + * 110 - 141, Bank 4 + * 142 - 173, Bank 5 + */ +#else + +#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a GPIO device */ +#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */ + +#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /*< Max pins in the GPIO device + * 0 - 31, Bank 0 + * 32 - 53, Bank 1 + * 54 - 85, Bank 2 + * 86 - 117, Bank 3 + */ + + +#endif +/**************************** Type Definitions *******************************/ + +/****************************************************************************/ +/** + * This handler data type allows the user to define a callback function to + * handle the interrupts for the GPIO device. The application using this + * driver is expected to define a handler of this type, to support interrupt + * driven mode. The handler executes in an interrupt context such that minimal + * processing should be performed. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions for a GPIO bank. It is + * passed back to the upper layer when the callback is invoked. Its + * type is not important to the driver component, so it is a void + * pointer. + * @param Bank is the bank for which the interrupt status has changed. + * @param Status is the Interrupt status of the GPIO bank. + * + *****************************************************************************/ +typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status); + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XGpioPs_Config; + +/** + * The XGpioPs driver instance data. The user is required to allocate a + * variable of this type for the GPIO device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XGpioPs_Config GpioConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + XGpioPs_Handler Handler; /**< Status handlers for all banks */ + void *CallBackRef; /**< Callback ref for bank handlers */ +} XGpioPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xgpiops.c + */ +s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, + u32 EffectiveAddr); + +/* + * Bank APIs in xgpiops.c + */ +u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data); +void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction); +u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable); +u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank); + +/* + * Pin APIs in xgpiops.c + */ +u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data); +void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction); +u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable); +u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin); + +/* + * Diagnostic functions in xgpiops_selftest.c + */ +s32 XGpioPs_SelfTest(XGpioPs *InstancePtr); + +/* + * Functions in xgpiops_intr.c + */ +/* + * Bank APIs in xgpiops_intr.c + */ +void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank); +u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType, + u32 IntrPolarity, u32 IntrOnAny); +void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, + u32 *IntrPolarity, u32 *IntrOnAny); +void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, + XGpioPs_Handler FuncPointer); +void XGpioPs_IntrHandler(XGpioPs *InstancePtr); + +/* + * Pin APIs in xgpiops_intr.c + */ +void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType); +u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin); + +void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin); + +/* + * Functions in xgpiops_sinit.c + */ +XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xgpiops_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xgpiops_hw.h new file mode 100644 index 000000000..2f4ea8041 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xgpiops_hw.h @@ -0,0 +1,161 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xgpiops_hw.h +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xgpiops.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ +#ifndef XGPIOPS_HW_H /* prevent circular inclusions */ +#define XGPIOPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the GPIO. Each register is 32 bits. + * @{ + */ +#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */ +#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */ +#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */ +#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */ +#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */ +#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */ +#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */ +#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */ +#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/ +#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */ +#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */ +#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */ +#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */ +/* @} */ + +/** @name Register offsets for each Bank. + * @{ + */ +#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */ +#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */ +#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */ +/* @} */ + +/* For backwards compatibility */ +#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 + +/** @name Interrupt type reset values for each bank + * @{ + */ +#ifdef XPAR_PSU_GPIO_0_BASEADDR +#define XGPIOPS_INTTYPE_BANK0_RESET 0x3FFFFFFFU +#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFFU +#define XGPIOPS_INTTYPE_BANK2_RESET 0x3FFFFFFFU +#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU +#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU +#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU +#else + +#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU +#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFFU +#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU +#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU +#endif +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + +/****************************************************************************/ +/** +* +* This macro writes to the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the offset of the register to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ + +void XGpioPs_ResetHw(u32 BaseAddress); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XGPIOPS_HW_H */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiicps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiicps.h new file mode 100644 index 000000000..9c6dc10eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiicps.h @@ -0,0 +1,416 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xiicps.h +* +* This is an implementation of IIC driver in the PS block. The device can +* be either a master or a slave on the IIC bus. This implementation supports +* both interrupt mode transfer and polled mode transfer. Only 7-bit address +* is used in the driver, although the hardware also supports 10-bit address. +* +* IIC is a 2-wire serial interface. The master controls the clock, so it can +* regulate when it wants to send or receive data. The slave is under control of +* the master, it must respond quickly since it has no control of the clock and +* must send/receive data as fast or as slow as the master does. +* +* The higher level software must implement a higher layer protocol to inform +* the slave what to send to the master. +* +* Initialization & Configuration +* +* The XIicPs_Config structure is used by the driver to configure itself. This +* configuration structure is typically created by the tool-chain based on HW +* build properties. +* +* To support multiple runtime loading and initialization strategies employed by +* various operating systems, the driver instance can be initialized in the +* following way: +* +* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find +* the static configuration structure defined in xiicps_g.c. This is +* setup by the tools. For some operating systems the config structure +* will be initialized by the software and this call is not needed. +* +* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a +* system with address translation, the provided virtual memory base +* address replaces the physical address in the configuration +* structure. +* +* Multiple Masters +* +* More than one master can exist, bus arbitration is defined in the IIC +* standard. Lost of arbitration causes arbitration loss interrupt on the device. +* +* Multiple Slaves +* +* Multiple slaves are supported by selecting them with unique addresses. It is +* up to the system designer to be sure all devices on the IIC bus have +* unique addresses. +* +* Addressing +* +* The IIC hardware can use 7 or 10 bit addresses. The driver provides the +* ability to control which address size is sent in messages as a master to a +* slave device. +* +* FIFO Size +* The hardware FIFO is 32 bytes deep. The user must know the limitations of +* other IIC devices on the bus. Some are only able to receive a limited number +* of bytes in a single transfer. +* +* Data Rates +* +* The data rate is set by values in the control register. The formula for +* determining the correct register values is: +* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) +* +* When the device is configured as a slave, the slck setting controls the +* sample rate and so must be set to be at least as fast as the fastest scl +* expected to be seen in the system. +* +* Polled Mode Operation +* +* This driver supports polled mode transfers. +* +* Interrupts +* +* The user must connect the interrupt handler of the driver, +* XIicPs_InterruptHandler to an interrupt system such that it will be called +* when an interrupt occurs. This function does not save and restore the +* processor context such that the user must provide this processing. +* +* The driver handles the following interrupts: +* - Transfer complete +* - More Data +* - Transfer not Acknowledged +* - Transfer Time out +* - Monitored slave ready - master mode only +* - Receive Overflow +* - Transmit FIFO overflow +* - Receive FIFO underflow +* - Arbitration lost +* +* Bus Busy +* +* Bus busy is checked before the setup of a master mode device, to avoid +* unnecessary arbitration loss interrupt. +* +* RTOS Independence +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads or +* thread mutual exclusion, virtual memory, or cache control must be satisfied by +* the layer above this driver. +* +*Repeated Start +* +* The I2C controller does not indicate completion of a receive transfer if HOLD +* bit is set. Due to this errata, repeated start cannot be used if a receive +* transfer is followed by any other transfer. +* +* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk  08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                    read mode and clear transfer size register.
+*                    Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	10/07/14 Repeated start feature deleted.
+* 3.0	sk	11/03/14 Modified TimeOut Register value to 0xFF
+* 					 in XIicPs_Reset.
+* 			12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+*
+*
+* +******************************************************************************/ + +#ifndef XIICPS_H /* prevent circular inclusions */ +#define XIICPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xiicps_hw.h" +#include "xplatform_info.h" + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * The following options may be specified or retrieved for the device and + * enable/disable additional features of the IIC. Each of the options + * are bit fields, so more than one may be specified. + * + * @{ + */ +#define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */ +#define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */ +#define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */ +#define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */ +/*@}*/ + +/** @name Callback events + * + * These constants specify the handler events that are passed to an application + * event handler from the driver. These constants are bit masks such that + * more than one event can be passed to the handler. + * + * @{ + */ +#define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/ +#define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/ +#define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */ +#define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */ +#define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */ +#define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */ +#define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */ +#define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */ +#define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */ +#define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */ +/*@}*/ + +/** @name Role constants + * + * These constants are used to pass into the device setup routines to + * set up the device according to transfer direction. + */ +#define SENDING_ROLE 1 /**< Transfer direction is sending */ +#define RECVING_ROLE 0 /**< Transfer direction is receiving */ + +/* Maximum transfer size */ +#define XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U) + +/**************************** Type Definitions *******************************/ + +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* not important to the driver, so it is a void pointer. +* @param StatusEvent indicates one or more status events that occurred. +*/ +typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ +} XIicPs_Config; + +/** + * The XIicPs driver instance data. The user is required to allocate a + * variable of this type for each IIC device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XIicPs_Config Config; /* Configuration structure */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Options set in the device */ + + u8 *SendBufferPtr; /* Pointer to send buffer */ + u8 *RecvBufferPtr; /* Pointer to recv buffer */ + s32 SendByteCount; /* Number of bytes still expected to send */ + s32 RecvByteCount; /* Number of bytes still expected to receive */ + s32 CurrByteCount; /* No. of bytes expected in current transfer */ + + s32 UpdateTxSize; /* If tx size register has to be updated */ + s32 IsSend; /* Whether master is sending or receiving */ + s32 IsRepeatedStart; /* Indicates if user set repeated start */ + + XIicPs_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XIicPs; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/* +* +* Place one byte into the transmit FIFO. +* +* @param InstancePtr is the instance of IIC +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_SendByte(XIicPs *InstancePtr) +* +*****************************************************************************/ +#define XIicPs_SendByte(InstancePtr) \ +{ \ + u8 Data; \ + Data = *((InstancePtr)->SendBufferPtr); \ + XIicPs_Out32((InstancePtr)->Config.BaseAddress \ + + (u32)(XIICPS_DATA_OFFSET), \ + (u32)(Data)); \ + (InstancePtr)->SendBufferPtr += 1; \ + (InstancePtr)->SendByteCount -= 1;\ +} + +/****************************************************************************/ +/* +* +* Receive one byte from FIFO. +* +* @param InstancePtr is the instance of IIC +* +* @return None. +* +* @note C-Style signature: +* u8 XIicPs_RecvByte(XIicPs *InstancePtr) +* +*****************************************************************************/ +#define XIicPs_RecvByte(InstancePtr) \ +{ \ + u8 *Data, Value; \ + Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \ + + (u32)XIICPS_DATA_OFFSET)); \ + Data = &Value; \ + *(InstancePtr)->RecvBufferPtr = *Data; \ + (InstancePtr)->RecvBufferPtr += 1; \ + (InstancePtr)->RecvByteCount --; \ +} + +/************************** Function Prototypes ******************************/ + +/* + * Function for configuration lookup, in xiicps_sinit.c + */ +XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId); + +/* + * Functions for general setup, in xiicps.c + */ +s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr, + u32 EffectiveAddr); + +void XIicPs_Abort(XIicPs *InstancePtr); +void XIicPs_Reset(XIicPs *InstancePtr); + +s32 XIicPs_BusIsBusy(XIicPs *InstancePtr); +s32 TransmitFifoFill(XIicPs *InstancePtr); + +/* + * Functions for interrupts, in xiicps_intr.c + */ +void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef, + XIicPs_IntrHandler FunctionPtr); + +/* + * Functions for device as master, in xiicps_master.c + */ +void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, + u16 SlaveAddr); +void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, + u16 SlaveAddr); +s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, + u16 SlaveAddr); +s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, + u16 SlaveAddr); +void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr); +void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr); +void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr); + +/* + * Functions for device as slave, in xiicps_slave.c + */ +void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr); +void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount); +void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount); +s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount); +s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount); +void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr); + +/* + * Functions for selftest, in xiicps_selftest.c + */ +s32 XIicPs_SelfTest(XIicPs *InstancePtr); + +/* + * Functions for setting and getting data rate, in xiicps_options.c + */ +s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options); +s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options); +u32 XIicPs_GetOptions(XIicPs *InstancePtr); + +s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz); +u32 XIicPs_GetSClk(XIicPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiicps_hw.h new file mode 100644 index 000000000..71b770ce4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiicps_hw.h @@ -0,0 +1,380 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xiicps_hw.h +* +* This header file contains the hardware definition for an IIC device. +* It includes register definitions and interface functions to read/write +* the registers. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype.
+* 3.0	sk		11/03/14 Modified the TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* +******************************************************************************/ +#ifndef XIICPS_HW_H /* prevent circular inclusions */ +#define XIICPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the IIC. + * @{ + */ +#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */ +#define XIICPS_SR_OFFSET 0x04U /**< Status */ +#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */ +#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */ +#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */ +#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */ +#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */ +#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */ +#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */ +#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */ +#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */ +/* @} */ + +/** @name Control Register + * + * This register contains various control bits that + * affects the operation of the IIC controller. Read/Write. + * @{ + */ + +#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */ +#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */ +#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */ +#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */ +#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */ +#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/ +#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */ +#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl, + 0=terminate transfer */ +#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when + Master receiver*/ +#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit, + 0=10 bit */ +#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master, + 0=Slave */ +#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master + transfer 0=Transmitter, + 1=Receiver*/ +#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control + register */ +/* @} */ + +/** @name IIC Status Register + * + * This register is used to indicate status of the IIC controller. Read only + * @{ + */ +#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */ +#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */ +#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */ +#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */ +#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */ +/* @} */ + +/** @name IIC Address Register + * + * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0]. + * A write access to this register always initiates a transfer if the IIC is in + * master mode. Read/Write + * @{ + */ +#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */ +/* @} */ + +/** @name IIC Data Register + * + * When written to, the data register sets data to transmit. When read from, the + * data register reads the last received byte of data. Read/Write + * @{ + */ +#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */ +/* @} */ + +/** @name IIC Interrupt Registers + * + * IIC Interrupt Status Register + * + * This register holds the interrupt status flags for the IIC controller. Some + * of the flags are level triggered + * - i.e. are set as long as the interrupt condition exists. Other flags are + * edge triggered, which means they are set one the interrupt condition occurs + * then remain set until they are cleared by software. + * The interrupts are cleared by writing a one to the interrupt bit position + * in the Interrupt Status Register. Read/Write. + * + * IIC Interrupt Enable Register + * + * This register is used to enable interrupt sources for the IIC controller. + * Writing a '1' to a bit in this register clears the corresponding bit in the + * IIC Interrupt Mask register. Write only. + * + * IIC Interrupt Disable Register + * + * This register is used to disable interrupt sources for the IIC controller. + * Writing a '1' to a bit in this register sets the corresponding bit in the + * IIC Interrupt Mask register. Write only. + * + * IIC Interrupt Mask Register + * + * This register shows the enabled/disabled status of each IIC controller + * interrupt source. A bit set to 1 will ignore the corresponding interrupt in + * the status register. A bit set to 0 means the interrupt is enabled. + * All mask bits are set and all interrupts are disabled after reset. Read only. + * + * All four registers have the same bit definitions. They are only defined once + * for each of the Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Interrupt Status Register + * @{ + */ + +#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt + mask */ +#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow + Interrupt mask */ +#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow + Interrupt mask */ +#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt + mask */ +#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready + Interrupt mask */ +#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out + Interrupt mask */ +#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */ +#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */ +#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete + Interrupt mask */ +#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */ +#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */ +/* @} */ + + +/** @name IIC Transfer Size Register +* +* The register's meaning varies according to the operating mode as follows: +* - Master transmitter mode: number of data bytes still not transmitted minus +* one +* - Master receiver mode: number of data bytes that are still expected to be +* received +* - Slave transmitter mode: number of bytes remaining in the FIFO after the +* master terminates the transfer +* - Slave receiver mode: number of valid data bytes in the FIFO +* +* This register is cleared if CLR_FIFO bit in the control register is set. +* Read/Write +* @{ +*/ +#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */ +#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */ +#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */ +/* @} */ + + +/** @name IIC Slave Monitor Pause Register +* +* This register is associated with the slave monitor mode of the I2C interface. +* It is meaningful only when the module is in master mode and bit SLVMON in the +* control register is set. +* +* This register defines the pause interval between consecutive attempts to +* address the slave once a write to an I2C address register is done by the +* host. It represents the number of sclk cycles minus one between two attempts. +* +* The reset value of the register is 0, which results in the master repeatedly +* trying to access the slave immediately after unsuccessful attempt. +* Read/Write +* @{ +*/ +#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */ +/* @} */ + + +/** @name IIC Time Out Register +* +* The value of time out register represents the time out interval in number of +* sclk cycles minus one. +* +* When the accessed slave holds the sclk line low for longer than the time out +* period, thus prohibiting the I2C interface in master mode to complete the +* current transfer, an interrupt is generated and TO interrupt flag is set. +* +* The reset value of the register is 0x1f. +* Read/Write +* @{ + */ +#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */ +#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XIicPs_In32 Xil_In32 +#define XIicPs_Out32 Xil_Out32 + +/****************************************************************************/ +/** +* Read an IIC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to select the specific register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XIicPs_ReadReg(BaseAddress, RegOffset) \ + XIicPs_In32((BaseAddress) + (u32)(RegOffset)) + +/***************************************************************************/ +/** +* Write an IIC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to select the specific register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue) +* +******************************************************************************/ +#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue)) + +/***************************************************************************/ +/** +* Read the interrupt enable register. +* +* @param BaseAddress contains the base address of the device. +* +* @return Current bit mask that represents currently enabled interrupts. +* +* @note C-Style signature: +* u32 XIicPs_ReadIER(u32 BaseAddress) +* +******************************************************************************/ +#define XIicPs_ReadIER(BaseAddress) \ + XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET) + +/***************************************************************************/ +/** +* Write to the interrupt enable register. +* +* @param BaseAddress contains the base address of the device. +* +* @param IntrMask is the interrupts to be enabled. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask) +* +******************************************************************************/ +#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \ + XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask)) + +/***************************************************************************/ +/** +* Disable all interrupts. +* +* @param BaseAddress contains the base address of the device. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_DisableAllInterrupts(u32 BaseAddress) +* +******************************************************************************/ +#define XIicPs_DisableAllInterrupts(BaseAddress) \ + XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ + XIICPS_IXR_ALL_INTR_MASK) + +/***************************************************************************/ +/** +* Disable selected interrupts. +* +* @param BaseAddress contains the base address of the device. +* +* @param IntrMask is the interrupts to be disabled. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask) +* +******************************************************************************/ +#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \ + XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ + (IntrMask)) + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the I2c interface + */ +void XIicPs_ResetHw(u32 BaseAddress); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_assert.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_assert.h new file mode 100644 index 000000000..6d3f96a83 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_assert.h @@ -0,0 +1,189 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_assert.h +* +* This file contains assert related functions. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+*
+* +******************************************************************************/ + +#ifndef XIL_ASSERT_H /* prevent circular inclusions */ +#define XIL_ASSERT_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +#define XIL_ASSERT_NONE 0U +#define XIL_ASSERT_OCCURRED 1U +#define XNULL NULL + +extern u32 Xil_AssertStatus; +extern void Xil_Assert(const char8 *File, s32 Line); +void XNullHandler(void *NullParameter); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do not return anything +* (void). This in conjunction with the Xil_AssertWait boolean can be used to +* accomodate tests so that asserts which fail allow execution to continue. +* +* @param Expression is the expression to evaluate. If it evaluates to +* false, the assert occurs. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertVoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do return a value. This in +* conjunction with the Xil_AssertWait boolean can be used to accomodate tests +* so that asserts which fail allow execution to continue. +* +* @param Expression is the expression to evaluate. If it evaluates to false, +* the assert occurs. +* +* @return Returns 0 unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertNonvoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do not +* return anything (void). Use for instances where an assert should always +* occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertVoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do return +* a value. Use for instances where an assert should always occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertNonvoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ +} + + +#else + +#define Xil_AssertVoid(Expression) +#define Xil_AssertVoidAlways() +#define Xil_AssertNonvoid(Expression) +#define Xil_AssertNonvoidAlways() + +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_AssertSetCallback(Xil_AssertCallback Routine); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_cache.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_cache.h new file mode 100644 index 000000000..940133290 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_cache.h @@ -0,0 +1,75 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* Contains required functions for the ARM cache functionality +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheInvalidateLine(INTPTR adr); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); +void Xil_DCacheFlushLine(INTPTR adr); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); +void Xil_ICacheInvalidateLine(INTPTR adr); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_cache_vxworks.h new file mode 100644 index 000000000..64ae0fd90 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_cache_vxworks.h @@ -0,0 +1,93 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_vxworks.h +* +* Contains the cache related functions for VxWorks that is wrapped by +* xil_cache. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+*
+* +* @note +* +******************************************************************************/ + +#ifndef XIL_CACHE_VXWORKS_H +#define XIL_CACHE_VXWORKS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vxWorks.h" +#include "vxLib.h" +#include "sysLibExtra.h" +#include "cacheLib.h" + +#if (CPU_FAMILY==PPC) + +#define Xil_DCacheEnable() cacheEnable(DATA_CACHE) + +#define Xil_DCacheDisable() cacheDisable(DATA_CACHE) + +#define Xil_DCacheInvalidateRange(Addr, Len) \ + cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_DCacheFlushRange(Addr, Len) \ + cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE) + +#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE) + +#define Xil_ICacheInvalidateRange(Addr, Len) \ + cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) + + +#else +#error "Unknown processor / architecture. Must be PPC for VxWorks." +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_exception.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_exception.h new file mode 100644 index 000000000..818d44300 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_exception.h @@ -0,0 +1,168 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Enable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ + +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) + +/****************************************************************************/ +/** +* Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Disable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ + +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) + +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); + +extern void Xil_ExceptionInit(void); + +void Xil_SyncAbortHandler(void *CallBackRef); + +void Xil_SErrorAbortHandler(void *CallBackRef); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_hal.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_hal.h new file mode 100644 index 000000000..e29d2a79d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_hal.h @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_hal.h +* +* Contains all the HAL header files. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+*
+* +* @note +* +******************************************************************************/ + +#ifndef XIL_HAL_H +#define XIL_HAL_H + +#include "xil_cache.h" +#include "xil_io.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xil_types.h" + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_io.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_io.h new file mode 100644 index 000000000..1c89574bb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_io.h @@ -0,0 +1,240 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* This file contains the interface for the general IO component, which +* encapsulates the Input/Output functions for processors that do not +* require any special I/O handling. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+*
+******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xil_printf.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() + + +/*****************************************************************************/ +/** +* +* Perform an big-endian input operation for a 16-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* @note None. +* +******************************************************************************/ +#define Xil_In16LE(Addr) Xil_In16((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian input operation for a 32-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* +* @note None. +* +******************************************************************************/ +#define Xil_In32LE(Addr) Xil_In32((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 16-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 32-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from host byte order to network byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from host byte order to network byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htons(Data) Xil_EndianSwap16((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from network byte order to host byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from network byte order to host byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) + +/************************** Function Prototypes ******************************/ + +/* The following functions allow the software to be transportable across + * processors which may use memory mapped I/O or I/O which is mapped into a + * seperate address space. + */ +u8 Xil_In8(INTPTR Addr); +u16 Xil_In16(INTPTR Addr); +u32 Xil_In32(INTPTR Addr); +u64 Xil_In64(INTPTR Addr); + +void Xil_Out8(INTPTR Addr, u8 Value); +void Xil_Out16(INTPTR Addr, u16 Value); +void Xil_Out32(INTPTR Addr, u32 Value); +void Xil_Out64(INTPTR Addr, u64 Value); + + +u16 Xil_In16BE(INTPTR Addr); +u32 Xil_In32BE(INTPTR Addr); +void Xil_Out16BE(INTPTR Addr, u16 Value); +void Xil_Out32BE(INTPTR Addr, u32 Value); + +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_macroback.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_macroback.h new file mode 100644 index 000000000..f5316efbf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_macroback.h @@ -0,0 +1,1052 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*********************************************************************/ +/** + * @file xil_macroback.h + * + * This header file is meant to bring back the removed _m macros. + * This header file must be included last. + * The following macros are not defined here due to the driver change: + * XGpio_mSetDataDirection + * XGpio_mGetDataReg + * XGpio_mSetDataReg + * XIIC_RESET + * XIIC_CLEAR_STATS + * XSpi_mReset + * XSysAce_mSetCfgAddr + * XSysAce_mIsCfgDone + * XTft_mSetPixel + * XTft_mGetPixel + * XWdtTb_mEnableWdt + * XWdtTb_mDisbleWdt + * XWdtTb_mRestartWdt + * XWdtTb_mGetTimebaseReg + * XWdtTb_mHasReset + * + * Please refer the corresonding driver document for replacement. + * + *********************************************************************/ + +#ifndef XIL_MACROBACK_H +#define XIL_MACROBACK_H + +/*********************************************************************/ +/** + * Macros for Driver XCan + * + *********************************************************************/ +#ifndef XCan_mReadReg +#define XCan_mReadReg XCan_ReadReg +#endif + +#ifndef XCan_mWriteReg +#define XCan_mWriteReg XCan_WriteReg +#endif + +#ifndef XCan_mIsTxDone +#define XCan_mIsTxDone XCan_IsTxDone +#endif + +#ifndef XCan_mIsTxFifoFull +#define XCan_mIsTxFifoFull XCan_IsTxFifoFull +#endif + +#ifndef XCan_mIsHighPriorityBufFull +#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull +#endif + +#ifndef XCan_mIsRxEmpty +#define XCan_mIsRxEmpty XCan_IsRxEmpty +#endif + +#ifndef XCan_mIsAcceptFilterBusy +#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy +#endif + +#ifndef XCan_mCreateIdValue +#define XCan_mCreateIdValue XCan_CreateIdValue +#endif + +#ifndef XCan_mCreateDlcValue +#define XCan_mCreateDlcValue XCan_CreateDlcValue +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDmaCentral + * + *********************************************************************/ +#ifndef XDmaCentral_mWriteReg +#define XDmaCentral_mWriteReg XDmaCentral_WriteReg +#endif + +#ifndef XDmaCentral_mReadReg +#define XDmaCentral_mReadReg XDmaCentral_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsAdc + * + *********************************************************************/ +#ifndef XDsAdc_mWriteReg +#define XDsAdc_mWriteReg XDsAdc_WriteReg +#endif + +#ifndef XDsAdc_mReadReg +#define XDsAdc_mReadReg XDsAdc_ReadReg +#endif + +#ifndef XDsAdc_mIsEmpty +#define XDsAdc_mIsEmpty XDsAdc_IsEmpty +#endif + +#ifndef XDsAdc_mSetFstmReg +#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg +#endif + +#ifndef XDsAdc_mGetFstmReg +#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg +#endif + +#ifndef XDsAdc_mEnableConversion +#define XDsAdc_mEnableConversion XDsAdc_EnableConversion +#endif + +#ifndef XDsAdc_mDisableConversion +#define XDsAdc_mDisableConversion XDsAdc_DisableConversion +#endif + +#ifndef XDsAdc_mGetFifoOccyReg +#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsDac + * + *********************************************************************/ +#ifndef XDsDac_mWriteReg +#define XDsDac_mWriteReg XDsDac_WriteReg +#endif + +#ifndef XDsDac_mReadReg +#define XDsDac_mReadReg XDsDac_ReadReg +#endif + +#ifndef XDsDac_mIsEmpty +#define XDsDac_mIsEmpty XDsDac_IsEmpty +#endif + +#ifndef XDsDac_mFifoIsFull +#define XDsDac_mFifoIsFull XDsDac_FifoIsFull +#endif + +#ifndef XDsDac_mGetVacancy +#define XDsDac_mGetVacancy XDsDac_GetVacancy +#endif + +/*********************************************************************/ +/** + * Macros for Driver XEmacLite + * + *********************************************************************/ +#ifndef XEmacLite_mReadReg +#define XEmacLite_mReadReg XEmacLite_ReadReg +#endif + +#ifndef XEmacLite_mWriteReg +#define XEmacLite_mWriteReg XEmacLite_WriteReg +#endif + +#ifndef XEmacLite_mGetTxStatus +#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus +#endif + +#ifndef XEmacLite_mSetTxStatus +#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus +#endif + +#ifndef XEmacLite_mGetRxStatus +#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus +#endif + +#ifndef XEmacLite_mSetRxStatus +#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus +#endif + +#ifndef XEmacLite_mIsTxDone +#define XEmacLite_mIsTxDone XEmacLite_IsTxDone +#endif + +#ifndef XEmacLite_mIsRxEmpty +#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty +#endif + +#ifndef XEmacLite_mNextTransmitAddr +#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr +#endif + +#ifndef XEmacLite_mNextReceiveAddr +#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr +#endif + +#ifndef XEmacLite_mIsMdioConfigured +#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured +#endif + +#ifndef XEmacLite_mIsLoopbackConfigured +#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured +#endif + +#ifndef XEmacLite_mGetReceiveDataLength +#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength +#endif + +#ifndef XEmacLite_mGetTxActive +#define XEmacLite_mGetTxActive XEmacLite_GetTxActive +#endif + +#ifndef XEmacLite_mSetTxActive +#define XEmacLite_mSetTxActive XEmacLite_SetTxActive +#endif + +/*********************************************************************/ +/** + * Macros for Driver XGpio + * + *********************************************************************/ +#ifndef XGpio_mWriteReg +#define XGpio_mWriteReg XGpio_WriteReg +#endif + +#ifndef XGpio_mReadReg +#define XGpio_mReadReg XGpio_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XHwIcap + * + *********************************************************************/ +#ifndef XHwIcap_mFifoWrite +#define XHwIcap_mFifoWrite XHwIcap_FifoWrite +#endif + +#ifndef XHwIcap_mFifoRead +#define XHwIcap_mFifoRead XHwIcap_FifoRead +#endif + +#ifndef XHwIcap_mSetSizeReg +#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg +#endif + +#ifndef XHwIcap_mGetControlReg +#define XHwIcap_mGetControlReg XHwIcap_GetControlReg +#endif + +#ifndef XHwIcap_mStartConfig +#define XHwIcap_mStartConfig XHwIcap_StartConfig +#endif + +#ifndef XHwIcap_mStartReadBack +#define XHwIcap_mStartReadBack XHwIcap_StartReadBack +#endif + +#ifndef XHwIcap_mGetStatusReg +#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg +#endif + +#ifndef XHwIcap_mIsTransferDone +#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone +#endif + +#ifndef XHwIcap_mIsDeviceBusy +#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy +#endif + +#ifndef XHwIcap_mIntrGlobalEnable +#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable +#endif + +#ifndef XHwIcap_mIntrGlobalDisable +#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable +#endif + +#ifndef XHwIcap_mIntrGetStatus +#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus +#endif + +#ifndef XHwIcap_mIntrDisable +#define XHwIcap_mIntrDisable XHwIcap_IntrDisable +#endif + +#ifndef XHwIcap_mIntrEnable +#define XHwIcap_mIntrEnable XHwIcap_IntrEnable +#endif + +#ifndef XHwIcap_mIntrGetEnabled +#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled +#endif + +#ifndef XHwIcap_mIntrClear +#define XHwIcap_mIntrClear XHwIcap_IntrClear +#endif + +#ifndef XHwIcap_mGetWrFifoVacancy +#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy +#endif + +#ifndef XHwIcap_mGetRdFifoOccupancy +#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy +#endif + +#ifndef XHwIcap_mSliceX2Col +#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col +#endif + +#ifndef XHwIcap_mSliceY2Row +#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row +#endif + +#ifndef XHwIcap_mSliceXY2Slice +#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice +#endif + +#ifndef XHwIcap_mReadReg +#define XHwIcap_mReadReg XHwIcap_ReadReg +#endif + +#ifndef XHwIcap_mWriteReg +#define XHwIcap_mWriteReg XHwIcap_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIic + * + *********************************************************************/ +#ifndef XIic_mReadReg +#define XIic_mReadReg XIic_ReadReg +#endif + +#ifndef XIic_mWriteReg +#define XIic_mWriteReg XIic_WriteReg +#endif + +#ifndef XIic_mEnterCriticalRegion +#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable +#endif + +#ifndef XIic_mExitCriticalRegion +#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_GINTR_DISABLE +#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable +#endif + +#ifndef XIIC_GINTR_ENABLE +#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_IS_GINTR_ENABLED +#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled +#endif + +#ifndef XIIC_WRITE_IISR +#define XIIC_WRITE_IISR XIic_WriteIisr +#endif + +#ifndef XIIC_READ_IISR +#define XIIC_READ_IISR XIic_ReadIisr +#endif + +#ifndef XIIC_WRITE_IIER +#define XIIC_WRITE_IIER XIic_WriteIier +#endif + +#ifndef XIic_mClearIisr +#define XIic_mClearIisr XIic_ClearIisr +#endif + +#ifndef XIic_mSend7BitAddress +#define XIic_mSend7BitAddress XIic_Send7BitAddress +#endif + +#ifndef XIic_mDynSend7BitAddress +#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress +#endif + +#ifndef XIic_mDynSendStartStopAddress +#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress +#endif + +#ifndef XIic_mDynSendStop +#define XIic_mDynSendStop XIic_DynSendStop +#endif + +#ifndef XIic_mSend10BitAddrByte1 +#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1 +#endif + +#ifndef XIic_mSend10BitAddrByte2 +#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2 +#endif + +#ifndef XIic_mSend7BitAddr +#define XIic_mSend7BitAddr XIic_Send7BitAddr +#endif + +#ifndef XIic_mDisableIntr +#define XIic_mDisableIntr XIic_DisableIntr +#endif + +#ifndef XIic_mEnableIntr +#define XIic_mEnableIntr XIic_EnableIntr +#endif + +#ifndef XIic_mClearIntr +#define XIic_mClearIntr XIic_ClearIntr +#endif + +#ifndef XIic_mClearEnableIntr +#define XIic_mClearEnableIntr XIic_ClearEnableIntr +#endif + +#ifndef XIic_mFlushRxFifo +#define XIic_mFlushRxFifo XIic_FlushRxFifo +#endif + +#ifndef XIic_mFlushTxFifo +#define XIic_mFlushTxFifo XIic_FlushTxFifo +#endif + +#ifndef XIic_mReadRecvByte +#define XIic_mReadRecvByte XIic_ReadRecvByte +#endif + +#ifndef XIic_mWriteSendByte +#define XIic_mWriteSendByte XIic_WriteSendByte +#endif + +#ifndef XIic_mSetControlRegister +#define XIic_mSetControlRegister XIic_SetControlRegister +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIntc + * + *********************************************************************/ +#ifndef XIntc_mMasterEnable +#define XIntc_mMasterEnable XIntc_MasterEnable +#endif + +#ifndef XIntc_mMasterDisable +#define XIntc_mMasterDisable XIntc_MasterDisable +#endif + +#ifndef XIntc_mEnableIntr +#define XIntc_mEnableIntr XIntc_EnableIntr +#endif + +#ifndef XIntc_mDisableIntr +#define XIntc_mDisableIntr XIntc_DisableIntr +#endif + +#ifndef XIntc_mAckIntr +#define XIntc_mAckIntr XIntc_AckIntr +#endif + +#ifndef XIntc_mGetIntrStatus +#define XIntc_mGetIntrStatus XIntc_GetIntrStatus +#endif + +/*********************************************************************/ +/** + * Macros for Driver XLlDma + * + *********************************************************************/ +#ifndef XLlDma_mBdRead +#define XLlDma_mBdRead XLlDma_BdRead +#endif + +#ifndef XLlDma_mBdWrite +#define XLlDma_mBdWrite XLlDma_BdWrite +#endif + +#ifndef XLlDma_mWriteReg +#define XLlDma_mWriteReg XLlDma_WriteReg +#endif + +#ifndef XLlDma_mReadReg +#define XLlDma_mReadReg XLlDma_ReadReg +#endif + +#ifndef XLlDma_mBdClear +#define XLlDma_mBdClear XLlDma_BdClear +#endif + +#ifndef XLlDma_mBdSetStsCtrl +#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl +#endif + +#ifndef XLlDma_mBdGetStsCtrl +#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl +#endif + +#ifndef XLlDma_mBdSetLength +#define XLlDma_mBdSetLength XLlDma_BdSetLength +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mBdSetId +#define XLlDma_mBdSetId XLlDma_BdSetId +#endif + +#ifndef XLlDma_mBdGetId +#define XLlDma_mBdGetId XLlDma_BdGetId +#endif + +#ifndef XLlDma_mBdSetBufAddr +#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr +#endif + +#ifndef XLlDma_mBdGetBufAddr +#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mGetTxRing +#define XLlDma_mGetTxRing XLlDma_GetTxRing +#endif + +#ifndef XLlDma_mGetRxRing +#define XLlDma_mGetRxRing XLlDma_GetRxRing +#endif + +#ifndef XLlDma_mGetCr +#define XLlDma_mGetCr XLlDma_GetCr +#endif + +#ifndef XLlDma_mSetCr +#define XLlDma_mSetCr XLlDma_SetCr +#endif + +#ifndef XLlDma_mBdRingCntCalc +#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc +#endif + +#ifndef XLlDma_mBdRingMemCalc +#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc +#endif + +#ifndef XLlDma_mBdRingGetCnt +#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt +#endif + +#ifndef XLlDma_mBdRingGetFreeCnt +#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt +#endif + +#ifndef XLlDma_mBdRingSnapShotCurrBd +#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd +#endif + +#ifndef XLlDma_mBdRingNext +#define XLlDma_mBdRingNext XLlDma_BdRingNext +#endif + +#ifndef XLlDma_mBdRingPrev +#define XLlDma_mBdRingPrev XLlDma_BdRingPrev +#endif + +#ifndef XLlDma_mBdRingGetSr +#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr +#endif + +#ifndef XLlDma_mBdRingSetSr +#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr +#endif + +#ifndef XLlDma_mBdRingGetCr +#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr +#endif + +#ifndef XLlDma_mBdRingSetCr +#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr +#endif + +#ifndef XLlDma_mBdRingBusy +#define XLlDma_mBdRingBusy XLlDma_BdRingBusy +#endif + +#ifndef XLlDma_mBdRingIntEnable +#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable +#endif + +#ifndef XLlDma_mBdRingIntDisable +#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable +#endif + +#ifndef XLlDma_mBdRingIntGetEnabled +#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled +#endif + +#ifndef XLlDma_mBdRingGetIrq +#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq +#endif + +#ifndef XLlDma_mBdRingAckIrq +#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMbox + * + *********************************************************************/ +#ifndef XMbox_mWriteReg +#define XMbox_mWriteReg XMbox_WriteReg +#endif + +#ifndef XMbox_mReadReg +#define XMbox_mReadReg XMbox_ReadReg +#endif + +#ifndef XMbox_mWriteMBox +#define XMbox_mWriteMBox XMbox_WriteMBox +#endif + +#ifndef XMbox_mReadMBox +#define XMbox_mReadMBox XMbox_ReadMBox +#endif + +#ifndef XMbox_mFSLReadMBox +#define XMbox_mFSLReadMBox XMbox_FSLReadMBox +#endif + +#ifndef XMbox_mFSLWriteMBox +#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox +#endif + +#ifndef XMbox_mFSLIsEmpty +#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty +#endif + +#ifndef XMbox_mFSLIsFull +#define XMbox_mFSLIsFull XMbox_FSLIsFull +#endif + +#ifndef XMbox_mIsEmpty +#define XMbox_mIsEmpty XMbox_IsEmptyHw +#endif + +#ifndef XMbox_mIsFull +#define XMbox_mIsFull XMbox_IsFullHw +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMpmc + * + *********************************************************************/ +#ifndef XMpmc_mReadReg +#define XMpmc_mReadReg XMpmc_ReadReg +#endif + +#ifndef XMpmc_mWriteReg +#define XMpmc_mWriteReg XMpmc_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMutex + * + *********************************************************************/ +#ifndef XMutex_mWriteReg +#define XMutex_mWriteReg XMutex_WriteReg +#endif + +#ifndef XMutex_mReadReg +#define XMutex_mReadReg XMutex_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XPcie + * + *********************************************************************/ +#ifndef XPcie_mReadReg +#define XPcie_mReadReg XPcie_ReadReg +#endif + +#ifndef XPcie_mWriteReg +#define XPcie_mWriteReg XPcie_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSpi + * + *********************************************************************/ +#ifndef XSpi_mIntrGlobalEnable +#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable +#endif + +#ifndef XSpi_mIntrGlobalDisable +#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable +#endif + +#ifndef XSpi_mIsIntrGlobalEnabled +#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled +#endif + +#ifndef XSpi_mIntrGetStatus +#define XSpi_mIntrGetStatus XSpi_IntrGetStatus +#endif + +#ifndef XSpi_mIntrClear +#define XSpi_mIntrClear XSpi_IntrClear +#endif + +#ifndef XSpi_mIntrEnable +#define XSpi_mIntrEnable XSpi_IntrEnable +#endif + +#ifndef XSpi_mIntrDisable +#define XSpi_mIntrDisable XSpi_IntrDisable +#endif + +#ifndef XSpi_mIntrGetEnabled +#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled +#endif + +#ifndef XSpi_mSetControlReg +#define XSpi_mSetControlReg XSpi_SetControlReg +#endif + +#ifndef XSpi_mGetControlReg +#define XSpi_mGetControlReg XSpi_GetControlReg +#endif + +#ifndef XSpi_mGetStatusReg +#define XSpi_mGetStatusReg XSpi_GetStatusReg +#endif + +#ifndef XSpi_mSetSlaveSelectReg +#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg +#endif + +#ifndef XSpi_mGetSlaveSelectReg +#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg +#endif + +#ifndef XSpi_mEnable +#define XSpi_mEnable XSpi_Enable +#endif + +#ifndef XSpi_mDisable +#define XSpi_mDisable XSpi_Disable +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysAce + * + *********************************************************************/ +#ifndef XSysAce_mGetControlReg +#define XSysAce_mGetControlReg XSysAce_GetControlReg +#endif + +#ifndef XSysAce_mSetControlReg +#define XSysAce_mSetControlReg XSysAce_SetControlReg +#endif + +#ifndef XSysAce_mOrControlReg +#define XSysAce_mOrControlReg XSysAce_OrControlReg +#endif + +#ifndef XSysAce_mAndControlReg +#define XSysAce_mAndControlReg XSysAce_AndControlReg +#endif + +#ifndef XSysAce_mGetErrorReg +#define XSysAce_mGetErrorReg XSysAce_GetErrorReg +#endif + +#ifndef XSysAce_mGetStatusReg +#define XSysAce_mGetStatusReg XSysAce_GetStatusReg +#endif + +#ifndef XSysAce_mWaitForLock +#define XSysAce_mWaitForLock XSysAce_WaitForLock +#endif + +#ifndef XSysAce_mEnableIntr +#define XSysAce_mEnableIntr XSysAce_EnableIntr +#endif + +#ifndef XSysAce_mDisableIntr +#define XSysAce_mDisableIntr XSysAce_DisableIntr +#endif + +#ifndef XSysAce_mIsReadyForCmd +#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd +#endif + +#ifndef XSysAce_mIsMpuLocked +#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked +#endif + +#ifndef XSysAce_mIsIntrEnabled +#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysMon + * + *********************************************************************/ +#ifndef XSysMon_mIsEventSamplingModeSet +#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet +#endif + +#ifndef XSysMon_mIsDrpBusy +#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy +#endif + +#ifndef XSysMon_mIsDrpLocked +#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked +#endif + +#ifndef XSysMon_mRawToTemperature +#define XSysMon_mRawToTemperature XSysMon_RawToTemperature +#endif + +#ifndef XSysMon_mRawToVoltage +#define XSysMon_mRawToVoltage XSysMon_RawToVoltage +#endif + +#ifndef XSysMon_mTemperatureToRaw +#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw +#endif + +#ifndef XSysMon_mVoltageToRaw +#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw +#endif + +#ifndef XSysMon_mReadReg +#define XSysMon_mReadReg XSysMon_ReadReg +#endif + +#ifndef XSysMon_mWriteReg +#define XSysMon_mWriteReg XSysMon_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XTmrCtr + * + *********************************************************************/ +#ifndef XTimerCtr_mReadReg +#define XTimerCtr_mReadReg XTimerCtr_ReadReg +#endif + +#ifndef XTmrCtr_mWriteReg +#define XTmrCtr_mWriteReg XTmrCtr_WriteReg +#endif + +#ifndef XTmrCtr_mSetControlStatusReg +#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetControlStatusReg +#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetTimerCounterReg +#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg +#endif + +#ifndef XTmrCtr_mSetLoadReg +#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg +#endif + +#ifndef XTmrCtr_mGetLoadReg +#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg +#endif + +#ifndef XTmrCtr_mEnable +#define XTmrCtr_mEnable XTmrCtr_Enable +#endif + +#ifndef XTmrCtr_mDisable +#define XTmrCtr_mDisable XTmrCtr_Disable +#endif + +#ifndef XTmrCtr_mEnableIntr +#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr +#endif + +#ifndef XTmrCtr_mDisableIntr +#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr +#endif + +#ifndef XTmrCtr_mLoadTimerCounterReg +#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg +#endif + +#ifndef XTmrCtr_mHasEventOccurred +#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartLite + * + *********************************************************************/ +#ifndef XUartLite_mUpdateStats +#define XUartLite_mUpdateStats XUartLite_UpdateStats +#endif + +#ifndef XUartLite_mWriteReg +#define XUartLite_mWriteReg XUartLite_WriteReg +#endif + +#ifndef XUartLite_mReadReg +#define XUartLite_mReadReg XUartLite_ReadReg +#endif + +#ifndef XUartLite_mClearStats +#define XUartLite_mClearStats XUartLite_ClearStats +#endif + +#ifndef XUartLite_mSetControlReg +#define XUartLite_mSetControlReg XUartLite_SetControlReg +#endif + +#ifndef XUartLite_mGetStatusReg +#define XUartLite_mGetStatusReg XUartLite_GetStatusReg +#endif + +#ifndef XUartLite_mIsReceiveEmpty +#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty +#endif + +#ifndef XUartLite_mIsTransmitFull +#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull +#endif + +#ifndef XUartLite_mIsIntrEnabled +#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled +#endif + +#ifndef XUartLite_mEnableIntr +#define XUartLite_mEnableIntr XUartLite_EnableIntr +#endif + +#ifndef XUartLite_mDisableIntr +#define XUartLite_mDisableIntr XUartLite_DisableIntr +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartNs550 + * + *********************************************************************/ +#ifndef XUartNs550_mUpdateStats +#define XUartNs550_mUpdateStats XUartNs550_UpdateStats +#endif + +#ifndef XUartNs550_mReadReg +#define XUartNs550_mReadReg XUartNs550_ReadReg +#endif + +#ifndef XUartNs550_mWriteReg +#define XUartNs550_mWriteReg XUartNs550_WriteReg +#endif + +#ifndef XUartNs550_mClearStats +#define XUartNs550_mClearStats XUartNs550_ClearStats +#endif + +#ifndef XUartNs550_mGetLineStatusReg +#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg +#endif + +#ifndef XUartNs550_mGetLineControlReg +#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg +#endif + +#ifndef XUartNs550_mSetLineControlReg +#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg +#endif + +#ifndef XUartNs550_mEnableIntr +#define XUartNs550_mEnableIntr XUartNs550_EnableIntr +#endif + +#ifndef XUartNs550_mDisableIntr +#define XUartNs550_mDisableIntr XUartNs550_DisableIntr +#endif + +#ifndef XUartNs550_mIsReceiveData +#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData +#endif + +#ifndef XUartNs550_mIsTransmitEmpty +#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUsb + * + *********************************************************************/ +#ifndef XUsb_mReadReg +#define XUsb_mReadReg XUsb_ReadReg +#endif + +#ifndef XUsb_mWriteReg +#define XUsb_mWriteReg XUsb_WriteReg +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_mmu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_mmu.h new file mode 100644 index 000000000..d74b3d930 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_mmu.h @@ -0,0 +1,79 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_MMU_H +#define XIL_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MMU_H */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_printf.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_printf.h new file mode 100644 index 000000000..2be5c5734 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_printf.h @@ -0,0 +1,44 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "xil_types.h" +#include "xparameters.h" + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); + +/* */ + +void xil_printf( const char8 *ctrl1, ...); +void print( const char8 *ptr); +extern void outbyte (char8 c); +extern char8 inbyte(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_testcache.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_testcache.h new file mode 100644 index 000000000..0ec0ea87e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_testcache.h @@ -0,0 +1,63 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testcache.h +* +* This file contains utility functions to test cache. +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a hbm 07/29/09 First release +* +******************************************************************************/ + +#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ +#define XIL_TESTCACHE_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern s32 Xil_TestDCacheRange(void); +extern s32 Xil_TestDCacheAll(void); +extern s32 Xil_TestICacheRange(void); +extern s32 Xil_TestICacheAll(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_testio.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_testio.h new file mode 100644 index 000000000..2fd4d5790 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_testio.h @@ -0,0 +1,91 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmemend.h +* +* This file contains utility functions to teach endian related memory +* IO functions. +* +* Memory test description +* +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+*
+* +******************************************************************************/ + +#ifndef XIL_TESTIO_H /* prevent circular inclusions */ +#define XIL_TESTIO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +#define XIL_TESTIO_DEFAULT 0 +#define XIL_TESTIO_LE 1 +#define XIL_TESTIO_BE 2 + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value); +extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap); +extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_testmem.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_testmem.h new file mode 100644 index 000000000..1b67a5214 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_testmem.h @@ -0,0 +1,162 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmem.h +* +* This file contains utility functions to test memory. +* +* Memory test description +* +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* +* Subtest descriptions: +* 
+* XIL_TESTMEM_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XIL_TESTMEM_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
+*	incrementing value as the test value for memory.
+*
+* XIL_TESTMEM_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XIL_TESTMEM_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XIL_TESTMEM_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XIL_TESTMEM_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* +* WARNING +* +* The tests are DESTRUCTIVE. Run before any initialized memory spaces +* have been set up. +* +* The address provided to the memory tests is not checked for +* validity except for the NULL case. It is possible to provide a code-space +* pointer for this test to start with and ultimately destroy executable code +* causing random failures. +* +* @note +* +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+*
+* +******************************************************************************/ + +#ifndef XIL_TESTMEM_H /* prevent circular inclusions */ +#define XIL_TESTMEM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/* xutil_memtest defines */ + +#define XIL_TESTMEM_INIT_VALUE 1U + +/** @name Memory subtests + * @{ + */ +/** + * See the detailed description of the subtests in the file description. + */ +#define XIL_TESTMEM_ALLMEMTESTS 0x00U +#define XIL_TESTMEM_INCREMENT 0x01U +#define XIL_TESTMEM_WALKONES 0x02U +#define XIL_TESTMEM_WALKZEROS 0x03U +#define XIL_TESTMEM_INVERSEADDR 0x04U +#define XIL_TESTMEM_FIXEDPATTERN 0x05U +#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/* xutil_testmem prototypes */ + +extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); +extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); +extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_types.h new file mode 100644 index 000000000..b9ef3c185 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xil_types.h @@ -0,0 +1,184 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* This file contains basic types for Xilinx software IP. + +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+*
+* +******************************************************************************/ + +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#include +#include + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */ + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/** + * guarded against xbasic_types.h. + */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +* @note None. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +* @note None. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/** + * xbasic_types.h does not typedef s* or u64 + */ + +typedef char char8; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; + +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#else +#include +#endif + + +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/*@}*/ + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiou_secure_slcr.h new file mode 100644 index 000000000..cb4ad4903 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiou_secure_slcr.h @@ -0,0 +1,174 @@ +/* ### HEADER ### */ + +#ifndef __XIOU_SECURE_SLCR_H__ +#define __XIOU_SECURE_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XiouSecureSlcr Base Address + */ +#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL + +/** + * Register: XiouSecSlcrAxiWprtcn + */ +#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL ) +#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrAxiRprtcn + */ +#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL ) +#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrCtrl + */ +#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL ) +#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrIsr + */ +#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL ) +#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrImr + */ +#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL ) +#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL + +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XiouSecSlcrIer + */ +#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrIdr + */ +#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL ) +#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrItr + */ +#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL ) +#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XIOU_SECURE_SLCR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiou_slcr.h new file mode 100644 index 000000000..d81d178d3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xiou_slcr.h @@ -0,0 +1,4029 @@ +/* ### HEADER ### */ + +#ifndef __XIOU_SLCR_H__ +#define __XIOU_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XiouSlcr Base Address + */ +#define XIOU_SLCR_BASEADDR 0xFF180000UL + +/** + * Register: XiouSlcrMioPin0 + */ +#define XIOU_SLCR_MIO_PIN_0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000000UL ) +#define XIOU_SLCR_MIO_PIN_0_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin1 + */ +#define XIOU_SLCR_MIO_PIN_1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000004UL ) +#define XIOU_SLCR_MIO_PIN_1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin2 + */ +#define XIOU_SLCR_MIO_PIN_2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000008UL ) +#define XIOU_SLCR_MIO_PIN_2_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin3 + */ +#define XIOU_SLCR_MIO_PIN_3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XIOU_SLCR_MIO_PIN_3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin4 + */ +#define XIOU_SLCR_MIO_PIN_4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000010UL ) +#define XIOU_SLCR_MIO_PIN_4_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin5 + */ +#define XIOU_SLCR_MIO_PIN_5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000014UL ) +#define XIOU_SLCR_MIO_PIN_5_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin6 + */ +#define XIOU_SLCR_MIO_PIN_6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000018UL ) +#define XIOU_SLCR_MIO_PIN_6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin7 + */ +#define XIOU_SLCR_MIO_PIN_7 ( ( XIOU_SLCR_BASEADDR ) + 0x0000001CUL ) +#define XIOU_SLCR_MIO_PIN_7_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin8 + */ +#define XIOU_SLCR_MIO_PIN_8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000020UL ) +#define XIOU_SLCR_MIO_PIN_8_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin9 + */ +#define XIOU_SLCR_MIO_PIN_9 ( ( XIOU_SLCR_BASEADDR ) + 0x00000024UL ) +#define XIOU_SLCR_MIO_PIN_9_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin10 + */ +#define XIOU_SLCR_MIO_PIN_10 ( ( XIOU_SLCR_BASEADDR ) + 0x00000028UL ) +#define XIOU_SLCR_MIO_PIN_10_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin11 + */ +#define XIOU_SLCR_MIO_PIN_11 ( ( XIOU_SLCR_BASEADDR ) + 0x0000002CUL ) +#define XIOU_SLCR_MIO_PIN_11_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin12 + */ +#define XIOU_SLCR_MIO_PIN_12 ( ( XIOU_SLCR_BASEADDR ) + 0x00000030UL ) +#define XIOU_SLCR_MIO_PIN_12_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin13 + */ +#define XIOU_SLCR_MIO_PIN_13 ( ( XIOU_SLCR_BASEADDR ) + 0x00000034UL ) +#define XIOU_SLCR_MIO_PIN_13_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin14 + */ +#define XIOU_SLCR_MIO_PIN_14 ( ( XIOU_SLCR_BASEADDR ) + 0x00000038UL ) +#define XIOU_SLCR_MIO_PIN_14_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin15 + */ +#define XIOU_SLCR_MIO_PIN_15 ( ( XIOU_SLCR_BASEADDR ) + 0x0000003CUL ) +#define XIOU_SLCR_MIO_PIN_15_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin16 + */ +#define XIOU_SLCR_MIO_PIN_16 ( ( XIOU_SLCR_BASEADDR ) + 0x00000040UL ) +#define XIOU_SLCR_MIO_PIN_16_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin17 + */ +#define XIOU_SLCR_MIO_PIN_17 ( ( XIOU_SLCR_BASEADDR ) + 0x00000044UL ) +#define XIOU_SLCR_MIO_PIN_17_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin18 + */ +#define XIOU_SLCR_MIO_PIN_18 ( ( XIOU_SLCR_BASEADDR ) + 0x00000048UL ) +#define XIOU_SLCR_MIO_PIN_18_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin19 + */ +#define XIOU_SLCR_MIO_PIN_19 ( ( XIOU_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XIOU_SLCR_MIO_PIN_19_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin20 + */ +#define XIOU_SLCR_MIO_PIN_20 ( ( XIOU_SLCR_BASEADDR ) + 0x00000050UL ) +#define XIOU_SLCR_MIO_PIN_20_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin21 + */ +#define XIOU_SLCR_MIO_PIN_21 ( ( XIOU_SLCR_BASEADDR ) + 0x00000054UL ) +#define XIOU_SLCR_MIO_PIN_21_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin22 + */ +#define XIOU_SLCR_MIO_PIN_22 ( ( XIOU_SLCR_BASEADDR ) + 0x00000058UL ) +#define XIOU_SLCR_MIO_PIN_22_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin23 + */ +#define XIOU_SLCR_MIO_PIN_23 ( ( XIOU_SLCR_BASEADDR ) + 0x0000005CUL ) +#define XIOU_SLCR_MIO_PIN_23_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin24 + */ +#define XIOU_SLCR_MIO_PIN_24 ( ( XIOU_SLCR_BASEADDR ) + 0x00000060UL ) +#define XIOU_SLCR_MIO_PIN_24_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin25 + */ +#define XIOU_SLCR_MIO_PIN_25 ( ( XIOU_SLCR_BASEADDR ) + 0x00000064UL ) +#define XIOU_SLCR_MIO_PIN_25_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin26 + */ +#define XIOU_SLCR_MIO_PIN_26 ( ( XIOU_SLCR_BASEADDR ) + 0x00000068UL ) +#define XIOU_SLCR_MIO_PIN_26_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin27 + */ +#define XIOU_SLCR_MIO_PIN_27 ( ( XIOU_SLCR_BASEADDR ) + 0x0000006CUL ) +#define XIOU_SLCR_MIO_PIN_27_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin28 + */ +#define XIOU_SLCR_MIO_PIN_28 ( ( XIOU_SLCR_BASEADDR ) + 0x00000070UL ) +#define XIOU_SLCR_MIO_PIN_28_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin29 + */ +#define XIOU_SLCR_MIO_PIN_29 ( ( XIOU_SLCR_BASEADDR ) + 0x00000074UL ) +#define XIOU_SLCR_MIO_PIN_29_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin30 + */ +#define XIOU_SLCR_MIO_PIN_30 ( ( XIOU_SLCR_BASEADDR ) + 0x00000078UL ) +#define XIOU_SLCR_MIO_PIN_30_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin31 + */ +#define XIOU_SLCR_MIO_PIN_31 ( ( XIOU_SLCR_BASEADDR ) + 0x0000007CUL ) +#define XIOU_SLCR_MIO_PIN_31_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin32 + */ +#define XIOU_SLCR_MIO_PIN_32 ( ( XIOU_SLCR_BASEADDR ) + 0x00000080UL ) +#define XIOU_SLCR_MIO_PIN_32_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin33 + */ +#define XIOU_SLCR_MIO_PIN_33 ( ( XIOU_SLCR_BASEADDR ) + 0x00000084UL ) +#define XIOU_SLCR_MIO_PIN_33_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin34 + */ +#define XIOU_SLCR_MIO_PIN_34 ( ( XIOU_SLCR_BASEADDR ) + 0x00000088UL ) +#define XIOU_SLCR_MIO_PIN_34_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin35 + */ +#define XIOU_SLCR_MIO_PIN_35 ( ( XIOU_SLCR_BASEADDR ) + 0x0000008CUL ) +#define XIOU_SLCR_MIO_PIN_35_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin36 + */ +#define XIOU_SLCR_MIO_PIN_36 ( ( XIOU_SLCR_BASEADDR ) + 0x00000090UL ) +#define XIOU_SLCR_MIO_PIN_36_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin37 + */ +#define XIOU_SLCR_MIO_PIN_37 ( ( XIOU_SLCR_BASEADDR ) + 0x00000094UL ) +#define XIOU_SLCR_MIO_PIN_37_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin38 + */ +#define XIOU_SLCR_MIO_PIN_38 ( ( XIOU_SLCR_BASEADDR ) + 0x00000098UL ) +#define XIOU_SLCR_MIO_PIN_38_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin39 + */ +#define XIOU_SLCR_MIO_PIN_39 ( ( XIOU_SLCR_BASEADDR ) + 0x0000009CUL ) +#define XIOU_SLCR_MIO_PIN_39_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin40 + */ +#define XIOU_SLCR_MIO_PIN_40 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A0UL ) +#define XIOU_SLCR_MIO_PIN_40_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin41 + */ +#define XIOU_SLCR_MIO_PIN_41 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A4UL ) +#define XIOU_SLCR_MIO_PIN_41_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin42 + */ +#define XIOU_SLCR_MIO_PIN_42 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A8UL ) +#define XIOU_SLCR_MIO_PIN_42_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin43 + */ +#define XIOU_SLCR_MIO_PIN_43 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ACUL ) +#define XIOU_SLCR_MIO_PIN_43_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin44 + */ +#define XIOU_SLCR_MIO_PIN_44 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B0UL ) +#define XIOU_SLCR_MIO_PIN_44_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin45 + */ +#define XIOU_SLCR_MIO_PIN_45 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B4UL ) +#define XIOU_SLCR_MIO_PIN_45_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin46 + */ +#define XIOU_SLCR_MIO_PIN_46 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B8UL ) +#define XIOU_SLCR_MIO_PIN_46_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin47 + */ +#define XIOU_SLCR_MIO_PIN_47 ( ( XIOU_SLCR_BASEADDR ) + 0x000000BCUL ) +#define XIOU_SLCR_MIO_PIN_47_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin48 + */ +#define XIOU_SLCR_MIO_PIN_48 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C0UL ) +#define XIOU_SLCR_MIO_PIN_48_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin49 + */ +#define XIOU_SLCR_MIO_PIN_49 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C4UL ) +#define XIOU_SLCR_MIO_PIN_49_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin50 + */ +#define XIOU_SLCR_MIO_PIN_50 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C8UL ) +#define XIOU_SLCR_MIO_PIN_50_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin51 + */ +#define XIOU_SLCR_MIO_PIN_51 ( ( XIOU_SLCR_BASEADDR ) + 0x000000CCUL ) +#define XIOU_SLCR_MIO_PIN_51_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin52 + */ +#define XIOU_SLCR_MIO_PIN_52 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D0UL ) +#define XIOU_SLCR_MIO_PIN_52_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin53 + */ +#define XIOU_SLCR_MIO_PIN_53 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D4UL ) +#define XIOU_SLCR_MIO_PIN_53_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin54 + */ +#define XIOU_SLCR_MIO_PIN_54 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D8UL ) +#define XIOU_SLCR_MIO_PIN_54_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin55 + */ +#define XIOU_SLCR_MIO_PIN_55 ( ( XIOU_SLCR_BASEADDR ) + 0x000000DCUL ) +#define XIOU_SLCR_MIO_PIN_55_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin56 + */ +#define XIOU_SLCR_MIO_PIN_56 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E0UL ) +#define XIOU_SLCR_MIO_PIN_56_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin57 + */ +#define XIOU_SLCR_MIO_PIN_57 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E4UL ) +#define XIOU_SLCR_MIO_PIN_57_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin58 + */ +#define XIOU_SLCR_MIO_PIN_58 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E8UL ) +#define XIOU_SLCR_MIO_PIN_58_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin59 + */ +#define XIOU_SLCR_MIO_PIN_59 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ECUL ) +#define XIOU_SLCR_MIO_PIN_59_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin60 + */ +#define XIOU_SLCR_MIO_PIN_60 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F0UL ) +#define XIOU_SLCR_MIO_PIN_60_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin61 + */ +#define XIOU_SLCR_MIO_PIN_61 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F4UL ) +#define XIOU_SLCR_MIO_PIN_61_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin62 + */ +#define XIOU_SLCR_MIO_PIN_62 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F8UL ) +#define XIOU_SLCR_MIO_PIN_62_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin63 + */ +#define XIOU_SLCR_MIO_PIN_63 ( ( XIOU_SLCR_BASEADDR ) + 0x000000FCUL ) +#define XIOU_SLCR_MIO_PIN_63_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin64 + */ +#define XIOU_SLCR_MIO_PIN_64 ( ( XIOU_SLCR_BASEADDR ) + 0x00000100UL ) +#define XIOU_SLCR_MIO_PIN_64_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin65 + */ +#define XIOU_SLCR_MIO_PIN_65 ( ( XIOU_SLCR_BASEADDR ) + 0x00000104UL ) +#define XIOU_SLCR_MIO_PIN_65_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin66 + */ +#define XIOU_SLCR_MIO_PIN_66 ( ( XIOU_SLCR_BASEADDR ) + 0x00000108UL ) +#define XIOU_SLCR_MIO_PIN_66_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin67 + */ +#define XIOU_SLCR_MIO_PIN_67 ( ( XIOU_SLCR_BASEADDR ) + 0x0000010CUL ) +#define XIOU_SLCR_MIO_PIN_67_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin68 + */ +#define XIOU_SLCR_MIO_PIN_68 ( ( XIOU_SLCR_BASEADDR ) + 0x00000110UL ) +#define XIOU_SLCR_MIO_PIN_68_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin69 + */ +#define XIOU_SLCR_MIO_PIN_69 ( ( XIOU_SLCR_BASEADDR ) + 0x00000114UL ) +#define XIOU_SLCR_MIO_PIN_69_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin70 + */ +#define XIOU_SLCR_MIO_PIN_70 ( ( XIOU_SLCR_BASEADDR ) + 0x00000118UL ) +#define XIOU_SLCR_MIO_PIN_70_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin71 + */ +#define XIOU_SLCR_MIO_PIN_71 ( ( XIOU_SLCR_BASEADDR ) + 0x0000011CUL ) +#define XIOU_SLCR_MIO_PIN_71_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin72 + */ +#define XIOU_SLCR_MIO_PIN_72 ( ( XIOU_SLCR_BASEADDR ) + 0x00000120UL ) +#define XIOU_SLCR_MIO_PIN_72_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin73 + */ +#define XIOU_SLCR_MIO_PIN_73 ( ( XIOU_SLCR_BASEADDR ) + 0x00000124UL ) +#define XIOU_SLCR_MIO_PIN_73_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin74 + */ +#define XIOU_SLCR_MIO_PIN_74 ( ( XIOU_SLCR_BASEADDR ) + 0x00000128UL ) +#define XIOU_SLCR_MIO_PIN_74_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin75 + */ +#define XIOU_SLCR_MIO_PIN_75 ( ( XIOU_SLCR_BASEADDR ) + 0x0000012CUL ) +#define XIOU_SLCR_MIO_PIN_75_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin76 + */ +#define XIOU_SLCR_MIO_PIN_76 ( ( XIOU_SLCR_BASEADDR ) + 0x00000130UL ) +#define XIOU_SLCR_MIO_PIN_76_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin77 + */ +#define XIOU_SLCR_MIO_PIN_77 ( ( XIOU_SLCR_BASEADDR ) + 0x00000134UL ) +#define XIOU_SLCR_MIO_PIN_77_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl0 + */ +#define XIOU_SLCR_BANK0_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000138UL ) +#define XIOU_SLCR_BANK0_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl1 + */ +#define XIOU_SLCR_BANK0_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000013CUL ) +#define XIOU_SLCR_BANK0_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl3 + */ +#define XIOU_SLCR_BANK0_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000140UL ) +#define XIOU_SLCR_BANK0_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl4 + */ +#define XIOU_SLCR_BANK0_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000144UL ) +#define XIOU_SLCR_BANK0_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl5 + */ +#define XIOU_SLCR_BANK0_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000148UL ) +#define XIOU_SLCR_BANK0_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl6 + */ +#define XIOU_SLCR_BANK0_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x0000014CUL ) +#define XIOU_SLCR_BANK0_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Sts + */ +#define XIOU_SLCR_BANK0_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000150UL ) +#define XIOU_SLCR_BANK0_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl0 + */ +#define XIOU_SLCR_BANK1_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000154UL ) +#define XIOU_SLCR_BANK1_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl1 + */ +#define XIOU_SLCR_BANK1_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000158UL ) +#define XIOU_SLCR_BANK1_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl3 + */ +#define XIOU_SLCR_BANK1_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000015CUL ) +#define XIOU_SLCR_BANK1_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl4 + */ +#define XIOU_SLCR_BANK1_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000160UL ) +#define XIOU_SLCR_BANK1_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl5 + */ +#define XIOU_SLCR_BANK1_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000164UL ) +#define XIOU_SLCR_BANK1_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl6 + */ +#define XIOU_SLCR_BANK1_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000168UL ) +#define XIOU_SLCR_BANK1_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Sts + */ +#define XIOU_SLCR_BANK1_STS ( ( XIOU_SLCR_BASEADDR ) + 0x0000016CUL ) +#define XIOU_SLCR_BANK1_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl0 + */ +#define XIOU_SLCR_BANK2_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000170UL ) +#define XIOU_SLCR_BANK2_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl1 + */ +#define XIOU_SLCR_BANK2_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000174UL ) +#define XIOU_SLCR_BANK2_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl3 + */ +#define XIOU_SLCR_BANK2_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000178UL ) +#define XIOU_SLCR_BANK2_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl4 + */ +#define XIOU_SLCR_BANK2_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x0000017CUL ) +#define XIOU_SLCR_BANK2_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl5 + */ +#define XIOU_SLCR_BANK2_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000180UL ) +#define XIOU_SLCR_BANK2_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl6 + */ +#define XIOU_SLCR_BANK2_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000184UL ) +#define XIOU_SLCR_BANK2_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Sts + */ +#define XIOU_SLCR_BANK2_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000188UL ) +#define XIOU_SLCR_BANK2_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioLpbck + */ +#define XIOU_SLCR_MIO_LPBCK ( ( XIOU_SLCR_BASEADDR ) + 0x00000200UL ) +#define XIOU_SLCR_MIO_LPBCK_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_SHIFT 3UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_MASK 0x00000008UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT 2UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK 0x00000004UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT 1UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK 0x00000002UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_SHIFT 0UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_MASK 0x00000001UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioMstTri0 + */ +#define XIOU_SLCR_MIO_MST_TRI0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000204UL ) +#define XIOU_SLCR_MIO_MST_TRI0_RSTVAL 0xffffffffUL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrMioMstTri1 + */ +#define XIOU_SLCR_MIO_MST_TRI1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000208UL ) +#define XIOU_SLCR_MIO_MST_TRI1_RSTVAL 0xffffffffUL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrMioMstTri2 + */ +#define XIOU_SLCR_MIO_MST_TRI2 ( ( XIOU_SLCR_BASEADDR ) + 0x0000020CUL ) +#define XIOU_SLCR_MIO_MST_TRI2_RSTVAL 0x00003fffUL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrWdtClkSel + */ +#define XIOU_SLCR_WDT_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000300UL ) +#define XIOU_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_WDT_CLK_SEL_SHIFT 0UL +#define XIOU_SLCR_WDT_CLK_SEL_WIDTH 1UL +#define XIOU_SLCR_WDT_CLK_SEL_MASK 0x00000001UL +#define XIOU_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrCanMioCtrl + */ +#define XIOU_SLCR_CAN_MIO_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000304UL ) +#define XIOU_SLCR_CAN_MIO_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT 23UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK 0x00800000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT 22UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK 0x00400000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT 15UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK 0x003f8000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT 8UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK 0x00000100UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK 0x00000080UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT 0UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK 0x0000007fUL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL 0x0UL + +/** + * Register: XiouSlcrGemClkCtrl + */ +#define XIOU_SLCR_GEM_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000308UL ) +#define XIOU_SLCR_GEM_CLK_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT 22UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK 0x00400000UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT 20UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH 2UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK 0x00300000UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 18UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00040000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 17UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00020000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 16UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00010000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 15UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00008000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 13UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00002000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 12UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00001000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 11UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000800UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 10UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000400UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 8UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000100UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 7UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000080UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 6UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000040UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 5UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000020UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 3UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000008UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 2UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000004UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000002UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 0UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000001UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdioClkCtrl + */ +#define XIOU_SLCR_SDIO_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000030CUL ) +#define XIOU_SLCR_SDIO_CLK_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT 18UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_MASK 0x00040000UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT 2UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_MASK 0x00000004UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT 0UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH 2UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK 0x00000003UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrCtrlRegSd + */ +#define XIOU_SLCR_CTRL_REG_SD ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL ) +#define XIOU_SLCR_CTRL_REG_SD_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 15UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00008000UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 0UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00000001UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdItapdly + */ +#define XIOU_SLCR_SD_ITAPDLY ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL ) +#define XIOU_SLCR_SD_ITAPDLY_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 25UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x02000000UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 24UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x01000000UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 16UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 9UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x00000200UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 8UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x00000100UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 0UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x000000ffUL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdOtapdlysel + */ +#define XIOU_SLCR_SD_OTAPDLYSEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL ) +#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 22UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00400000UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x003f0000UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 6UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00000040UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x0000003fUL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg1 + */ +#define XIOU_SLCR_SD_CFG_REG1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL ) +#define XIOU_SLCR_SD_CFG_REG1_RSTVAL 0x32403240UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 23UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x7f800000UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 17UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x007e0000UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 16UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00010000UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 7UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x00007f80UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 1UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x0000007eUL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 0UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00000001UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg2 + */ +#define XIOU_SLCR_SD_CFG_REG2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL ) +#define XIOU_SLCR_SD_CFG_REG2_RSTVAL 0x0ffc0ffcUL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 28UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x30000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 27UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x08000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 26UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x04000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 25UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x02000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 24UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x01000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 23UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00800000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 22UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00400000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 21UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00200000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 20UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00100000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 19UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00080000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 18UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00040000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 16UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00030000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 12UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x00003000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 11UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x00000800UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 10UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x00000400UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 9UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x00000200UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 8UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x00000100UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 7UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00000080UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 6UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00000040UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 5UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00000020UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 4UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00000010UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 3UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00000008UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00000004UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 0UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00000003UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg3 + */ +#define XIOU_SLCR_SD_CFG_REG3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL ) +#define XIOU_SLCR_SD_CFG_REG3_RSTVAL 0x06070607UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 26UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x04000000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 22UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x03c00000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 21UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00200000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 20UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00100000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 19UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00080000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 18UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00040000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 17UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00020000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 16UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00010000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 10UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x00000400UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 6UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x000003c0UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 5UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00000020UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 4UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00000010UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 3UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00000008UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 2UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00000004UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00000002UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 0UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00000001UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL + +/** + * Register: XiouSlcrSdInitpreset + */ +#define XIOU_SLCR_SD_INITPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL ) +#define XIOU_SLCR_SD_INITPRESET_RSTVAL 0x01000100UL + +#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL + +#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL + +/** + * Register: XiouSlcrSdDsppreset + */ +#define XIOU_SLCR_SD_DSPPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL ) +#define XIOU_SLCR_SD_DSPPRESET_RSTVAL 0x00040004UL + +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL + +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL + +/** + * Register: XiouSlcrSdHspdpreset + */ +#define XIOU_SLCR_SD_HSPDPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL ) +#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdSdr12preset + */ +#define XIOU_SLCR_SD_SDR12PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL ) +#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL 0x00040004UL + +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL + +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL + +/** + * Register: XiouSlcrSdSdr25preset + */ +#define XIOU_SLCR_SD_SDR25PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL ) +#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdSdr50prset + */ +#define XIOU_SLCR_SD_SDR50PRSET ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL ) +#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL 0x00010001UL + +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 16UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 0UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL + +/** + * Register: XiouSlcrSdSdr104prst + */ +#define XIOU_SLCR_SD_SDR104PRST ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL ) +#define XIOU_SLCR_SD_SDR104PRST_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 16UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 0UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdDdr50preset + */ +#define XIOU_SLCR_SD_DDR50PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL ) +#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdMaxcur1p8 + */ +#define XIOU_SLCR_SD_MAXCUR1P8 ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL ) +#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdMaxcur3p0 + */ +#define XIOU_SLCR_SD_MAXCUR3P0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL ) +#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdMaxcur3p3 + */ +#define XIOU_SLCR_SD_MAXCUR3P3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL ) +#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdDllCtrl + */ +#define XIOU_SLCR_SD_DLL_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL ) +#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 18UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00040000UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 17UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00020000UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 16UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00010000UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 2UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00000004UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00000002UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 0UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00000001UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCdnCtrl + */ +#define XIOU_SLCR_SD_CDN_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL ) +#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00010000UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00000001UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrGemCtrl + */ +#define XIOU_SLCR_GEM_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL ) +#define XIOU_SLCR_GEM_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 6UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x000000c0UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 4UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000030UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x0000000cUL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 0UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000003UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +/** + * Register: XiouSlcrTtcApbClk + */ +#define XIOU_SLCR_TTC_APB_CLK ( ( XIOU_SLCR_BASEADDR ) + 0x00000380UL ) +#define XIOU_SLCR_TTC_APB_CLK_RSTVAL 0x00000000UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT 6UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK 0x000000c0UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT 4UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000cUL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT 0UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrTapdlyBypass + */ +#define XIOU_SLCR_TAPDLY_BYPASS ( ( XIOU_SLCR_BASEADDR ) + 0x00000390UL ) +#define XIOU_SLCR_TAPDLY_BYPASS_RSTVAL 0x00000007UL + +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x1UL + +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_SHIFT 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_MASK 0x00000002UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_DEFVAL 0x1UL + +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_SHIFT 0UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_MASK 0x00000001UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_DEFVAL 0x1UL + +/** + * Register: XiouSlcrCoherentCtrl + */ +#define XIOU_SLCR_COHERENT_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000400UL ) +#define XIOU_SLCR_COHERENT_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT 28UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_MASK 0xf0000000UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_SHIFT 24UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK 0x0f000000UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 20UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x00f00000UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 16UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x000f0000UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 12UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000f000UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 8UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x00000f00UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x000000f0UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 0UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000000fUL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +/** + * Register: XiouSlcrVideoPssClkSel + */ +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000404UL ) +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_SHIFT 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_WIDTH 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_MASK 0x00000002UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_DEFVAL 0x0UL + +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_SHIFT 0UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_WIDTH 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_MASK 0x00000001UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrInterconnectRoute + */ +#define XIOU_SLCR_INTERCONNECT_ROUTE ( ( XIOU_SLCR_BASEADDR ) + 0x00000408UL ) +#define XIOU_SLCR_INTERCONNECT_ROUTE_RSTVAL 0x00000000UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_SHIFT 7UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_MASK 0x00000080UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_SHIFT 6UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK 0x00000040UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 5UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000020UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 4UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000010UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 3UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000008UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 2UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000004UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000002UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 0UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000001UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXsdps + */ +#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL ) +#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXsdps + */ +#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL ) +#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamCan0 + */ +#define XIOU_SLCR_RAM_CAN0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000518UL ) +#define XIOU_SLCR_RAM_CAN0_RSTVAL 0x005b5b5bUL + +#define XIOU_SLCR_RAM_CAN0_EMASA2_SHIFT 22UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_MASK 0x00400000UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB2_SHIFT 19UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_MASK 0x00380000UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA2_SHIFT 16UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_MASK 0x00070000UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamCan1 + */ +#define XIOU_SLCR_RAM_CAN1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000051CUL ) +#define XIOU_SLCR_RAM_CAN1_RSTVAL 0x005b5b5bUL + +#define XIOU_SLCR_RAM_CAN1_EMASA2_SHIFT 22UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_MASK 0x00400000UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB2_SHIFT 19UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_MASK 0x00380000UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA2_SHIFT 16UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_MASK 0x00070000UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamLqspi + */ +#define XIOU_SLCR_RAM_LQSPI ( ( XIOU_SLCR_BASEADDR ) + 0x00000520UL ) +#define XIOU_SLCR_RAM_LQSPI_RSTVAL 0x00002ddbUL + +#define XIOU_SLCR_RAM_LQSPI_EMASA1_SHIFT 13UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_MASK 0x00002000UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_LQSPI_EMAB1_SHIFT 10UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_MASK 0x00001c00UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMAA1_SHIFT 7UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_MASK 0x00000380UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_LQSPI_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXnandps8 + */ +#define XIOU_SLCR_RAM_XNANDPS8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000524UL ) +#define XIOU_SLCR_RAM_XNANDPS8_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrCtrl + */ +#define XIOU_SLCR_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000600UL ) +#define XIOU_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XIOU_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XIOU_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XiouSlcrIsr + */ +#define XIOU_SLCR_ISR ( ( XIOU_SLCR_BASEADDR ) + 0x00000700UL ) +#define XIOU_SLCR_ISR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrImr + */ +#define XIOU_SLCR_IMR ( ( XIOU_SLCR_BASEADDR ) + 0x00000704UL ) +#define XIOU_SLCR_IMR_RSTVAL 0x00000001UL + +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XiouSlcrIer + */ +#define XIOU_SLCR_IER ( ( XIOU_SLCR_BASEADDR ) + 0x00000708UL ) +#define XIOU_SLCR_IER_RSTVAL 0x00000000UL + +#define XIOU_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrIdr + */ +#define XIOU_SLCR_IDR ( ( XIOU_SLCR_BASEADDR ) + 0x0000070CUL ) +#define XIOU_SLCR_IDR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrItr + */ +#define XIOU_SLCR_ITR ( ( XIOU_SLCR_BASEADDR ) + 0x00000710UL ) +#define XIOU_SLCR_ITR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XIOU_SLCR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xipipsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xipipsu.h new file mode 100644 index 000000000..81edd534d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xipipsu.h @@ -0,0 +1,277 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * @file xipipsu.h + * + * This is the header file for implementation of IPIPSU driver. + * Inter Processor Interrupt (IPI) is used for communication between + * different processors on ZynqMP SoC. Each IPI register set has Trigger, Status + * and Observation registers for communication between processors. Each IPI path + * has a 32 byte buffer associated with it and these buffers are located in the + * XPPU RAM. This driver supports the following operations: + * + * - Trigger IPIs to CPUs on the SoC + * - Write and Read Message buffers + * - Read the status of Observation Register to get status of Triggered IPI + * - Enable/Disable IPIs from selected Masters + * - Read the Status register to get the source of an incoming IPI + * + * Initialization + * The config data for the driver is loaded and is based on the HW build. The + * XIpiPsu_Config data structure contains all the data related to the + * IPI driver instance and also teh available Target CPUs. + * + * Sending an IPI + * The following steps can be followed to send an IPI: + * - Write the Message into Message Buffer using XIpiPsu_WriteMessage() + * - Trigger IPI using XIpiPsu_TriggerIpi() + * - Wait for Ack using XIpiPsu_PollForAck() + * - Read response using XIpiPsu_ReadMessage() + * + * @note XIpiPsu_GetObsStatus() before sending an IPI to ensure that the + * previous IPI was serviced by the target + * + * Receiving an IPI + * To receive an IPI, the following sequence can be followed: + * - Register an interrupt handler for the IPIs interrupt ID + * - Enable the required sources using XIpiPsu_InterruptEnable() + * - In the interrupt handler, Check for source using XIpiPsu_GetInterruptStatus + * - Read the message form source using XIpiPsu_ReadMessage() + * - Write the response using XIpiPsu_WriteMessage() + * - Ack the IPI using XIpiPsu_ClearInterruptStatus() + * + * @note XIpiPsu_Reset can be used at startup to clear the status and + * disable all sources + * + */ +/*****************************************************************************/ +#ifndef XIPIPSU_H_ +#define XIPIPSU_H_ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "xstatus.h" +#include "xipipsu_hw.h" + +/************************** Constant Definitions *****************************/ +#define XIPIPSU_BUF_TYPE_MSG (0x00000001U) +#define XIPIPSU_BUF_TYPE_RESP (0x00000002U) +#define XIPIPSU_MAX_MSG_LEN XIPIPSU_MSG_BUF_SIZE +/**************************** Type Definitions *******************************/ +/** + * Data structure used to refer IPI Targets + */ +typedef struct { + u32 Mask; /**< Bit Mask for the target */ + u32 BufferIndex; /**< Buffer Index used for calculating buffer address */ +} XIpiPsu_Target; + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u32 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 BitMask; /**< BitMask to be used to identify this CPU */ + u32 BufferIndex; /**< Index of the IPI Message Buffer */ + u32 IntId; /**< Interrupt ID on GIC **/ + u32 TargetCount; /**< Number of available IPI Targets */ + XIpiPsu_Target TargetList[XIPIPSU_MAX_TARGETS] ; /** < List of IPI Targets */ +} XIpiPsu_Config; + +/** + * The XIpiPsu driver instance data. The user is required to allocate a + * variable of this type for each IPI device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XIpiPsu_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + u32 Options; /**< Options set in the device */ +} XIpiPsu; + +/***************** Macros (Inline Functions) Definitions *********************/ +/** +* +* Read the register specified by the base address and offset +* +* @param BaseAddress is the base address of the IPI instance +* @param RegOffset is the offset of the register relative to base +* +* @return Value of the specified register +* @note +* C-style signature +* u32 XIpiPsu_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ + +#define XIpiPsu_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write a value into a register specified by base address and offset +* +* @param BaseAddress is the base address of the IPI instance +* @param RegOffset is the offset of the register relative to base +* @param Data is a 32-bit value that is to be written into the specified register +* +* @note +* C-style signature +* void XIpiPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +*****************************************************************************/ + +#define XIpiPsu_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32(((BaseAddress) + (RegOffset)), (Data)) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values of individual CPU masks +* +* @note +* C-style signature +* void XIpiPsu_InterruptEnable(XIpiPsu *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XIpiPsu_InterruptEnable(InstancePtr, Mask) \ + XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + XIPIPSU_IER_OFFSET, \ + ((Mask) & XIPIPSU_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be disabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values of individual CPU masks +* +* @note +* C-style signature +* void XIpiPsu_InterruptDisable(XIpiPsu *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XIpiPsu_InterruptDisable(InstancePtr, Mask) \ + XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + XIPIPSU_IDR_OFFSET, \ + ((Mask) & XIPIPSU_ALL_MASK)); +/****************************************************************************/ +/** +* +* Get the STATUS REGISTER of the current IPI instance. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @return Returns the Interrupt Status register(ISR) contents +* @note User needs to parse this 32-bit value to check the source CPU +* C-style signature +* u32 XIpiPsu_GetInterruptStatus(XIpiPsu *InstancePtr) +* +*****************************************************************************/ +#define XIpiPsu_GetInterruptStatus(InstancePtr) \ + XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \ + XIPIPSU_ISR_OFFSET) +/****************************************************************************/ +/** +* +* Clear the STATUS REGISTER of the current IPI instance. +* The corresponding interrupt status for +* each bit set to 1 in Mask, will be cleared +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask corresponding to the source CPU* +* +* @note This function should be used after handling the IPI. +* Clearing the status will automatically clear the corresponding bit in +* OBSERVATION register of Source CPU +* C-style signature +* void XIpiPsu_ClearInterruptStatus(XIpiPsu *InstancePtr, u32 Mask) +* +*****************************************************************************/ + +#define XIpiPsu_ClearInterruptStatus(InstancePtr, Mask) \ + XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + XIPIPSU_ISR_OFFSET, \ + ((Mask) & XIPIPSU_ALL_MASK)); +/****************************************************************************/ +/** +* +* Get the OBSERVATION REGISTER of the current IPI instance. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @return Returns the Observation register(OBS) contents +* @note User needs to parse this 32-bit value to check the status of +* individual CPUs +* C-style signature +* u32 XIpiPsu_GetObsStatus(XIpiPsu *InstancePtr) +* +*****************************************************************************/ +#define XIpiPsu_GetObsStatus(InstancePtr) \ + XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \ + XIPIPSU_OBS_OFFSET) +/****************************************************************************/ +/************************** Function Prototypes *****************************/ + +/* Static lookup function implemented in xipipsu_sinit.c */ + +XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId); + +/* Interface Functions implemented in xipipsu.c */ + +XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr, + UINTPTR EffectiveAddress); + +void XIpiPsu_Reset(XIpiPsu *InstancePtr); + +XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask); + +XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask, + u32 TimeOutCount); + +XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr, + u32 MsgLength, u8 BufType); + +XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr, + u32 MsgLength, u8 BufType); + +#endif /* XIPIPSU_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xipipsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xipipsu_hw.h new file mode 100644 index 000000000..2f3fb0830 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xipipsu_hw.h @@ -0,0 +1,76 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/** +* +* @file xipipsu_hw.h +* +* This file contains macro definitions for low level HW related params +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   mjr  03/15/15 First release
+*
+*
+* +******************************************************************************/ +#ifndef XIPIPSU_HW_H_ /* prevent circular inclusions */ +#define XIPIPSU_HW_H_ /* by using protection macros */ + +/************************** Constant Definitions *****************************/ +/* Message RAM related params */ +#define XIPIPSU_MSG_RAM_BASE 0xFF990000U +#define XIPIPSU_MSG_BUF_SIZE 8U /* Size in Words */ +#define XIPIPSU_MAX_BUFF_INDEX 7 + +/* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */ +#define XIPIPSU_BUFFER_OFFSET_GROUP (8U * 2U * 32U) +#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U) +#define XIPIPSU_BUFFER_OFFSET_RESPONSE (32U) + +/* Max Number of IPI slots on the device */ +#define XIPIPSU_MAX_TARGETS 11 + +/* Register Offsets for each member of IPI Register Set */ +#define XIPIPSU_TRIG_OFFSET 0x00U +#define XIPIPSU_OBS_OFFSET 0x04U +#define XIPIPSU_ISR_OFFSET 0x10U +#define XIPIPSU_IMR_OFFSET 0x14U +#define XIPIPSU_IER_OFFSET 0x18U +#define XIPIPSU_IDR_OFFSET 0x1CU + +/* MASK of all valid IPI bits in above registers */ +#define XIPIPSU_ALL_MASK 0x0F0F0301U + +#endif /* XIPIPSU_HW_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_slcr.h new file mode 100644 index 000000000..cc05672e4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_slcr.h @@ -0,0 +1,5667 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_SLCR_H__ +#define __XLPD_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdSlcr Base Address + */ +#define XLPD_SLCR_BASEADDR 0xFF410000UL + +/** + * Register: XlpdSlcrWprot0 + */ +#define XLPD_SLCR_WPROT0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL ) +#define XLPD_SLCR_WPROT0_RSTVAL 0x00000001UL + +#define XLPD_SLCR_WPROT0_ACT_SHIFT 0UL +#define XLPD_SLCR_WPROT0_ACT_WIDTH 1UL +#define XLPD_SLCR_WPROT0_ACT_MASK 0x00000001UL +#define XLPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrCtrl + */ +#define XLPD_SLCR_CTRL ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL ) +#define XLPD_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XLPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsr + */ +#define XLPD_SLCR_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL ) +#define XLPD_SLCR_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrImr + */ +#define XLPD_SLCR_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XLPD_SLCR_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIer + */ +#define XLPD_SLCR_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL ) +#define XLPD_SLCR_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIdr + */ +#define XLPD_SLCR_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL ) +#define XLPD_SLCR_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrItr + */ +#define XLPD_SLCR_ITR ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL ) +#define XLPD_SLCR_ITR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk0 + */ +#define XLPD_SLCR_SAFETY_CHK0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000040UL ) +#define XLPD_SLCR_SAFETY_CHK0_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK0_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK0_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK0_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK0_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk1 + */ +#define XLPD_SLCR_SAFETY_CHK1 ( ( XLPD_SLCR_BASEADDR ) + 0x00000044UL ) +#define XLPD_SLCR_SAFETY_CHK1_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK1_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK1_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK1_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK1_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk2 + */ +#define XLPD_SLCR_SAFETY_CHK2 ( ( XLPD_SLCR_BASEADDR ) + 0x00000048UL ) +#define XLPD_SLCR_SAFETY_CHK2_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK2_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK2_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK2_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK2_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk3 + */ +#define XLPD_SLCR_SAFETY_CHK3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XLPD_SLCR_SAFETY_CHK3_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK3_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK3_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK3_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK3_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrXcsupmuWdtClkSel + */ +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL ( ( XLPD_SLCR_BASEADDR ) + 0x00000050UL ) +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_SHIFT 0UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_WIDTH 1UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_MASK 0x00000001UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAdmaCfg + */ +#define XLPD_SLCR_ADMA_CFG ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL ) +#define XLPD_SLCR_ADMA_CFG_RSTVAL 0x00000028UL + +#define XLPD_SLCR_ADMA_CFG_BUSWID_SHIFT 5UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_WIDTH 2UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_MASK 0x00000060UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT 0UL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH 5UL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK 0x0000001fUL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL 0x8UL + +/** + * Register: XlpdSlcrAdmaRam + */ +#define XLPD_SLCR_ADMA_RAM ( ( XLPD_SLCR_BASEADDR ) + 0x00002010UL ) +#define XLPD_SLCR_ADMA_RAM_RSTVAL 0x00003b3bUL + +#define XLPD_SLCR_ADMA_RAM1_EMAB_SHIFT 12UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_MASK 0x00007000UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM1_EMASA_SHIFT 11UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_WIDTH 1UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_MASK 0x00000800UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_RAM1_EMAA_SHIFT 8UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_MASK 0x00000700UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM0_EMAB_SHIFT 4UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_MASK 0x00000070UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM0_EMASA_SHIFT 3UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_WIDTH 1UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_MASK 0x00000008UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_RAM0_EMAA_SHIFT 0UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_MASK 0x00000007UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrErrAibaxiIsr + */ +#define XLPD_SLCR_ERR_AIBAXI_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003000UL ) +#define XLPD_SLCR_ERR_AIBAXI_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibaxiImr + */ +#define XLPD_SLCR_ERR_AIBAXI_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003008UL ) +#define XLPD_SLCR_ERR_AIBAXI_IMR_RSTVAL 0x1dcf000fUL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAibaxiIer + */ +#define XLPD_SLCR_ERR_AIBAXI_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003010UL ) +#define XLPD_SLCR_ERR_AIBAXI_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibaxiIdr + */ +#define XLPD_SLCR_ERR_AIBAXI_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00003018UL ) +#define XLPD_SLCR_ERR_AIBAXI_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbIsr + */ +#define XLPD_SLCR_ERR_AIBAPB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003020UL ) +#define XLPD_SLCR_ERR_AIBAPB_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbImr + */ +#define XLPD_SLCR_ERR_AIBAPB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003024UL ) +#define XLPD_SLCR_ERR_AIBAPB_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAibapbIer + */ +#define XLPD_SLCR_ERR_AIBAPB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003028UL ) +#define XLPD_SLCR_ERR_AIBAPB_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbIdr + */ +#define XLPD_SLCR_ERR_AIBAPB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000302CUL ) +#define XLPD_SLCR_ERR_AIBAPB_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibaxiReq + */ +#define XLPD_SLCR_ISO_AIBAXI_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003030UL ) +#define XLPD_SLCR_ISO_AIBAXI_REQ_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibaxiType + */ +#define XLPD_SLCR_ISO_AIBAXI_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00003038UL ) +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RSTVAL 0x19cf000fUL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIsoAibaxiAck + */ +#define XLPD_SLCR_ISO_AIBAXI_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003040UL ) +#define XLPD_SLCR_ISO_AIBAXI_ACK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibapbReq + */ +#define XLPD_SLCR_ISO_AIBAPB_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003048UL ) +#define XLPD_SLCR_ISO_AIBAPB_REQ_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibapbType + */ +#define XLPD_SLCR_ISO_AIBAPB_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x0000304CUL ) +#define XLPD_SLCR_ISO_AIBAPB_TYPE_RSTVAL 0x00000001UL + +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIsoAibapbAck + */ +#define XLPD_SLCR_ISO_AIBAPB_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003050UL ) +#define XLPD_SLCR_ISO_AIBAPB_ACK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbIsr + */ +#define XLPD_SLCR_ERR_ATB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00006000UL ) +#define XLPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbImr + */ +#define XLPD_SLCR_ERR_ATB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00006004UL ) +#define XLPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAtbIer + */ +#define XLPD_SLCR_ERR_ATB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00006008UL ) +#define XLPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_IER_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbIdr + */ +#define XLPD_SLCR_ERR_ATB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000600CUL ) +#define XLPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAtbCmdStoreEn + */ +#define XLPD_SLCR_ATB_CMD_STORE_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006010UL ) +#define XLPD_SLCR_ATB_CMD_STORE_EN_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrAtbRespEn + */ +#define XLPD_SLCR_ATB_RESP_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006014UL ) +#define XLPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ATB_RESP_EN_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAtbRespType + */ +#define XLPD_SLCR_ATB_RESP_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00006018UL ) +#define XLPD_SLCR_ATB_RESP_TYPE_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrAtbPrescale + */ +#define XLPD_SLCR_ATB_PRESCALE ( ( XLPD_SLCR_BASEADDR ) + 0x00006020UL ) +#define XLPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL + +#define XLPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL +#define XLPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL +#define XLPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL +#define XLPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL + +#define XLPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL +#define XLPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL +#define XLPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL +#define XLPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL + +/** + * Register: XlpdSlcrMutex0 + */ +#define XLPD_SLCR_MUTEX0 ( ( XLPD_SLCR_BASEADDR ) + 0x00007000UL ) +#define XLPD_SLCR_MUTEX0_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX0_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX0_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX0_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX0_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex1 + */ +#define XLPD_SLCR_MUTEX1 ( ( XLPD_SLCR_BASEADDR ) + 0x00007004UL ) +#define XLPD_SLCR_MUTEX1_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX1_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX1_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX1_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX1_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex2 + */ +#define XLPD_SLCR_MUTEX2 ( ( XLPD_SLCR_BASEADDR ) + 0x00007008UL ) +#define XLPD_SLCR_MUTEX2_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX2_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX2_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX2_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX2_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex3 + */ +#define XLPD_SLCR_MUTEX3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000700CUL ) +#define XLPD_SLCR_MUTEX3_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX3_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX3_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX3_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX3_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqSts + */ +#define XLPD_SLCR_GICP0_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008000UL ) +#define XLPD_SLCR_GICP0_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqMsk + */ +#define XLPD_SLCR_GICP0_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008004UL ) +#define XLPD_SLCR_GICP0_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp0IrqEn + */ +#define XLPD_SLCR_GICP0_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008008UL ) +#define XLPD_SLCR_GICP0_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqDis + */ +#define XLPD_SLCR_GICP0_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000800CUL ) +#define XLPD_SLCR_GICP0_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqTrig + */ +#define XLPD_SLCR_GICP0_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008010UL ) +#define XLPD_SLCR_GICP0_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqSts + */ +#define XLPD_SLCR_GICP1_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008014UL ) +#define XLPD_SLCR_GICP1_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqMsk + */ +#define XLPD_SLCR_GICP1_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008018UL ) +#define XLPD_SLCR_GICP1_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp1IrqEn + */ +#define XLPD_SLCR_GICP1_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x0000801CUL ) +#define XLPD_SLCR_GICP1_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqDis + */ +#define XLPD_SLCR_GICP1_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008020UL ) +#define XLPD_SLCR_GICP1_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqTrig + */ +#define XLPD_SLCR_GICP1_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008024UL ) +#define XLPD_SLCR_GICP1_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqSts + */ +#define XLPD_SLCR_GICP2_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008028UL ) +#define XLPD_SLCR_GICP2_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqMsk + */ +#define XLPD_SLCR_GICP2_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x0000802CUL ) +#define XLPD_SLCR_GICP2_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp2IrqEn + */ +#define XLPD_SLCR_GICP2_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008030UL ) +#define XLPD_SLCR_GICP2_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqDis + */ +#define XLPD_SLCR_GICP2_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008034UL ) +#define XLPD_SLCR_GICP2_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqTrig + */ +#define XLPD_SLCR_GICP2_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008038UL ) +#define XLPD_SLCR_GICP2_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqSts + */ +#define XLPD_SLCR_GICP3_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x0000803CUL ) +#define XLPD_SLCR_GICP3_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqMsk + */ +#define XLPD_SLCR_GICP3_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008040UL ) +#define XLPD_SLCR_GICP3_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp3IrqEn + */ +#define XLPD_SLCR_GICP3_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008044UL ) +#define XLPD_SLCR_GICP3_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqDis + */ +#define XLPD_SLCR_GICP3_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008048UL ) +#define XLPD_SLCR_GICP3_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqTrig + */ +#define XLPD_SLCR_GICP3_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x0000804CUL ) +#define XLPD_SLCR_GICP3_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqSts + */ +#define XLPD_SLCR_GICP4_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008050UL ) +#define XLPD_SLCR_GICP4_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqMsk + */ +#define XLPD_SLCR_GICP4_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008054UL ) +#define XLPD_SLCR_GICP4_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp4IrqEn + */ +#define XLPD_SLCR_GICP4_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008058UL ) +#define XLPD_SLCR_GICP4_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqDis + */ +#define XLPD_SLCR_GICP4_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000805CUL ) +#define XLPD_SLCR_GICP4_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqTrig + */ +#define XLPD_SLCR_GICP4_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008060UL ) +#define XLPD_SLCR_GICP4_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqSts + */ +#define XLPD_SLCR_GICP_PMU_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x000080A0UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqMsk + */ +#define XLPD_SLCR_GICP_PMU_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x000080A4UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_RSTVAL 0x000000ffUL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicpPmuIrqEn + */ +#define XLPD_SLCR_GICP_PMU_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x000080A8UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqDis + */ +#define XLPD_SLCR_GICP_PMU_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x000080ACUL ) +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqTrig + */ +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x000080B0UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAfiFs + */ +#define XLPD_SLCR_AFI_FS ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL ) +#define XLPD_SLCR_AFI_FS_RSTVAL 0x00000200UL + +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH 2UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK 0x00000300UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL 0x2UL + +/** + * Register: XlpdSlcrCci + */ +#define XLPD_SLCR_CCI ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL ) +#define XLPD_SLCR_CCI_RSTVAL 0x03801c07UL + +#define XLPD_SLCR_CCI_SPR_SHIFT 28UL +#define XLPD_SLCR_CCI_SPR_WIDTH 4UL +#define XLPD_SLCR_CCI_SPR_MASK 0xf0000000UL +#define XLPD_SLCR_CCI_SPR_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS4_SHIFT 27UL +#define XLPD_SLCR_CCI_QVNVNETS4_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS4_MASK 0x08000000UL +#define XLPD_SLCR_CCI_QVNVNETS4_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS3_SHIFT 26UL +#define XLPD_SLCR_CCI_QVNVNETS3_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS3_MASK 0x04000000UL +#define XLPD_SLCR_CCI_QVNVNETS3_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS2_SHIFT 25UL +#define XLPD_SLCR_CCI_QVNVNETS2_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS2_MASK 0x02000000UL +#define XLPD_SLCR_CCI_QVNVNETS2_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QVNVNETS1_SHIFT 24UL +#define XLPD_SLCR_CCI_QVNVNETS1_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS1_MASK 0x01000000UL +#define XLPD_SLCR_CCI_QVNVNETS1_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QVNVNETS0_SHIFT 23UL +#define XLPD_SLCR_CCI_QVNVNETS0_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS0_MASK 0x00800000UL +#define XLPD_SLCR_CCI_QVNVNETS0_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QOS_OVRRD_SHIFT 18UL +#define XLPD_SLCR_CCI_QOS_OVRRD_WIDTH 5UL +#define XLPD_SLCR_CCI_QOS_OVRRD_MASK 0x007c0000UL +#define XLPD_SLCR_CCI_QOS_OVRRD_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVN_EN_M2_SHIFT 17UL +#define XLPD_SLCR_CCI_QVN_EN_M2_WIDTH 1UL +#define XLPD_SLCR_CCI_QVN_EN_M2_MASK 0x00020000UL +#define XLPD_SLCR_CCI_QVN_EN_M2_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVN_EN_M1_SHIFT 16UL +#define XLPD_SLCR_CCI_QVN_EN_M1_WIDTH 1UL +#define XLPD_SLCR_CCI_QVN_EN_M1_MASK 0x00010000UL +#define XLPD_SLCR_CCI_QVN_EN_M1_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_STRPG_GRAN_SHIFT 13UL +#define XLPD_SLCR_CCI_STRPG_GRAN_WIDTH 3UL +#define XLPD_SLCR_CCI_STRPG_GRAN_MASK 0x0000e000UL +#define XLPD_SLCR_CCI_STRPG_GRAN_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ACCHNLLEN4_SHIFT 12UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_MASK 0x00001000UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ACCHNLLEN3_SHIFT 11UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_MASK 0x00000800UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ACCHNLLEN0_SHIFT 10UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_MASK 0x00000400UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ECOREVNUM_SHIFT 6UL +#define XLPD_SLCR_CCI_ECOREVNUM_WIDTH 4UL +#define XLPD_SLCR_CCI_ECOREVNUM_MASK 0x000003c0UL +#define XLPD_SLCR_CCI_ECOREVNUM_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA2_SHIFT 5UL +#define XLPD_SLCR_CCI_ASA2_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA2_MASK 0x00000020UL +#define XLPD_SLCR_CCI_ASA2_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA1_SHIFT 4UL +#define XLPD_SLCR_CCI_ASA1_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA1_MASK 0x00000010UL +#define XLPD_SLCR_CCI_ASA1_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA0_SHIFT 3UL +#define XLPD_SLCR_CCI_ASA0_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA0_MASK 0x00000008UL +#define XLPD_SLCR_CCI_ASA0_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_OWO2_SHIFT 2UL +#define XLPD_SLCR_CCI_OWO2_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO2_MASK 0x00000004UL +#define XLPD_SLCR_CCI_OWO2_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_OWO1_SHIFT 1UL +#define XLPD_SLCR_CCI_OWO1_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO1_MASK 0x00000002UL +#define XLPD_SLCR_CCI_OWO1_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_OWO0_SHIFT 0UL +#define XLPD_SLCR_CCI_OWO0_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO0_MASK 0x00000001UL +#define XLPD_SLCR_CCI_OWO0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrCciAddrmap + */ +#define XLPD_SLCR_CCI_ADDRMAP ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL ) +#define XLPD_SLCR_CCI_ADDRMAP_RSTVAL 0x00c000ffUL + +#define XLPD_SLCR_CCI_ADDRMAP_15_SHIFT 30UL +#define XLPD_SLCR_CCI_ADDRMAP_15_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_15_MASK 0xc0000000UL +#define XLPD_SLCR_CCI_ADDRMAP_15_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_14_SHIFT 28UL +#define XLPD_SLCR_CCI_ADDRMAP_14_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_14_MASK 0x30000000UL +#define XLPD_SLCR_CCI_ADDRMAP_14_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_13_SHIFT 26UL +#define XLPD_SLCR_CCI_ADDRMAP_13_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_13_MASK 0x0c000000UL +#define XLPD_SLCR_CCI_ADDRMAP_13_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_12_SHIFT 24UL +#define XLPD_SLCR_CCI_ADDRMAP_12_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_12_MASK 0x03000000UL +#define XLPD_SLCR_CCI_ADDRMAP_12_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_11_SHIFT 22UL +#define XLPD_SLCR_CCI_ADDRMAP_11_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_11_MASK 0x00c00000UL +#define XLPD_SLCR_CCI_ADDRMAP_11_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_10_SHIFT 20UL +#define XLPD_SLCR_CCI_ADDRMAP_10_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_10_MASK 0x00300000UL +#define XLPD_SLCR_CCI_ADDRMAP_10_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_9_SHIFT 18UL +#define XLPD_SLCR_CCI_ADDRMAP_9_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_9_MASK 0x000c0000UL +#define XLPD_SLCR_CCI_ADDRMAP_9_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_8_SHIFT 16UL +#define XLPD_SLCR_CCI_ADDRMAP_8_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_8_MASK 0x00030000UL +#define XLPD_SLCR_CCI_ADDRMAP_8_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_7_SHIFT 14UL +#define XLPD_SLCR_CCI_ADDRMAP_7_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_7_MASK 0x0000c000UL +#define XLPD_SLCR_CCI_ADDRMAP_7_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_6_SHIFT 12UL +#define XLPD_SLCR_CCI_ADDRMAP_6_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_6_MASK 0x00003000UL +#define XLPD_SLCR_CCI_ADDRMAP_6_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_5_SHIFT 10UL +#define XLPD_SLCR_CCI_ADDRMAP_5_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_5_MASK 0x00000c00UL +#define XLPD_SLCR_CCI_ADDRMAP_5_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_4_SHIFT 8UL +#define XLPD_SLCR_CCI_ADDRMAP_4_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_4_MASK 0x00000300UL +#define XLPD_SLCR_CCI_ADDRMAP_4_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_3_SHIFT 6UL +#define XLPD_SLCR_CCI_ADDRMAP_3_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_3_MASK 0x000000c0UL +#define XLPD_SLCR_CCI_ADDRMAP_3_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_2_SHIFT 4UL +#define XLPD_SLCR_CCI_ADDRMAP_2_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_2_MASK 0x00000030UL +#define XLPD_SLCR_CCI_ADDRMAP_2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_1_SHIFT 2UL +#define XLPD_SLCR_CCI_ADDRMAP_1_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_1_MASK 0x0000000cUL +#define XLPD_SLCR_CCI_ADDRMAP_1_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_0_SHIFT 0UL +#define XLPD_SLCR_CCI_ADDRMAP_0_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_0_MASK 0x00000003UL +#define XLPD_SLCR_CCI_ADDRMAP_0_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrCciQvnprealloc + */ +#define XLPD_SLCR_CCI_QVNPREALLOC ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL ) +#define XLPD_SLCR_CCI_QVNPREALLOC_RSTVAL 0x00330330UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_SHIFT 20UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_MASK 0x00f00000UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_SHIFT 16UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_MASK 0x000f0000UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_SHIFT 8UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_MASK 0x00000f00UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_SHIFT 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_MASK 0x000000f0UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrSmmu + */ +#define XLPD_SLCR_SMMU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL ) +#define XLPD_SLCR_SMMU_RSTVAL 0x0000003fUL + +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_SHIFT 7UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_WIDTH 1UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_MASK 0x00000080UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_DEFVAL 0x0UL + +#define XLPD_SLCR_SMMU_CTTW_SHIFT 6UL +#define XLPD_SLCR_SMMU_CTTW_WIDTH 1UL +#define XLPD_SLCR_SMMU_CTTW_MASK 0x00000040UL +#define XLPD_SLCR_SMMU_CTTW_DEFVAL 0x0UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_SHIFT 5UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_MASK 0x00000020UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_SHIFT 4UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_MASK 0x00000010UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_SHIFT 3UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_MASK 0x00000008UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_SHIFT 2UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_MASK 0x00000004UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_SHIFT 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_MASK 0x00000002UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_SHIFT 0UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_MASK 0x00000001UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrApu + */ +#define XLPD_SLCR_APU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL ) +#define XLPD_SLCR_APU_RSTVAL 0x00000001UL + +#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT 3UL +#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_BARRIER_MASK 0x00000008UL +#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT 2UL +#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_CMNT_MASK 0x00000004UL +#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_INNER_SHIFT 1UL +#define XLPD_SLCR_APU_BRDC_INNER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_INNER_MASK 0x00000002UL +#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT 0UL +#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_OUTER_MASK 0x00000001UL +#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL 0x1UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_SLCR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_slcr_secure.h new file mode 100644 index 000000000..aff3bf2fa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_slcr_secure.h @@ -0,0 +1,141 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_SLCR_SECURE_H__ +#define __XLPD_SLCR_SECURE_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdSlcrSecure Base Address + */ +#define XLPD_SLCR_SECURE_BASEADDR 0xFF4B0000UL + +/** + * Register: XlpdSlcrSecCtrl + */ +#define XLPD_SLCR_SEC_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) +#define XLPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecIsr + */ +#define XLPD_SLCR_SEC_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) +#define XLPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecImr + */ +#define XLPD_SLCR_SEC_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) +#define XLPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrSecIer + */ +#define XLPD_SLCR_SEC_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) +#define XLPD_SLCR_SEC_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecIdr + */ +#define XLPD_SLCR_SEC_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) +#define XLPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecItr + */ +#define XLPD_SLCR_SEC_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) +#define XLPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecRpu + */ +#define XLPD_SLCR_SEC_RPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) +#define XLPD_SLCR_SEC_RPU_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK 0x00000002UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL 0x0UL + +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT 0UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK 0x00000001UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecAdma + */ +#define XLPD_SLCR_SEC_ADMA ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL ) +#define XLPD_SLCR_SEC_ADMA_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT 0UL +#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH 8UL +#define XLPD_SLCR_SEC_ADMA_TZ_MASK 0x000000ffUL +#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecSafetyChk + */ +#define XLPD_SLCR_SEC_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) +#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT 0UL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH 32UL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecUsb + */ +#define XLPD_SLCR_SEC_USB ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL ) +#define XLPD_SLCR_SEC_USB_RSTVAL 0x00000003UL + +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK 0x00000002UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL 0x1UL + +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT 0UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK 0x00000001UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL 0x1UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_SLCR_SECURE_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_xppu.h new file mode 100644 index 000000000..a5145eac7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_xppu.h @@ -0,0 +1,858 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_XPPU_H__ +#define __XLPD_XPPU_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdXppu Base Address + */ +#define XLPD_XPPU_BASEADDR 0xFF980000UL + +/** + * Register: XlpdXppuCtrl + */ +#define XLPD_XPPU_CTRL ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL ) +#define XLPD_XPPU_CTRL_RSTVAL 0x00000000UL + +#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT 2UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK 0x00000004UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL 0x0UL + +#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT 1UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK 0x00000002UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL 0x0UL + +#define XLPD_XPPU_CTRL_EN_SHIFT 0UL +#define XLPD_XPPU_CTRL_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_EN_MASK 0x00000001UL +#define XLPD_XPPU_CTRL_EN_DEFVAL 0x0UL + +/** + * Register: XlpdXppuErrSts1 + */ +#define XLPD_XPPU_ERR_STS1 ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL ) +#define XLPD_XPPU_ERR_STS1_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuErrSts2 + */ +#define XLPD_XPPU_ERR_STS2 ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL ) +#define XLPD_XPPU_ERR_STS2_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT 0UL +#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH 16UL +#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuPoison + */ +#define XLPD_XPPU_POISON ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL ) +#define XLPD_XPPU_POISON_RSTVAL 0x00000000UL + +#define XLPD_XPPU_POISON_BASE_SHIFT 0UL +#define XLPD_XPPU_POISON_BASE_WIDTH 20UL +#define XLPD_XPPU_POISON_BASE_MASK 0x000fffffUL +#define XLPD_XPPU_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XlpdXppuIsr + */ +#define XLPD_XPPU_ISR ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL ) +#define XLPD_XPPU_ISR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ISR_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_ISR_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_ISR_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_ISR_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_ISR_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_ISR_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_ISR_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_RO_SHIFT 2UL +#define XLPD_XPPU_ISR_MID_RO_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_ISR_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_ISR_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_ISR_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_INV_APB_SHIFT 0UL +#define XLPD_XPPU_ISR_INV_APB_WIDTH 1UL +#define XLPD_XPPU_ISR_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuImr + */ +#define XLPD_XPPU_IMR ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL ) +#define XLPD_XPPU_IMR_RSTVAL 0x000000efUL + +#define XLPD_XPPU_IMR_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IMR_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IMR_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IMR_APER_TZ_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IMR_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IMR_APER_PERM_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IMR_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IMR_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IMR_MID_RO_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IMR_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IMR_MID_MISS_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IMR_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IMR_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XlpdXppuIen + */ +#define XLPD_XPPU_IEN ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL ) +#define XLPD_XPPU_IEN_RSTVAL 0x00000000UL + +#define XLPD_XPPU_IEN_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IEN_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IEN_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IEN_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IEN_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IEN_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IEN_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IEN_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IEN_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IEN_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IEN_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IEN_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IEN_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuIds + */ +#define XLPD_XPPU_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL ) +#define XLPD_XPPU_IDS_RSTVAL 0x00000000UL + +#define XLPD_XPPU_IDS_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IDS_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IDS_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IDS_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IDS_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IDS_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IDS_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IDS_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IDS_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IDS_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IDS_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IDS_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IDS_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMMstrIds + */ +#define XLPD_XPPU_M_MSTR_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL ) +#define XLPD_XPPU_M_MSTR_IDS_RSTVAL 0x00000014UL + +#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT 0UL +#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH 32UL +#define XLPD_XPPU_M_MSTR_IDS_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL 0x14UL + +/** + * Register: XlpdXppuMAperture32b + */ +#define XLPD_XPPU_M_APERTURE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL ) +#define XLPD_XPPU_M_APERTURE_32B_RSTVAL 0x00000080UL + +#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_32B_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMAperture64kb + */ +#define XLPD_XPPU_M_APERTURE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL ) +#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL 0x00000100UL + +#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL 0x100UL + +/** + * Register: XlpdXppuMAperture1mb + */ +#define XLPD_XPPU_M_APERTURE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL ) +#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL 0x00000010UL + +#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL 0x10UL + +/** + * Register: XlpdXppuMAperture512mb + */ +#define XLPD_XPPU_M_APERTURE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL ) +#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL 0x00000001UL + +#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL 0x1UL + +/** + * Register: XlpdXppuBase32b + */ +#define XLPD_XPPU_BASE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL ) +#define XLPD_XPPU_BASE_32B_RSTVAL 0xff990000UL + +#define XLPD_XPPU_BASE_32B_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_32B_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_32B_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL 0xff990000UL + +/** + * Register: XlpdXppuBase64kb + */ +#define XLPD_XPPU_BASE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL ) +#define XLPD_XPPU_BASE_64KB_RSTVAL 0xff000000UL + +#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_64KB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL 0xff000000UL + +/** + * Register: XlpdXppuBase1mb + */ +#define XLPD_XPPU_BASE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL ) +#define XLPD_XPPU_BASE_1MB_RSTVAL 0xfe000000UL + +#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_1MB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL 0xfe000000UL + +/** + * Register: XlpdXppuBase512mb + */ +#define XLPD_XPPU_BASE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL ) +#define XLPD_XPPU_BASE_512MB_RSTVAL 0xc0000000UL + +#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_512MB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL 0xc0000000UL + +/** + * Register: XlpdXppuMstrId00 + */ +#define XLPD_XPPU_MSTR_ID00 ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL ) +#define XLPD_XPPU_MSTR_ID00_RSTVAL 0x83ff0040UL + +#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID00_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID00_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID00_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL 0x3ffUL + +#define XLPD_XPPU_MSTR_ID00_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID00_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID00_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL 0x40UL + +/** + * Register: XlpdXppuMstrId01 + */ +#define XLPD_XPPU_MSTR_ID01 ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL ) +#define XLPD_XPPU_MSTR_ID01_RSTVAL 0x03f00000UL + +#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID01_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID01_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID01_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL 0x3f0UL + +#define XLPD_XPPU_MSTR_ID01_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID01_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID01_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId02 + */ +#define XLPD_XPPU_MSTR_ID02 ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL ) +#define XLPD_XPPU_MSTR_ID02_RSTVAL 0x83f00010UL + +#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID02_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID02_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID02_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL 0x3f0UL + +#define XLPD_XPPU_MSTR_ID02_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID02_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID02_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL 0x10UL + +/** + * Register: XlpdXppuMstrId03 + */ +#define XLPD_XPPU_MSTR_ID03 ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL ) +#define XLPD_XPPU_MSTR_ID03_RSTVAL 0x83c00080UL + +#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID03_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID03_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID03_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL 0x3c0UL + +#define XLPD_XPPU_MSTR_ID03_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID03_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID03_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMstrId04 + */ +#define XLPD_XPPU_MSTR_ID04 ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL ) +#define XLPD_XPPU_MSTR_ID04_RSTVAL 0x83c30080UL + +#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID04_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID04_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID04_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID04_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID04_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID04_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMstrId05 + */ +#define XLPD_XPPU_MSTR_ID05 ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL ) +#define XLPD_XPPU_MSTR_ID05_RSTVAL 0x03c30081UL + +#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID05_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID05_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID05_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID05_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID05_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID05_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL 0x81UL + +/** + * Register: XlpdXppuMstrId06 + */ +#define XLPD_XPPU_MSTR_ID06 ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL ) +#define XLPD_XPPU_MSTR_ID06_RSTVAL 0x03c30082UL + +#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID06_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID06_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID06_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID06_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID06_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID06_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL 0x82UL + +/** + * Register: XlpdXppuMstrId07 + */ +#define XLPD_XPPU_MSTR_ID07 ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL ) +#define XLPD_XPPU_MSTR_ID07_RSTVAL 0x83c30083UL + +#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID07_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID07_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID07_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID07_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID07_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID07_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL 0x83UL + +/** + * Register: XlpdXppuMstrId08 + */ +#define XLPD_XPPU_MSTR_ID08 ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL ) +#define XLPD_XPPU_MSTR_ID08_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID08_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID08_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID08_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID08_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID08_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId09 + */ +#define XLPD_XPPU_MSTR_ID09 ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL ) +#define XLPD_XPPU_MSTR_ID09_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID09_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID09_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID09_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID09_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID09_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId10 + */ +#define XLPD_XPPU_MSTR_ID10 ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL ) +#define XLPD_XPPU_MSTR_ID10_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID10_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID10_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID10_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID10_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID10_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId11 + */ +#define XLPD_XPPU_MSTR_ID11 ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL ) +#define XLPD_XPPU_MSTR_ID11_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID11_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID11_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID11_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID11_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID11_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId12 + */ +#define XLPD_XPPU_MSTR_ID12 ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL ) +#define XLPD_XPPU_MSTR_ID12_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID12_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID12_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID12_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID12_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID12_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId13 + */ +#define XLPD_XPPU_MSTR_ID13 ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL ) +#define XLPD_XPPU_MSTR_ID13_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID13_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID13_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID13_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID13_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID13_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId14 + */ +#define XLPD_XPPU_MSTR_ID14 ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL ) +#define XLPD_XPPU_MSTR_ID14_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID14_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID14_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID14_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID14_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID14_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId15 + */ +#define XLPD_XPPU_MSTR_ID15 ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL ) +#define XLPD_XPPU_MSTR_ID15_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID15_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID15_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID15_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID15_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID15_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId16 + */ +#define XLPD_XPPU_MSTR_ID16 ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL ) +#define XLPD_XPPU_MSTR_ID16_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID16_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID16_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID16_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID16_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID16_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId17 + */ +#define XLPD_XPPU_MSTR_ID17 ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL ) +#define XLPD_XPPU_MSTR_ID17_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID17_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID17_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID17_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID17_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID17_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId18 + */ +#define XLPD_XPPU_MSTR_ID18 ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL ) +#define XLPD_XPPU_MSTR_ID18_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID18_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID18_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID18_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID18_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID18_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId19 + */ +#define XLPD_XPPU_MSTR_ID19 ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL ) +#define XLPD_XPPU_MSTR_ID19_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID19_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID19_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID19_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID19_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID19_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_XPPU_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_xppu_sink.h new file mode 100644 index 000000000..95f7e20a2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_xppu_sink.h @@ -0,0 +1,81 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_XPPU_SINK_H__ +#define __XLPD_XPPU_SINK_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdXppuSink Base Address + */ +#define XLPD_XPPU_SINK_BASEADDR 0xFF9C0000UL + +/** + * Register: XlpdXppuSinkErrSts + */ +#define XLPD_XPPU_SINK_ERR_STS ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL ) +#define XLPD_XPPU_SINK_ERR_STS_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT 31UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH 1UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL + +#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT 0UL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH 12UL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkIsr + */ +#define XLPD_XPPU_SINK_ISR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL ) +#define XLPD_XPPU_SINK_ISR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkImr + */ +#define XLPD_XPPU_SINK_IMR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL ) +#define XLPD_XPPU_SINK_IMR_RSTVAL 0x00000001UL + +#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL + +/** + * Register: XlpdXppuSinkIer + */ +#define XLPD_XPPU_SINK_IER ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL ) +#define XLPD_XPPU_SINK_IER_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkIdr + */ +#define XLPD_XPPU_SINK_IDR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL ) +#define XLPD_XPPU_SINK_IDR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_XPPU_SINK_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu.h new file mode 100644 index 000000000..134116f2b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu.h @@ -0,0 +1,584 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xnandpsu.h +* +* This file implements a driver to support Arasan NAND controller +* present in Zynq Ultrascale Mp. +* +* Driver Initialization +* +* The function call XNandPsu_CfgInitialize() should be called by the application +* before any other function in the driver. The initialization function takes +* device specific data (like device id, instance id, and base address) and +* initializes the XNandPsu instance with the device specific data. +* +* Device Geometry +* +* NAND flash device is memory device and it is segmented into areas called +* Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device +* can have multiple LUN. LUN is sequential raw of multiple blocks of the same +* size. A block is the smallest erasable unit of data within the Flash array of +* a LUN. The size of each block is based on a power of 2. There is no +* restriction on the number of blocks within the LUN. A block contains a number +* of pages. A page is the smallest addressable unit for read and program +* operations. The arrangement of LUN, blocks, and pages is referred to by this +* module as the part's geometry. +* +* The cells within the part can be programmed from a logic 1 to a logic 0 +* and not the other way around. To change a cell back to a logic 1, the +* entire block containing that cell must be erased. When a block is erased +* all bytes contain the value 0xFF. The number of times a block can be +* erased is finite. Eventually the block will wear out and will no longer +* be capable of erasure. As of this writing, the typical flash block can +* be erased 100,000 or more times. +* +* The jobs done by this driver typically are: +* - 8-bit operational mode +* - Read, Write, and Erase operation +* +* Write Operation +* +* The write call can be used to write a minimum of one byte and a maximum +* entire flash. If the address offset specified to write is out of flash or if +* the number of bytes specified from the offset exceed flash boundaries +* an error is reported back to the user. The write is blocking in nature in that +* the control is returned back to user only after the write operation is +* completed successfully or an error is reported. +* +* Read Operation +* +* The read call can be used to read a minimum of one byte and maximum of +* entire flash. If the address offset specified to read is out of flash or if +* the number of bytes specified from the offset exceed flash boundaries +* an error is reported back to the user. The read is blocking in nature in that +* the control is returned back to user only after the read operation is +* completed successfully or an error is reported. +* +* Erase Operation +* +* The erase operations are provided to erase a Block in the Flash memory. The +* erase call is blocking in nature in that the control is returned back to user +* only after the erase operation is completed successfully or an error is +* reported. +* +* @note Driver has been renamed to nandpsu after change in +* naming convention. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads, +* mutual exclusion, virtual memory, cache control, or HW write protection +* management must be satisfied by the layer above this driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 2.0   sb     01/12/2015  Removed Null checks for Buffer passed
+*			   as parameter to Read API's
+*			   - XNandPsu_Read()
+*			   - XNandPsu_ReadPage
+*			   Modified
+*			   - XNandPsu_SetFeature()
+*			   - XNandPsu_GetFeature()
+*			   and made them public.
+*			   Removed Failure Return for BCF Error check in
+*			   XNandPsu_ReadPage() and added BCH_Error counter
+*			   in the instance pointer structure.
+* 			   Added XNandPsu_Prepare_Cmd API
+*			   Replaced
+*			   - XNandPsu_IntrStsEnable
+*			   - XNandPsu_IntrStsClear
+*			   - XNandPsu_IntrClear
+*			   - XNandPsu_SetProgramReg
+*			   with XNandPsu_WriteReg call
+*			   Modified xnandpsu.c file API's with above changes.
+* 			   Corrected the program command for Set Feature API.
+*			   Modified
+*			   - XNandPsu_OnfiReadStatus
+*			   - XNandPsu_GetFeature
+*			   - XNandPsu_SetFeature
+*			   to add support for DDR mode.
+*			   Changed Convention for SLC/MLC
+*			   SLC --> HAMMING
+*			   MLC --> BCH
+*			   SlcMlc --> IsBCH
+*			   Added support for writing BBT signature and version
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
+*			   Removed extra DMA mode initialization from
+*			   the XNandPsu_CfgInitialize API.
+*			   Modified
+*			   - XNandPsu_SetEccAddrSize
+*			   ECC address now is calculated based upon the
+*			   size of spare area
+*			   Modified Block Erase API, removed clearing of
+*			   packet register before erase.
+*			   Clearing Data Interface Register before
+*			   XNandPsu_OnfiReset call.
+*			   Modified XNandPsu_ChangeTimingMode API supporting
+*			   SDR and NVDDR interface for timing modes 0 to 5.
+*			   Modified Bbt Signature and Version Offset value for
+*			   Oob and No-Oob region.
+*
+* +******************************************************************************/ + +#ifndef XNANDPSU_H /* prevent circular inclusions */ +#define XNANDPSU_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include +#include "xstatus.h" +#include "xil_assert.h" +#include "xnandpsu_hw.h" +#include "xnandpsu_onfi.h" +#include "xil_cache.h" +/************************** Constant Definitions *****************************/ + +#define XNANDPSU_DEBUG + +#define XNANDPSU_MAX_TARGETS 1U /**< ce_n0, ce_n1 */ +#define XNANDPSU_MAX_PKT_SIZE 0x7FFU /**< Max packet size */ +#define XNANDPSU_MAX_PKT_COUNT 0xFFFU /**< Max packet count */ + +#define XNANDPSU_PAGE_SIZE_512 512U /**< 512 bytes page */ +#define XNANDPSU_PAGE_SIZE_2K 2048U /**< 2K bytes page */ +#define XNANDPSU_PAGE_SIZE_4K 4096U /**< 4K bytes page */ +#define XNANDPSU_PAGE_SIZE_8K 8192U /**< 8K bytes page */ +#define XNANDPSU_PAGE_SIZE_16K 16384U /**< 16K bytes page */ +#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U /**< 16-bit 2K bytes page */ +#define XNANDPSU_MAX_PAGE_SIZE 16384U /**< Max page size supported */ + +#define XNANDPSU_BUS_WIDTH_8 0U /**< 8-bit bus width */ +#define XNANDPSU_BUS_WIDTH_16 1U /**< 16-bit bus width */ + +#define XNANDPSU_HAMMING 0x1U /**< Hamming Flash */ +#define XNANDPSU_BCH 0x2U /**< BCH Flash */ + +#define XNANDPSU_MAX_BLOCKS 32768U /**< Max number of Blocks */ +#define XNANDPSU_MAX_SPARE_SIZE 0x800U /**< Max spare bytes of a NAND + flash page of 16K */ + +#define XNANDPSU_INTR_POLL_TIMEOUT 10000U + +#define XNANDPSU_SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U) + +/** + * The XNandPsu_Config structure contains configuration information for NAND + * controller. + */ +typedef struct { + u16 DeviceId; /**< Instance ID of NAND flash controller */ + u32 BaseAddress; /**< Base address of NAND flash controller */ +} XNandPsu_Config; + +/** + * The XNandPsu_DataInterface enum contains flash operating mode. + */ +typedef enum { + XNANDPSU_SDR = 0U, /**< Single Data Rate */ + XNANDPSU_NVDDR /**< Double Data Rate */ +} XNandPsu_DataInterface; + +/** + * XNandPsu_TimingMode enum contains timing modes. + */ +typedef enum { + XNANDPSU_SDR0 = 0U, + XNANDPSU_SDR1, + XNANDPSU_SDR2, + XNANDPSU_SDR3, + XNANDPSU_SDR4, + XNANDPSU_SDR5, + XNANDPSU_NVDDR0, + XNANDPSU_NVDDR1, + XNANDPSU_NVDDR2, + XNANDPSU_NVDDR3, + XNANDPSU_NVDDR4, + XNANDPSU_NVDDR5 +} XNandPsu_TimingMode; + +/** + * The XNandPsu_SWMode enum contains the driver operating mode. + */ +typedef enum { + XNANDPSU_POLLING = 0, /**< Polling */ + XNANDPSU_INTERRUPT /**< Interrupt */ +} XNandPsu_SWMode; + +/** + * The XNandPsu_DmaMode enum contains the controller MDMA mode. + */ +typedef enum { + XNANDPSU_PIO = 0, /**< PIO Mode */ + XNANDPSU_SDMA, /**< SDMA Mode */ + XNANDPSU_MDMA /**< MDMA Mode */ +} XNandPsu_DmaMode; + +/** + * The XNandPsu_EccMode enum contains ECC functionality. + */ +typedef enum { + XNANDPSU_NONE = 0, + XNANDPSU_HWECC, + XNANDPSU_EZNAND, + XNANDPSU_ONDIE +} XNandPsu_EccMode; + +/** + * The XNandPsu_BbtOption enum contains the BBT storage option. + */ +typedef enum { + XNANDPSU_BBT_OOB = 0, /**< OOB area */ + XNANDPSU_BBT_NO_OOB, /**< No OOB i.e page area */ +} XNandPsu_BbtOption; + +/** + * Bad block table descriptor + */ +typedef struct { + u32 PageOffset[XNANDPSU_MAX_TARGETS]; + /**< Page offset where BBT resides */ + u32 SigOffset; /**< Signature offset in Spare area */ + u32 VerOffset; /**< Offset of BBT version */ + u32 SigLength; /**< Length of the signature */ + u32 MaxBlocks; /**< Max blocks to search for BBT */ + char Signature[4]; /**< BBT signature */ + u8 Version[XNANDPSU_MAX_TARGETS]; + /**< BBT version */ + u32 Valid; /**< BBT descriptor is valid or not */ + XNandPsu_BbtOption Option; /**< BBT Oob option enabled/disabled */ +} XNandPsu_BbtDesc; + +/** + * Bad block pattern + */ +typedef struct { + u32 Options; /**< Options to search the bad block pattern */ + u32 Offset; /**< Offset to search for specified pattern */ + u32 Length; /**< Number of bytes to check the pattern */ + u8 Pattern[2]; /**< Pattern format to search for */ +} XNandPsu_BadBlockPattern; + +/** + * The XNandPsu_Geometry structure contains the ONFI geometry information. + */ +typedef struct { + /* + * Parameter page information + */ + u32 BytesPerPage; /**< Number of bytes per page */ + u16 SpareBytesPerPage; /**< Number of spare bytes per page */ + u32 PagesPerBlock; /**< Number of pages per block */ + u32 BlocksPerLun; /**< Number of blocks per LUN */ + u8 NumLuns; /**< Number of LUN's */ + u8 RowAddrCycles; /**< Row address cycles */ + u8 ColAddrCycles; /**< Column address cycles */ + u8 NumBitsPerCell; /**< Number of bits per cell (Hamming/BCH) */ + u8 NumBitsECC; /**< Number of bits ECC correctability */ + u32 EccCodeWordSize; /**< ECC codeword size */ + /* + * Driver specific information + */ + u32 BlockSize; /**< Block size */ + u32 NumTargetPages; /**< Total number of pages in a Target */ + u32 NumTargetBlocks; /**< Total number of blocks in a Target */ + u64 TargetSize; /**< Target size in bytes */ + u8 NumTargets; /**< Number of targets present */ + u32 NumPages; /**< Total number of pages */ + u32 NumBlocks; /**< Total number of blocks */ + u64 DeviceSize; /**< Total flash size in bytes */ +} XNandPsu_Geometry; + +/** + * The XNandPsu_Features structure contains the ONFI features information. + */ +typedef struct { + u32 BusWidth; + u32 NvDdr; + u32 EzNand; + u32 OnDie; + u32 ExtPrmPage; +} XNandPsu_Features; + +/** + * The XNandPsu_EccMatrix structure contains ECC features information. + */ +typedef struct { + u16 PageSize; + u16 CodeWordSize; + u8 NumEccBits; + u8 IsBCH; + u16 EccAddr; + u16 EccSize; +} XNandPsu_EccMatrix; + +/** + * The XNandPsu_EccCfg structure contains ECC configuration. + */ +typedef struct { + u16 EccAddr; + u16 EccSize; + u16 CodeWordSize; + u8 NumEccBits; + u8 IsBCH; +} XNandPsu_EccCfg; + +/** + * The XNandPsu structure contains the driver instance data. The user is + * required to allocate a variable of this type for the NAND controller. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + u32 IsReady; /**< Device is initialized and ready */ + XNandPsu_Config Config; + u16 Ecc_Stat_PerPage_flips; /**< Ecc Correctable Error Counter for Current Page */ + u32 Ecc_Stats_total_flips; /**< Total Ecc Errors Corrected */ + XNandPsu_DataInterface DataInterface; + XNandPsu_TimingMode TimingMode; + XNandPsu_SWMode Mode; /**< Driver operating mode */ + XNandPsu_DmaMode DmaMode; /**< MDMA mode enabled/disabled */ + XNandPsu_EccMode EccMode; /**< ECC Mode */ + XNandPsu_EccCfg EccCfg; /**< ECC configuration */ + XNandPsu_Geometry Geometry; /**< Flash geometry */ + XNandPsu_Features Features; /**< ONFI features */ + u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64))); + /**< Partial read/write buffer */ + /* Bad block table definitions */ + XNandPsu_BbtDesc BbtDesc; /**< Bad block table descriptor */ + XNandPsu_BbtDesc BbtMirrorDesc; /**< Mirror BBT descriptor */ + XNandPsu_BadBlockPattern BbPattern; /**< Bad block pattern to + search */ + u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2]; /**< Bad block table array */ +} XNandPsu; + +/******************* Macro Definitions (Inline Functions) *******************/ + +/*****************************************************************************/ +/** + * This macro sets the bitmask in the register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param RegOffset is the register offset. + * @param BitMask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset, + * u32 BitMask) + * + *****************************************************************************/ +#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask) \ + XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset), \ + ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset)) | (BitMask)))) + +/*****************************************************************************/ +/** + * This macro clears the bitmask in the register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param RegOffset is the register offset. + * @param BitMask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset, + * u32 BitMask) + * + *****************************************************************************/ +#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask) \ + XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset), \ + ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset)) & ~(BitMask)))) + +/*****************************************************************************/ +/** + * This macro clears and updates the bitmask in the register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param RegOffset is the register offset. + * @param Mask is the bitmask. + * @param Value is the register value to write. + * + * @note C-style signature: + * void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr, + * u32 RegOffset, u32 Mask, u32 Val) + * + *****************************************************************************/ +#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value) \ + XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset), \ + ((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\ + (u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value)))) + +/*****************************************************************************/ +/** + * This macro enables bitmask in Interrupt Signal Enable register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param Mask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask) + * + *****************************************************************************/ +#define XNandPsu_IntrSigEnable(InstancePtr, Mask) \ + XNandPsu_SetBits((InstancePtr), \ + XNANDPSU_INTR_SIG_EN_OFFSET, \ + (Mask)) + +/*****************************************************************************/ +/** + * This macro clears bitmask in Interrupt Signal Enable register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param Mask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask) + * + *****************************************************************************/ +#define XNandPsu_IntrSigClear(InstancePtr, Mask) \ + XNandPsu_ClrBits((InstancePtr), \ + XNANDPSU_INTR_SIG_EN_OFFSET, \ + (Mask)) + +/*****************************************************************************/ +/** + * This macro enables bitmask in Interrupt Status Enable register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param Mask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask) + * + *****************************************************************************/ +#define XNandPsu_IntrStsEnable(InstancePtr, Mask) \ + XNandPsu_SetBits((InstancePtr), \ + XNANDPSU_INTR_STS_EN_OFFSET, \ + (Mask)) + +/*****************************************************************************/ +/** + * This macro checks for the ONFI ID. + * + * @param Buff is the buffer holding ONFI ID + * + * @note none. + * + *****************************************************************************/ +#define IS_ONFI(Buff) \ + (Buff[0] == (u8)'O') && (Buff[1] == (u8)'N') && \ + (Buff[2] == (u8)'F') && (Buff[3] == (u8)'I') + +/************************** Function Prototypes *****************************/ + +s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr, + u32 EffectiveAddr); + +s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length); + +s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, + u8 *SrcBuf); + +s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, + u8 *DestBuf); + +s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block); + +s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf); + +s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf); + +s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr, + XNandPsu_DataInterface NewIntf, + XNandPsu_TimingMode NewMode); + +s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature, + u8 *Buf); + +s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature, + u8 *Buf); + +s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr); + +s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block); + +void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr); + +void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr); + +void XNandPsu_EnableEccMode(XNandPsu *InstancePtr); + +void XNandPsu_DisableEccMode(XNandPsu *InstancePtr); + +void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState, + u8 DmaMode, u8 AddrCycles); + +void XNandPsu_EnableBbtOobMode(XNandPsu *InstancePtr); + +void XNandPsu_DisableBbtOobMode(XNandPsu *InstancePtr); +/* + * XNandPsu_LookupConfig in xnandpsu_sinit.c + */ +XNandPsu_Config *XNandPsu_LookupConfig(u16 DeviceID); + + +#ifdef __cplusplus +} +#endif + +#endif /* XNANDPSU_H end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu_bbm.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu_bbm.h new file mode 100644 index 000000000..c128d9657 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu_bbm.h @@ -0,0 +1,211 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xnandpsu_bbm.h +* +* This file implements the Bad Block Management(BBM) functionality. This is +* similar to the Bad Block Management which is a part of the MTD subsystem in +* Linux. The factory marked bad blocks are scanned initially and a Bad Block +* Table(BBT) is created in the memory. This table is also written to the flash +* so that upon reboot, the BBT is read back from the flash and loaded into the +* memory instead of scanning every time. The Bad Block Table(BBT) is written +* into one of the the last four blocks in the flash memory. The last four +* blocks are marked as Reserved so that user can't erase/program those blocks. +* +* There are two bad block tables, a primary table and a mirror table. The +* tables are versioned and incrementing version number is used to detect and +* recover from interrupted updates. Each table is stored in a separate block, +* beginning in the first page of that block. Only two blocks would be necessary +* in the absence of bad blocks within the last four; the range of four provides +* a little slack in case one or two of those blocks is bad. These blocks are +* marked as reserved and cannot be programmed by the user. A NAND Flash device +* with 3 or more factory bad blocks in the last 4 cannot be used. The bad block +* table signature is written into the spare data area of the pages containing +* bad block table so that upon rebooting the bad block table signature is +* searched and the bad block table is loaded into RAM. The signature is "Bbt0" +* for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The +* version offset follows the signature offset in the spare data area. The +* version number increments on every update to the bad block table and the +* version wraps at 0xff. +* +* Each block in the Bad Block Table(BBT) is represented by 2 bits. +* The two bits are encoded as follows in RAM BBT. +* 0'b00 -> Good Block +* 0'b01 -> Block is bad due to wear +* 0'b10 -> Reserved block +* 0'b11 -> Factory marked bad block +* +* While writing to the flash the two bits are encoded as follows. +* 0'b00 -> Factory marked bad block +* 0'b01 -> Reserved block +* 0'b10 -> Block is bad due to wear +* 0'b11 -> Good Block +* +* The user can check for the validity of the block using the API +* XNandPsu_IsBlockBad and take the action based on the return value. Also user +* can update the bad block table using XNandPsu_MarkBlockBad API. +* +* @note None +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date        Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 2.0   sb     01/12/2015  Added support for writing BBT signature and version
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
+*			   Modified Bbt Signature and Version Offset value for
+*			   Oob and No-Oob region.
+*
+* +******************************************************************************/ +#ifndef XNANDPSU_BBM_H /* prevent circular inclusions */ +#define XNANDPSU_BBM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xnandpsu.h" + +/************************** Constant Definitions *****************************/ +/* + * Block definitions for RAM based Bad Block Table (BBT) + */ +#define XNANDPSU_BLOCK_GOOD 0x0U /**< Block is good */ +#define XNANDPSU_BLOCK_BAD 0x1U /**< Block is bad */ +#define XNANDPSU_BLOCK_RESERVED 0x2U /**< Reserved block */ +#define XNANDPSU_BLOCK_FACTORY_BAD 0x3U /**< Factory marked bad + block */ +/* + * Block definitions for FLASH based Bad Block Table (BBT) + */ +#define XNANDPSU_FLASH_BLOCK_GOOD 0x3U /**< Block is good */ +#define XNANDPSU_FLASH_BLOCK_BAD 0x2U /**< Block is bad */ +#define XNANDPSU_FLASH_BLOCK_RESERVED 0x1U /**< Reserved block */ +#define XNANDPSU_FLASH_BLOCK_FAC_BAD 0x0U /**< Factory marked bad + block */ + +#define XNANDPSU_BBT_SCAN_2ND_PAGE 0x00000001U /**< Scan the + second page + for bad block + information + */ +#define XNANDPSU_BBT_DESC_PAGE_OFFSET 0U /**< Page offset of Bad + Block Table Desc */ +#define XNANDPSU_BBT_DESC_SIG_OFFSET 8U /**< Bad Block Table + signature offset */ +#define XNANDPSU_BBT_DESC_VER_OFFSET 12U /**< Bad block Table + version offset */ +#define XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET 0U /**< Bad Block Table + signature offset in + page memory */ +#define XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET 4U /**< Bad block Table + version offset in + page memory */ +#define XNANDPSU_BBT_DESC_SIG_LEN 4U /**< Bad block Table + signature length */ +#define XNANDPSU_BBT_DESC_MAX_BLOCKS 64U /**< Bad block Table + max blocks */ + +#define XNANDPSU_BBT_BLOCK_SHIFT 2U /**< Block shift value + for a block in BBT */ +#define XNANDPSU_BBT_ENTRY_NUM_BLOCKS 4U /**< Num of blocks in + one BBT entry */ +#define XNANDPSU_BB_PTRN_OFF_SML_PAGE 5U /**< Bad block pattern + offset in a page */ +#define XNANDPSU_BB_PTRN_LEN_SML_PAGE 1U /**< Bad block pattern + length */ +#define XNANDPSU_BB_PTRN_OFF_LARGE_PAGE 0U /**< Bad block pattern + offset in a large + page */ +#define XNANDPSU_BB_PTRN_LEN_LARGE_PAGE 2U /**< Bad block pattern + length */ +#define XNANDPSU_BB_PATTERN 0xFFU /**< Bad block pattern + to search in a page + */ +#define XNANDPSU_BLOCK_TYPE_MASK 0x03U /**< Block type mask */ +#define XNANDPSU_BLOCK_SHIFT_MASK 0x06U /**< Block shift mask + for a Bad Block Table + entry byte */ + +#define XNANDPSU_ONDIE_SIG_OFFSET 0x4U +#define XNANDPSU_ONDIE_VER_OFFSET 0x14U + +#define XNANDPSU_BBT_VERSION_LENGTH 1U +#define XNANDPSU_BBT_SIG_LENGTH 4U + +#define XNANDPSU_BBT_BUF_LENGTH ((XNANDPSU_MAX_BLOCKS >> \ + XNANDPSU_BBT_BLOCK_SHIFT) + \ + (XNANDPSU_BBT_DESC_SIG_OFFSET + \ + XNANDPSU_BBT_SIG_LENGTH + \ + XNANDPSU_BBT_VERSION_LENGTH)) +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro returns the Block shift value corresponding to a Block. +* +* @param Block is the block number. +* +* @return Block shift value +* +* @note None. +* +*****************************************************************************/ +#define XNandPsu_BbtBlockShift(Block) \ + ((u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK)) + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr); + +s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr); + +s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block); + +s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu_hw.h new file mode 100644 index 000000000..f59b5b661 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu_hw.h @@ -0,0 +1,504 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xnandpsu_hw.h +* +* This file contains identifiers and low-level macros/functions for the Arasan +* NAND flash controller driver. +* +* See xnandpsu.h for more information. +* +* @note None +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date        Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First Release
+* 2.0   sb     11/04/2014  Changed XNANDPSU_ECC_SLC_MLC_MASK to
+*			   XNANDPSU_ECC_HAMMING_BCH_MASK.
+*
+* +******************************************************************************/ + +#ifndef XNANDPSU_HW_H /* prevent circular inclusions */ +#define XNANDPSU_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/************************** Register Offset Definitions **********************/ + +#define XNANDPSU_PKT_OFFSET 0x00U /**< Packet Register */ +#define XNANDPSU_MEM_ADDR1_OFFSET 0x04U /**< Memory Address + Register 1 */ +#define XNANDPSU_MEM_ADDR2_OFFSET 0x08U /**< Memory Address + Register 2 */ +#define XNANDPSU_CMD_OFFSET 0x0CU /**< Command Register */ +#define XNANDPSU_PROG_OFFSET 0x10U /**< Program Register */ +#define XNANDPSU_INTR_STS_EN_OFFSET 0x14U /**< Interrupt Status + Enable Register */ +#define XNANDPSU_INTR_SIG_EN_OFFSET 0x18U /**< Interrupt Signal + Enable Register */ +#define XNANDPSU_INTR_STS_OFFSET 0x1CU /**< Interrupt Status + Register */ +#define XNANDPSU_READY_BUSY_OFFSET 0x20U /**< Ready/Busy status + Register */ +#define XNANDPSU_FLASH_STS_OFFSET 0x28U /**< Flash Status Register */ +#define XNANDPSU_TIMING_OFFSET 0x2CU /**< Timing Register */ +#define XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U /**< Buffer Data Port + Register */ +#define XNANDPSU_ECC_OFFSET 0x34U /**< ECC Register */ +#define XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U /**< ECC Error Count + Register */ +#define XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU /**< ECC Spare Command + Register */ +#define XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U /**< Error Count 1bit + Register */ +#define XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U /**< Error Count 2bit + Register */ +#define XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U /**< Error Count 3bit + Register */ +#define XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU /**< Error Count 4bit + Register */ +#define XNANDPSU_CPU_REL_OFFSET 0x58U /**< CPU Release Register */ +#define XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU /**< Error Count 5bit + Register */ +#define XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U /**< Error Count 6bit + Register */ +#define XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U /**< Error Count 7bit + Register */ +#define XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U /**< Error Count 8bit + Register */ +#define XNANDPSU_DATA_INTF_OFFSET 0x6CU /**< Data Interface Register */ +#define XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U /**< DMA System Address 0 + Register */ +#define XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U /**< DMA System Address 1 + Register */ +#define XNANDPSU_DMA_BUF_BND_OFFSET 0x54U /**< DMA Buffer Boundary + Register */ +#define XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U /**< Slave DMA Configuration + Register */ + +/** @name Packet Register bit definitions and masks + * @{ + */ +#define XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU /**< Packet Size */ +#define XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U /**< Packet Count*/ +#define XNANDPSU_PKT_PKT_CNT_SHIFT 12U /**< Packet Count Shift */ +/* @} */ + +/** @name Memory Address Register 1 bit definitions and masks + * @{ + */ +#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU /**< Column Address + Mask */ +#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U /**< Page, Block + Address Mask */ +#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U /**< Page Shift */ +/* @} */ + +/** @name Memory Address Register 2 bit definitions and masks + * @{ + */ +#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU /**< Memory Address + */ +#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U /**< Bus Width */ +#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U /**< BCH Mode + Value */ +#define XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U /**< Flash + Connection Mode */ +#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U /**< Chip Select */ +#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U /**< Chip select + shift */ +#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U /**< Bus width shift */ +#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U +/* @} */ + +/** @name Command Register bit definitions and masks + * @{ + */ +#define XNANDPSU_CMD_CMD1_MASK 0x000000FFU /**< 1st Cycle + Command */ +#define XNANDPSU_CMD_CMD2_MASK 0x0000FF00U /**< 2nd Cycle + Command */ +#define XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U /**< Page Size */ +#define XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U /**< DMA Enable + Mode */ +#define XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U /**< Number of + Address Cycles */ +#define XNANDPSU_CMD_ECC_ON_MASK 0x80000000U /**< ECC ON/OFF */ +#define XNANDPSU_CMD_CMD2_SHIFT 8U /**< 2nd Cycle Command + Shift */ +#define XNANDPSU_CMD_PG_SIZE_SHIFT 23U /**< Page Size Shift */ +#define XNANDPSU_CMD_DMA_EN_SHIFT 26U /**< DMA Enable Shift */ +#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U /**< Number of Address + Cycles Shift */ +#define XNANDPSU_CMD_ECC_ON_SHIFT 31U /**< ECC ON/OFF */ +/* @} */ + +/** @name Program Register bit definitions and masks + * @{ + */ +#define XNANDPSU_PROG_RD_MASK 0x00000001U /**< Read */ +#define XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U /**< Multi Die */ +#define XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U /**< Block Erase */ +#define XNANDPSU_PROG_RD_STS_MASK 0x00000008U /**< Read Status */ +#define XNANDPSU_PROG_PG_PROG_MASK 0x00000010U /**< Page Program */ +#define XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U /**< Multi Die Rd */ +#define XNANDPSU_PROG_RD_ID_MASK 0x00000040U /**< Read ID */ +#define XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U /**< Read Param + Page */ +#define XNANDPSU_PROG_RST_MASK 0x00000100U /**< Reset */ +#define XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U /**< Get Features */ +#define XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U /**< Set Features */ +#define XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U /**< Read Unique + ID */ +#define XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U /**< Read Status + Enhanced */ +#define XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U /**< Read + Interleaved */ +#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U /**< Change Read + Column + Enhanced */ +#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U /**< Copy Back + Interleaved */ +#define XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U /**< Read Cache + Start */ +#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U /**< Read Cache + Sequential */ +#define XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U /**< Read Cache + Random */ +#define XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U /**< Read Cache + End */ +#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U /**< Small Data + Move */ +#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U /**< Change Row + Address */ +#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U /**< Change Row + Address End */ +#define XNANDPSU_PROG_RST_LUN_MASK 0x00800000U /**< Reset LUN */ +#define XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U /**< Enhanced + Program Page + Register Clear */ +#define XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U /**< Volume Select */ +#define XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U /**< ODT Configure */ +/* @} */ + +/** @name Interrupt Status Enable Register bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer + Write Ready + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer + Read Ready + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi + Bit Error + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single + Bit Error + Status + Enable, + BCH Detect + Error + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error + AHB Status + Enable */ +/* @} */ + +/** @name Interrupt Signal Enable Register bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer + Write Ready + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer + Read Ready + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi + Bit Error + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single + Bit Error + Signal + Enable, + BCH Detect + Error + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error + AHB Signal + Enable */ +/* @} */ + +/** @name Interrupt Status Register bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer + Write + Ready */ +#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer + Read + Ready */ +#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete */ +#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi + Bit Error */ +#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single + Bit Error, + BCH Detect + Error */ +#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA + Interrupt + */ +#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error + AHB */ +/* @} */ + +/** @name Interrupt bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer Write + Ready Status + Enable */ +#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer Read + Ready Status + Enable */ +#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete Status + Enable */ +#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi Bit Error + Status Enable */ +#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single Bit Error + Status Enable, + BCH Detect Error + Status Enable */ +#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA Status + Enable */ +#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error AHB Status + Enable */ +/* @} */ + +/** @name ID2 Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU /**< MSB Device ID */ +/* @} */ + +/** @name Flash Status Register bit definitions and masks + * @{ + */ +#define XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU /**< Flash Status + Value */ +/* @} */ + +/** @name Timing Register bit definitions and masks + * @{ + */ +#define XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U /**< Change column + setup time */ +#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U /**< Slow/Fast device + */ +#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U /**< Write/Read data + transaction value + */ +#define XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U /**< Address latch + enable to Data + loading time */ +/* @} */ + +/** @name ECC Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU /**< ECC address */ +#define XNANDPSU_ECC_SIZE_MASK 0x01FF0000U /**< ECC size */ +#define XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U /**< Hamming/BCH + support */ +/* @} */ + +/** @name ECC Error Count Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU /**< Packet + bound error + count */ +#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U /**< Page + bound error + count */ +/* @} */ + +/** @name ECC Spare Command Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU /**< ECC + spare + command */ +#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U /**< Number + of ECC/ + spare + address + cycles */ +/* @} */ + +/** @name Data Interface Register bit definitions and masks + * @{ + */ +#define XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U /**< SDR mode */ +#define XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U /**< NVDDR mode */ +#define XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U /**< NVDDR2 mode */ +#define XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U /**< Data + Interface */ +#define XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U /**< NVDDR mode shift */ +#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U /**< Data Interface Shift */ +/* @} */ + +/** @name DMA Buffer Boundary Register bit definitions and masks + * @{ + */ +#define XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U /**< DMA buffer + boundary */ +#define XNANDPSU_DMA_BUF_BND_4K 0x0U +#define XNANDPSU_DMA_BUF_BND_8K 0x1U +#define XNANDPSU_DMA_BUF_BND_16K 0x2U +#define XNANDPSU_DMA_BUF_BND_32K 0x3U +#define XNANDPSU_DMA_BUF_BND_64K 0x4U +#define XNANDPSU_DMA_BUF_BND_128K 0x5U +#define XNANDPSU_DMA_BUF_BND_256K 0x6U +#define XNANDPSU_DMA_BUF_BND_512K 0x7U +/* @} */ + +/** @name Slave DMA Configuration Register bit definitions and masks + * @{ + */ +#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U /**< Slave + DMA + Transfer + Direction + */ +#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU /**< Slave + DMA + Transfer + Count */ +#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U /**< Slave + DMA + Burst + Size */ +#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U /**< DMA + Timeout + Counter + Value */ +#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U /**< Slave + DMA + Enable */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the base address of controller registers. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XNandPsu_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddress is the the base address of controller registers. +* @param RegOffset is the register offset to be written. +* @param Data is the the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +******************************************************************************/ +#define XNandPsu_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32(((BaseAddress) + (RegOffset)), (Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* XNANDPSU_HW_H end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu_onfi.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu_onfi.h new file mode 100644 index 000000000..41da5569c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xnandpsu_onfi.h @@ -0,0 +1,340 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xnandpsu_onfi.h +* +* This file defines all the ONFI 3.1 specific commands and values. +* +* @note None +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+*
+* +******************************************************************************/ +#ifndef XNANDPSU_ONFI_H /* prevent circular inclusions */ +#define XNANDPSU_ONFI_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ +/* + * Standard ONFI 3.1 Commands + */ +/* + * ONFI 3.1 Mandatory Commands + */ +#define ONFI_CMD_RD1 0x00U /**< Read (1st cycle) */ +#define ONFI_CMD_RD2 0x30U /**< Read (2nd cycle) */ +#define ONFI_CMD_CHNG_RD_COL1 0x05U /**< Change Read Column + (1st cycle) */ +#define ONFI_CMD_CHNG_RD_COL2 0xE0U /**< Change Read Column + (2nd cycle) */ +#define ONFI_CMD_BLK_ERASE1 0x60U /**< Block Erase (1st cycle) */ +#define ONFI_CMD_BLK_ERASE2 0xD0U /**< Block Erase (2nd cycle) */ +#define ONFI_CMD_RD_STS 0x70U /**< Read Status */ +#define ONFI_CMD_PG_PROG1 0x80U /**< Page Program(1st cycle) */ +#define ONFI_CMD_PG_PROG2 0x10U /**< Page Program(2nd cycle) */ +#define ONFI_CMD_CHNG_WR_COL 0x85U /**< Change Write Column */ +#define ONFI_CMD_RD_ID 0x90U /**< Read ID */ +#define ONFI_CMD_RD_PRM_PG 0xECU /**< Read Parameter Page */ +#define ONFI_CMD_RST 0xFFU /**< Reset */ +/* + * ONFI 3.1 Optional Commands + */ +#define ONFI_CMD_MUL_RD1 0x00U /**< Multiplane Read + (1st cycle) */ +#define ONFI_CMD_MUL_RD2 0x32U /**< Multiplane Read + (2nd cycle) */ +#define ONFI_CMD_CPBK_RD1 0x00U /**< Copyback Read + (1st cycle) */ +#define ONFI_CMD_CPBK_RD2 0x35U /**< Copyback Read + (2nd cycle) */ +#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U /**< Change Read Column + Enhanced (1st cycle) */ +#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U /**< Change Read Column + Enhanced (2nd cycle) */ +#define ONFI_CMD_RD_CACHE_RND1 0x00U /**< Read Cache Random + (1st cycle) */ +#define ONFI_CMD_RD_CACHE_RND2 0x31U /**< Read Cache Random + (2nd cycle) */ +#define ONFI_CMD_RD_CACHE_SEQ 0x31U /**< Read Cache Sequential */ +#define ONFI_CMD_RD_CACHE_END 0x3FU /**< Read Cache End */ +#define ONFI_CMD_MUL_BLK_ERASE1 0x60U /**< Multiplane Block Erase + (1st cycle) */ +#define ONFI_CMD_MUL_BLK_ERASE2 0xD1U /**< Multiplane Block Erase + (2nd cycle) */ +#define ONFI_CMD_RD_STS_ENHCD 0x78U /**< Read Status Enhanced */ +#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U /**< Block Erase Interleaved + (2nd cycle) */ +#define ONFI_CMD_MUL_PG_PROG1 0x80U /**< Multiplane Page Program + (1st cycle) */ +#define ONFI_CMD_MUL_PG_PROG2 0x11U /**< Multiplane Page Program + (2nd cycle) */ +#define ONFI_CMD_PG_CACHE_PROG1 0x80U /**< Page Cache Program + (1st cycle) */ +#define ONFI_CMD_PG_CACHE_PROG2 0x15U /**< Page Cache Program + (2nd cycle) */ +#define ONFI_CMD_CPBK_PROG1 0x85U /**< Copyback Program + (1st cycle) */ +#define ONFI_CMD_CPBK_PROG2 0x10U /**< Copyback Program + (2nd cycle) */ +#define ONFI_CMD_MUL_CPBK_PROG1 0x85U /**< Multiplane Copyback + Program (1st cycle) */ +#define ONFI_CMD_MUL_CPBK_PROG2 0x10U /**< Multiplane Copyback + Program (2nd cycle) */ +#define ONFI_CMD_SMALL_DATA_MV1 0x85U /**< Small Data Move + (1st cycle) */ +#define ONFI_CMD_SMALL_DATA_MV2 0x10U /**< Small Data Move + (2nd cycle) */ +#define ONFI_CMD_CHNG_ROW_ADDR 0x85U /**< Change Row Address */ +#define ONFI_CMD_VOL_SEL 0xE1U /**< Volume Select */ +#define ONFI_CMD_ODT_CONF 0xE2U /**< ODT Configure */ +#define ONFI_CMD_RD_UNIQID 0xEDU /**< Read Unique ID */ +#define ONFI_CMD_GET_FEATURES 0xEEU /**< Get Features */ +#define ONFI_CMD_SET_FEATURES 0xEFU /**< Set Features */ +#define ONFI_CMD_LUN_GET_FEATURES 0xD4U /**< LUN Get Features */ +#define ONFI_CMD_LUN_SET_FEATURES 0xD5U /**< LUN Set Features */ +#define ONFI_CMD_RST_LUN 0xFAU /**< Reset LUN */ +#define ONFI_CMD_SYN_RST 0xFCU /**< Synchronous Reset */ + +/* + * ONFI Status Register bit offsets + */ +#define ONFI_STS_FAIL 0x01U /**< FAIL */ +#define ONFI_STS_FAILC 0x02U /**< FAILC */ +#define ONFI_STS_CSP 0x08U /**< CSP */ +#define ONFI_STS_VSP 0x10U /**< VSP */ +#define ONFI_STS_ARDY 0x20U /**< ARDY */ +#define ONFI_STS_RDY 0x40U /**< RDY */ +#define ONFI_STS_WP 0x80U /**< WP_n */ + +/* + * ONFI constants + */ +#define ONFI_CRC_LEN 254U /**< ONFI CRC Buf Length */ +#define ONFI_PRM_PG_LEN 256U /**< Parameter Page Length */ +#define ONFI_MND_PRM_PGS 3U /**< Number of mandatory + parameter pages */ +#define ONFI_SIG_LEN 4U /**< Signature Length */ +#define ONFI_CMD_INVALID 0x00U /**< Invalid Command */ + +#define ONFI_READ_ID_LEN 4U /**< ONFI ID length */ +#define ONFI_READ_ID_ADDR 0x20U /**< ONFI Read ID Address */ +#define ONFI_READ_ID_ADDR_CYCLES 1U /**< ONFI Read ID Address + cycles */ + +#define ONFI_PRM_PG_ADDR_CYCLES 1U /**< ONFI Read Parameter page + address cycles */ + +/** + * This enum defines the ONFI 3.1 commands. + */ +enum OnfiCommandList { + READ=0, /**< Read */ + MULTIPLANE_READ, /**< Multiplane Read */ + COPYBACK_READ, /**< Copyback Read */ + CHANGE_READ_COLUMN, /**< Change Read Column */ + CHANGE_READ_COLUMN_ENHANCED, /**< Change Read Column Enhanced */ + READ_CACHE_RANDOM, /**< Read Cache Random */ + READ_CACHE_SEQUENTIAL, /**< Read Cache Sequential */ + READ_CACHE_END, /**< Read Cache End */ + BLOCK_ERASE, /**< Block Erase */ + MULTIPLANE_BLOCK_ERASE, /**< Multiplane Block Erase */ + READ_STATUS, /**< Read Status */ + READ_STATUS_ENHANCED, /**< Read Status Enhanced */ + PAGE_PROGRAM, /**< Page Program */ + MULTIPLANE_PAGE_PROGRAM, /**< Multiplane Page Program */ + PAGE_CACHE_PROGRAM, /**< Page Cache Program */ + COPYBACK_PROGRAM, /**< Copyback Program */ + MULTIPLANE_COPYBACK_PROGRAM, /**< Multiplance Copyback Program */ + SMALL_DATA_MOVE, /**< Small Data Move */ + CHANGE_WRITE_COLUMN, /**< Change Write Column */ + CHANGE_ROW_ADDR, /**< Change Row Address */ + READ_ID, /**< Read ID */ + VOLUME_SELECT, /**< Volume Select */ + ODT_CONFIGURE, /**< ODT Configure */ + READ_PARAM_PAGE, /**< Read Parameter Page */ + READ_UNIQUE_ID, /**< Read Unique ID */ + GET_FEATURES, /**< Get Features */ + SET_FEATURES, /**< Set Features */ + LUN_GET_FEATURES, /**< LUN Get Features */ + LUN_SET_FEATURES, /**< LUN Set Features */ + RESET_LUN, /**< Reset LUN */ + SYN_RESET, /**< Synchronous Reset */ + RESET, /**< Reset */ + MAX_CMDS /**< Dummy Command */ +}; + +/**************************** Type Definitions *******************************/ +/* + * Parameter page structure of ONFI 3.1 specification. + */ +typedef struct { + /* + * Revision information and features block + */ + u8 Signature[4]; /**< Parameter page signature */ + u16 Revision; /**< Revision Number */ + u16 Features; /**< Features supported */ + u16 OptionalCmds; /**< Optional commands supported */ + u8 JedecJtgPrmAdvCmd; /**< ONFI JEDEC JTG primary advanced + command support */ + u8 Reserved0; /**< Reserved (11) */ + u16 ExtParamPageLen; /**< Extended Parameter Page Length */ + u8 NumOfParamPages; /**< Number of Parameter Pages */ + u8 Reserved1[17]; /**< Reserved (15-31) */ + /* + * Manufacturer information block + */ + u8 DeviceManufacturer[12]; /**< Device manufacturer */ + u8 DeviceModel[20]; /**< Device model */ + u8 JedecManufacturerId; /**< JEDEC Manufacturer ID */ + u8 DateCode[2]; /**< Date code */ + u8 Reserved2[13]; /**< Reserved (67-79) */ + /* + * Memory organization block + */ + u32 BytesPerPage; /**< Number of data bytes per page */ + u16 SpareBytesPerPage; /**< Number of spare bytes per page */ + u32 BytesPerPartialPage; /**< Number of data bytes per + partial page */ + u16 SpareBytesPerPartialPage; /**< Number of spare bytes per + partial page */ + u32 PagesPerBlock; /**< Number of pages per block */ + u32 BlocksPerLun; /**< Number of blocks per LUN */ + u8 NumLuns; /**< Number of LUN's */ + u8 AddrCycles; /**< Number of address cycles */ + u8 BitsPerCell; /**< Number of bits per cell */ + u16 MaxBadBlocksPerLun; /**< Bad blocks maximum per LUN */ + u16 BlockEndurance; /**< Block endurance */ + u8 GuaranteedValidBlock; /**< Guaranteed valid blocks at + beginning of target */ + u16 BlockEnduranceGVB; /**< Block endurance for guaranteed + valid block */ + u8 ProgramsPerPage; /**< Number of programs per page */ + u8 PartialProgAttr; /**< Partial programming attributes */ + u8 EccBits; /**< Number of bits ECC + correctability */ + u8 PlaneAddrBits; /**< Number of plane address bits */ + u8 PlaneOperationAttr; /**< Multi-plane operation + attributes */ + u8 EzNandSupport; /**< EZ NAND support */ + u8 Reserved3[12]; /**< Reserved (116 - 127) */ + /* + * Electrical parameters block + */ + u8 IOPinCapacitance; /**< I/O pin capacitance, maximum */ + u16 SDRTimingMode; /**< SDR Timing mode support */ + u16 SDRPagecacheTimingMode; /**< SDR Program cache timing mode */ + u16 TProg; /**< Maximum page program time */ + u16 TBers; /**< Maximum block erase time */ + u16 TR; /**< Maximum page read time */ + u16 TCcs; /**< Maximum change column setup + time */ + u8 NVDDRTimingMode; /**< NVDDR timing mode support */ + u8 NVDDR2TimingMode; /**< NVDDR2 timing mode support */ + u8 SynFeatures; /**< NVDDR/NVDDR2 features */ + u16 ClkInputPinCap; /**< CLK input pin capacitance */ + u16 IOPinCap; /**< I/O pin capacitance */ + u16 InputPinCap; /**< Input pin capacitance typical */ + u8 InputPinCapMax; /**< Input pin capacitance maximum */ + u8 DrvStrength; /**< Driver strength support */ + u16 TMr; /**< Maximum multi-plane read time */ + u16 TAdl; /**< Program page register clear + enhancement value */ + u16 TEr; /**< Typical page read time for + EZ NAND */ + u8 NVDDR2Features; /**< NVDDR2 Features */ + u8 NVDDR2WarmupCycles; /**< NVDDR2 Warmup Cycles */ + u8 Reserved4[4]; /**< Reserved (160 - 163) */ + /* + * Vendor block + */ + u16 VendorRevisionNum; /**< Vendor specific revision number */ + u8 VendorSpecific[88]; /**< Vendor specific */ + u16 Crc; /**< Integrity CRC */ +}__attribute__((packed))OnfiParamPage; + +/* + * ONFI extended parameter page structure. + */ +typedef struct { + u16 Crc; + u8 Sig[4]; + u8 Reserved1[10]; + u8 Section0Type; + u8 Section0Len; + u8 Section1Type; + u8 Section1Len; + u8 ResSection[12]; + u8 SectionData[256]; +}__attribute__((packed))OnfiExtPrmPage; + +/* + * Driver extended parameter page information. + */ +typedef struct { + u8 NumBitsEcc; + u8 CodeWordSize; + u16 MaxBadBlocks; + u16 BlockEndurance; + u16 Reserved; +}__attribute__((packed))OnfiExtEccBlock; + +typedef struct { + u8 Command1; /**< Command Cycle 1 */ + u8 Command2; /**< Command Cycle 2 */ +} OnfiCmdFormat; + +extern const OnfiCmdFormat OnfiCmd[MAX_CMDS]; + +/************************** Function Prototypes ******************************/ + +u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length); + +#ifdef __cplusplus +} +#endif + +#endif /* XNANDPSU_ONFI_H end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xocm_xmpu_cfg.h new file mode 100644 index 000000000..5e3631f3e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xocm_xmpu_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XOCM_XMPU_CFG_H__ +#define __XOCM_XMPU_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XocmXmpuCfg Base Address + */ +#define XOCM_XMPU_CFG_BASEADDR 0xFFA70000UL + +/** + * Register: XocmXmpuCfgCtrl + */ +#define XOCM_XMPU_CFG_CTRL ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000000UL ) +#define XOCM_XMPU_CFG_CTRL_RSTVAL 0x00000003UL + +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XocmXmpuCfgErrSts1 + */ +#define XOCM_XMPU_CFG_ERR_STS1 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000004UL ) +#define XOCM_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgErrSts2 + */ +#define XOCM_XMPU_CFG_ERR_STS2 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000008UL ) +#define XOCM_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgPoison + */ +#define XOCM_XMPU_CFG_POISON ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) +#define XOCM_XMPU_CFG_POISON_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_POISON_BASE_SHIFT 0UL +#define XOCM_XMPU_CFG_POISON_BASE_WIDTH 20UL +#define XOCM_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL +#define XOCM_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgIsr + */ +#define XOCM_XMPU_CFG_ISR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000010UL ) +#define XOCM_XMPU_CFG_ISR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_ISR_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgImr + */ +#define XOCM_XMPU_CFG_IMR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000014UL ) +#define XOCM_XMPU_CFG_IMR_RSTVAL 0x0000000fUL + +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IMR_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XocmXmpuCfgIen + */ +#define XOCM_XMPU_CFG_IEN ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000018UL ) +#define XOCM_XMPU_CFG_IEN_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IEN_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgIds + */ +#define XOCM_XMPU_CFG_IDS ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) +#define XOCM_XMPU_CFG_IDS_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IDS_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgLock + */ +#define XOCM_XMPU_CFG_LOCK ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000020UL ) +#define XOCM_XMPU_CFG_LOCK_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00Strt + */ +#define XOCM_XMPU_CFG_R00_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000100UL ) +#define XOCM_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00End + */ +#define XOCM_XMPU_CFG_R00_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000104UL ) +#define XOCM_XMPU_CFG_R00_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00Mstr + */ +#define XOCM_XMPU_CFG_R00_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000108UL ) +#define XOCM_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00 + */ +#define XOCM_XMPU_CFG_R00 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) +#define XOCM_XMPU_CFG_R00_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R00_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R00_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R00_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R00_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01Strt + */ +#define XOCM_XMPU_CFG_R01_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000110UL ) +#define XOCM_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01End + */ +#define XOCM_XMPU_CFG_R01_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000114UL ) +#define XOCM_XMPU_CFG_R01_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01Mstr + */ +#define XOCM_XMPU_CFG_R01_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000118UL ) +#define XOCM_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01 + */ +#define XOCM_XMPU_CFG_R01 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) +#define XOCM_XMPU_CFG_R01_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R01_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R01_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R01_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R01_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02Strt + */ +#define XOCM_XMPU_CFG_R02_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000120UL ) +#define XOCM_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02End + */ +#define XOCM_XMPU_CFG_R02_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000124UL ) +#define XOCM_XMPU_CFG_R02_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02Mstr + */ +#define XOCM_XMPU_CFG_R02_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000128UL ) +#define XOCM_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02 + */ +#define XOCM_XMPU_CFG_R02 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) +#define XOCM_XMPU_CFG_R02_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R02_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R02_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R02_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R02_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03Strt + */ +#define XOCM_XMPU_CFG_R03_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000130UL ) +#define XOCM_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03End + */ +#define XOCM_XMPU_CFG_R03_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000134UL ) +#define XOCM_XMPU_CFG_R03_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03Mstr + */ +#define XOCM_XMPU_CFG_R03_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000138UL ) +#define XOCM_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03 + */ +#define XOCM_XMPU_CFG_R03 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) +#define XOCM_XMPU_CFG_R03_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R03_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R03_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R03_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R03_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04Strt + */ +#define XOCM_XMPU_CFG_R04_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000140UL ) +#define XOCM_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04End + */ +#define XOCM_XMPU_CFG_R04_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000144UL ) +#define XOCM_XMPU_CFG_R04_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04Mstr + */ +#define XOCM_XMPU_CFG_R04_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000148UL ) +#define XOCM_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04 + */ +#define XOCM_XMPU_CFG_R04 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) +#define XOCM_XMPU_CFG_R04_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R04_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R04_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R04_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R04_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05Strt + */ +#define XOCM_XMPU_CFG_R05_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000150UL ) +#define XOCM_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05End + */ +#define XOCM_XMPU_CFG_R05_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000154UL ) +#define XOCM_XMPU_CFG_R05_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05Mstr + */ +#define XOCM_XMPU_CFG_R05_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000158UL ) +#define XOCM_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05 + */ +#define XOCM_XMPU_CFG_R05 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) +#define XOCM_XMPU_CFG_R05_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R05_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R05_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R05_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R05_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06Strt + */ +#define XOCM_XMPU_CFG_R06_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000160UL ) +#define XOCM_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06End + */ +#define XOCM_XMPU_CFG_R06_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000164UL ) +#define XOCM_XMPU_CFG_R06_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06Mstr + */ +#define XOCM_XMPU_CFG_R06_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000168UL ) +#define XOCM_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06 + */ +#define XOCM_XMPU_CFG_R06 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) +#define XOCM_XMPU_CFG_R06_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R06_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R06_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R06_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R06_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07Strt + */ +#define XOCM_XMPU_CFG_R07_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000170UL ) +#define XOCM_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07End + */ +#define XOCM_XMPU_CFG_R07_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000174UL ) +#define XOCM_XMPU_CFG_R07_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07Mstr + */ +#define XOCM_XMPU_CFG_R07_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000178UL ) +#define XOCM_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07 + */ +#define XOCM_XMPU_CFG_R07 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) +#define XOCM_XMPU_CFG_R07_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R07_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R07_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R07_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R07_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08Strt + */ +#define XOCM_XMPU_CFG_R08_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000180UL ) +#define XOCM_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08End + */ +#define XOCM_XMPU_CFG_R08_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000184UL ) +#define XOCM_XMPU_CFG_R08_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08Mstr + */ +#define XOCM_XMPU_CFG_R08_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000188UL ) +#define XOCM_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08 + */ +#define XOCM_XMPU_CFG_R08 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) +#define XOCM_XMPU_CFG_R08_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R08_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R08_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R08_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R08_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09Strt + */ +#define XOCM_XMPU_CFG_R09_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000190UL ) +#define XOCM_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09End + */ +#define XOCM_XMPU_CFG_R09_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000194UL ) +#define XOCM_XMPU_CFG_R09_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09Mstr + */ +#define XOCM_XMPU_CFG_R09_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000198UL ) +#define XOCM_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09 + */ +#define XOCM_XMPU_CFG_R09 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) +#define XOCM_XMPU_CFG_R09_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R09_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R09_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R09_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R09_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10Strt + */ +#define XOCM_XMPU_CFG_R10_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) +#define XOCM_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10End + */ +#define XOCM_XMPU_CFG_R10_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) +#define XOCM_XMPU_CFG_R10_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10Mstr + */ +#define XOCM_XMPU_CFG_R10_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) +#define XOCM_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10 + */ +#define XOCM_XMPU_CFG_R10 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) +#define XOCM_XMPU_CFG_R10_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R10_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R10_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R10_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R10_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11Strt + */ +#define XOCM_XMPU_CFG_R11_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) +#define XOCM_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11End + */ +#define XOCM_XMPU_CFG_R11_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) +#define XOCM_XMPU_CFG_R11_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11Mstr + */ +#define XOCM_XMPU_CFG_R11_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) +#define XOCM_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11 + */ +#define XOCM_XMPU_CFG_R11 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) +#define XOCM_XMPU_CFG_R11_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R11_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R11_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R11_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R11_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12Strt + */ +#define XOCM_XMPU_CFG_R12_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) +#define XOCM_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12End + */ +#define XOCM_XMPU_CFG_R12_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) +#define XOCM_XMPU_CFG_R12_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12Mstr + */ +#define XOCM_XMPU_CFG_R12_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) +#define XOCM_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12 + */ +#define XOCM_XMPU_CFG_R12 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) +#define XOCM_XMPU_CFG_R12_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R12_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R12_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R12_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R12_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13Strt + */ +#define XOCM_XMPU_CFG_R13_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) +#define XOCM_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13End + */ +#define XOCM_XMPU_CFG_R13_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) +#define XOCM_XMPU_CFG_R13_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13Mstr + */ +#define XOCM_XMPU_CFG_R13_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) +#define XOCM_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13 + */ +#define XOCM_XMPU_CFG_R13 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) +#define XOCM_XMPU_CFG_R13_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R13_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R13_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R13_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R13_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14Strt + */ +#define XOCM_XMPU_CFG_R14_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) +#define XOCM_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14End + */ +#define XOCM_XMPU_CFG_R14_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) +#define XOCM_XMPU_CFG_R14_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14Mstr + */ +#define XOCM_XMPU_CFG_R14_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) +#define XOCM_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14 + */ +#define XOCM_XMPU_CFG_R14 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) +#define XOCM_XMPU_CFG_R14_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R14_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R14_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R14_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R14_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15Strt + */ +#define XOCM_XMPU_CFG_R15_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) +#define XOCM_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15End + */ +#define XOCM_XMPU_CFG_R15_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) +#define XOCM_XMPU_CFG_R15_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15Mstr + */ +#define XOCM_XMPU_CFG_R15_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) +#define XOCM_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15 + */ +#define XOCM_XMPU_CFG_R15 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) +#define XOCM_XMPU_CFG_R15_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R15_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R15_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R15_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R15_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XOCM_XMPU_CFG_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h new file mode 100644 index 000000000..91f1bf835 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h @@ -0,0 +1,1458 @@ +/* Definition for CPU ID */ +#define XPAR_CPU_ID 0 + +/* Definitions for peripheral PSU_CORTEXA53_0 */ +#define XPAR_PSU_CORTEXA53_0_CPU_CLK_FREQ_HZ 23809000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_CORTEXA53_0 */ +#define XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ 23809000 + + +/******************************************************************/ + +#include "xparameters_ps.h" + +#define STDIN_BASEADDRESS 0xFF000000 +#define STDOUT_BASEADDRESS 0xFF000000 + +/******************************************************************/ + +/* Definitions for driver AXIPMON */ +#define XPAR_XAXIPMON_NUM_INSTANCES 4 + +/* Definitions for peripheral PSU_APM_0 */ +#define XPAR_PSU_APM_0_DEVICE_ID 0 +#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000 +#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFF +#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32 +#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1 +#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6 +#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10 +#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0 +#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32 +#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1 +#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1 +#define XPAR_PSU_APM_0_ENABLE_PROFILE 0 +#define XPAR_PSU_APM_0_ENABLE_TRACE 0 +#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000 +#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 0 + + +/* Definitions for peripheral PSU_APM_1 */ +#define XPAR_PSU_APM_1_DEVICE_ID 1 +#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000 +#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFF +#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32 +#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1 +#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1 +#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3 +#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0 +#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32 +#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1 +#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1 +#define XPAR_PSU_APM_1_ENABLE_PROFILE 0 +#define XPAR_PSU_APM_1_ENABLE_TRACE 0 +#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000 +#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 0 + + +/* Definitions for peripheral PSU_APM_2 */ +#define XPAR_PSU_APM_2_DEVICE_ID 2 +#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000 +#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFF +#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32 +#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1 +#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1 +#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3 +#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0 +#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32 +#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1 +#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1 +#define XPAR_PSU_APM_2_ENABLE_PROFILE 0 +#define XPAR_PSU_APM_2_ENABLE_TRACE 0 +#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000 +#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 0 + + +/* Definitions for peripheral PSU_APM_5 */ +#define XPAR_PSU_APM_5_DEVICE_ID 3 +#define XPAR_PSU_APM_5_BASEADDR 0xFD490000 +#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFF +#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32 +#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1 +#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1 +#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3 +#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0 +#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32 +#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1 +#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1 +#define XPAR_PSU_APM_5_ENABLE_PROFILE 0 +#define XPAR_PSU_APM_5_ENABLE_TRACE 0 +#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000 +#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_APM_0 */ +#define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID +#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000 +#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFF +#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32 +#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1 +#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6 +#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10 +#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0 +#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32 +#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1 +#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1 +#define XPAR_AXIPMON_0_ENABLE_PROFILE 0 +#define XPAR_AXIPMON_0_ENABLE_TRACE 0 +#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000 +#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 0 + +/* Canonical definitions for peripheral PSU_APM_1 */ +#define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID +#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000 +#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFF +#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32 +#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1 +#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1 +#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3 +#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0 +#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32 +#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1 +#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1 +#define XPAR_AXIPMON_1_ENABLE_PROFILE 0 +#define XPAR_AXIPMON_1_ENABLE_TRACE 0 +#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000 +#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 0 + +/* Canonical definitions for peripheral PSU_APM_2 */ +#define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID +#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000 +#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFF +#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32 +#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1 +#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1 +#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3 +#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0 +#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32 +#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1 +#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1 +#define XPAR_AXIPMON_2_ENABLE_PROFILE 0 +#define XPAR_AXIPMON_2_ENABLE_TRACE 0 +#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000 +#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 0 + +/* Canonical definitions for peripheral PSU_APM_5 */ +#define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID +#define XPAR_AXIPMON_3_BASEADDR 0xFD490000 +#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFF +#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32 +#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1 +#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1 +#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3 +#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0 +#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32 +#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1 +#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1 +#define XPAR_AXIPMON_3_ENABLE_PROFILE 0 +#define XPAR_AXIPMON_3_ENABLE_TRACE 0 +#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000 +#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 0 + + +/******************************************************************/ + +/* Definitions for driver CANPS */ +#define XPAR_XCANPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_CAN_0 */ +#define XPAR_PSU_CAN_0_DEVICE_ID 0 +#define XPAR_PSU_CAN_0_BASEADDR 0xFF060000 +#define XPAR_PSU_CAN_0_HIGHADDR 0xFF06FFFF +#define XPAR_PSU_CAN_0_CAN_CLK_FREQ_HZ 25000000 + + +/* Definitions for peripheral PSU_CAN_1 */ +#define XPAR_PSU_CAN_1_DEVICE_ID 1 +#define XPAR_PSU_CAN_1_BASEADDR 0xFF070000 +#define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF +#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 25000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_CAN_0 */ +#define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_0_DEVICE_ID +#define XPAR_XCANPS_0_BASEADDR 0xFF060000 +#define XPAR_XCANPS_0_HIGHADDR 0xFF06FFFF +#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 25000000 + +/* Canonical definitions for peripheral PSU_CAN_1 */ +#define XPAR_XCANPS_1_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID +#define XPAR_XCANPS_1_BASEADDR 0xFF070000 +#define XPAR_XCANPS_1_HIGHADDR 0xFF07FFFF +#define XPAR_XCANPS_1_CAN_CLK_FREQ_HZ 25000000 + + +/******************************************************************/ + +/* Definitions for driver CSUDMA */ +#define XPAR_XCSUDMA_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_CSUDMA */ +#define XPAR_PSU_CSUDMA_DEVICE_ID 0 +#define XPAR_PSU_CSUDMA_BASEADDR 0xFFC80000 +#define XPAR_PSU_CSUDMA_HIGHADDR 0xFFC9FFFF +#define XPAR_PSU_CSUDMA_CSUDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_CSUDMA */ +#define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSU_CSUDMA_DEVICE_ID +#define XPAR_XCSUDMA_0_BASEADDR 0xFFC80000 +#define XPAR_XCSUDMA_0_HIGHADDR 0xFFC9FFFF +#define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +/* Definitions for driver EMACPS */ +#define XPAR_XEMACPS_NUM_INSTANCES 4 + +/* Definitions for peripheral PSU_ETHERNET_0 */ +#define XPAR_PSU_ETHERNET_0_DEVICE_ID 0 +#define XPAR_PSU_ETHERNET_0_BASEADDR 0xFF0B0000 +#define XPAR_PSU_ETHERNET_0_HIGHADDR 0xFF0BFFFF +#define XPAR_PSU_ETHERNET_0_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50000000 + + +/* Definitions for peripheral PSU_ETHERNET_1 */ +#define XPAR_PSU_ETHERNET_1_DEVICE_ID 1 +#define XPAR_PSU_ETHERNET_1_BASEADDR 0xFF0C0000 +#define XPAR_PSU_ETHERNET_1_HIGHADDR 0xFF0CFFFF +#define XPAR_PSU_ETHERNET_1_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 50000000 + + +/* Definitions for peripheral PSU_ETHERNET_2 */ +#define XPAR_PSU_ETHERNET_2_DEVICE_ID 2 +#define XPAR_PSU_ETHERNET_2_BASEADDR 0xFF0D0000 +#define XPAR_PSU_ETHERNET_2_HIGHADDR 0xFF0DFFFF +#define XPAR_PSU_ETHERNET_2_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1 50000000 + + +/* Definitions for peripheral PSU_ETHERNET_3 */ +#define XPAR_PSU_ETHERNET_3_DEVICE_ID 3 +#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000 +#define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF +#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_ETHERNET_0 */ +#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_0_DEVICE_ID +#define XPAR_XEMACPS_0_BASEADDR 0xFF0B0000 +#define XPAR_XEMACPS_0_HIGHADDR 0xFF0BFFFF +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000 + +/* Canonical definitions for peripheral PSU_ETHERNET_1 */ +#define XPAR_XEMACPS_1_DEVICE_ID XPAR_PSU_ETHERNET_1_DEVICE_ID +#define XPAR_XEMACPS_1_BASEADDR 0xFF0C0000 +#define XPAR_XEMACPS_1_HIGHADDR 0xFF0CFFFF +#define XPAR_XEMACPS_1_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV0 50000000 +#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV1 50000000 +#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV0 50000000 +#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV1 50000000 +#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV0 50000000 +#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV1 50000000 + +/* Canonical definitions for peripheral PSU_ETHERNET_2 */ +#define XPAR_XEMACPS_2_DEVICE_ID XPAR_PSU_ETHERNET_2_DEVICE_ID +#define XPAR_XEMACPS_2_BASEADDR 0xFF0D0000 +#define XPAR_XEMACPS_2_HIGHADDR 0xFF0DFFFF +#define XPAR_XEMACPS_2_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_XEMACPS_2_ENET_SLCR_1000Mbps_DIV0 50000000 +#define XPAR_XEMACPS_2_ENET_SLCR_1000Mbps_DIV1 50000000 +#define XPAR_XEMACPS_2_ENET_SLCR_100Mbps_DIV0 50000000 +#define XPAR_XEMACPS_2_ENET_SLCR_100Mbps_DIV1 50000000 +#define XPAR_XEMACPS_2_ENET_SLCR_10Mbps_DIV0 50000000 +#define XPAR_XEMACPS_2_ENET_SLCR_10Mbps_DIV1 50000000 + +/* Canonical definitions for peripheral PSU_ETHERNET_3 */ +#define XPAR_XEMACPS_3_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID +#define XPAR_XEMACPS_3_BASEADDR 0xFF0E0000 +#define XPAR_XEMACPS_3_HIGHADDR 0xFF0EFFFF +#define XPAR_XEMACPS_3_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_XEMACPS_3_ENET_SLCR_1000Mbps_DIV0 50000000 +#define XPAR_XEMACPS_3_ENET_SLCR_1000Mbps_DIV1 50000000 +#define XPAR_XEMACPS_3_ENET_SLCR_100Mbps_DIV0 50000000 +#define XPAR_XEMACPS_3_ENET_SLCR_100Mbps_DIV1 50000000 +#define XPAR_XEMACPS_3_ENET_SLCR_10Mbps_DIV0 50000000 +#define XPAR_XEMACPS_3_ENET_SLCR_10Mbps_DIV1 50000000 + + +/******************************************************************/ + + +/* Definitions for peripheral PSU_AFI_0 */ +#define XPAR_PSU_AFI_0_S_AXI_BASEADDR 0xFD360000 +#define XPAR_PSU_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF + + +/* Definitions for peripheral PSU_AFI_1 */ +#define XPAR_PSU_AFI_1_S_AXI_BASEADDR 0xFD370000 +#define XPAR_PSU_AFI_1_S_AXI_HIGHADDR 0xFD37FFFF + + +/* Definitions for peripheral PSU_AFI_2 */ +#define XPAR_PSU_AFI_2_S_AXI_BASEADDR 0xFD380000 +#define XPAR_PSU_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF + + +/* Definitions for peripheral PSU_AFI_3 */ +#define XPAR_PSU_AFI_3_S_AXI_BASEADDR 0xFD390000 +#define XPAR_PSU_AFI_3_S_AXI_HIGHADDR 0xFD39FFFF + + +/* Definitions for peripheral PSU_AFI_4 */ +#define XPAR_PSU_AFI_4_S_AXI_BASEADDR 0xFD3A0000 +#define XPAR_PSU_AFI_4_S_AXI_HIGHADDR 0xFD3AFFFF + + +/* Definitions for peripheral PSU_AFI_5 */ +#define XPAR_PSU_AFI_5_S_AXI_BASEADDR 0xFD3B0000 +#define XPAR_PSU_AFI_5_S_AXI_HIGHADDR 0xFD3BFFFF + + +/* Definitions for peripheral PSU_AFI_6 */ +#define XPAR_PSU_AFI_6_S_AXI_BASEADDR 0xFF9B0000 +#define XPAR_PSU_AFI_6_S_AXI_HIGHADDR 0xFF9BFFFF + + +/* Definitions for peripheral PSU_AMS */ +#define XPAR_PSU_AMS_S_AXI_BASEADDR 0xFFA50000 +#define XPAR_PSU_AMS_S_AXI_HIGHADDR 0xFFA5FFFF + + +/* Definitions for peripheral PSU_APU */ +#define XPAR_PSU_APU_S_AXI_BASEADDR 0xFD5C0000 +#define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF + + +/* Definitions for peripheral PSU_BBRAM_0 */ +#define XPAR_PSU_BBRAM_0_S_AXI_BASEADDR 0xFFCD0000 +#define XPAR_PSU_BBRAM_0_S_AXI_HIGHADDR 0xFFCDFFFF + + +/* Definitions for peripheral PSU_CCI_GPV */ +#define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000 +#define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF + + +/* Definitions for peripheral PSU_CCI_REG */ +#define XPAR_PSU_CCI_REG_S_AXI_BASEADDR 0xFD5E0000 +#define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF + + +/* Definitions for peripheral PSU_CORESIGHT_0 */ +#define XPAR_PSU_CORESIGHT_0_S_AXI_BASEADDR 0xFE800000 +#define XPAR_PSU_CORESIGHT_0_S_AXI_HIGHADDR 0xFE80FFFF + + +/* Definitions for peripheral PSU_CRF_APB */ +#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000 +#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF + + +/* Definitions for peripheral PSU_CRL_APB */ +#define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000 +#define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF + + +/* Definitions for peripheral PSU_DDR_0 */ +#define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000 +#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF + + +/* Definitions for peripheral PSU_DDR_PHY */ +#define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000 +#define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF + + +/* Definitions for peripheral PSU_DDR_QOS_CTRL */ +#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_BASEADDR 0xFD090000 +#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_HIGHADDR 0xFD09FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU0_CFG */ +#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_BASEADDR 0xFD000000 +#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_HIGHADDR 0xFD00FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU1_CFG */ +#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_BASEADDR 0xFD010000 +#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_HIGHADDR 0xFD01FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU2_CFG */ +#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_BASEADDR 0xFD020000 +#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_HIGHADDR 0xFD02FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU3_CFG */ +#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_BASEADDR 0xFD030000 +#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_HIGHADDR 0xFD03FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU4_CFG */ +#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_BASEADDR 0xFD040000 +#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_HIGHADDR 0xFD04FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU5_CFG */ +#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_BASEADDR 0xFD050000 +#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF + + +/* Definitions for peripheral PSU_DDRC_0 */ +#define XPAR_PSU_DDRC_0_S_AXI_BASEADDR 0xFD070000 +#define XPAR_PSU_DDRC_0_S_AXI_HIGHADDR 0xFD070FFF + + +/* Definitions for peripheral PSU_DP */ +#define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000 +#define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF + + +/* Definitions for peripheral PSU_DPDMA */ +#define XPAR_PSU_DPDMA_S_AXI_BASEADDR 0xFD4C0000 +#define XPAR_PSU_DPDMA_S_AXI_HIGHADDR 0xFD4CFFFF + + +/* Definitions for peripheral PSU_EFUSE */ +#define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000 +#define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF + + +/* Definitions for peripheral PSU_FPD_GPV */ +#define XPAR_PSU_FPD_GPV_S_AXI_BASEADDR 0xFD700000 +#define XPAR_PSU_FPD_GPV_S_AXI_HIGHADDR 0xFD7FFFFF + + +/* Definitions for peripheral PSU_FPD_SLCR */ +#define XPAR_PSU_FPD_SLCR_S_AXI_BASEADDR 0xFD610000 +#define XPAR_PSU_FPD_SLCR_S_AXI_HIGHADDR 0xFD68FFFF + + +/* Definitions for peripheral PSU_FPD_SLCR_SECURE */ +#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_BASEADDR 0xFD690000 +#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFD6CFFFF + + +/* Definitions for peripheral PSU_FPD_XMPU_CFG */ +#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_BASEADDR 0xFD5D0000 +#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_HIGHADDR 0xFD5DFFFF + + +/* Definitions for peripheral PSU_FPD_XMPU_SINK */ +#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_BASEADDR 0xFD4F0000 +#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_HIGHADDR 0xFD4FFFFF + + +/* Definitions for peripheral PSU_GPU */ +#define XPAR_PSU_GPU_S_AXI_BASEADDR 0xFD4B0000 +#define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF + + +/* Definitions for peripheral PSU_IOU_S */ +#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000 +#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF + + +/* Definitions for peripheral PSU_IOU_SCNTR */ +#define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000 +#define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF + + +/* Definitions for peripheral PSU_IOU_SCNTRS */ +#define XPAR_PSU_IOU_SCNTRS_S_AXI_BASEADDR 0xFF260000 +#define XPAR_PSU_IOU_SCNTRS_S_AXI_HIGHADDR 0xFF26FFFF + + +/* Definitions for peripheral PSU_IOUSECURE_SLCR */ +#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_BASEADDR 0xFF240000 +#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_HIGHADDR 0xFF24FFFF + + +/* Definitions for peripheral PSU_IOUSLCR_0 */ +#define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000 +#define XPAR_PSU_IOUSLCR_0_S_AXI_HIGHADDR 0xFF23FFFF + + +/* Definitions for peripheral PSU_LPD_SLCR */ +#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000 +#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF + + +/* Definitions for peripheral PSU_LPD_SLCR_SECURE */ +#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_BASEADDR 0xFF4B0000 +#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFF4DFFFF + + +/* Definitions for peripheral PSU_LPD_XPPU */ +#define XPAR_PSU_LPD_XPPU_S_AXI_BASEADDR 0xFF980000 +#define XPAR_PSU_LPD_XPPU_S_AXI_HIGHADDR 0xFF99FFFF + + +/* Definitions for peripheral PSU_LPD_XPPU_SINK */ +#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_BASEADDR 0xFF9C0000 +#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_HIGHADDR 0xFF9CFFFF + + +/* Definitions for peripheral PSU_MBISTJTAG */ +#define XPAR_PSU_MBISTJTAG_S_AXI_BASEADDR 0xFFCF0000 +#define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF + + +/* Definitions for peripheral PSU_OCM */ +#define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000 +#define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF + + +/* Definitions for peripheral PSU_OCM_RAM_0 */ +#define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000 +#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF + + +/* Definitions for peripheral PSU_OCM_RAM_1 */ +#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000 +#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF + + +/* Definitions for peripheral PSU_OCM_XMPU_CFG */ +#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000 +#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF + + +/* Definitions for peripheral PSU_PCIE */ +#define XPAR_PSU_PCIE_S_AXI_BASEADDR 0xFD0E0000 +#define XPAR_PSU_PCIE_S_AXI_HIGHADDR 0xFD0EFFFF + + +/* Definitions for peripheral PSU_PCIE_ATTRIB_0 */ +#define XPAR_PSU_PCIE_ATTRIB_0_S_AXI_BASEADDR 0xFD480000 +#define XPAR_PSU_PCIE_ATTRIB_0_S_AXI_HIGHADDR 0xFD48FFFF + + +/* Definitions for peripheral PSU_PCIE_DMA */ +#define XPAR_PSU_PCIE_DMA_S_AXI_BASEADDR 0xFD0F0000 +#define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF + + +/* Definitions for peripheral PSU_PMU_GLOBAL_0 */ +#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000 +#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF + + +/* Definitions for peripheral PSU_PMU_IOMODULE */ +#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000 +#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF + + +/* Definitions for peripheral PSU_PMU_RAM */ +#define XPAR_PSU_PMU_RAM_S_AXI_BASEADDR 0xFFDC0000 +#define XPAR_PSU_PMU_RAM_S_AXI_HIGHADDR 0xFFDDFFFF + + +/* Definitions for peripheral PSU_QSPI_LINEAR_0 */ +#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000 +#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF + + +/* Definitions for peripheral PSU_R5_0_ATCM */ +#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0xFFE00000 +#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0xFFE0FFFF + + +/* Definitions for peripheral PSU_R5_0_ATCM_LOCKSTEP */ +#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE10000 +#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE1FFFF + + +/* Definitions for peripheral PSU_R5_0_BTCM */ +#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0xFFE20000 +#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0xFFE2FFFF + + +/* Definitions for peripheral PSU_R5_0_BTCM_LOCKSTEP */ +#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE30000 +#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE3FFFF + + +/* Definitions for peripheral PSU_R5_1_ATCM */ +#define XPAR_PSU_R5_1_ATCM_S_AXI_BASEADDR 0xFFE90000 +#define XPAR_PSU_R5_1_ATCM_S_AXI_HIGHADDR 0xFFE9FFFF + + +/* Definitions for peripheral PSU_R5_1_BTCM */ +#define XPAR_PSU_R5_1_BTCM_S_AXI_BASEADDR 0xFFEB0000 +#define XPAR_PSU_R5_1_BTCM_S_AXI_HIGHADDR 0xFFEBFFFF + + +/* Definitions for peripheral PSU_R5_DDR_0 */ +#define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000 +#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF + + +/* Definitions for peripheral PSU_RPU */ +#define XPAR_PSU_RPU_S_AXI_BASEADDR 0xFF9A0000 +#define XPAR_PSU_RPU_S_AXI_HIGHADDR 0xFF9AFFFF + + +/* Definitions for peripheral PSU_RSA */ +#define XPAR_PSU_RSA_S_AXI_BASEADDR 0xFFCE0000 +#define XPAR_PSU_RSA_S_AXI_HIGHADDR 0xFFCEFFFF + + +/* Definitions for peripheral PSU_RTC */ +#define XPAR_PSU_RTC_S_AXI_BASEADDR 0xFFA60000 +#define XPAR_PSU_RTC_S_AXI_HIGHADDR 0xFFA6FFFF + + +/* Definitions for peripheral PSU_SATA */ +#define XPAR_PSU_SATA_S_AXI_BASEADDR 0xFD0C0000 +#define XPAR_PSU_SATA_S_AXI_HIGHADDR 0xFD0CFFFF + + +/* Definitions for peripheral PSU_SERDES */ +#define XPAR_PSU_SERDES_S_AXI_BASEADDR 0xFD400000 +#define XPAR_PSU_SERDES_S_AXI_HIGHADDR 0xFD47FFFF + + +/* Definitions for peripheral PSU_SIOU */ +#define XPAR_PSU_SIOU_S_AXI_BASEADDR 0xFD3D0000 +#define XPAR_PSU_SIOU_S_AXI_HIGHADDR 0xFD3DFFFF + + +/* Definitions for peripheral PSU_SMMU_GPV */ +#define XPAR_PSU_SMMU_GPV_S_AXI_BASEADDR 0xFD800000 +#define XPAR_PSU_SMMU_GPV_S_AXI_HIGHADDR 0xFDFFFFFF + + +/* Definitions for peripheral PSU_SMMU_REG */ +#define XPAR_PSU_SMMU_REG_S_AXI_BASEADDR 0xFD5F0000 +#define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF + + +/******************************************************************/ + +/* Definitions for driver GPIOPS */ +#define XPAR_XGPIOPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_GPIO_0 */ +#define XPAR_PSU_GPIO_0_DEVICE_ID 0 +#define XPAR_PSU_GPIO_0_BASEADDR 0xFF0A0000 +#define XPAR_PSU_GPIO_0_HIGHADDR 0xFF0AFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_GPIO_0 */ +#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID +#define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000 +#define XPAR_XGPIOPS_0_HIGHADDR 0xFF0AFFFF + + +/******************************************************************/ + +/* Definitions for driver IICPS */ +#define XPAR_XIICPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_I2C_0 */ +#define XPAR_PSU_I2C_0_DEVICE_ID 0 +#define XPAR_PSU_I2C_0_BASEADDR 0xFF020000 +#define XPAR_PSU_I2C_0_HIGHADDR 0xFF02FFFF +#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 25000000 + + +/* Definitions for peripheral PSU_I2C_1 */ +#define XPAR_PSU_I2C_1_DEVICE_ID 1 +#define XPAR_PSU_I2C_1_BASEADDR 0xFF030000 +#define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF +#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 4000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_I2C_0 */ +#define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_0_DEVICE_ID +#define XPAR_XIICPS_0_BASEADDR 0xFF020000 +#define XPAR_XIICPS_0_HIGHADDR 0xFF02FFFF +#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 25000000 + +/* Canonical definitions for peripheral PSU_I2C_1 */ +#define XPAR_XIICPS_1_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID +#define XPAR_XIICPS_1_BASEADDR 0xFF030000 +#define XPAR_XIICPS_1_HIGHADDR 0xFF03FFFF +#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 4000000 + + +/******************************************************************/ + +#define XPAR_XIPIPSU_NUM_INSTANCES 1 + +/* Parameter definitions for peripheral psu_ipi_0 */ +#define XPAR_PSU_IPI_0_DEVICE_ID 0 +#define XPAR_PSU_IPI_0_BASE_ADDRESS 0xFF300000 +#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001 +#define XPAR_PSU_IPI_0_BUFFER_INDEX 2 +#define XPAR_PSU_IPI_0_INT_ID 67 + +/* Canonical definitions for peripheral psu_ipi_0 */ +#define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_0_DEVICE_ID +#define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_0_BASE_ADDRESS +#define XPAR_XIPIPSU_0_BIT_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_0_BUFFER_INDEX +#define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_0_INT_ID + +#define XPAR_XIPIPSU_NUM_TARGETS 11 + +#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001 +#define XPAR_PSU_IPI_0_BUFFER_INDEX 2 +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100 +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0 +#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200 +#define XPAR_PSU_IPI_2_BUFFER_INDEX 1 +#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000 +#define XPAR_PSU_IPI_3_BUFFER_INDEX 7 +#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000 +#define XPAR_PSU_IPI_4_BUFFER_INDEX 7 +#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000 +#define XPAR_PSU_IPI_5_BUFFER_INDEX 7 +#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000 +#define XPAR_PSU_IPI_6_BUFFER_INDEX 7 +#define XPAR_PSU_IPI_7_BIT_MASK 0x01000000 +#define XPAR_PSU_IPI_7_BUFFER_INDEX 3 +#define XPAR_PSU_IPI_8_BIT_MASK 0x02000000 +#define XPAR_PSU_IPI_8_BUFFER_INDEX 4 +#define XPAR_PSU_IPI_9_BIT_MASK 0x04000000 +#define XPAR_PSU_IPI_9_BUFFER_INDEX 5 +#define XPAR_PSU_IPI_10_BIT_MASK 0x08000000 +#define XPAR_PSU_IPI_10_BUFFER_INDEX 6 +/* Target List for referring to processor IPI Targets */ + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_MICROBLAZE_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_MICROBLAZE_0_CH0_INDEX 3 +#define XPAR_XIPIPS_TARGET_PSU_MICROBLAZE_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_MICROBLAZE_0_CH1_INDEX 4 +#define XPAR_XIPIPS_TARGET_PSU_MICROBLAZE_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_MICROBLAZE_0_CH2_INDEX 5 +#define XPAR_XIPIPS_TARGET_PSU_MICROBLAZE_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_MICROBLAZE_0_CH3_INDEX 6 + +/* Definitions for driver NANDPSU */ +#define XPAR_XNANDPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_NAND_0 */ +#define XPAR_PSU_NAND_0_DEVICE_ID 0 +#define XPAR_PSU_NAND_0_BASEADDR 0xFF100000 +#define XPAR_PSU_NAND_0_HIGHADDR 0xFF10FFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_NAND_0 */ +#define XPAR_XNANDPSU_0_DEVICE_ID XPAR_PSU_NAND_0_DEVICE_ID +#define XPAR_XNANDPSU_0_BASEADDR 0xFF100000 +#define XPAR_XNANDPSU_0_HIGHADDR 0xFF10FFFF + + +/******************************************************************/ + +/* Definitions for driver QSPIPSU */ +#define XPAR_XQSPIPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_QSPI_0 */ +#define XPAR_PSU_QSPI_0_DEVICE_ID 0 +#define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000 +#define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF +#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 20000000 +#define XPAR_PSU_QSPI_0_QSPI_MODE 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_QSPI_0 */ +#define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID +#define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000 +#define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF +#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 20000000 +#define XPAR_XQSPIPSU_0_QSPI_MODE 0 + + +/******************************************************************/ + +/* Definitions for driver SCUGIC */ +#define XPAR_XSCUGIC_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_ACPU_GIC */ +#define XPAR_PSU_ACPU_GIC_DEVICE_ID 0 +#define XPAR_PSU_ACPU_GIC_BASEADDR 0xF9020000 +#define XPAR_PSU_ACPU_GIC_HIGHADDR 0xF9020FFF +#define XPAR_PSU_ACPU_GIC_DIST_BASEADDR 0xF9010000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_ACPU_GIC */ +#define XPAR_SCUGIC_0_DEVICE_ID 0 +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9020000 +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9020FFF +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9010000 + + +/******************************************************************/ + +/* Definitions for driver SDPS */ +#define XPAR_XSDPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_SD_0 */ +#define XPAR_PSU_SD_0_DEVICE_ID 0 +#define XPAR_PSU_SD_0_BASEADDR 0xFF160000 +#define XPAR_PSU_SD_0_HIGHADDR 0xFF16FFFF +#define XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ 20000000 +#define XPAR_PSU_SD_0_HAS_CD 50000000 +#define XPAR_PSU_SD_0_HAS_WP 50000000 + + +/* Definitions for peripheral PSU_SD_1 */ +#define XPAR_PSU_SD_1_DEVICE_ID 1 +#define XPAR_PSU_SD_1_BASEADDR 0xFF170000 +#define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF +#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 20000000 +#define XPAR_PSU_SD_1_HAS_CD 50000000 +#define XPAR_PSU_SD_1_HAS_WP 50000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_SD_0 */ +#define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_0_DEVICE_ID +#define XPAR_XSDPS_0_BASEADDR 0xFF160000 +#define XPAR_XSDPS_0_HIGHADDR 0xFF16FFFF +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 20000000 +#define XPAR_XSDPS_0_HAS_CD 50000000 +#define XPAR_XSDPS_0_HAS_WP 50000000 + +/* Canonical definitions for peripheral PSU_SD_1 */ +#define XPAR_XSDPS_1_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID +#define XPAR_XSDPS_1_BASEADDR 0xFF170000 +#define XPAR_XSDPS_1_HIGHADDR 0xFF17FFFF +#define XPAR_XSDPS_1_SDIO_CLK_FREQ_HZ 20000000 +#define XPAR_XSDPS_1_HAS_CD 50000000 +#define XPAR_XSDPS_1_HAS_WP 50000000 + + +/******************************************************************/ + +/* Definitions for driver SPIPS */ +#define XPAR_XSPIPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_SPI_0 */ +#define XPAR_PSU_SPI_0_DEVICE_ID 0 +#define XPAR_PSU_SPI_0_BASEADDR 0xFF040000 +#define XPAR_PSU_SPI_0_HIGHADDR 0xFF04FFFF +#define XPAR_PSU_SPI_0_SPI_CLK_FREQ_HZ 25000000 + + +/* Definitions for peripheral PSU_SPI_1 */ +#define XPAR_PSU_SPI_1_DEVICE_ID 1 +#define XPAR_PSU_SPI_1_BASEADDR 0xFF050000 +#define XPAR_PSU_SPI_1_HIGHADDR 0xFF05FFFF +#define XPAR_PSU_SPI_1_SPI_CLK_FREQ_HZ 4000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_SPI_0 */ +#define XPAR_XSPIPS_0_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID +#define XPAR_XSPIPS_0_BASEADDR 0xFF040000 +#define XPAR_XSPIPS_0_HIGHADDR 0xFF04FFFF +#define XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ 25000000 + +/* Canonical definitions for peripheral PSU_SPI_1 */ +#define XPAR_XSPIPS_1_DEVICE_ID XPAR_PSU_SPI_1_DEVICE_ID +#define XPAR_XSPIPS_1_BASEADDR 0xFF050000 +#define XPAR_XSPIPS_1_HIGHADDR 0xFF05FFFF +#define XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ 4000000 + + +/******************************************************************/ + +/* Definitions for driver TTCPS */ +#define XPAR_XTTCPS_NUM_INSTANCES 12 + +/* Definitions for peripheral PSU_TTC_0 */ +#define XPAR_PSU_TTC_0_DEVICE_ID 0 +#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000 +#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_1_DEVICE_ID 1 +#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004 +#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_2_DEVICE_ID 2 +#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008 +#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0 + + +/* Definitions for peripheral PSU_TTC_1 */ +#define XPAR_PSU_TTC_3_DEVICE_ID 3 +#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000 +#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_4_DEVICE_ID 4 +#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004 +#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_5_DEVICE_ID 5 +#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008 +#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0 + + +/* Definitions for peripheral PSU_TTC_2 */ +#define XPAR_PSU_TTC_6_DEVICE_ID 6 +#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000 +#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_7_DEVICE_ID 7 +#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004 +#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_8_DEVICE_ID 8 +#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008 +#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0 + + +/* Definitions for peripheral PSU_TTC_3 */ +#define XPAR_PSU_TTC_9_DEVICE_ID 9 +#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000 +#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_10_DEVICE_ID 10 +#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004 +#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_11_DEVICE_ID 11 +#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008 +#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_TTC_0 */ +#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID +#define XPAR_XTTCPS_0_BASEADDR 0xFF110000 +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID +#define XPAR_XTTCPS_1_BASEADDR 0xFF110004 +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID +#define XPAR_XTTCPS_2_BASEADDR 0xFF110008 +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0 + +/* Canonical definitions for peripheral PSU_TTC_1 */ +#define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID +#define XPAR_XTTCPS_3_BASEADDR 0xFF120000 +#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID +#define XPAR_XTTCPS_4_BASEADDR 0xFF120004 +#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID +#define XPAR_XTTCPS_5_BASEADDR 0xFF120008 +#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0 + +/* Canonical definitions for peripheral PSU_TTC_2 */ +#define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID +#define XPAR_XTTCPS_6_BASEADDR 0xFF130000 +#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID +#define XPAR_XTTCPS_7_BASEADDR 0xFF130004 +#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID +#define XPAR_XTTCPS_8_BASEADDR 0xFF130008 +#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0 + +/* Canonical definitions for peripheral PSU_TTC_3 */ +#define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID +#define XPAR_XTTCPS_9_BASEADDR 0xFF140000 +#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID +#define XPAR_XTTCPS_10_BASEADDR 0xFF140004 +#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID +#define XPAR_XTTCPS_11_BASEADDR 0xFF140008 +#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 25000000 +#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0 + + +/******************************************************************/ + +/* Definitions for driver UARTPS */ +#define XPAR_XUARTPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_UART_0 */ +#define XPAR_PSU_UART_0_DEVICE_ID 0 +#define XPAR_PSU_UART_0_BASEADDR 0xFF000000 +#define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF +#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_UART_0_HAS_MODEM 0 + + +/* Definitions for peripheral PSU_UART_1 */ +#define XPAR_PSU_UART_1_DEVICE_ID 1 +#define XPAR_PSU_UART_1_BASEADDR 0xFF010000 +#define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF +#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 25000000 +#define XPAR_PSU_UART_1_HAS_MODEM 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_UART_0 */ +#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID +#define XPAR_XUARTPS_0_BASEADDR 0xFF000000 +#define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 25000000 +#define XPAR_XUARTPS_0_HAS_MODEM 0 + +/* Canonical definitions for peripheral PSU_UART_1 */ +#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID +#define XPAR_XUARTPS_1_BASEADDR 0xFF010000 +#define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF +#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 25000000 +#define XPAR_XUARTPS_1_HAS_MODEM 0 + + +/******************************************************************/ + +/* Definitions for driver USBPSU */ +#define XPAR_XUSBPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_USB_0 */ +#define XPAR_PSU_USB_0_DEVICE_ID 0 +#define XPAR_PSU_USB_0_BASEADDR 0xFE200000 +#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_USB_0 */ +#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID +#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000 +#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF + + +/******************************************************************/ + +/* Definitions for driver WDTPS */ +#define XPAR_XWDTPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_WDT_0 */ +#define XPAR_PSU_WDT_0_DEVICE_ID 0 +#define XPAR_PSU_WDT_0_BASEADDR 0xFF150000 +#define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF +#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000 + + +/* Definitions for peripheral PSU_WDT_1 */ +#define XPAR_PSU_WDT_1_DEVICE_ID 1 +#define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000 +#define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF +#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_WDT_0 */ +#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID +#define XPAR_XWDTPS_0_BASEADDR 0xFF150000 +#define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF +#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000 + +/* Canonical definitions for peripheral PSU_WDT_1 */ +#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID +#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000 +#define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF +#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000 + + +/******************************************************************/ + +/* Definitions for driver ZDMA */ +#define XPAR_XZDMA_NUM_INSTANCES 16 + +/* Definitions for peripheral PSU_ADMA_0 */ +#define XPAR_PSU_ADMA_0_DEVICE_ID 0 +#define XPAR_PSU_ADMA_0_BASEADDR 0xFFA80000 +#define XPAR_PSU_ADMA_0_DMA_MODE 1 +#define XPAR_PSU_ADMA_0_HIGHADDR 0xFFA8FFFF +#define XPAR_PSU_ADMA_0_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_1 */ +#define XPAR_PSU_ADMA_1_DEVICE_ID 1 +#define XPAR_PSU_ADMA_1_BASEADDR 0xFFA90000 +#define XPAR_PSU_ADMA_1_DMA_MODE 1 +#define XPAR_PSU_ADMA_1_HIGHADDR 0xFFA9FFFF +#define XPAR_PSU_ADMA_1_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_2 */ +#define XPAR_PSU_ADMA_2_DEVICE_ID 2 +#define XPAR_PSU_ADMA_2_BASEADDR 0xFFAA0000 +#define XPAR_PSU_ADMA_2_DMA_MODE 1 +#define XPAR_PSU_ADMA_2_HIGHADDR 0xFFAAFFFF +#define XPAR_PSU_ADMA_2_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_3 */ +#define XPAR_PSU_ADMA_3_DEVICE_ID 3 +#define XPAR_PSU_ADMA_3_BASEADDR 0xFFAB0000 +#define XPAR_PSU_ADMA_3_DMA_MODE 1 +#define XPAR_PSU_ADMA_3_HIGHADDR 0xFFABFFFF +#define XPAR_PSU_ADMA_3_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_4 */ +#define XPAR_PSU_ADMA_4_DEVICE_ID 4 +#define XPAR_PSU_ADMA_4_BASEADDR 0xFFAC0000 +#define XPAR_PSU_ADMA_4_DMA_MODE 1 +#define XPAR_PSU_ADMA_4_HIGHADDR 0xFFACFFFF +#define XPAR_PSU_ADMA_4_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_5 */ +#define XPAR_PSU_ADMA_5_DEVICE_ID 5 +#define XPAR_PSU_ADMA_5_BASEADDR 0xFFAD0000 +#define XPAR_PSU_ADMA_5_DMA_MODE 1 +#define XPAR_PSU_ADMA_5_HIGHADDR 0xFFADFFFF +#define XPAR_PSU_ADMA_5_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_6 */ +#define XPAR_PSU_ADMA_6_DEVICE_ID 6 +#define XPAR_PSU_ADMA_6_BASEADDR 0xFFAE0000 +#define XPAR_PSU_ADMA_6_DMA_MODE 1 +#define XPAR_PSU_ADMA_6_HIGHADDR 0xFFAEFFFF +#define XPAR_PSU_ADMA_6_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_7 */ +#define XPAR_PSU_ADMA_7_DEVICE_ID 7 +#define XPAR_PSU_ADMA_7_BASEADDR 0xFFAF0000 +#define XPAR_PSU_ADMA_7_DMA_MODE 1 +#define XPAR_PSU_ADMA_7_HIGHADDR 0xFFAFFFFF +#define XPAR_PSU_ADMA_7_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_0 */ +#define XPAR_PSU_GDMA_0_DEVICE_ID 8 +#define XPAR_PSU_GDMA_0_BASEADDR 0xFD500000 +#define XPAR_PSU_GDMA_0_DMA_MODE 0 +#define XPAR_PSU_GDMA_0_HIGHADDR 0xFD50FFFF +#define XPAR_PSU_GDMA_0_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_1 */ +#define XPAR_PSU_GDMA_1_DEVICE_ID 9 +#define XPAR_PSU_GDMA_1_BASEADDR 0xFD510000 +#define XPAR_PSU_GDMA_1_DMA_MODE 0 +#define XPAR_PSU_GDMA_1_HIGHADDR 0xFD51FFFF +#define XPAR_PSU_GDMA_1_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_2 */ +#define XPAR_PSU_GDMA_2_DEVICE_ID 10 +#define XPAR_PSU_GDMA_2_BASEADDR 0xFD520000 +#define XPAR_PSU_GDMA_2_DMA_MODE 0 +#define XPAR_PSU_GDMA_2_HIGHADDR 0xFD52FFFF +#define XPAR_PSU_GDMA_2_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_3 */ +#define XPAR_PSU_GDMA_3_DEVICE_ID 11 +#define XPAR_PSU_GDMA_3_BASEADDR 0xFD530000 +#define XPAR_PSU_GDMA_3_DMA_MODE 0 +#define XPAR_PSU_GDMA_3_HIGHADDR 0xFD53FFFF +#define XPAR_PSU_GDMA_3_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_4 */ +#define XPAR_PSU_GDMA_4_DEVICE_ID 12 +#define XPAR_PSU_GDMA_4_BASEADDR 0xFD540000 +#define XPAR_PSU_GDMA_4_DMA_MODE 0 +#define XPAR_PSU_GDMA_4_HIGHADDR 0xFD54FFFF +#define XPAR_PSU_GDMA_4_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_5 */ +#define XPAR_PSU_GDMA_5_DEVICE_ID 13 +#define XPAR_PSU_GDMA_5_BASEADDR 0xFD550000 +#define XPAR_PSU_GDMA_5_DMA_MODE 0 +#define XPAR_PSU_GDMA_5_HIGHADDR 0xFD55FFFF +#define XPAR_PSU_GDMA_5_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_6 */ +#define XPAR_PSU_GDMA_6_DEVICE_ID 14 +#define XPAR_PSU_GDMA_6_BASEADDR 0xFD560000 +#define XPAR_PSU_GDMA_6_DMA_MODE 0 +#define XPAR_PSU_GDMA_6_HIGHADDR 0xFD56FFFF +#define XPAR_PSU_GDMA_6_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_7 */ +#define XPAR_PSU_GDMA_7_DEVICE_ID 15 +#define XPAR_PSU_GDMA_7_BASEADDR 0xFD570000 +#define XPAR_PSU_GDMA_7_DMA_MODE 0 +#define XPAR_PSU_GDMA_7_HIGHADDR 0xFD57FFFF +#define XPAR_PSU_GDMA_7_ZDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_ADMA_0 */ +#define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID +#define XPAR_XZDMA_0_BASEADDR 0xFFA80000 +#define XPAR_XZDMA_0_DMA_MODE 1 +#define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF +#define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_1 */ +#define XPAR_XZDMA_1_DEVICE_ID XPAR_PSU_ADMA_1_DEVICE_ID +#define XPAR_XZDMA_1_BASEADDR 0xFFA90000 +#define XPAR_XZDMA_1_DMA_MODE 1 +#define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF +#define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_2 */ +#define XPAR_XZDMA_2_DEVICE_ID XPAR_PSU_ADMA_2_DEVICE_ID +#define XPAR_XZDMA_2_BASEADDR 0xFFAA0000 +#define XPAR_XZDMA_2_DMA_MODE 1 +#define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF +#define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_3 */ +#define XPAR_XZDMA_3_DEVICE_ID XPAR_PSU_ADMA_3_DEVICE_ID +#define XPAR_XZDMA_3_BASEADDR 0xFFAB0000 +#define XPAR_XZDMA_3_DMA_MODE 1 +#define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF +#define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_4 */ +#define XPAR_XZDMA_4_DEVICE_ID XPAR_PSU_ADMA_4_DEVICE_ID +#define XPAR_XZDMA_4_BASEADDR 0xFFAC0000 +#define XPAR_XZDMA_4_DMA_MODE 1 +#define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF +#define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_5 */ +#define XPAR_XZDMA_5_DEVICE_ID XPAR_PSU_ADMA_5_DEVICE_ID +#define XPAR_XZDMA_5_BASEADDR 0xFFAD0000 +#define XPAR_XZDMA_5_DMA_MODE 1 +#define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF +#define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_6 */ +#define XPAR_XZDMA_6_DEVICE_ID XPAR_PSU_ADMA_6_DEVICE_ID +#define XPAR_XZDMA_6_BASEADDR 0xFFAE0000 +#define XPAR_XZDMA_6_DMA_MODE 1 +#define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF +#define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_7 */ +#define XPAR_XZDMA_7_DEVICE_ID XPAR_PSU_ADMA_7_DEVICE_ID +#define XPAR_XZDMA_7_BASEADDR 0xFFAF0000 +#define XPAR_XZDMA_7_DMA_MODE 1 +#define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF +#define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_0 */ +#define XPAR_XZDMA_8_DEVICE_ID XPAR_PSU_GDMA_0_DEVICE_ID +#define XPAR_XZDMA_8_BASEADDR 0xFD500000 +#define XPAR_XZDMA_8_DMA_MODE 0 +#define XPAR_XZDMA_8_HIGHADDR 0xFD50FFFF +#define XPAR_XZDMA_8_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_1 */ +#define XPAR_XZDMA_9_DEVICE_ID XPAR_PSU_GDMA_1_DEVICE_ID +#define XPAR_XZDMA_9_BASEADDR 0xFD510000 +#define XPAR_XZDMA_9_DMA_MODE 0 +#define XPAR_XZDMA_9_HIGHADDR 0xFD51FFFF +#define XPAR_XZDMA_9_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_2 */ +#define XPAR_XZDMA_10_DEVICE_ID XPAR_PSU_GDMA_2_DEVICE_ID +#define XPAR_XZDMA_10_BASEADDR 0xFD520000 +#define XPAR_XZDMA_10_DMA_MODE 0 +#define XPAR_XZDMA_10_HIGHADDR 0xFD52FFFF +#define XPAR_XZDMA_10_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_3 */ +#define XPAR_XZDMA_11_DEVICE_ID XPAR_PSU_GDMA_3_DEVICE_ID +#define XPAR_XZDMA_11_BASEADDR 0xFD530000 +#define XPAR_XZDMA_11_DMA_MODE 0 +#define XPAR_XZDMA_11_HIGHADDR 0xFD53FFFF +#define XPAR_XZDMA_11_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_4 */ +#define XPAR_XZDMA_12_DEVICE_ID XPAR_PSU_GDMA_4_DEVICE_ID +#define XPAR_XZDMA_12_BASEADDR 0xFD540000 +#define XPAR_XZDMA_12_DMA_MODE 0 +#define XPAR_XZDMA_12_HIGHADDR 0xFD54FFFF +#define XPAR_XZDMA_12_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_5 */ +#define XPAR_XZDMA_13_DEVICE_ID XPAR_PSU_GDMA_5_DEVICE_ID +#define XPAR_XZDMA_13_BASEADDR 0xFD550000 +#define XPAR_XZDMA_13_DMA_MODE 0 +#define XPAR_XZDMA_13_HIGHADDR 0xFD55FFFF +#define XPAR_XZDMA_13_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_6 */ +#define XPAR_XZDMA_14_DEVICE_ID XPAR_PSU_GDMA_6_DEVICE_ID +#define XPAR_XZDMA_14_BASEADDR 0xFD560000 +#define XPAR_XZDMA_14_DMA_MODE 0 +#define XPAR_XZDMA_14_HIGHADDR 0xFD56FFFF +#define XPAR_XZDMA_14_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_7 */ +#define XPAR_XZDMA_15_DEVICE_ID XPAR_PSU_GDMA_7_DEVICE_ID +#define XPAR_XZDMA_15_BASEADDR 0xFD570000 +#define XPAR_XZDMA_15_DMA_MODE 0 +#define XPAR_XZDMA_15_HIGHADDR 0xFD57FFFF +#define XPAR_XZDMA_15_ZDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters_ps.h new file mode 100644 index 000000000..d86e6fc54 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters_ps.h @@ -0,0 +1,317 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* This file contains the address definitions for the hard peripherals +* attached to the ARM Cortex A53 core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XPARAMETERS_PS_H_ +#define _XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID +#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID +#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID +#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID +#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID +#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID +#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID +#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID +#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID +#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID +#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID +#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID +#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID +#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID +#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID +#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID +#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID +#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID +#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID +#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID +#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID +#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID +#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID +#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID +#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID +#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID +#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID +#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID +#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID +#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID +#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID +#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for backwards compatibilty + */ + + +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U +#define XPS_SCU_PERIPH_BASE 0xF9000000U + + + +/* Shared Peripheral Interrupts (SPI) */ + +/* FIXME */ +/*#define XPS_FPGA0_INT_ID 100U */ +#define XPS_FPGA1_INT_ID 62U +#define XPS_FPGA2_INT_ID 63U +#define XPS_FPGA3_INT_ID 64U +#define XPS_FPGA4_INT_ID 65U +#define XPS_FPGA5_INT_ID 66U +#define XPS_FPGA6_INT_ID 67U +#define XPS_FPGA7_INT_ID 68U +#define XPS_DMA4_INT_ID 72U +#define XPS_DMA5_INT_ID 73U +#define XPS_DMA6_INT_ID 74U +#define XPS_DMA7_INT_ID 75U +#define XPS_FPGA8_INT_ID 84U +#define XPS_FPGA9_INT_ID 85U +#define XPS_FPGA10_INT_ID 86U +#define XPS_FPGA11_INT_ID 87U +#define XPS_FPGA12_INT_ID 88U +#define XPS_FPGA13_INT_ID 89U +#define XPS_FPGA14_INT_ID 90U +#define XPS_FPGA15_INT_ID 91U + +/* Updated Interrupt-IDs */ +#define XPS_OCMINTR_INT_ID (10U + 32U) +#define XPS_NAND_INT_ID (14U + 32U) +#define XPS_QSPI_INT_ID (15U + 32U) +#define XPS_GPIO_INT_ID (16U + 32U) +#define XPS_I2C0_INT_ID (17U + 32U) +#define XPS_I2C1_INT_ID (18U + 32U) +#define XPS_SPI0_INT_ID (19U + 32U) +#define XPS_SPI1_INT_ID (20U + 32U) +#define XPS_UART0_INT_ID (21U + 32U) +#define XPS_UART1_INT_ID (22U + 32U) +#define XPS_CAN0_INT_ID (23U + 32U) +#define XPS_CAN1_INT_ID (24U + 32U) +#define XPS_WDT_INT_ID (52U + 32U) +#define XPS_TTC0_0_INT_ID (36U + 32U) +#define XPS_TTC0_1_INT_ID (37U + 32U) +#define XPS_TTC0_2_INT_ID (38U + 32U) +#define XPS_TTC1_0_INT_ID (39U + 32U) +#define XPS_TTC1_1_INT_ID (40U + 32U) +#define XPS_TTC1_2_INT_ID (41U + 32U) +#define XPS_TTC2_0_INT_ID (42U + 32U) +#define XPS_TTC2_1_INT_ID (43U + 32U) +#define XPS_TTC2_2_INT_ID (44U + 32U) +#define XPS_TTC3_0_INT_ID (45U + 32U) +#define XPS_TTC3_1_INT_ID (46U + 32U) +#define XPS_TTC3_2_INT_ID (47U + 32U) +#define XPS_SDIO0_INT_ID (48U + 32U) +#define XPS_SDIO1_INT_ID (49U + 32U) +#define XPS_GEM0_INT_ID (57U + 32U) +#define XPS_GEM0_WAKE_INT_ID (58U + 32U) +#define XPS_GEM1_INT_ID (59U + 32U) +#define XPS_GEM1_WAKE_INT_ID (60U + 32U) +#define XPS_GEM2_INT_ID (61U + 32U) +#define XPS_GEM2_WAKE_INT_ID (62U + 32U) +#define XPS_GEM3_INT_ID (63U + 32U) +#define XPS_GEM3_WAKE_INT_ID (64U + 32U) +#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U) +#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U) +#define XPS_ADMA_CH0_INT_ID (77U + 32U) +#define XPS_ADMA_CH1_INT_ID (78U + 32U) +#define XPS_ADMA_CH2_INT_ID (79U + 32U) +#define XPS_ADMA_CH3_INT_ID (80U + 32U) +#define XPS_ADMA_CH4_INT_ID (81U + 32U) +#define XPS_ADMA_CH5_INT_ID (82U + 32U) +#define XPS_ADMA_CH6_INT_ID (83U + 32U) +#define XPS_ADMA_CH7_INT_ID (84U + 32U) +#define XPS_CSU_DMA_INT_ID (86U + 32U) +#define XPS_XMPU_LPD_INT_ID (88U + 32U) +#define XPS_ZDMA_CH0_INT_ID (124U + 32U) +#define XPS_ZDMA_CH1_INT_ID (125U + 32U) +#define XPS_ZDMA_CH2_INT_ID (126U + 32U) +#define XPS_ZDMA_CH3_INT_ID (127U + 32U) +#define XPS_ZDMA_CH4_INT_ID (128U + 32U) +#define XPS_ZDMA_CH5_INT_ID (129U + 32U) +#define XPS_ZDMA_CH6_INT_ID (130U + 32U) +#define XPS_ZDMA_CH7_INT_ID (131U + 32U) +#define XPS_XMPU_FPD_INT_ID (134U + 32U) +#define XPS_FPD_CCI_INT_ID (154U + 32U) +#define XPS_FPD_SMMU_INT_ID (155U + 32U) + +/* Private Peripheral Interrupts (PPI) */ +/*#define XPS_GLOBAL_TMR_INT_ID 27 SCU Global Timer interrupt */ +/*#define XPS_FIQ_INT_ID 28 FIQ from FPGA fabric */ +/*#define XPS_SCU_TMR_INT_ID 29 SCU Private Timer interrupt */ +/*#define XPS_SCU_WDT_INT_ID 30 SCU Private WDT interrupt */ +/*#define XPS_IRQ_INT_ID 31 IRQ from FPGA fabric */ + +/* REDEFINES for TEST APP */ +/* Definitions for UART */ +#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID +#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID +#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID + +#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID +#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID +#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID +#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID + +#define XPAR_XADCPS_NUM_INSTANCES 1U +#define XPAR_XADCPS_0_DEVICE_ID 0U +#define XPAR_XADCPS_0_BASEADDR (0xF8007000U) +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibilty */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUTIMER_DEVICE_ID 0U +#define XPAR_SCUWDT_DEVICE_ID 0U + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xplatform_info.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xplatform_info.h new file mode 100644 index 000000000..d71a692c1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xplatform_info.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xplatform_info.h +* +* This file contains definitions for various platforms available +* +******************************************************************************/ + +#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */ +#define XPLATFORM_INFO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +#define XPAR_CSU_BASEADDR 0xFFCA0000U +#define XPAR_CSU_VER_OFFSET 0x00000044U + +#define XPLAT_ZYNQ_ULTRA_MP 0x1 +#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2 +#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3 +#define XPLAT_ZYNQ 0x4 +#define XPLAT_MICROBLAZE 0x5 + +#define XPLAT_INFO_MASK (0xF) +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +u32 XGetPlatform_Info(); + +#if defined (ARMR5) || (__aarch64__) +u32 XGet_Zynq_UltraMp_Platform_info(); +#endif +/************************** Function Prototypes ******************************/ + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xpseudo_asm.h new file mode 100644 index 000000000..e5e02751d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xpseudo_asm.h @@ -0,0 +1,53 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* This header file contains macros for using inline assembler code. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H +#include "xreg_cortexa53.h" +#include "xpseudo_asm_gcc.h" + +#endif /* XPSEUDO_ASM_H */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xpseudo_asm_gcc.h new file mode 100644 index 000000000..5f0e9c25c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xpseudo_asm_gcc.h @@ -0,0 +1,169 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+*
+* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) + +#define mtcpsr(v) asm ("msr DAIF, %0" : : "r" (v)) + +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") + +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ + +#define mfgpr(rn) /*({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() asm ("isb sy") + +/* Data Synchronization Barrier */ +#define dsb() asm("dsb sy") + +/* Data Memory Barrier */ +#define dmb() asm("dmb sy") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) +#define mtcpdc(reg,val) asm("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) asm("ic " #reg ",%0" : : "r" (val)) + +#define mtcpicall(reg) asm("ic " #reg) +#define mtcptlbi(reg) asm("tlbi " #reg) +#define mtcpat(reg,val) asm("at " #reg ",%0" : : "r" (val)) +/* CP15 operations */ +#define mfcp(reg) ({u32 rval;\ + asm("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) + +#define mtcp(reg,val) asm("msr " #reg ",%0" : : "r" (val)) + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xqspipsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xqspipsu.h new file mode 100644 index 000000000..9395ea260 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xqspipsu.h @@ -0,0 +1,263 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspipsu.h +* +* This is the header file for the implementation of QSPIPSU driver. +* Generic QSPI interface allows for communication to any QSPI slave device. +* GQSPI contains a GENFIFO into which the bus transfers required are to be +* pushed with appropriate configuration. The controller provides TX and RX +* FIFO's and a DMA to be used for RX transfers. The controller executes each +* GENFIFO entry noting the configuration and places data on the bus as required +* +* The different options in GENFIFO are as follows: +* IMM_DATA : Can be one byte of data to be transmitted, number of clocks or +* number of bytes in transfer. +* DATA_XFER : Indicates that data/clocks need to be transmitted or received. +* EXPONENT : e when 2^e bytes are involved in transfer. +* SPI_MODE : SPI/Dual SPI/Quad SPI +* CS : Lower or Upper CS or Both +* Bus : Lower or Upper Bus or Both +* TX : When selected, controller transmits data in IMM or fetches number of +* bytes mentioned form TX FIFO. If not selected, dummies are pumped. +* RX : When selected, controller receives and fills the RX FIFO/allows RX DMA +* of requested number of bytes. If not selected, RX data is discarded. +* Stripe : Byte stripe over lower and upper bus or not. +* Poll : Polls response to match for to a set value (used along with POLL_CFG +* registers) and then proceeds to next GENFIFO entry. +* This feature is not currently used in the driver. +* +* GENFIFO has manual and auto start options. +* All DMA requests need a 4-byte aligned destination address buffer and +* size of transfer should also be a multiple of 4. +* This driver supports DMA RX and IO RX. +* +* Initialization: +* This driver uses the GQSPI controller with RX DMA. It supports both +* interrupt and polled transfers. Manual start of GENFIFO is used. +* XQspiPsu_CfgInitialize() initializes the instance variables. +* Additional setting can be done using SetOptions/ClearOptions functions +* and SelectSlave function. +* +* Transfer: +* Polled or Interrupt transfers can be done. The transfer function needs the +* message(s) to be transmitted in the form of an array of type XQspiPsu_Msg. +* This is supposed to contain the byte count and any TX/RX buffers as required. +* Flags can be used indicate further information such as whether the message +* should be striped. The transfer functions form and write GENFIFO entries, +* check the status of the transfer and report back to the application +* when done. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+*                    Clear and disbale DMA interrupts/status in abort.
+*                    Use DMA DONE bit instead of BUSY as recommended.
+*
+*
+* +******************************************************************************/ +#ifndef _XQSPIPSU_H_ /* prevent circular inclusions */ +#define _XQSPIPSU_H_ /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xqspipsu_hw.h" + +/**************************** Type Definitions *******************************/ +/** + * The handler data type allows the user to define a callback function to + * handle the asynchronous processing for the QSPIPSU device. The application + * using this driver is expected to define a handler of this type to support + * interrupt driven mode. The handler executes in an interrupt context, so + * only minimal processing should be performed. + * + * @param CallBackRef is the callback reference passed in by the upper + * layer when setting the callback functions, and passed back to + * the upper layer when the callback is invoked. Its type is + * not important to the driver, so it is a void pointer. + * @param StatusEvent holds one or more status events that have occurred. + * See the XQspiPsu_SetStatusHandler() for details on the status + * events that can be passed in the callback. + * @param ByteCount indicates how many bytes of data were successfully + * transferred. This may be less than the number of bytes + * requested if the status event indicates an error. + */ +typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent, + unsigned ByteCount); + +/** + * This typedef contains configuration information for a flash message. + */ +typedef struct { + u8 *TxBfrPtr; + u8 *RxBfrPtr; + u32 ByteCount; + u32 BusWidth; + u32 Flags; +} XQspiPsu_Msg; + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ + u8 BusWidth; /**< Bus width available on board */ +} XQspiPsu_Config; + +/** + * The XQspiPsu driver instance data. The user is required to allocate a + * variable of this type for every QSPIPSU device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XQspiPsu_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + + u8 *SendBufferPtr; /**< Buffer to send (state) */ + u8 *RecvBufferPtr; /**< Buffer to receive (state) */ + u8 *GenFifoBufferPtr; /**< Gen FIFO entries */ + int TxBytes; /**< Number of bytes to transfer (state) */ + int RxBytes; /**< Number of bytes left to transfer(state) */ + int GenFifoEntries; /**< Number of Gen FIFO entries remaining */ + u32 IsBusy; /**< A transfer is in progress (state) */ + u32 ReadMode; /**< DMA or IO mode */ + u32 GenFifoCS; + u32 GenFifoBus; + int NumMsg; + int MsgCnt; + int IsUnaligned; + XQspiPsu_Msg *Msg; + XQspiPsu_StatusHandler StatusHandler; + void *StatusRef; /**< Callback reference for status handler */ +} XQspiPsu; + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XQSPIPSU_READMODE_DMA 0x0 +#define XQSPIPSU_READMODE_IO 0x1 + +#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1 +#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2 +#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3 + +#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1 +#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2 +#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3 + +#define XQSPIPSU_SELECT_MODE_SPI 0x1 +#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2 +#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4 + +#define XQSPIPSU_GENFIFO_CS_SETUP 0x04 +#define XQSPIPSU_GENFIFO_CS_HOLD 0x03 + +#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2 +#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4 +#define XQSPIPSU_MANUAL_START_OPTION 0x8 + +#define XQSPIPSU_GENFIFO_EXP_START 0x100 + +#define XQSPIPSU_DMA_BYTES_MAX 0x10000000 + +#define XQSPIPSU_CLK_PRESCALE_2 0x00 +#define XQSPIPSU_CLK_PRESCALE_4 0x01 +#define XQSPIPSU_CLK_PRESCALE_8 0x02 +#define XQSPIPSU_CLK_PRESCALE_16 0x03 +#define XQSPIPSU_CLK_PRESCALE_32 0x04 +#define XQSPIPSU_CLK_PRESCALE_64 0x05 +#define XQSPIPSU_CLK_PRESCALE_128 0x06 +#define XQSPIPSU_CLK_PRESCALE_256 0x07 +#define XQSPIPSU_CR_PRESC_MAXIMUM 7 + +#define XQSPIPSU_CONNECTION_MODE_SINGLE 0 +#define XQSPIPSU_CONNECTION_MODE_STACKED 1 +#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2 + +/* Add more flags as required */ +#define XQSPIPSU_MSG_FLAG_STRIPE 0x1 + +#define XQspiPsu_Select(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK) + +#define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK) + +#define XQspiPsu_Disable(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0) + +#define XQspiPsu_IsManualStart(InstancePtr) ((XQspiPsu_GetOptions(InstancePtr) & XQSPIPSU_MANUAL_START_OPTION) ? TRUE : FALSE) + +/************************** Function Prototypes ******************************/ + +/* Initialization and reset */ +XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId); +int XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr, + u32 EffectiveAddr); +void XQspiPsu_Reset(XQspiPsu *InstancePtr); +void XQspiPsu_Abort(XQspiPsu *InstancePtr); + +/* Transfer functions and handlers */ +int XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + unsigned NumMsg); +int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + unsigned NumMsg); +int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr); +void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef, + XQspiPsu_StatusHandler FuncPtr); + +/* Configuration functions */ +int XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler); +void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus); +int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options); +int XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options); +u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr); +int XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode); + +#ifdef __cplusplus +} +#endif + + +#endif /* _XQSPIPSU_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xqspipsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xqspipsu_hw.h new file mode 100644 index 000000000..bd189ba7a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xqspipsu_hw.h @@ -0,0 +1,837 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspipsu_hw.h +* +* This file contains low level access funcitons using the base address +* directly without an instance. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   hk  08/21/14 First release
+*       hk  03/18/15 Add DMA status register masks required.
+*
+*
+* +******************************************************************************/ +#ifndef _XQSPIPSU_HW_H_ /* prevent circular inclusions */ +#define _XQSPIPSU_HW_H_ /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** + * QSPI Base Address + */ +#define XQSPIPS_BASEADDR 0XFF0F0000 + +/** + * GQSPI Base Address + */ +#define XQSPIPSU_BASEADDR 0xFF0F0100 +#define XQSPIPSU_OFFSET 0x100 + +/** + * Register: XQSPIPS_EN_REG + */ +#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014 ) + +#define XQSPIPS_EN_SHIFT 0 +#define XQSPIPS_EN_WIDTH 1 +#define XQSPIPS_EN_MASK 0X00000001 + +/** + * Register: XQSPIPSU_CFG + */ +#define XQSPIPSU_CFG_OFFSET 0X00000000 + +#define XQSPIPSU_CFG_MODE_EN_SHIFT 30 +#define XQSPIPSU_CFG_MODE_EN_WIDTH 2 +#define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000 +#define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000 + +#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29 +#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1 +#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000 + +#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28 +#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1 +#define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000 + +#define XQSPIPSU_CFG_ENDIAN_SHIFT 26 +#define XQSPIPSU_CFG_ENDIAN_WIDTH 1 +#define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000 + +#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20 +#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1 +#define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000 + +#define XQSPIPSU_CFG_WP_HOLD_SHIFT 19 +#define XQSPIPSU_CFG_WP_HOLD_WIDTH 1 +#define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000 + +#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3 +#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3 +#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038 + +#define XQSPIPSU_CFG_CLK_PHA_SHIFT 2 +#define XQSPIPSU_CFG_CLK_PHA_WIDTH 1 +#define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004 + +#define XQSPIPSU_CFG_CLK_POL_SHIFT 1 +#define XQSPIPSU_CFG_CLK_POL_WIDTH 1 +#define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002 + +/** + * Register: XQSPIPSU_ISR + */ +#define XQSPIPSU_ISR_OFFSET 0X00000004 + +#define XQSPIPSU_ISR_RXEMPTY_SHIFT 11 +#define XQSPIPSU_ISR_RXEMPTY_WIDTH 1 +#define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800 + +#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10 +#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1 +#define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400 + +#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9 +#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1 +#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200 + +#define XQSPIPSU_ISR_TXEMPTY_SHIFT 8 +#define XQSPIPSU_ISR_TXEMPTY_WIDTH 1 +#define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100 + +#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7 +#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1 +#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080 + +#define XQSPIPSU_ISR_RXFULL_SHIFT 5 +#define XQSPIPSU_ISR_RXFULL_WIDTH 1 +#define XQSPIPSU_ISR_RXFULL_MASK 0X00000020 + +#define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4 +#define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1 +#define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010 + +#define XQSPIPSU_ISR_TXFULL_SHIFT 3 +#define XQSPIPSU_ISR_TXFULL_WIDTH 1 +#define XQSPIPSU_ISR_TXFULL_MASK 0X00000008 + +#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2 +#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1 +#define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004 + +#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1 +#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1 +#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002 + +#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002 + +/** + * Register: XQSPIPSU_IER + */ +#define XQSPIPSU_IER_OFFSET 0X00000008 + +#define XQSPIPSU_IER_RXEMPTY_SHIFT 11 +#define XQSPIPSU_IER_RXEMPTY_WIDTH 1 +#define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800 + +#define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10 +#define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1 +#define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400 + +#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9 +#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1 +#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200 + +#define XQSPIPSU_IER_TXEMPTY_SHIFT 8 +#define XQSPIPSU_IER_TXEMPTY_WIDTH 1 +#define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100 + +#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7 +#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1 +#define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080 + +#define XQSPIPSU_IER_RXFULL_SHIFT 5 +#define XQSPIPSU_IER_RXFULL_WIDTH 1 +#define XQSPIPSU_IER_RXFULL_MASK 0X00000020 + +#define XQSPIPSU_IER_RXNEMPTY_SHIFT 4 +#define XQSPIPSU_IER_RXNEMPTY_WIDTH 1 +#define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010 + +#define XQSPIPSU_IER_TXFULL_SHIFT 3 +#define XQSPIPSU_IER_TXFULL_WIDTH 1 +#define XQSPIPSU_IER_TXFULL_MASK 0X00000008 + +#define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2 +#define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1 +#define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004 + +#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1 +#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1 +#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002 + +/** + * Register: XQSPIPSU_IDR + */ +#define XQSPIPSU_IDR_OFFSET 0X0000000C + +#define XQSPIPSU_IDR_RXEMPTY_SHIFT 11 +#define XQSPIPSU_IDR_RXEMPTY_WIDTH 1 +#define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800 + +#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10 +#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1 +#define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400 + +#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9 +#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1 +#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200 + +#define XQSPIPSU_IDR_TXEMPTY_SHIFT 8 +#define XQSPIPSU_IDR_TXEMPTY_WIDTH 1 +#define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100 + +#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7 +#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1 +#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080 + +#define XQSPIPSU_IDR_RXFULL_SHIFT 5 +#define XQSPIPSU_IDR_RXFULL_WIDTH 1 +#define XQSPIPSU_IDR_RXFULL_MASK 0X00000020 + +#define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4 +#define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1 +#define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010 + +#define XQSPIPSU_IDR_TXFULL_SHIFT 3 +#define XQSPIPSU_IDR_TXFULL_WIDTH 1 +#define XQSPIPSU_IDR_TXFULL_MASK 0X00000008 + +#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2 +#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1 +#define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004 + +#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1 +#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1 +#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002 + +#define XQSPIPSU_IDR_ALL_MASK 0X0FBE + +/** + * Register: XQSPIPSU_IMR + */ +#define XQSPIPSU_IMR_OFFSET 0X00000010 + +#define XQSPIPSU_IMR_RXEMPTY_SHIFT 11 +#define XQSPIPSU_IMR_RXEMPTY_WIDTH 1 +#define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800 + +#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10 +#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1 +#define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400 + +#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9 +#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1 +#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200 + +#define XQSPIPSU_IMR_TXEMPTY_SHIFT 8 +#define XQSPIPSU_IMR_TXEMPTY_WIDTH 1 +#define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100 + +#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7 +#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1 +#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080 + +#define XQSPIPSU_IMR_RXFULL_SHIFT 5 +#define XQSPIPSU_IMR_RXFULL_WIDTH 1 +#define XQSPIPSU_IMR_RXFULL_MASK 0X00000020 + +#define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4 +#define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1 +#define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010 + +#define XQSPIPSU_IMR_TXFULL_SHIFT 3 +#define XQSPIPSU_IMR_TXFULL_WIDTH 1 +#define XQSPIPSU_IMR_TXFULL_MASK 0X00000008 + +#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2 +#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1 +#define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004 + +#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1 +#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1 +#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002 + +/** + * Register: XQSPIPSU_EN_REG + */ +#define XQSPIPSU_EN_OFFSET 0X00000014 + +#define XQSPIPSU_EN_SHIFT 0 +#define XQSPIPSU_EN_WIDTH 1 +#define XQSPIPSU_EN_MASK 0X00000001 + +/** + * Register: XQSPIPSU_TXD + */ +#define XQSPIPSU_TXD_OFFSET 0X0000001C + +#define XQSPIPSU_TXD_SHIFT 0 +#define XQSPIPSU_TXD_WIDTH 32 +#define XQSPIPSU_TXD_MASK 0XFFFFFFFF + +#define XQSPIPSU_TXD_DEPTH 32 + +/** + * Register: XQSPIPSU_RXD + */ +#define XQSPIPSU_RXD_OFFSET 0X00000020 + +#define XQSPIPSU_RXD_SHIFT 0 +#define XQSPIPSU_RXD_WIDTH 32 +#define XQSPIPSU_RXD_MASK 0XFFFFFFFF + +/** + * Register: XQSPIPSU_TX_THRESHOLD + */ +#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028 + +#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0 +#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6 +#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003F +#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01 + +/** + * Register: XQSPIPSU_RX_THRESHOLD + */ +#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002C + +#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0 +#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6 +#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003F +#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01 + +#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32 + +/** + * Register: XQSPIPSU_GPIO + */ +#define XQSPIPSU_GPIO_OFFSET 0X00000030 + +#define XQSPIPSU_GPIO_WP_N_SHIFT 0 +#define XQSPIPSU_GPIO_WP_N_WIDTH 1 +#define XQSPIPSU_GPIO_WP_N_MASK 0X00000001 + +/** + * Register: XQSPIPSU_LPBK_DLY_ADJ + */ +#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038 + +#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5 +#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1 +#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020 + +#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3 +#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2 +#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018 + +#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0 +#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3 +#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007 + +/** + * Register: XQSPIPSU_GEN_FIFO + */ +#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040 + +#define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0 +#define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20 +#define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFF + +/** + * Register: XQSPIPSU_SEL + */ +#define XQSPIPSU_SEL_OFFSET 0X00000044 + +#define XQSPIPSU_SEL_SHIFT 0 +#define XQSPIPSU_SEL_WIDTH 1 +#define XQSPIPSU_SEL_MASK 0X00000001 + +/** + * Register: XQSPIPSU_FIFO_CTRL + */ +#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004C + +#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2 +#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1 +#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004 + +#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1 +#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1 +#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002 + +#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0 +#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1 +#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001 + +/** + * Register: XQSPIPSU_GF_THRESHOLD + */ +#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050 + +#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0 +#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5 +#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001F +#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10 + +/** + * Register: XQSPIPSU_POLL_CFG + */ +#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054 + +#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31 +#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1 +#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000 + +#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30 +#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1 +#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000 + +#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8 +#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8 +#define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00 + +#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0 +#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8 +#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FF + +/** + * Register: XQSPIPSU_P_TIMEOUT + */ +#define XQSPIPSU_P_TO_OFFSET 0X00000058 + +#define XQSPIPSU_P_TO_VALUE_SHIFT 0 +#define XQSPIPSU_P_TO_VALUE_WIDTH 32 +#define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFF + +/** + * Register: XQSPIPSU_XFER_STS + */ +#define XQSPIPSU_XFER_STS_OFFSET 0X0000005C + +#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0 +#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32 +#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFF + +/** + * Register: XQSPIPSU_GF_SNAPSHOT + */ +#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060 + +#define XQSPIPSU_GF_SNAPSHOT_SHIFT 0 +#define XQSPIPSU_GF_SNAPSHOT_WIDTH 20 +#define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFF + +/** + * Register: XQSPIPSU_RX_COPY + */ +#define XQSPIPSU_RX_COPY_OFFSET 0X00000064 + +#define XQSPIPSU_RX_COPY_UPPER_SHIFT 8 +#define XQSPIPSU_RX_COPY_UPPER_WIDTH 8 +#define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00 + +#define XQSPIPSU_RX_COPY_LOWER_SHIFT 0 +#define XQSPIPSU_RX_COPY_LOWER_WIDTH 8 +#define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FF + +/** + * Register: XQSPIPSU_MOD_ID + */ +#define XQSPIPSU_MOD_ID_OFFSET 0X000000FC + +#define XQSPIPSU_MOD_ID_SHIFT 0 +#define XQSPIPSU_MOD_ID_WIDTH 32 +#define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFF + +/** + * Register: XQSPIPSU_QSPIDMA_DST_ADDR + */ +#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700 + +#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2 +#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30 +#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFC + +/** + * Register: XQSPIPSU_QSPIDMA_DST_SIZE + */ +#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704 + +#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2 +#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27 +#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFC + +/** + * Register: XQSPIPSU_QSPIDMA_DST_STS + */ +#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708 + +#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13 +#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3 +#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000 + +#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5 +#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8 +#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0 + +#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1 +#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4 +#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001E + +#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0 +#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001 + +#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000 + +/** + * Register: XQSPIPSU_QSPIDMA_DST_CTRL + */ +#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070C + +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25 +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7 +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000 + +#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24 +#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000 + +#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23 +#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000 + +#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22 +#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000 + +#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10 +#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12 +#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00 + +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2 +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8 +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FC + +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1 +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002 + +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0 +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001 + +#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00 + +/** + * Register: XQSPIPSU_QSPIDMA_DST_I_STS + */ +#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714 + +#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7 +#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080 + +#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6 +#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040 + +#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5 +#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020 + +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4 +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010 + +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3 +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008 + +#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2 +#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004 + +#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1 +#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002 + +#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FC +#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FE + +/** + * Register: XQSPIPSU_QSPIDMA_DST_I_EN + */ +#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718 + +#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7 +#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080 + +#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6 +#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040 + +#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5 +#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020 + +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4 +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010 + +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3 +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008 + +#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2 +#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004 + +#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1 +#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002 + +/** + * Register: XQSPIPSU_QSPIDMA_DST_I_DIS + */ +#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071C + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080 + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040 + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020 + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010 + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008 + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004 + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002 + +/** + * Register: XQSPIPSU_QSPIDMA_DST_IMR + */ +#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720 + +#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7 +#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080 + +#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6 +#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040 + +#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5 +#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020 + +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4 +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010 + +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3 +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008 + +#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2 +#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004 + +#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1 +#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002 + +/** + * Register: XQSPIPSU_QSPIDMA_DST_CTRL2 + */ +#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724 + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000 + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000 + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000 + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000 + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000 + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0 + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4 +#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000F + +/** + * Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB + */ +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728 + +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0 +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12 +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFF + +/** + * Register: XQSPIPSU_QSPIDMA_FUTURE_ECO + */ +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFC + +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0 +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32 +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFF + +/* + * Generic FIFO masks + */ +#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFF +#define XQSPIPSU_GENFIFO_DATA_XFER 0x100 +#define XQSPIPSU_GENFIFO_EXP 0x200 +#define XQSPIPSU_GENFIFO_MODE_SPI 0x400 +#define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800 +#define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00 +#define XQSPIPSU_GENFIFO_MODE_MASK 0xC00 /* And with ~MASK first */ +#define XQSPIPSU_GENFIFO_CS_LOWER 0x1000 +#define XQSPIPSU_GENFIFO_CS_UPPER 0x2000 +#define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000 +#define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000 +#define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000 /* inverse is no bus */ +#define XQSPIPSU_GENFIFO_BUS_MASK 0xC000 /* And with ~MASK first */ +#define XQSPIPSU_GENFIFO_TX 0x10000 /* inverse is zero pump */ +#define XQSPIPSU_GENFIFO_RX 0x20000 /* inverse is RX discard */ +#define XQSPIPSU_GENFIFO_STRIPE 0x40000 +#define XQSPIPSU_GENFIFO_POLL 0x80000 + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XQspiPsu_In32 Xil_In32 +#define XQspiPsu_Out32 Xil_Out32 + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XQspiPsu_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPsu_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + + +#ifdef __cplusplus +} +#endif + + +#endif /* _XQSPIPSU_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xreg_cortexa53.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xreg_cortexa53.h new file mode 100644 index 000000000..dbc0134e6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xreg_cortexa53.h @@ -0,0 +1,182 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xreg_cortexa53.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* +******************************************************************************/ +#ifndef XREG_CORTEXA53_H +#define XREG_CORTEXA53_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/* GPRs */ +#define XREG_GPR0 x0 +#define XREG_GPR1 x1 +#define XREG_GPR2 x2 +#define XREG_GPR3 x3 +#define XREG_GPR4 x4 +#define XREG_GPR5 x5 +#define XREG_GPR6 x6 +#define XREG_GPR7 x7 +#define XREG_GPR8 x8 +#define XREG_GPR9 x9 +#define XREG_GPR10 x10 +#define XREG_GPR11 x11 +#define XREG_GPR12 x12 +#define XREG_GPR13 x13 +#define XREG_GPR14 x14 +#define XREG_GPR15 x15 +#define XREG_GPR16 x16 +#define XREG_GPR17 x17 +#define XREG_GPR18 x18 +#define XREG_GPR19 x19 +#define XREG_GPR20 x20 +#define XREG_GPR21 x21 +#define XREG_GPR22 x22 +#define XREG_GPR23 x23 +#define XREG_GPR24 x24 +#define XREG_GPR25 x25 +#define XREG_GPR26 x26 +#define XREG_GPR27 x27 +#define XREG_GPR28 x28 +#define XREG_GPR29 x29 +#define XREG_GPR30 x30 +#define XREG_CPSR cpsr + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_EL3h_MODE 0xD +#define XREG_CPSR_EL3t_MODE 0xC +#define XREG_CPSR_EL2h_MODE 0x9 +#define XREG_CPSR_EL2t_MODE 0x8 +#define XREG_CPSR_EL1h_MODE 0x5 +#define XREG_CPSR_EL1t_MODE 0x4 +#define XREG_CPSR_EL0t_MODE 0x0 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U<<23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (0X00000012U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) + + +#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U) +#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA53_H */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xscugic.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xscugic.h new file mode 100644 index 000000000..86adf7b18 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xscugic.h @@ -0,0 +1,315 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xscugic.h +* +* The generic interrupt controller driver component. +* +* The interrupt controller driver uses the idea of priority for the various +* handlers. Priority is an integer within the range of 1 and 31 inclusive with +* default of 1 being the highest priority interrupt source. The priorities +* of the various sources can be dynamically altered as needed through +* hardware configuration. +* +* The generic interrupt controller supports the following +* features: +* +* - specific individual interrupt enabling/disabling +* - specific individual interrupt acknowledging +* - attaching specific callback function to handle interrupt source +* - assigning desired priority to interrupt source if default is not +* acceptable. +* +* Details about connecting the interrupt handler of the driver are contained +* in the source file specific to interrupt processing, xscugic_intr.c. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads +* or thread mutual exclusion, virtual memory, or cache control must be +* satisfied by the layer above this driver. +* +* Interrupt Vector Tables +* +* The device ID of the interrupt controller device is used by the driver as a +* direct index into the configuration data table. The user should populate the +* vector table with handlers and callbacks at run-time using the +* XScuGic_Connect() and XScuGic_Disconnect() functions. +* +* Each vector table entry corresponds to a device that can generate an +* interrupt. Each entry contains an interrupt handler function and an +* argument to be passed to the handler when an interrupt occurs. The +* user must use XScuGic_Connect() when the interrupt handler takes an +* argument other than the base address. +* +* Nested Interrupts Processing +* +* Nested interrupts are not supported by this driver. +* +* NOTE: +* The generic interrupt controller is not a part of the snoop control unit +* as indicated by the prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+* +******************************************************************************/ + +#ifndef XSCUGIC_H /* prevent circular inclusions */ +#define XSCUGIC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_io.h" +#include "xscugic_hw.h" +#include "xil_exception.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/* The following data type defines each entry in an interrupt vector table. + * The callback reference is the base address of the interrupting device + * for the low level driver and an instance pointer for the high level driver. + */ +typedef struct +{ + Xil_InterruptHandler Handler; + void *CallBackRef; +} XScuGic_VectorTableEntry; + +/** + * This typedef contains configuration information for the device. + */ +typedef struct +{ + u16 DeviceId; /**< Unique ID of device */ + u32 CpuBaseAddress; /**< CPU Interface Register base address */ + u32 DistBaseAddress; /**< Distributor Register base address */ + XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**< + Vector table of interrupt handlers */ +} XScuGic_Config; + +/** + * The XScuGic driver instance data. The user is required to allocate a + * variable of this type for every intc device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct +{ + XScuGic_Config *Config; /**< Configuration table entry */ + u32 IsReady; /**< Device is initialized and ready */ + u32 UnhandledInterrupts; /**< Intc Statistics */ +} XScuGic; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Write the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \ + ((u32)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \ + (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \ + ((u32)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_DistReadReg(InstancePtr, RegOffset) \ +(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset))) + +/************************** Function Prototypes ******************************/ + +/* + * Required functions in xscugic.c + */ + +s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, + Xil_InterruptHandler Handler, void *CallBackRef); +void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id); + +void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id); +void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id); + +s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, + u32 EffectiveAddr); + +s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id); + +void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 *Priority, u8 *Trigger); +void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 Priority, u8 Trigger); + +/* + * Initialization functions in xscugic_sinit.c + */ +XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId); + +/* + * Interrupt functions in xscugic_intr.c + */ +void XScuGic_InterruptHandler(XScuGic *InstancePtr); + +/* + * Self-test functions in xscugic_selftest.c + */ +s32 XScuGic_SelfTest(XScuGic *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xscugic_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xscugic_hw.h new file mode 100644 index 000000000..580ce6ba9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xscugic_hw.h @@ -0,0 +1,637 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xscugic_hw.h +* +* This header file contains identifiers and HW access functions (or +* macros) that can be used to access the device. The user should refer to the +* hardware device specification for more details of the device operation. +* The driver functions/APIs are defined in xscugic.h. +* +* This GIC device has two parts, a distributor and CPU interface(s). Each part +* has separate register definition sections. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +#ifndef XSCUGIC_HW_H /* prevent circular inclusions */ +#define XSCUGIC_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xil_exception.h" + +/************************** Constant Definitions *****************************/ + +/* + * The maximum number of interrupts supported by the hardware. + */ +#ifdef __ARM_NEON__ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */ +#else +#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */ +#endif + +/* + * The maximum priority value that can be used in the GIC. + */ +#define XSCUGIC_MAX_INTR_PRIO_VAL 248U +#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U + +/** @name Distributor Interface Register Map + * + * Define the offsets from the base address for all Distributor registers of + * the interrupt controller, some registers may be reserved in the hardware + * device. + * @{ + */ +#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable + Register */ +#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller + Type Register */ +#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID + Register */ +#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security + Register */ +#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set + Register */ +#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */ +#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set + Register */ +#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear + Register */ +#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */ +#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */ +#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target + Register 0x800-0x8FB */ +#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration + Register 0xC00-0xCFC */ +#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */ +#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register + 0xd04-0xd7C */ +#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration + Register */ +#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered + Interrupt Register */ +#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */ +#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */ +/* @} */ + +/** @name Distributor Enable Register + * Controls if the distributor response to external interrupt inputs. + * @{ + */ +#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */ +/* @} */ + +/** @name Interrupt Controller Type Register + * @{ + */ +#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable + Shared Peripheral + Interrupts*/ +#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/ +#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */ +#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */ +/* @} */ + +/** @name Implementor ID Register + * Implementor and revision information. + * @{ + */ +#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */ +#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */ +/* @} */ + +/** @name Interrupt Security Registers + * Each bit controls the security level of an interrupt, either secure or non + * secure. These registers can only be accessed using secure read and write. + * There are registers for each of the CPU interfaces at offset 0x080. A + * register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x084. + * @{ + */ +#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Set Register + * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a + * bit to 0. + * There are registers for each of the CPU interfaces at offset 0x100. With up + * to 8 registers aliased to the same address. A register set for the SPI + * interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x104. + * @{ + */ +#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Clear Register + * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and + * sets the corresponding bit to 0. + * There are registers for each of the CPU interfaces at offset 0x180. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x184. + * @{ + */ +#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Set Register + * Each bit controls the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets + * an interrupt to the pending state. + * There are registers for each of the CPU interfaces at offset 0x200. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x204. + * @{ + */ +#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Clear Register + * Each bit can clear the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 + * clears the pending state of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x280. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x284. + * @{ + */ +#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Active Status Register + * Each bit provides the Active status of an interrupt, a + * 0 is not Active, a 1 is Active. This is a read only register. + * There are registers for each of the CPU interfaces at offset 0x300. With up + * to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x380. + * @{ + */ +#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Priority Level Register + * Each byte in a Priority Level Register sets the priority level of an + * interrupt. Reading the register provides the priority level of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x400 through + * 0x41C. With up to 8 registers aliased to each address. + * 0 is highest priority, 0xFF is lowest. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x420. + * @{ + */ +#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an + INT_ID */ +#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority + actually the lowest priority*/ +/* @} */ + +/** @name SPI Target Register 0x800-0x8FB + * Each byte references a separate SPI and programs which of the up to 8 CPU + * interfaces are sent a Pending interrupt. + * There are registers for each of the CPU interfaces at offset 0x800 through + * 0x81C. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x820. + * + * This driver does not support multiple CPU interfaces. These are included + * for complete documentation. + * @{ + */ +#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/ +#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/ +#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/ +#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/ +#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/ +#define XSCUGIC_SPI_CPU2_MASK 0x00000003U /**< CPU 2 Mask*/ +#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/ +#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/ +/* @} */ + +/** @name Interrupt Configuration Register 0xC00-0xCFC + * The interrupt configuration registers program an SFI to be active HIGH level + * sensitive or rising edge sensitive. + * Each bit pair describes the configuration for an INT_ID. + * SFI Read Only b10 always + * PPI Read Only depending on how the PPIs are configured. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive + * SPI LSB is read only. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive/ + * There are registers for each of the CPU interfaces at offset 0xC00 through + * 0xC04. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0xC08. + * @{ + */ +#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */ +/* @} */ + +/** @name PPI Status Register + * Enables an external AMBA master to access the status of the PPI inputs. + * A CPU can only read the status of its local PPI signals and cannot read the + * status for other CPUs. + * This register is aliased for each CPU interface. + * @{ + */ +#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */ +#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */ +#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */ +#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */ +#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */ +#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */ +#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */ +#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */ +#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */ +#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */ +#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */ +#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */ +#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */ +#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */ +#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */ +#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */ +/* @} */ + +/** @name SPI Status Register 0xd04-0xd7C + * Enables an external AMBA master to access the status of the SPI inputs. + * There are up to 63 registers if the maximum number of SPI inputs are + * configured. + * @{ + */ +#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI + input */ +/* @} */ + +/** @name AHB Configuration Register + * Provides the status of the CFGBIGEND input signal and allows the endianess + * of the GIC to be set. + * @{ + */ +#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian, + 1-GIC uses Big Endian */ +#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control, + 1-use the AHB_END bit */ +#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */ + +/* @} */ + +/** @name Software Triggered Interrupt Register + * Controls issueing of software interrupts. + * @{ + */ +#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U +#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter + b00-Use the target List + b01-All CPUs except requester + b10-To Requester + b11-reserved */ +#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */ +#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */ +#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID + signaled to the CPU*/ +/* @} */ + +/** @name CPU Interface Register Map + * + * Define the offsets from the base address for all CPU registers of the + * interrupt controller, some registers may be reserved in the hardware device. + * @{ + */ +#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control + Register */ +#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */ +#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */ +#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */ +#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */ +#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */ +#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt + Register */ +#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure + Binary Point Register */ + +/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written + * to. */ +/* @} */ + + +/** @name Control Register + * CPU Interface Control register definitions + * All bits are defined here although some are not available in the non-secure + * mode. + * @{ + */ +#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer, + 0=separate registers, + 1=both use bin_pt_s */ +#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure + interrupts, + 0= use IRQ for both, + 1=Use FIQ for secure, IRQ for non*/ +#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */ +#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */ +#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */ +/* @} */ + +/** @name Priority Mask Register + * Priority Mask register definitions + * The CPU interface does not send interrupt if the level of the interrupt is + * lower than the level of the register. + * @{ + */ +/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */ +/* @} */ + +/** @name Binary Point Register + * Binary Point register definitions + * @{ + */ + +#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value + Value Secure Non-secure + b000 0xFE 0xFF + b001 0xFC 0xFE + b010 0xF8 0xFC + b011 0xF0 0xF8 + b100 0xE0 0xF0 + b101 0xC0 0xE0 + b110 0x80 0xC0 + b111 0x00 0x80 + */ +/*@}*/ + +/** @name Interrupt Acknowledge Register + * Interrupt Acknowledge register definitions + * Identifies the current Pending interrupt, and the CPU ID for software + * interrupts. + */ +#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */ +#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */ +/* @} */ + +/** @name End of Interrupt Register + * End of Interrupt register definitions + * Allows the CPU to signal the GIC when it completes an interrupt service + * routine. + */ +#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */ + +/* @} */ + +/** @name Running Priority Register + * Running Priority register definitions + * Identifies the interrupt priority level of the highest priority active + * interrupt. + */ +#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */ +/* @} */ + +/* + * Highest Pending Interrupt register definitions + * Identifies the interrupt priority of the highest priority pending interupt + */ +#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */ +/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */ +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the Interrupt Configuration Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Priority Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the SPI Target Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Clear-Enable Register offset for an interrupt ID +* +* @param Register is the register offset for the clear/enable bank. +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \ + ((Register) + (((InterruptID)/32U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + + +/****************************************************************************/ +/** +* +* Write the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data)))) + + +/****************************************************************************/ +/** +* +* Enable specific interrupt(s) in the interrupt controller. +* +* @param DistBaseAddress is the Distributor Register base address of the +* device +* @param Int_Id is the ID of the interrupt source and should be in the +* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* +* @return None. +* +* @note C-style signature: +* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id) +* +*****************************************************************************/ +#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \ + XScuGic_WriteReg((DistBaseAddress), \ + XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \ + (0x00000001U << ((Int_Id) % 32U))) + +/****************************************************************************/ +/** +* +* Disable specific interrupt(s) in the interrupt controller. +* +* @param DistBaseAddress is the Distributor Register base address of the +* device +* @param Int_Id is the ID of the interrupt source and should be in the +* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* +* +* @return None. +* +* @note C-style signature: +* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id) +* +*****************************************************************************/ +#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \ + XScuGic_WriteReg((DistBaseAddress), \ + XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \ + (0x00000001U << ((Int_Id) % 32U))) + + +/************************** Function Prototypes ******************************/ + +void XScuGic_DeviceInterruptHandler(void *DeviceId); +s32 XScuGic_DeviceInitialize(u32 DeviceId); +void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID, + Xil_InterruptHandler Handler, void *CallBackRef); +void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 Priority, u8 Trigger); +void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 *Priority, u8 *Trigger); +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xsdps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xsdps.h new file mode 100644 index 000000000..64532a0d3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xsdps.h @@ -0,0 +1,208 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsdps.h +* +* This file contains the implementation of XSdPs driver. +* This driver is used initialize read from and write to the SD card. +* Features such as switching bus width to 4-bit and switching to high speed, +* changing clock frequency, block size etc. are supported. +* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however +* is done using 1-bit bus width and 400KHz clock frequency. +* SD commands are classified as broadcast and addressed. Commands can be +* those with response only (using only command line) or +* response + data (using command and data lines). +* Only one command can be sent at a time. During a data transfer however, +* when dsta lines are in use, certain commands (which use only the command +* line) can be sent, most often to obtain status. +* This driver does not support multi card slots at present. +* +* Intialization: +* This includes initialization on the host controller side to select +* clock frequency, bus power and default transfer related parameters. +* The default voltage is 3.3V. +* On the SD card side, the initialization and identification state diagram is +* implemented. This resets the card, gives it a unique address/ID and +* identifies key card related specifications. +* +* Data transfer: +* The SD card is put in tranfer state to read from or write to it. +* The default block size is 512 bytes and if supported, +* default bus width is 4-bit and bus speed is High speed. +* The read and write functions are implemented in polled mode using ADMA2. +* +* At any point, when key parameters such as block size or +* clock/speed or bus width are modified, this driver takes care of +* maintaining the same selection on host and card. +* All error bits in host controller are monitored by the driver and in the +* event one of them is set, driver will clear the interrupt status and +* communicate failure to the upper layer. +* +* File system use: +* This driver can be used with xilffs library to read and write files to SD. +* (Please refer to procedure in diskio.c). The file system read/write example +* in polled mode can used for reference. +* +* There is no example for using SD driver without file system at present. +* However, the driver can be used without the file system. The glue layer +* in filesytem can be used as reference for the same. The block count +* passed to the read/write function in one call is limited by the ADMA2 +* descriptor table and hence care will have to be taken to call read/write +* API's in a loop for large file sizes. +* +* Interrupt mode is not supported because it offers no improvement when used +* with file system. +* +* eMMC support: +* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. +* The features of eMMC supported by the driver will depend on those supported +* by the host controller. The current driver supports read/write on eMMC card +* using 4-bit and high speed mode currently. +* +* Features not supported include - card write protect, password setting, +* lock/unlock, interrupts, SDMA mode, programmed I/O mode and +* 64-bit addressed ADMA2, erase/pre-erase commands. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+*
+*
+* +******************************************************************************/ + + +#ifndef SDPS_H_ +#define SDPS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xstatus.h" +#include "xsdps_hw.h" +#include + +/************************** Constant Definitions *****************************/ + +#define XSDPS_CLK_400_KHZ 400000 /**< 400 KHZ */ +#define XSDPS_CLK_50_MHZ 50000000 /**< 50 MHZ */ +#define CT_MMC 0x1 /**< MMC Card */ +#define CT_SD1 0x2 /**< SD ver 1 */ +#define CT_SD2 0x3 /**< SD ver 2 */ +/**************************** Type Definitions *******************************/ +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u32 CardDetect; /**< Card Detect */ + u32 WriteProtect; /**< Write Protect */ +} XSdPs_Config; + +/* + * ADMA2 descriptor table + */ +typedef struct { + u16 Attribute; /**< Attributes of descriptor */ + u16 Length; /**< Length of current dma transfer */ + u32 Address; /**< Address of current dma transfer */ +} XSdPs_Adma2Descriptor; + +/** + * The XSdPs driver instance data. The user is required to allocate a + * variable of this type for every SD device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XSdPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + u32 Host_Caps; /**< Capabilities of host controller */ + u32 HCS; /**< High capacity support in card */ + u32 CardID[4]; /**< Card ID */ + u32 RelCardAddr; /**< Relative Card Address */ + u32 CardType; /**< Card Type(version) */ + /**< ADMA Descriptors */ +#ifdef __ICCARM__ +#pragma data_alignment = 32 + XSdPs_Adma2Descriptor Adma2_DescrTbl[32]; +#pragma data_alignment = 4 +#else + XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32))); +#endif +} XSdPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId); +int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, + u32 EffectiveAddr); +int XSdPs_SdCardInitialize(XSdPs *InstancePtr); +int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); +int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); +int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize); +int XSdPs_Select_Card (XSdPs *InstancePtr); +int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq); +int XSdPs_Change_BusWidth(XSdPs *InstancePtr); +int XSdPs_Change_BusSpeed(XSdPs *InstancePtr); +int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR); +int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff); +int XSdPs_Pullup(XSdPs *InstancePtr); +int XSdPs_MmcCardInitialize(XSdPs *InstancePtr); +int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); + +#ifdef __cplusplus +} +#endif + +#endif /* SD_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xsdps_hw.h new file mode 100644 index 000000000..a9670d0fc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xsdps_hw.h @@ -0,0 +1,605 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsdps_hw.h +* +* This header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xsdps.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*
+*
+* +******************************************************************************/ + +#ifndef SD_HW_H_ +#define SD_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an SD device. + * @{ + */ + +#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00 /**< SDMA System Address + Register */ +#define XSDPS_BLK_SIZE_OFFSET 0x04 /**< Block Size Register */ +#define XSDPS_BLK_CNT_OFFSET 0x06 /**< Block Count Register */ +#define XSDPS_ARGMT_OFFSET 0x08 /**< Argument Register */ +#define XSDPS_XFER_MODE_OFFSET 0x0C /**< Transfer Mode Register */ +#define XSDPS_CMD_OFFSET 0x0E /**< Command Register */ +#define XSDPS_RESP0_OFFSET 0x10 /**< Response0 Register */ +#define XSDPS_RESP1_OFFSET 0x14 /**< Response1 Register */ +#define XSDPS_RESP2_OFFSET 0x18 /**< Response2 Register */ +#define XSDPS_RESP3_OFFSET 0x1C /**< Response3 Register */ +#define XSDPS_BUF_DAT_PORT_OFFSET 0x20 /**< Buffer Data Port */ +#define XSDPS_PRES_STATE_OFFSET 0x24 /**< Present State */ +#define XSDPS_HOST_CTRL1_OFFSET 0x28 /**< Host Control 1 */ +#define XSDPS_POWER_CTRL_OFFSET 0x29 /**< Power Control */ +#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2A /**< Block Gap Control */ +#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2B /**< Wake Up Control */ +#define XSDPS_CLK_CTRL_OFFSET 0x2C /**< Clock Control */ +#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2E /**< Timeout Control */ +#define XSDPS_SW_RST_OFFSET 0x2F /**< Software Reset */ +#define XSDPS_NORM_INTR_STS_OFFSET 0x30 /**< Normal Interrupt + Status Register */ +#define XSDPS_ERR_INTR_STS_OFFSET 0x32 /**< Error Interrupt + Status Register */ +#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34 /**< Normal Interrupt + Status Enable Register */ +#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36 /**< Error Interrupt + Status Enable Register */ +#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38 /**< Normal Interrupt + Signal Enable Register */ +#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3A /**< Error Interrupt + Signal Enable Register */ + +#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3C /**< Auto CMD12 Error Status + Register */ +#define XSDPS_HOST_CTRL2_OFFSET 0x3E /**< Host Control2 Register */ +#define XSDPS_CAPS_OFFSET 0x40 /**< Capabilities Register */ +#define XSDPS_CAPS_EXT_OFFSET 0x44 /**< Capabilities Extended */ +#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48 /**< Maximum Current + Capabilities Register */ +#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4C /**< Maximum Current + Capabilities Ext Register */ +#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52 /**< Force Event for + Error Interrupt Status */ +#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50 /**< Auto CM12 Error Interrupt + Status Register */ +#define XSDPS_ADMA_ERR_STS_OFFSET 0x54 /**< ADMA Error Status + Register */ +#define XSDPS_ADMA_SAR_OFFSET 0x58 /**< ADMA System Address + Register */ +#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5C /**< ADMA System Address + Extended Register */ +#define XSDPS_PRE_VAL_1_OFFSET 0x60 /**< Preset Value Register */ +#define XSDPS_PRE_VAL_2_OFFSET 0x64 /**< Preset Value Register */ +#define XSDPS_PRE_VAL_3_OFFSET 0x68 /**< Preset Value Register */ +#define XSDPS_PRE_VAL_4_OFFSET 0x6C /**< Preset Value Register */ +#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0 /**< Shared Bus Control + Register */ +#define XSDPS_SLOT_INTR_STS_OFFSET 0xFC /**< Slot Interrupt Status + Register */ +#define XSDPS_HOST_CTRL_VER_OFFSET 0xFE /**< Host Controller Version + Register */ + +/* @} */ + +/** @name Control Register - Host control, Power control, + * Block Gap control and Wakeup control + * + * This register contains bits for various configuration options of + * the SD host controller. Read/Write apart from the reserved bits. + * @{ + */ + +#define XSDPS_HC_LED_MASK 0x00000001 /**< LED Control */ +#define XSDPS_HC_WIDTH_MASK 0x00000002 /**< Bus width */ +#define XSDPS_HC_SPEED_MASK 0x00000004 /**< High Speed */ +#define XSDPS_HC_DMA_MASK 0x00000018 /**< DMA Mode Select */ +#define XSDPS_HC_DMA_SDMA_MASK 0x00000000 /**< SDMA Mode */ +#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008 /**< ADMA1 Mode */ +#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010 /**< ADMA2 Mode - 32 bit */ +#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018 /**< ADMA2 Mode - 64 bit */ +#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020 /**< Bus width - 8 bit */ +#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040 /**< Card Detect Tst Lvl */ +#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080 /**< Card Detect Sig Det */ + +#define XSDPS_PC_BUS_PWR_MASK 0x00000001 /**< Bus Power Control */ +#define XSDPS_PC_BUS_VSEL_MASK 0x0000000E /**< Bus Voltage Select */ +#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000E /**< Bus Voltage 3.3V */ +#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000C /**< Bus Voltage 3.0V */ +#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000A /**< Bus Voltage 1.8V */ + +#define XSDPS_BGC_STP_REQ_MASK 0x00000001 /**< Block Gap Stop Req */ +#define XSDPS_BGC_CNT_REQ_MASK 0x00000002 /**< Block Gap Cont Req */ +#define XSDPS_BGC_RWC_MASK 0x00000004 /**< Block Gap Rd Wait */ +#define XSDPS_BGC_INTR_MASK 0x00000008 /**< Block Gap Intr */ +#define XSDPS_BGC_SPI_MODE_MASK 0x00000010 /**< Block Gap SPI Mode */ +#define XSDPS_BGC_BOOT_EN_MASK 0x00000020 /**< Block Gap Boot Enb */ +#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040 /**< Block Gap Alt BootEn */ +#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080 /**< Block Gap Boot Ack */ + +#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001 /**< Wakeup Card Intr */ +#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002 /**< Wakeup Card Insert */ +#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004 /**< Wakeup Card Removal */ + +/* @} */ + +/** @name Control Register - Clock control, Timeout control & Software reset + * + * This register contains bits for configuration options of clock, timeout and + * software reset. + * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits. + * @{ + */ + +#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001 +#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002 +#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004 +#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020 +#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0 +#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00 +#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000 +#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000 +#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000 +#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000 +#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800 +#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400 +#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200 +#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100 +#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000 + +#define XSDPS_TC_CNTR_VAL_MASK 0x0000000F + +#define XSDPS_SWRST_ALL_MASK 0x00000001 +#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002 +#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004 + +#define XSDPS_CC_MAX_NUM_OF_DIV 9 +#define XSDPS_CC_DIV_SHIFT 8 + +/* @} */ + +/** @name SD Interrupt Registers + * + * Normal and Error Interrupt Status Register + * This register shows the normal and error interrupt status. + * Status enable register affects reads of this register. + * If Signal enable register is set and the corresponding status bit is set, + * interrupt is generated. + * Write to clear except + * Error_interrupt and Card_Interrupt bits - Read only + * + * Normal and Error Interrupt Status Enable Register + * Setting this register bits enables Interrupt status. + * Read/Write except Fixed_to_0 bit (Read only) + * + * Normal and Error Interrupt Signal Enable Register + * This register is used to select which interrupt status is + * indicated to the Host System as the interrupt. + * Read/Write except Fixed_to_0 bit (Read only) + * + * All three registers have same bit definitions + * @{ + */ + +#define XSDPS_INTR_CC_MASK 0x00000001 /**< Command Complete */ +#define XSDPS_INTR_TC_MASK 0x00000002 /**< Transfer Complete */ +#define XSDPS_INTR_BGE_MASK 0x00000004 /**< Block Gap Event */ +#define XSDPS_INTR_DMA_MASK 0x00000008 /**< DMA Interrupt */ +#define XSDPS_INTR_BWR_MASK 0x00000010 /**< Buffer Write Ready */ +#define XSDPS_INTR_BRR_MASK 0x00000020 /**< Buffer Read Ready */ +#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040 /**< Card Insert */ +#define XSDPS_INTR_CARD_REM_MASK 0x00000080 /**< Card Remove */ +#define XSDPS_INTR_CARD_MASK 0x00000100 /**< Card Interrupt */ +#define XSDPS_INTR_INT_A_MASK 0x00000200 /**< INT A Interrupt */ +#define XSDPS_INTR_INT_B_MASK 0x00000400 /**< INT B Interrupt */ +#define XSDPS_INTR_INT_C_MASK 0x00000800 /**< INT C Interrupt */ +#define XSDPS_INTR_RE_TUNING_MASK 0x00001000 /**< Re-Tuning Interrupt */ +#define XSDPS_INTR_BOOT_TERM_MASK 0x00002000 /**< Boot Terminate + Interrupt */ +#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00004000 /**< Boot Ack Recv + Interrupt */ +#define XSDPS_INTR_ERR_MASK 0x00008000 /**< Error Interrupt */ +#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFF + +#define XSDPS_INTR_ERR_CT_MASK 0x00000001 /**< Command Timeout + Error */ +#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002 /**< Command CRC Error */ +#define XSDPS_INTR_ERR_CEB_MASK 0x00000004 /**< Command End Bit + Error */ +#define XSDPS_INTR_ERR_CI_MASK 0x00000008 /**< Command Index Error */ +#define XSDPS_INTR_ERR_DT_MASK 0x00000010 /**< Data Timeout Error */ +#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020 /**< Data CRC Error */ +#define XSDPS_INTR_ERR_DEB_MASK 0x00000040 /**< Data End Bit Error */ +#define XSDPS_INTR_ERR_I_LMT_MASK 0x00000080 /**< Current Limit Error */ +#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100 /**< Auto CMD12 Error */ +#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200 /**< ADMA Error */ +#define XSDPS_INTR_ERR_TR_MASK 0x00001000 /**< Tuning Error */ +#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000 /**< Vendor Specific + Error */ +#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FF /**< Mask for error bits */ +/* @} */ + +/** @name Block Size and Block Count Register + * + * This register contains the block count for current transfer, + * block size and SDMA buffer size. + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_BLK_SIZE_MASK 0x00000FFF /**< Transfer Block Size */ +#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000 /**< Host SDMA Buffer Size */ +#define XSDPS_BLK_CNT_MASK 0x0000FFFF /**< Block Count for + Current Transfer */ + +/* @} */ + +/** @name Transfer Mode and Command Register + * + * The Transfer Mode register is used to control the data transfers and + * Command register is used for command generation + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_TM_DMA_EN_MASK 0x00000001 /**< DMA Enable */ +#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002 /**< Block Count Enable */ +#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004 /**< Auto CMD12 Enable */ +#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010 /**< Data Transfer + Direction Select */ +#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020 /**< Multi/Single + Block Select */ + +#define XSDPS_CMD_RESP_SEL_MASK 0x00000003 /**< Response Type + Select */ +#define XSDPS_CMD_RESP_NONE_MASK 0x00000000 /**< No Response */ +#define XSDPS_CMD_RESP_L136_MASK 0x00000001 /**< Response length 138 */ +#define XSDPS_CMD_RESP_L48_MASK 0x00000002 /**< Response length 48 */ +#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003 /**< Response length 48 & + check busy after + response */ +#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008 /**< Command CRC Check + Enable */ +#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010 /**< Command Index Check + Enable */ +#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020 /**< Data Present Select */ +#define XSDPS_CMD_TYPE_MASK 0x000000C0 /**< Command Type */ +#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000 /**< CMD Type - Normal */ +#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040 /**< CMD Type - Suspend */ +#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080 /**< CMD Type - Resume */ +#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0 /**< CMD Type - Abort */ +#define XSDPS_CMD_MASK 0x00003F00 /**< Command Index Mask - + Set to CMD0-63, + AMCD0-63 */ + +/* @} */ + +/** @name Capabilities Register + * + * Capabilities register is a read only register which contains + * information about the host controller. + * Sufficient if read once after power on. + * Read Only + * @{ + */ +#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003F /**< Timeout clock freq + select */ +#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080 /**< Timeout clock unit - + MHz/KHz */ +#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000 /**< Max block length */ +#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000 /**< Max block 512 bytes */ +#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000 /**< Extended media bus */ +#define XSDPS_CAP_ADMA2_MASK 0x00080000 /**< ADMA2 support */ +#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000 /**< High speed support */ +#define XSDPS_CAP_SDMA_MASK 0x00400000 /**< SDMA support */ +#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000 /**< Suspend/Resume + support */ +#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000 /**< 3.3V support */ +#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000 /**< 3.0V support */ +#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000 /**< 1.8V support */ +#define XSDPS_CAP_INTR_MODE_MASK 0x08000000 /**< Interrupt mode + support */ +#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000 /**< 64 bit system bus + support */ +#define XSDPS_CAP_SPI_MODE_MASK 0x20000000 /**< SPI mode */ +#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x20000000 /**< SPI block mode */ +/* @} */ + +/** @name Present State Register + * + * Gives the current status of the host controller + * Read Only + * @{ + */ + +#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001 /**< Command inhibit - CMD */ +#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002 /**< Command Inhibit - DAT */ +#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004 /**< DAT line active */ +#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100 /**< Write transfer active */ +#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200 /**< Read transfer active */ +#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400 /**< Buffer write enable */ +#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800 /**< Buffer read enable */ +#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000 /**< Card inserted */ +#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000 /**< Card state stable */ +#define XSDPS_PSR_CARD_DPL_MASK 0x00040000 /**< Card detect pin level */ +#define XSDPS_PSR_WPS_PL_MASK 0x00080000 /**< Write protect switch + pin level */ + +/* @} */ + +/** @name Block size mask for 512 bytes + * + * Block size mask for 512 bytes - This is the default block size. + * @{ + */ + +#define XSDPS_BLK_SIZE_512_MASK 0x200 + +/* @} */ + +/** @name Commands + * + * Constant definitions for commands and response related to SD + * @{ + */ + +#define XSDPS_APP_CMD_PREFIX 0x8000 +#define CMD0 0x0000 +#define CMD1 0x0100 +#define CMD2 0x0200 +#define CMD3 0x0300 +#define CMD4 0x0400 +#define CMD5 0x0500 +#define CMD6 0x0600 +#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600) +#define CMD7 0x0700 +#define CMD8 0x0800 +#define CMD9 0x0900 +#define CMD10 0x0A00 +#define CMD12 0x0C00 +#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00) +#define CMD16 0x1000 +#define CMD17 0x1100 +#define CMD18 0x1200 +#define CMD23 0x1700 +#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700) +#define CMD24 0x1800 +#define CMD25 0x1900 +#define CMD41 0x2900 +#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900) +#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00) +#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300) +#define CMD52 0x3400 +#define CMD55 0x3700 +#define CMD58 0x3A00 + +#define RESP_NONE XSDPS_CMD_RESP_NONE_MASK +#define RESP_R1 XSDPS_CMD_RESP_L48_MASK | XSDPS_CMD_CRC_CHK_EN_MASK | \ + XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R1B XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R2 XSDPS_CMD_RESP_L136_MASK | XSDPS_CMD_CRC_CHK_EN_MASK +#define RESP_R3 XSDPS_CMD_RESP_L48_MASK + +#define RESP_R6 XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK + +/* @} */ + +/** @name ADMA2 Descriptor related definitions + * + * ADMA2 Descriptor related definitions + * @{ + */ + +#define XSDPS_DESC_MAX_LENGTH 65536 + +#define XSDPS_DESC_VALID (0x1 << 0) +#define XSDPS_DESC_END (0x1 << 1) +#define XSDPS_DESC_INT (0x1 << 2) +#define XSDPS_DESC_TRAN (0x2 << 4) + +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XSdPs_In32 Xil_In32 +#define XSdPs_Out32 Xil_Out32 + +#define XSdPs_In16 Xil_In16 +#define XSdPs_Out16 Xil_Out16 + +#define XSdPs_In8 Xil_In8 +#define XSdPs_Out8 Xil_Out8 + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg(BaseAddress, RegOffset) \ + XSdPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg16(BaseAddress, RegOffset) \ + XSdPs_In16((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg8(BaseAddress, RegOffset) \ + XSdPs_In8((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)) + +/***************************************************************************/ +/** +* Macro to get present status register +* +* @param BaseAddress contains the base address of the device. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +#define XSdPs_GetPresentStatusReg(BaseAddress) \ + XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* SD_HW_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xspips.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xspips.h new file mode 100644 index 000000000..3d699105e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xspips.h @@ -0,0 +1,691 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xspips.h +* +* This file contains the implementation of the XSpiPs driver. It works for +* both the master and slave mode. User documentation for the driver functions +* is contained in this file in the form of comment blocks at the front of each +* function. +* +* An SPI device connects to an SPI bus through a 4-wire serial interface. +* The SPI bus is a full-duplex, synchronous bus that facilitates communication +* between one master and one slave. The device is always full-duplex, +* which means that for every byte sent, one is received, and vice-versa. +* The master controls the clock, so it can regulate when it wants to +* send or receive data. The slave is under control of the master, it must +* respond quickly since it has no control of the clock and must send/receive +* data as fast or as slow as the master does. +* +* Initialization & Configuration +* +* The XSpiPs_Config structure is used by the driver to configure itself. This +* configuration structure is typically created by the tool-chain based on HW +* build properties. +* +* To support multiple runtime loading and initialization strategies employed by +* various operating systems, the driver instance can be initialized in the +* following way: +* - XSpiPs_LookupConfig(DeviceId) - Use the devide identifier to find the +* static configuration structure defined in xspips_g.c. This is setup by +* the tools. For some operating systems the config structure will be +* initialized by the software and this call is not needed. +* - XSpiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the provided virtual memory base address +* replaces the physical address present in the configuration structure. +* +* Multiple Masters +* +* More than one master can exist, but arbitration is the responsibility of +* the higher layer software. The device driver does not perform any type of +* arbitration. +* +* Multiple Slaves +* +* Contention between multiple masters is detected by the hardware, in which +* case a mode fault occurs on the device. The device is disabled immediately +* by hardware, and the current word transfer is stopped. The Aborted word +* transfer due to the mode fault is resumed once the devie is enabled again. +* +* Modes of Operation +* +* There are four modes to perform a data transfer and the selection of a mode +* is based on Chip Select(CS) and Start. These two options individually, can +* be controlled either by software(Manual) or hardware(Auto). +* - Auto CS: Chip select is automatically asserted as soon as the first word +* is written into the TXFIFO and deasserted when the TXFIFO becomes +* empty +* - Manual CS: Software must assert and deassert CS. +* - Auto Start: Data transmission starts as soon as there is data in the +* TXFIFO and stalls when the TXFIFO is empty +* - Manual Start: Software must start data transmission at the beginning of +* the transaction or whenever the TXFIFO has become empty +* +* The preferred combination is Manual CS and Auto Start. +* In this combination, the software asserts CS before loading any data into +* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it +* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the +* data is available. If no further data, software disables CS. +* +* Risks/challenges of other combinations: +* - Manual CS and Manual Start: Manual Start bit should be set after each +* TXFIFO write otherwise there could be a race condition where the TXFIFO +* becomes empty before the new word is written. In that case the +* transmission stops. +* - Auto CS with Manual or Auto Start: It is very difficult for software to +* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is deasserted. +* This results in a single transaction to be split into multiple pieces each +* with its own chip select. This will result in garbage data to be sent. +* +* Interrupts +* +* The user must connect the interrupt handler of the driver, +* XSpiPs_InterruptHandler, to an interrupt system such that it will be +* called when an interrupt occurs. This function does not save and restore +* the processor context such that the user must provide this processing. +* +* The driver handles the following interrupts: +* - Data Transmit Register/FIFO Underflow +* - Data Receive Register/FIFO Full +* - Data Receive Register/FIFO Not Empty +* - Data Transmit Register/FIFO Full +* - Data Transmit Register/FIFO Overwater +* - Mode Fault Error +* - Data Receive Register/FIFO Overrun +* +* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the +* SPI device has transmitted the data available to transmit, and now its data +* register and FIFO is ready to accept more data. The driver uses this +* interrupt to indicate progress while sending data. The driver may have +* more data to send, in which case the data transmit register and FIFO is +* filled for subsequent transmission. When this interrupt arrives and all +* the data has been sent, the driver invokes the status callback with a +* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that +* all data has been sent. +* +* The Data Transmit Register/FIFO Underflow interrupt -- indicates that, +* as slave, the SPI device was required to transmit but there was no data +* available to transmit in the transmit register (or FIFO). This may not +* be an error if the master is not expecting data. But in the case where +* the master is expecting data, this serves as a notification of such a +* condition. The driver reports this condition to the upper layer +* software through the status handler. +* +* The Data Receive Register/FIFO Overrun interrupt -- indicates that the SPI +* device received data and subsequently dropped the data because the data +* receive register and FIFO was full. The interrupt applies to both master +* and slave operation. The driver reports this condition to the upper layer +* software through the status handler. This likely indicates a problem with +* the higher layer protocol, or a problem with the slave performance. +* +* The Mode Fault Error interrupt -- indicates that while configured as a +* master, the device was selected as a slave by another master. This can be +* used by the application for arbitration in a multimaster environment or to +* indicate a problem with arbitration. When this interrupt occurs, the +* driver invokes the status callback with a status value of +* XST_SPI_MODE_FAULT. It is up to the application to resolve the conflict. +* When configured as a slave, Mode Fault Error interrupt indicates that a slave +* device was selected as a slave by a master, but the slave device was +* disabled. When configured as a master, Mode Fault Error interrupt indicates +* that another SPI device is acting as a master on the bus. +* +* +* Polled Operation +* +* Transfer in polled mode is supported through a separate interface function +* XSpiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode, +* this function blocks until all data has been sent/received. +* +* Device Busy +* +* Some operations are disallowed when the device is busy. The driver tracks +* whether a device is busy. The device is considered busy when a data transfer +* request is outstanding, and is considered not busy only when that transfer +* completes (or is aborted with a mode fault error). This applies to both +* master and slave devices. +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xspips_g.c file or +* passed in via XSpiPs_CfgInitialize(). A table is defined where each entry +* contains configuration information for an SPI device, including the base +* address for the device. +* +* RTOS Independence +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads or +* thread mutual exclusion, virtual memory, or cache control must be satisfied +* by the layer above this driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	drg/jz 01/25/10 First release
+* 1.00	sdm    10/25/11 Removed the Divide by 2 in the SPI Clock Prescaler
+*			options as this is not supported in the device.
+* 1.01	sg     03/07/12 Updated the code to always clear the relevant bits
+*			before writing to config register.
+*			Always clear the slave select bits before write and
+*			clear the bits to no slave at the end of transfer
+*			Modified the Polled transfer transmit/receive logic.
+*			Tx should wait on TXOW Interrupt and Rx on RXNEMTY.
+* 1.02	sg     05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
+*			for CR 658289
+* 1.03	sg     09/21/12 Added memory barrier dmb in polled transfer and
+*			interrupt handler to overcome the clock domain
+*			crossing issue in the controller. For CR #679252.
+* 1.04a	sg     01/30/13 Created XSPIPS_MANUAL_START_OPTION. Created macros
+*			XSpiPs_IsMaster, XSpiPs_IsManualStart and
+*			XSpiPs_IsManualChipSelect. Changed SPI
+*			Enable/Disable macro argument from BaseAddress to
+*			Instance Pointer. Added DelayNss argument to SetDelays
+*			and GetDelays API's. Added macros to set/get the
+*			RX Watermark value.Created macros XSpiPs_IsMaster,
+*			XSpiPs_IsManualStart and XSpiPs_IsManualChipSelect.
+*			Changed SPI transfer logic for polled and interrupt
+*			modes to be based on filled tx fifo count and receive
+*			based on it. RXNEMPTY interrupt is not used.
+*			SetSlaveSelect API logic is modified to drive the bit
+*			position low based on the slave select value
+*			requested. GetSlaveSelect API will return the value
+*			based on bit position that is low.
+*			Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
+*			to XSPIPS_CR_RESET_STATE. Created
+* 			XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
+*			write-to-clear. Added shift and mask macros for d_nss
+*			parameter. Added Rx Watermark mask.
+* 1.05a hk 	   26/04/13 Added disable and enable in XSpiPs_SetOptions when
+*				CPOL/CPHA bits are set/reset. Fix for CR#707669.
+* 1.06a hk     08/22/13 Changed GetSlaveSelect function. CR# 727866.
+*                       Added masking ConfigReg before writing in SetSlaveSel
+*                       Added extended slave select support - CR#722569.
+*                       Added prototypes of reset API and related constant
+*                       definitions.
+*                       Added check for MODF in polled transfer function.
+* 3.0   vm    12/09/14	Modified driver source code for MISRA-C:2012 compliance.
+*			Support for Zynq Ultrascale Mp added.
+*
+*
+* +******************************************************************************/ +#ifndef XSPIPS_H /* prevent circular inclusions */ +#define XSPIPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xspips_hw.h" + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * The following options are supported to enable/disable certain features of + * an SPI device. Each of the options is a bit mask, so more than one may be + * specified. + * + * The Master option configures the SPI device as a master. + * By default, the device is a slave. + * + * The Active Low Clock option configures the device's clock polarity. + * Setting this option means the clock is active low and the SCK signal idles + * high. By default, the clock is active high and SCK idles low. + * + * The Clock Phase option configures the SPI device for one of two + * transfer formats. A clock phase of 0, the default, means data is valid on + * the first SCK edge (rising or falling) after the slave select (SS) signal + * has been asserted. A clock phase of 1 means data is valid on the second SCK + * edge (rising or falling) after SS has been asserted. + * + * The Slave Select Decode Enable option selects how the SPI_SS_outN are + * controlled by the SPI Slave Select Decode bits. + * 0: Use this setting for the standard configuration of up to three slave + * select outputs. Only one of the three slave select outputs will be low. + * (Default) + * 1: Use this setting for the optional configuration of an additional decoder + * to support 8 slave select outputs. SPI_SS_outN reflects the value in the + * register. + * + * The SPI Force Slave Select option is used to enable manual control of + * the signals SPI_SS_outN. + * 0: The SPI_SS_outN signals are controlled by the SPI controller during + * transfers. (Default) + * 1: The SPI_SS_outN signal indicated by the Slave Select Control bit is + * forced active (driven low) regardless of any transfers in progress. + * + * NOTE: The driver will handle setting and clearing the Slave Select when + * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the + * SPI clock to be set to a faster speed. If the SPI clock is too fast, the + * processor cannot empty and refill the FIFOs before the TX FIFO is empty + * When the SPI hardware is controlling the Slave Select signals, this + * will cause slave to be de-selected and terminate the transfer. + * + * The Manual Start option is used to enable manual control of + * the Start command to perform data transfer. + * 0: The Start command is controlled by the SPI controller during + * transfers(Default). Data transmission starts as soon as there is data in + * the TXFIFO and stalls when the TXFIFO is empty + * 1: The Start command must be issued by software to perform data transfer. + * Bit 15 of Configuration register is used to issue Start command. This bit + * must be set whenever TXFIFO is filled with new data. + * + * NOTE: The driver will set the Manual Start Enable bit in Configuration + * Register, if Manual Start option is selected. Software will issue + * Manual Start command whenever TXFIFO is filled with data. When there is + * no further data, driver will clear the Manual Start Enable bit. + * + * @{ + */ +#define XSPIPS_MASTER_OPTION 0x00000001U /**< Master mode option */ +#define XSPIPS_CLK_ACTIVE_LOW_OPTION 0x00000002U /**< Active Low Clock option */ +#define XSPIPS_CLK_PHASE_1_OPTION 0x00000004U /**< Clock Phase one option */ +#define XSPIPS_DECODE_SSELECT_OPTION 0x00000008U /**< Select 16 slaves Option */ +#define XSPIPS_FORCE_SSELECT_OPTION 0x00000010U /**< Force Slave Select */ +#define XSPIPS_MANUAL_START_OPTION 0x00000020U /**< Manual Start mode option */ +/*@}*/ + + +/** @name SPI Clock Prescaler options + * The SPI Clock Prescaler Configuration bits are used to program master mode + * bit rate. The bit rate can be programmed in divide-by-two decrements from + * pclk/4 to pclk/256. + * + * @{ + */ + +#define XSPIPS_CLK_PRESCALE_4 0x01U /**< PCLK/4 Prescaler */ +#define XSPIPS_CLK_PRESCALE_8 0x02U /**< PCLK/8 Prescaler */ +#define XSPIPS_CLK_PRESCALE_16 0x03U /**< PCLK/16 Prescaler */ +#define XSPIPS_CLK_PRESCALE_32 0x04U /**< PCLK/32 Prescaler */ +#define XSPIPS_CLK_PRESCALE_64 0x05U /**< PCLK/64 Prescaler */ +#define XSPIPS_CLK_PRESCALE_128 0x06U /**< PCLK/128 Prescaler */ +#define XSPIPS_CLK_PRESCALE_256 0x07U /**< PCLK/256 Prescaler */ +/*@}*/ + + +/** @name Callback events + * + * These constants specify the handler events that are passed to + * a handler from the driver. These constants are not bit masks such that + * only one will be passed at a time to the handler. + * + * @{ + */ +#define XSPIPS_EVENT_MODE_FAULT 1U /**< Mode fault error */ +#define XSPIPS_EVENT_TRANSFER_DONE 2U /**< Transfer done */ +#define XSPIPS_EVENT_TRANSMIT_UNDERRUN 3U /**< TX FIFO empty */ +#define XSPIPS_EVENT_RECEIVE_OVERRUN 4U /**< Receive data loss because + RX FIFO full */ +/*@}*/ + + +/**************************** Type Definitions *******************************/ +/** + * The handler data type allows the user to define a callback function to + * handle the asynchronous processing for the SPI device. The application + * using this driver is expected to define a handler of this type to support + * interrupt driven mode. The handler executes in an interrupt context, so + * only minimal processing should be performed. + * + * @param CallBackRef is the callback reference passed in by the upper + * layer when setting the callback functions, and passed back to + * the upper layer when the callback is invoked. Its type is + * not important to the driver, so it is a void pointer. + * @param StatusEvent holds one or more status events that have occurred. + * See the XSpiPs_SetStatusHandler() for details on the status + * events that can be passed in the callback. + * @param ByteCount indicates how many bytes of data were successfully + * transferred. This may be less than the number of bytes + * requested if the status event indicates an error. + */ +typedef void (*XSpiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent, + u32 ByteCount); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ +} XSpiPs_Config; + +/** + * The XSpiPs driver instance data. The user is required to allocate a + * variable of this type for every SPI device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XSpiPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + + u8 *SendBufferPtr; /**< Buffer to send (state) */ + u8 *RecvBufferPtr; /**< Buffer to receive (state) */ + u32 RequestedBytes; /**< Number of bytes to transfer (state) */ + u32 RemainingBytes; /**< Number of bytes left to transfer(state) */ + u32 IsBusy; /**< A transfer is in progress (state) */ + u32 SlaveSelect; /**< The slave select value when + XSPIPS_FORCE_SSELECT_OPTION is set */ + + XSpiPs_StatusHandler StatusHandler; + void *StatusRef; /**< Callback reference for status handler */ + +} XSpiPs; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/* +* +* Check in OptionsTable if Manual Start Option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XSpiPs_IsManualStart(XSpiPs *InstancePtr); +* +*****************************************************************************/ +#define XSpiPs_IsManualStart(InstancePtr) \ + (((XSpiPs_GetOptions(InstancePtr) & \ + XSPIPS_MANUAL_START_OPTION) != (u32)0U) ? TRUE : FALSE) + +/****************************************************************************/ +/* +* +* Check in OptionsTable if Manual Chip Select Option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XSpiPs_IsManualChipSelect(XSpiPs *InstancePtr); +* +*****************************************************************************/ +#define XSpiPs_IsManualChipSelect(InstancePtr) \ + (((XSpiPs_GetOptions(InstancePtr) & \ + XSPIPS_FORCE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE) + +/****************************************************************************/ +/* +* +* Check in OptionsTable if Decode Slave Select option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XSpiPs_IsDecodeSSelect(XSpiPs *InstancePtr); +* +*****************************************************************************/ +#define XSpiPs_IsDecodeSSelect(InstancePtr) \ + (((XSpiPs_GetOptions(InstancePtr) & \ + XSPIPS_DECODE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE) + +/****************************************************************************/ +/* +* +* Check in OptionsTable if Master Option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XSpiPs_IsMaster(XSpiPs *InstancePtr); +* +*****************************************************************************/ +#define XSpiPs_IsMaster(InstancePtr) \ + (((XSpiPs_GetOptions(InstancePtr) & \ + XSPIPS_MASTER_OPTION) != (u32)0U) ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* Set the contents of the slave idle count register. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* @param RegisterValue is the value to be writen, valid values are +* 0-255. +* +* @return None +* +* @note +* C-Style signature: +* void XSpiPs_SetSlaveIdle(XSpiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XSpiPs_SetSlaveIdle(InstancePtr, RegisterValue) \ + XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XSPIPS_SICR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the slave idle count register. Use the XSPIPS_SICR_* +* constants defined in xspips_hw.h to interpret the bit-mask returned. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return 8-bit value representing the contents of the SIC register. +* +* @note C-Style signature: +* u32 XSpiPs_GetSlaveIdle(XSpiPs *InstancePtr) +* +*****************************************************************************/ +#define XSpiPs_GetSlaveIdle(InstancePtr) \ + XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + \ + XSPIPS_SICR_OFFSET) + +/****************************************************************************/ +/** +* +* Set the contents of the transmit FIFO watermark register. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* @param RegisterValue is the value to be written, valid values +* are 1-128. +* +* @return None. +* +* @note +* C-Style signature: +* void XSpiPs_SetTXWatermark(XSpiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XSpiPs_SetTXWatermark(InstancePtr, RegisterValue) \ + XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XSPIPS_TXWR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the transmit FIFO watermark register. +* Use the XSPIPS_TXWR_* constants defined xspips_hw.h to interpret +* the bit-mask returned. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return 8-bit value representing the contents of the TXWR register. +* +* @note C-Style signature: +* u32 XSpiPs_GetTXWatermark(u32 *InstancePtr) +* +*****************************************************************************/ +#define XSpiPs_GetTXWatermark(InstancePtr) \ + XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_TXWR_OFFSET) + +/****************************************************************************/ +/** +* +* Set the contents of the receive FIFO watermark register. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* @param RegisterValue is the value to be written, valid values +* are 1-128. +* +* @return None. +* +* @note +* C-Style signature: +* void XSpiPs_SetRXWatermark(XSpiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XSpiPs_SetRXWatermark(InstancePtr, RegisterValue) \ + XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XSPIPS_RXWR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the receive FIFO watermark register. +* Use the XSPIPS_RXWR_* constants defined xspips_hw.h to interpret +* the bit-mask returned. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return A 8-bit value representing the contents of the RXWR register. +* +* @note C-Style signature: +* u32 XSpiPs_GetRXWatermark(u32 *InstancePtr) +* +*****************************************************************************/ +#define XSpiPs_GetRXWatermark(InstancePtr) \ + XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_RXWR_OFFSET) + +/****************************************************************************/ +/** +* +* Enable the device and uninhibit master transactions. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XSpiPs_Enable(u32 *InstancePtr) +* +*****************************************************************************/ +#define XSpiPs_Enable(InstancePtr) \ + XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, \ + XSPIPS_ER_ENABLE_MASK) + +/****************************************************************************/ +/** +* +* Disable the device. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XSpiPs_Disable(u32 *InstancePtr) +* +*****************************************************************************/ +#define XSpiPs_Disable(InstancePtr) \ + XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, 0U) + +/************************** Function Prototypes ******************************/ + +/* + * Initialization function, implemented in xspips_sinit.c + */ +XSpiPs_Config *XSpiPs_LookupConfig(u16 DeviceId); + +/* + * Functions implemented in xspips.c + */ +s32 XSpiPs_CfgInitialize(XSpiPs *InstancePtr, XSpiPs_Config * ConfigPtr, + u32 EffectiveAddr); + +void XSpiPs_Reset(XSpiPs *InstancePtr); + +s32 XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, + u32 ByteCount); + +s32 XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr, + u8 *RecvBufPtr, u32 ByteCount); + +void XSpiPs_SetStatusHandler(XSpiPs *InstancePtr, void *CallBackRef, + XSpiPs_StatusHandler FunctionPtr); +void XSpiPs_InterruptHandler(XSpiPs *InstancePtr); + +void XSpiPs_Abort(XSpiPs *InstancePtr); + +s32 XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel); +u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr); + +/* + * Functions for selftest, in xspips_selftest.c + */ +s32 XSpiPs_SelfTest(XSpiPs *InstancePtr); + +/* + * Functions for options, in xspips_options.c + */ +s32 XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options); +u32 XSpiPs_GetOptions(XSpiPs *InstancePtr); + +s32 XSpiPs_SetClkPrescaler(XSpiPs *InstancePtr, u8 Prescaler); +u8 XSpiPs_GetClkPrescaler(XSpiPs *InstancePtr); + +s32 XSpiPs_SetDelays(XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, + u8 DelayAfter, u8 DelayInit); +void XSpiPs_GetDelays(XSpiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, + u8 *DelayAfter, u8 *DelayInit); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xspips_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xspips_hw.h new file mode 100644 index 000000000..897340369 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xspips_hw.h @@ -0,0 +1,310 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xspips_hw.h +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xspips.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00   drg/jz 01/25/10 First release
+* 1.02a  sg     05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
+*			 for CR 658289
+* 1.04a	 sg     01/30/13 Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
+*			 to XSPIPS_CR_RESET_STATE. Created
+* 			 XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
+*			 write-to-clear. Added shift and mask macros for d_nss
+*			 parameter. Added Rx Watermark mask.
+* 1.06a hk      08/22/13 Added prototypes of reset API and related constant
+*                        definitions.
+* 3.00  kvn     02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+* +******************************************************************************/ + +#ifndef XSPIPS_HW_H /* prevent circular inclusions */ +#define XSPIPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an SPI device. + * @{ + */ +#define XSPIPS_CR_OFFSET 0x00U /**< Configuration */ +#define XSPIPS_SR_OFFSET 0x04U /**< Interrupt Status */ +#define XSPIPS_IER_OFFSET 0x08U /**< Interrupt Enable */ +#define XSPIPS_IDR_OFFSET 0x0CU /**< Interrupt Disable */ +#define XSPIPS_IMR_OFFSET 0x10U /**< Interrupt Enabled Mask */ +#define XSPIPS_ER_OFFSET 0x14U /**< Enable/Disable Register */ +#define XSPIPS_DR_OFFSET 0x18U /**< Delay Register */ +#define XSPIPS_TXD_OFFSET 0x1CU /**< Data Transmit Register */ +#define XSPIPS_RXD_OFFSET 0x20U /**< Data Receive Register */ +#define XSPIPS_SICR_OFFSET 0x24U /**< Slave Idle Count */ +#define XSPIPS_TXWR_OFFSET 0x28U /**< Transmit FIFO Watermark */ +#define XSPIPS_RXWR_OFFSET 0x2CU /**< Receive FIFO Watermark */ +/* @} */ + +/** @name Configuration Register + * + * This register contains various control bits that + * affects the operation of an SPI device. Read/Write. + * @{ + */ +#define XSPIPS_CR_MODF_GEN_EN_MASK 0x00020000U /**< Modefail Generation + Enable */ +#define XSPIPS_CR_MANSTRT_MASK 0x00010000U /**< Manual Transmission Start */ +#define XSPIPS_CR_MANSTRTEN_MASK 0x00008000U /**< Manual Transmission Start + Enable */ +#define XSPIPS_CR_SSFORCE_MASK 0x00004000U /**< Force Slave Select */ +#define XSPIPS_CR_SSCTRL_MASK 0x00003C00U /**< Slave Select Decode */ +#define XSPIPS_CR_SSCTRL_SHIFT 10U /**< Slave Select Decode shift */ +#define XSPIPS_CR_SSCTRL_MAXIMUM 0xFU /**< Slave Select maximum value */ +#define XSPIPS_CR_SSDECEN_MASK 0x00000200U /**< Slave Select Decode Enable */ + +#define XSPIPS_CR_PRESC_MASK 0x00000038U /**< Prescaler Setting */ +#define XSPIPS_CR_PRESC_SHIFT 3U /**< Prescaler shift */ +#define XSPIPS_CR_PRESC_MAXIMUM 0x07U /**< Prescaler maximum value */ + +#define XSPIPS_CR_CPHA_MASK 0x00000004U /**< Phase Configuration */ +#define XSPIPS_CR_CPOL_MASK 0x00000002U /**< Polarity Configuration */ + +#define XSPIPS_CR_MSTREN_MASK 0x00000001U /**< Master Mode Enable */ +#define XSPIPS_CR_RESET_STATE 0x00020000U /**< Mode Fail Generation Enable */ +/* @} */ + + +/** @name SPI Interrupt Registers + * + * SPI Status Register + * + * This register holds the interrupt status flags for an SPI device. Some + * of the flags are level triggered, which means that they are set as long + * as the interrupt condition exists. Other flags are edge triggered, + * which means they are set once the interrupt condition occurs and remain + * set until they are cleared by software. The interrupts are cleared by + * writing a '1' to the interrupt bit position in the Status Register. + * Read/Write. + * + * SPI Interrupt Enable Register + * + * This register is used to enable chosen interrupts for an SPI device. + * Writing a '1' to a bit in this register sets the corresponding bit in the + * SPI Interrupt Mask register. Write only. + * + * SPI Interrupt Disable Register + * + * This register is used to disable chosen interrupts for an SPI device. + * Writing a '1' to a bit in this register clears the corresponding bit in the + * SPI Interrupt Mask register. Write only. + * + * SPI Interrupt Mask Register + * + * This register shows the enabled/disabled interrupts of an SPI device. + * Read only. + * + * All four registers have the same bit definitions. They are only defined once + * for each of the Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Channel Interrupt Status Register + * @{ + */ + +#define XSPIPS_IXR_TXUF_MASK 0x00000040U /**< Tx FIFO Underflow */ +#define XSPIPS_IXR_RXFULL_MASK 0x00000020U /**< Rx FIFO Full */ +#define XSPIPS_IXR_RXNEMPTY_MASK 0x00000010U /**< Rx FIFO Not Empty */ +#define XSPIPS_IXR_TXFULL_MASK 0x00000008U /**< Tx FIFO Full */ +#define XSPIPS_IXR_TXOW_MASK 0x00000004U /**< Tx FIFO Overwater */ +#define XSPIPS_IXR_MODF_MASK 0x00000002U /**< Mode Fault */ +#define XSPIPS_IXR_RXOVR_MASK 0x00000001U /**< Rx FIFO Overrun */ +#define XSPIPS_IXR_DFLT_MASK 0x00000027U /**< Default interrupts + mask */ +#define XSPIPS_IXR_WR_TO_CLR_MASK 0x00000043U /**< Interrupts which + need write to clear */ +#define XSPIPS_ISR_RESET_STATE 0x04U /**< Default to tx/rx + * reg empty */ +#define XSPIPS_IXR_DISABLE_ALL_MASK 0x00000043U /**< Disable all + * interrupts */ +/* @} */ + + +/** @name Enable Register + * + * This register is used to enable or disable an SPI device. + * Read/Write + * @{ + */ +#define XSPIPS_ER_ENABLE_MASK 0x00000001U /**< SPI Enable Bit Mask */ +/* @} */ + + +/** @name Delay Register + * + * This register is used to program timing delays in + * slave mode. Read/Write + * @{ + */ +#define XSPIPS_DR_NSS_MASK 0xFF000000U /**< Delay for slave select + * de-assertion between + * word transfers mask */ +#define XSPIPS_DR_NSS_SHIFT 24U /**< Delay for slave select + * de-assertion between + * word transfers shift */ +#define XSPIPS_DR_BTWN_MASK 0x00FF0000U /**< Delay Between Transfers mask */ +#define XSPIPS_DR_BTWN_SHIFT 16U /**< Delay Between Transfers shift */ +#define XSPIPS_DR_AFTER_MASK 0x0000FF00U /**< Delay After Transfers mask */ +#define XSPIPS_DR_AFTER_SHIFT 8U /**< Delay After Transfers shift */ +#define XSPIPS_DR_INIT_MASK 0x000000FFU /**< Delay Initially mask */ +/* @} */ + + +/** @name Slave Idle Count Registers + * + * This register defines the number of pclk cycles the slave waits for a the + * SPI clock to become stable in quiescent state before it can detect the start + * of the next transfer in CPHA = 1 mode. + * Read/Write + * + * @{ + */ +#define XSPIPS_SICR_MASK 0x000000FFU /**< Slave Idle Count Mask */ +/* @} */ + + + +/** @name Transmit FIFO Watermark Register + * + * This register defines the watermark setting for the Transmit FIFO. The + * transmit FIFO is 128 bytes deep, so the register is 7 bits. Valid values + * are 1 to 128. + * + * @{ + */ +#define XSPIPS_TXWR_MASK 0x0000007FU /**< Transmit Watermark Mask */ +#define XSPIPS_TXWR_RESET_VALUE 0x00000001U /**< Transmit Watermark + * register reset value */ +/* @} */ + +/** @name Receive FIFO Watermark Register + * + * This register defines the watermark setting for the Receive FIFO. The + * receive FIFO is 128 bytes deep, so the register is 7 bits. Valid values + * are 1 to 128. + * + * @{ + */ +#define XSPIPS_RXWR_MASK 0x0000007FU /**< Receive Watermark Mask */ +#define XSPIPS_RXWR_RESET_VALUE 0x00000001U /**< Receive Watermark + * register reset value */ +/* @} */ + +/** @name FIFO Depth + * + * This macro provides the depth of transmit FIFO and receive FIFO. + * + * @{ + */ +#define XSPIPS_FIFO_DEPTH 128U /**< FIFO depth of Tx and Rx */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XSpiPs_In32 Xil_In32 +#define XSpiPs_Out32 Xil_Out32 + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSpiPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSpiPs_ReadReg(BaseAddress, RegOffset) \ + XSpiPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSpiPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XSpiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XSpiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/************************** Function Prototypes ******************************/ + +void XSpiPs_ResetHw(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xstatus.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xstatus.h new file mode 100644 index 000000000..7db874c88 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xstatus.h @@ -0,0 +1,430 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* This file contains Xilinx software status codes. Status codes have their +* own data type called int. These codes are used throughout the Xilinx +* device drivers. +* +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ + +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /* an error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /* an error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /* a DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /* the device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /* there was no data available */ +#define XST_REGISTER_ERROR 14L /* a register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /* an invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /* the device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ +#define XST_NO_CALLBACK 18L /* a callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /* device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /* device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /* device is busy */ +#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /* used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /* used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /* driver defined error */ +#define XST_RECV_ERROR 27L /* generic receive error */ +#define XST_SEND_ERROR 28L /* generic transmit error */ +#define XST_NOT_ENABLED 29L /* a requested service is not + available because it has not + been enabled */ + +/***************** Utility Component statuses 401 - 500 *********************/ + +#define XST_MEMTEST_FAILED 401L /* memory test failed */ + + +/***************** Common Components statuses 501 - 1000 *********************/ + +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting + * empty and full simultaneously + */ + +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /* general buffer descriptor + error */ + +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /* generic ipif error */ + +/****************** Device specific statuses 1001 - 4095 *********************/ + +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ +#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late + * collision on polled send */ + +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + + +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ +#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ + +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ + +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /* Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /* Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ + +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ + +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ + +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ + +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ + +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L + +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L + +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L + +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L + +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ + +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L + +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 + +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 + +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + + +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 + +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /* Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /* Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /* Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected + */ + +/**************************** Type Definitions *******************************/ + +typedef int XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xtime_l.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xtime_l.h new file mode 100644 index 000000000..fd75790a4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xtime_l.h @@ -0,0 +1,88 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.h +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp	   05/29/14 First release
+*
+* +* @note None. +* +******************************************************************************/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ + +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND 0x007A1200U + +#define XIOU_SCNTRS_BASEADDR 0XFF260000U +#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET 0x00000000U +#define XIOU_SCNTRS_FREQ_REG_OFFSET 0x00000020U +#define XIOU_SCNTRS_FREQ 0x02FAF080U /* 50 MHz */ +#define XIOU_SCNTRS_CNT_CNTRL_REG_EN 0X00000001U + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xttcps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xttcps.h new file mode 100644 index 000000000..86bcb97cc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xttcps.h @@ -0,0 +1,408 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps.h +* +* This is the driver for one 16-bit timer counter in the Triple Timer Counter +* (TTC) module in the Ps block. +* +* The TTC module provides three independent timer/counter modules that can each +* be clocked using either the system clock (pclk) or an externally driven +* clock (ext_clk). In addition, each counter can independently prescale its +* selected clock input (divided by 2 to 65536). Counters can be set to +* decrement or increment. +* +* Each of the counters can be programmed to generate interrupt pulses: +* . At a regular, predefined period, that is on a timed interval +* . When the counter registers overflow +* . When the count matches any one of the three 'match' registers +* +* Therefore, up to six different events can trigger a timer interrupt: three +* match interrupts, an overflow interrupt, an interval interrupt and an event +* timer interrupt. Note that the overflow interrupt and the interval interrupt +* are mutually exclusive. +* +* Initialization & Configuration +* +* An XTtcPs_Config structure is used to configure a driver instance. +* Information in the XTtcPs_Config structure is the hardware properties +* about the device. +* +* A driver instance is initialized through +* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr +* is a pointer to the XTtcPs_Config structure, it can be looked up statically +* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The +* EffectiveAddr can be the static base address of the device or virtual +* mapped address if address translation is supported. +* +* Interrupts +* +* Interrupt handler is not provided by the driver, as handling of interrupt +* is application specific. +* +* @note +* The default setting for a timer/counter is: +* - Overflow Mode +* - Internal clock (pclk) selected +* - Counter disabled +* - All Interrupts disabled +* - Output waveforms disabled +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+* 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +#ifndef XTTCPS_H /* prevent circular inclusions */ +#define XTTCPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xttcps_hw.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * Options for the device. Each of the options is bit field, so more than one + * options can be specified. + * + * @{ + */ +#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */ +#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for + external clock*/ +#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */ +#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */ +#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */ +#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */ +#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID for device */ + u32 BaseAddress; /**< Base address for device */ + u32 InputClockHz; /**< Input clock frequency */ +} XTtcPs_Config; + +/** + * The XTtcPs driver instance data. The user is required to allocate a + * variable of this type for each PS timer/counter device in the system. A + * pointer to a variable of this type is then passed to various driver API + * functions. + */ +typedef struct { + XTtcPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ +} XTtcPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/* + * Internal helper macros + */ +#define InstReadReg(InstancePtr, RegOffset) \ + (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset))) + +#define InstWriteReg(InstancePtr, RegOffset, Data) \ + (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data))) + +/*****************************************************************************/ +/** +* +* This function starts the counter/timer without resetting the counter value. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_Start(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_Start(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \ + ~XTTCPS_CNT_CNTRL_DIS_MASK)) + +/*****************************************************************************/ +/** +* +* This function stops the counter/timer. This macro may be called at any time +* to stop the counter. The counter holds the last value until it is reset, +* restarted or enabled. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_Stop(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_Stop(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \ + XTTCPS_CNT_CNTRL_DIS_MASK)) + +/*****************************************************************************/ +/** +* +* This function checks whether the timer counter has already started. +* +* @param InstancePtr is a pointer to the XTtcPs instance +* +* @return Non-zero if the device has started, '0' otherwise. +* +* @note C-style signature: +* int XTtcPs_IsStarted(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_IsStarted(InstancePtr) \ + ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \ + XTTCPS_CNT_CNTRL_DIS_MASK) == 0U) + +/*****************************************************************************/ +/** +* +* This function returns the current 16-bit counter value. It may be called at +* any time. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return 16-bit counter value. +* +* @note C-style signature: +* u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_GetCounterValue(InstancePtr) \ + (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET) + +/*****************************************************************************/ +/** +* +* This function sets the interval value to be used in interval mode. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param Value is the 16-bit value to be set in the interval register. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value) +* +****************************************************************************/ +#define XTtcPs_SetInterval(InstancePtr, Value) \ + InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value)) + +/*****************************************************************************/ +/** +* +* This function gets the interval value from the interval register. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return 16-bit interval value +* +* @note C-style signature: +* u16 XTtcPs_GetInterval(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_GetInterval(InstancePtr) \ + (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET) + +/*****************************************************************************/ +/** +* +* This macro resets the count register. It may be called at any time. The +* counter is reset to either 0 or 0xFFFF, or the interval value, depending on +* the increment/decrement mode. The state of the counter, as started or +* stopped, is not affected by calling reset. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_ResetCounterValue(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \ + (u32)XTTCPS_CNT_CNTRL_RST_MASK)) + +/*****************************************************************************/ +/** +* +* This function enables the interrupts. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be enabled. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be enabled, cleared bits +* will not be disabled. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \ + (InterruptMask))) + +/*****************************************************************************/ +/** +* +* This function disables the interrupts. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be disabled. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be disabled, cleared bits +* will not be disabled. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \ + ~(InterruptMask))) + +/*****************************************************************************/ +/** +* +* This function reads the interrupt status. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None. +* +* @note C-style signature: +* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr) +* +******************************************************************************/ +#define XTtcPs_GetInterruptStatus(InstancePtr) \ + InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears the interrupt status. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be cleared. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be cleared, cleared bits +* will not be cleared. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \ + (InterruptMask)) + + +/************************** Function Prototypes ******************************/ + +/* + * Initialization functions in xttcps_sinit.c + */ +XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); + +/* + * Required functions, in xttcps.c + */ +s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, + XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); + +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value); +u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); + +void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue); +u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr); + +void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, + u16 *Interval, u8 *Prescaler); + +/* + * Functions for options, in file xttcps_options.c + */ +s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options); +u32 XTtcPs_GetOptions(XTtcPs *InstancePtr); + +/* + * Function for self-test, in file xttcps_selftest.c + */ +s32 XTtcPs_SelfTest(XTtcPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xttcps_hw.h new file mode 100644 index 000000000..8f12e3c10 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xttcps_hw.h @@ -0,0 +1,209 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps_hw.h +* +* This file defines the hardware interface to one of the three timer counters +* in the Ps block. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+* +******************************************************************************/ + +#ifndef XTTCPS_HW_H /* prevent circular inclusions */ +#define XTTCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of the device. + * + * @{ + */ +#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/ +#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */ +#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */ +#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */ +#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */ +#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */ +#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */ +#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */ +/* @} */ + +/** @name Clock Control Register + * Clock Control Register definitions + * @{ + */ +#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */ +#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */ +#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */ +#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */ +#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */ +#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */ +/* @} */ + +/** @name Counter Control Register + * Counter Control Register definitions + * @{ + */ +#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */ +#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */ +#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */ +#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */ +#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */ +#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */ +#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */ +#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */ +/* @} */ + +/** @name Current Counter Value Register + * Current Counter Value Register definitions + * @{ + */ +#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */ +/* @} */ + +/** @name Interval Value Register + * Interval Value Register is the maximum value the counter will count up or + * down to. + * @{ + */ +#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/ +/* @} */ + +/** @name Match Registers + * Definitions for Match registers, each timer counter has three match + * registers. + * @{ + */ +#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */ +#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */ +/* @} */ + +/** @name Interrupt Registers + * Following register bit mask is for all interrupt registers. + * + * @{ + */ +#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */ +#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */ +#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */ +#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */ +#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */ +#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */ +/* @} */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XTtcPs_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (u32)(RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))) + +/****************************************************************************/ +/** +* +* Calculate a match register offset using the Match Register index. +* +* @param MatchIndex is the 0-2 value of the match register +* +* @return MATCH_N_OFFSET. +* +* @note C-style signature: +* u32 XTtcPs_Match_N_Offset(u8 MatchIndex) +* +*****************************************************************************/ +#define XTtcPs_Match_N_Offset(MatchIndex) \ + ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex))) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xuartps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xuartps.h new file mode 100644 index 000000000..ae72e66d7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xuartps.h @@ -0,0 +1,509 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xuartps.h +* +* This driver supports the following features: +* +* - Dynamic data format (baud rate, data bits, stop bits, parity) +* - Polled mode +* - Interrupt driven mode +* - Transmit and receive FIFOs (32 byte FIFO depth) +* - Access to the external modem control lines +* +* Initialization & Configuration +* +* The XUartPs_Config structure is used by the driver to configure itself. +* Fields inside this structure are properties of XUartPs based on its hardware +* build. +* +* To support multiple runtime loading and initialization strategies employed +* by various operating systems, the driver instance can be initialized in the +* following way: +* +* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the parameter EffectiveAddr should be the +* virtual address. +* +* Baud Rate +* +* The UART has an internal baud rate generator, which furnishes the baud rate +* clock for both the receiver and the transmitter. Ther input clock frequency +* can be either the master clock or the master clock divided by 8, configured +* through the mode register. +* +* Accompanied with the baud rate divider register, the baud rate is determined +* by: +* 
+*	baud_rate = input_clock / (bgen * (bdiv + 1)
+*
+* where bgen is the value of the baud rate generator, and bdiv is the value of +* baud rate divider. +* +* Interrupts +* +* The FIFOs are not flushed when the driver is initialized, but a function is +* provided to allow the user to reset the FIFOs if desired. +* +* The driver defaults to no interrupts at initialization such that interrupts +* must be enabled if desired. An interrupt is generated for one of the +* following conditions. +* +* - A change in the modem signals +* - Data in the receive FIFO for a configuable time without receiver activity +* - A parity error +* - A framing error +* - An overrun error +* - Transmit FIFO is full +* - Transmit FIFO is empty +* - Receive FIFO is full +* - Receive FIFO is empty +* - Data in the receive FIFO equal to the receive threshold +* +* The application can control which interrupts are enabled using the +* XUartPs_SetInterruptMask() function. +* +* In order to use interrupts, it is necessary for the user to connect the +* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt +* system of the application. A separate handler should be provided by the +* application to communicate with the interrupt system, and conduct +* application specific interrupt handling. An application registers its own +* handler through the XUartPs_SetHandler() function. +* +* Data Transfer +* +* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the +* driver to allow data to be sent and received. They can be used in either +* polled or interrupt mode. +* +* @note +* +* The default configuration for the UART after initialization is: +* +* - 9,600 bps or XPAR_DFT_BAUDRATE if defined +* - 8 data bits +* - 1 stop bit +* - no parity +* - FIFO's are enabled with a receive threshold of 8 bytes +* - The RX timeout is enabled with a timeout of 1 (4 char times) +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+*
+*
+* +*****************************************************************************/ + +#ifndef XUARTPS_H /* prevent circular inclusions */ +#define XUARTPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xuartps_hw.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constants indicate the max and min baud rates and these + * numbers are based only on the testing that has been done. The hardware + * is capable of other baud rates. + */ +#define XUARTPS_MAX_RATE 921600U +#define XUARTPS_MIN_RATE 110U + +#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */ + +/** @name Configuration options + * @{ + */ +/** + * These constants specify the options that may be set or retrieved + * with the driver, each is a unique bit mask such that multiple options + * may be specified. These constants indicate the available options + * in active state. + * + */ + +#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */ +#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */ +#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */ +#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */ +#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */ +#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */ +#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */ +#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */ +/*@}*/ + + +/** @name Channel Operational Mode + * + * The UART can operate in one of four modes: Normal, Local Loopback, Remote + * Loopback, or automatic echo. + * + * @{ + */ + +#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */ +#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */ +#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */ +#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */ + +/* @} */ + +/** @name Data format values + * + * These constants specify the data format that the driver supports. + * The data format includes the number of data bits, the number of stop + * bits and parity. + * + * @{ + */ +#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */ +#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */ +#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */ + +#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */ +#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */ +#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */ +#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */ +#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */ + +#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */ +#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */ +#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */ +/*@}*/ + +/** @name Callback events + * + * These constants specify the handler events that an application can handle + * using its specific handler function. Note that these constants are not bit + * mask, so only one event can be passed to an application at a time. + * + * @{ + */ +#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */ +#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */ +#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */ +#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */ +#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */ +/*@}*/ + + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ + u32 InputClockHz;/**< Input clock frequency */ + s32 ModemPinsConnected; /** Specifies whether modem pins are connected + * to MIO or FMIO */ +} XUartPs_Config; + +/* + * Keep track of state information about a data buffer in the interrupt mode. + */ +typedef struct { + u8 *NextBytePtr; + u32 RequestedBytes; + u32 RemainingBytes; +} XUartPsBuffer; + +/** + * Keep track of data format setting of a device. + */ +typedef struct { + u32 BaudRate; /**< In bps, ie 1200 */ + u32 DataBits; /**< Number of data bits */ + u32 Parity; /**< Parity */ + u8 StopBits; /**< Number of stop bits */ +} XUartPsFormat; + +/******************************************************************************/ +/** + * This data type defines a handler that an application defines to communicate + * with interrupt system to retrieve state information about an application. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the handler, and is passed back to the upper layer + * when the handler is called. It is used to find the device driver + * instance. + * @param Event contains one of the event constants indicating events that + * have occurred. + * @param EventData contains the number of bytes sent or received at the + * time of the call for send and receive events and contains the + * modem status for modem events. + * + ******************************************************************************/ +typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event, + u32 EventData); + +/** + * The XUartPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XUartPs_Config Config; /* Configuration data structure */ + u32 InputClockHz; /* Input clock frequency */ + u32 IsReady; /* Device is initialized and ready */ + u32 BaudRate; /* Current baud rate */ + + XUartPsBuffer SendBuffer; + XUartPsBuffer ReceiveBuffer; + + XUartPs_Handler Handler; + void *CallBackRef; /* Callback reference for event handler */ +} XUartPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Get the UART Channel Status Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetChannelStatus(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) + +/****************************************************************************/ +/** +* Get the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_GetControl(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetModeControl(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET) + +/****************************************************************************/ +/** +* Set the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \ + (u32)(RegisterValue)) + +/****************************************************************************/ +/** +* Enable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_EnableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_EnableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \ + ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \ + (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN))) + +/****************************************************************************/ +/** +* Disable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_DisableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_DisableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \ + (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \ + (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS))) + +/****************************************************************************/ +/** +* Determine if the transmitter FIFO is empty. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return +* - TRUE if a byte can be sent +* - FALSE if the Transmitter Fifo is not empty +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr) +* +******************************************************************************/ +#define XUartPs_IsTransmitEmpty(InstancePtr) \ + ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY) + + +/************************** Function Prototypes *****************************/ + +/* + * Static lookup function implemented in xuartps_sinit.c + */ +XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId); + +/* + * Interface functions implemented in xuartps.c + */ +s32 XUartPs_CfgInitialize(XUartPs *InstancePtr, + XUartPs_Config * Config, u32 EffectiveAddr); + +u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr, + u32 NumBytes); + +u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr, + u32 NumBytes); + +s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate); + +/* + * Options functions in xuartps_options.c + */ +void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options); + +u16 XUartPs_GetOptions(XUartPs *InstancePtr); + +void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel); + +u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr); + +u16 XUartPs_GetModemStatus(XUartPs *InstancePtr); + +u32 XUartPs_IsSending(XUartPs *InstancePtr); + +u8 XUartPs_GetOperMode(XUartPs *InstancePtr); + +void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode); + +u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr); + +void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue); + +u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr); + +void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout); + +s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr); + +void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr); + +/* + * interrupt functions in xuartps_intr.c + */ +u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr); + +void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask); + +void XUartPs_InterruptHandler(XUartPs *InstancePtr); + +void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr, + void *CallBackRef); + +/* + * self-test functions in xuartps_selftest.c + */ +s32 XUartPs_SelfTest(XUartPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xuartps_hw.h new file mode 100644 index 000000000..a47629dae --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xuartps_hw.h @@ -0,0 +1,424 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xuartps_hw.h +* +* This header file contains the hardware interface of an XUartPs device. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+* +******************************************************************************/ +#ifndef XUARTPS_HW_H /* prevent circular inclusions */ +#define XUARTPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the UART. + * @{ + */ +#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */ +#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */ +#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */ +#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */ +#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */ +#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/ +#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */ +#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */ +#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */ +#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */ +#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */ +#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */ +#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */ +#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */ +#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */ +#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */ +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */ +#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */ +#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */ +#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */ +#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */ +#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */ +#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */ +#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */ +#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */ +#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */ +/* @}*/ + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ +#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */ +#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */ +#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */ +#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */ +#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */ +#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */ +#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */ +#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */ +#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */ +#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */ +#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */ +#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */ +#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */ +#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */ +#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */ +#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */ +#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */ +#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */ +#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */ +#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */ +#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */ +#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */ +#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */ +#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */ +#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */ +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ +#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */ +#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */ +#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */ +#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */ +#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */ +#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */ +#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */ +#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */ +#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */ +#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */ +#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */ +#define XUARTPS_IXR_MASK 0x00001FFFU /**< Valid bit mask */ +/* @} */ + + +/** @name Baud Rate Generator Register + * + * The baud rate generator control register (BRGR) is a 16 bit register that + * controls the receiver bit sample clock and baud rate. + * Valid values are 1 - 65535. + * + * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit + * in the MR register. + * @{ + */ +#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */ +#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */ +#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */ + +/** @name Baud Divisor Rate register + * + * The baud rate divider register (BDIV) controls how much the bit sample + * rate is divided by. It sets the baud rate. + * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. + * + * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by + * the MR_CCLK bit in the MR register. + * @{ + */ +#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */ +#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */ +/* @} */ + + +/** @name Receiver Timeout Register + * + * Use the receiver timeout register (RTR) to detect an idle condition on + * the receiver data line. + * + * @{ + */ +#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */ +#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */ + +/** @name Receiver FIFO Trigger Level Register + * + * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at + * which the RX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */ +#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Transmit FIFO Trigger Level Register + * + * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at + * which the TX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Modem Control Register + * + * This register (MODEMCR) controls the interface with the modem or data set, + * or a peripheral device emulating a modem. + * + * @{ + */ +#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */ +#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */ +#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */ +/* @} */ + +/** @name Modem Status Register + * + * This register (MODEMSR) indicates the current state of the control lines + * from a modem, or another peripheral device, to the CPU. In addition, four + * bits of the modem status register provide change information. These bits + * are set to a logic 1 whenever a control input from the modem changes state. + * + * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem + * status interrupt is generated and this is reflected in the modem status + * register. + * + * @{ + */ +#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */ +#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */ +#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */ +#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */ +#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */ +#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */ +#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */ +#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */ +#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */ +/* @} */ + +/** @name Channel Status Register + * + * The channel status register (CSR) is provided to enable the control logic + * to monitor the status of bits in the channel interrupt status register, + * even if these are masked out by the interrupt mask register. + * + * @{ + */ +#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */ +#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */ +#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */ +#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */ +#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */ +#define XUARTPS_SR_DMS 0x00000200U /**< Delta modem status change */ +#define XUARTPS_SR_TOUT 0x00000100U /**< RX timeout */ +#define XUARTPS_SR_PARITY 0x00000080U /**< RX parity error */ +#define XUARTPS_SR_FRAME 0x00000040U /**< RX frame error */ +#define XUARTPS_SR_OVER 0x00000020U /**< RX overflow error */ +#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */ +#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */ +#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */ +#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */ +#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */ +/* @} */ + +/** @name Flow Delay Register + * + * Operation of the flow delay register (FLOWDEL) is very similar to the + * receive FIFO trigger register. An internal trigger signal activates when the + * FIFO is filled to the level set by this register. This trigger will not + * cause an interrupt, although it can be read through the channel status + * register. In hardware flow control mode, RTS is deactivated when the trigger + * becomes active. RTS only resets when the FIFO level is four less than the + * level of the flow delay trigger and the flow delay trigger is not activated. + * A value less than 4 disables the flow delay. + * @{ + */ +#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */ +/* @} */ + + + +/* + * Defines for backwards compatabilty, will be removed + * in the next version of the driver + */ +#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD +#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI +#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR +#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS + + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* Read a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset) +* +******************************************************************************/ +#define XUartPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (u32)(RegOffset)) + +/***************************************************************************/ +/** +* Write a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue)) + +/****************************************************************************/ +/** +* Determine if there is receive data in the receiver and/or FIFO. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if there is receive data, FALSE otherwise. +* +* @note C-Style signature: +* u32 XUartPs_IsReceiveData(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsReceiveData(BaseAddress) \ + !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY) + +/****************************************************************************/ +/** +* Determine if a byte of data can be sent with the transmitter. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the +* FIFO. +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitFull(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsTransmitFull(BaseAddress) \ + ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL) + +/************************** Function Prototypes ******************************/ + +void XUartPs_SendByte(u32 BaseAddress, u8 Data); + +u8 XUartPs_RecvByte(u32 BaseAddress); + +void XUartPs_ResetHw(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xusbpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xusbpsu.h new file mode 100644 index 000000000..a7ad3d7e7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xusbpsu.h @@ -0,0 +1,569 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xusbpsu.h +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    01/22/15 First release
+* 1.00a bss    03/18/15 Added support for Non-control endpoints
+*						Added mass storage example
+*
+*
+* +*****************************************************************************/ +#ifndef XUSBPSU_H /* Prevent circular inclusions */ +#define XUSBPSU_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ +#include "xparameters.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xusbpsu_hw.h" + +/************************** Constant Definitions ****************************/ + +#define ALIGNMENT_CACHELINE __attribute__ ((aligned(64))) + +#define XUSBPSU_PHY_TIMEOUT 5000 /* in micro seconds */ + +#define XUSBPSU_EP_DIR_IN 1 +#define XUSBPSU_EP_DIR_OUT 0 + +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 +#define USB_ENDPOINT_MAX_ADJUSTABLE 0x80 + +#define TEST_J 1 +#define TEST_K 2 +#define TEST_SE0_NAK 3 +#define TEST_PACKET 4 +#define TEST_FORCE_ENABLE 5 + +#define XUSBPSU_NUM_TRBS 8 + +#define XUSBPSU_EVENT_PENDING (1 << 0) + +#define XUSBPSU_EP_ENABLED (1 << 0) +#define XUSBPSU_EP_STALL (1 << 1) +#define XUSBPSU_EP_WEDGE (1 << 2) +#define XUSBPSU_EP_BUSY (1 << 4) +#define XUSBPSU_EP_PENDING_REQUEST (1 << 5) +#define XUSBPSU_EP_MISSED_ISOC (1 << 6) + +#define XUSBPSU_GHWPARAMS0 0 +#define XUSBPSU_GHWPARAMS1 1 +#define XUSBPSU_GHWPARAMS2 2 +#define XUSBPSU_GHWPARAMS3 3 +#define XUSBPSU_GHWPARAMS4 4 +#define XUSBPSU_GHWPARAMS5 5 +#define XUSBPSU_GHWPARAMS6 6 +#define XUSBPSU_GHWPARAMS7 7 + +/* HWPARAMS0 */ +#define XUSBPSU_MODE(n) ((n) & 0x7) +#define XUSBPSU_MDWIDTH(n) (((n) & 0xff00) >> 8) + +/* HWPARAMS1 */ +#define XUSBPSU_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) + +/* HWPARAMS3 */ +#define XUSBPSU_NUM_IN_EPS_MASK (0x1f << 18) +#define XUSBPSU_NUM_EPS_MASK (0x3f << 12) +#define XUSBPSU_NUM_EPS(p) (((p) & \ + (XUSBPSU_NUM_EPS_MASK)) >> 12) +#define XUSBPSU_NUM_IN_EPS(p) (((p) & \ + (XUSBPSU_NUM_IN_EPS_MASK)) >> 18) + +/* HWPARAMS7 */ +#define XUSBPSU_RAM1_DEPTH(n) ((n) & 0xffff) + +#define XUSBPSU_DEPEVT_XFERCOMPLETE 0x01 +#define XUSBPSU_DEPEVT_XFERINPROGRESS 0x02 +#define XUSBPSU_DEPEVT_XFERNOTREADY 0x03 +#define XUSBPSU_DEPEVT_STREAMEVT 0x06 +#define XUSBPSU_DEPEVT_EPCMDCMPLT 0x07 + +/* Within XferNotReady */ +#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) + +/* Within XferComplete */ +#define DEPEVT_STATUS_BUSERR (1 << 0) +#define DEPEVT_STATUS_SHORT (1 << 1) +#define DEPEVT_STATUS_IOC (1 << 2) +#define DEPEVT_STATUS_LST (1 << 3) + +/* Stream event only */ +#define DEPEVT_STREAMEVT_FOUND 1 +#define DEPEVT_STREAMEVT_NOTFOUND 2 + +/* Control-only Status */ +#define DEPEVT_STATUS_CONTROL_DATA 1 +#define DEPEVT_STATUS_CONTROL_STATUS 2 +#define DEPEVT_STATUS_CONTROL_DATA_INVALTRB 9 +#define DEPEVT_STATUS_CONTROL_STATUS_INVALTRB 0xA + +#define XUSBPSU_ENDPOINTS_NUM 12 + +#define XUSBPSU_EVENT_SIZE 4 /* bytes */ +#define XUSBPSU_EVENT_MAX_NUM 64 /* 2 events/endpoint */ +#define XUSBPSU_EVENT_BUFFERS_SIZE (XUSBPSU_EVENT_SIZE * \ + XUSBPSU_EVENT_MAX_NUM) + +#define XUSBPSU_EVENT_TYPE_MASK 0xfe + +#define XUSBPSU_EVENT_TYPE_DEV 0 +#define XUSBPSU_EVENT_TYPE_CARKIT 3 +#define XUSBPSU_EVENT_TYPE_I2C 4 + +#define XUSBPSU_DEVICE_EVENT_DISCONNECT 0 +#define XUSBPSU_DEVICE_EVENT_RESET 1 +#define XUSBPSU_DEVICE_EVENT_CONNECT_DONE 2 +#define XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE 3 +#define XUSBPSU_DEVICE_EVENT_WAKEUP 4 +#define XUSBPSU_DEVICE_EVENT_HIBER_REQ 5 +#define XUSBPSU_DEVICE_EVENT_EOPF 6 +#define XUSBPSU_DEVICE_EVENT_SOF 7 +#define XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR 9 +#define XUSBPSU_DEVICE_EVENT_CMD_CMPL 10 +#define XUSBPSU_DEVICE_EVENT_OVERFLOW 11 + +#define XUSBPSU_GEVNTCOUNT_MASK 0xfffc + +/* + * Control Endpoint state + */ +#define XUSBPSU_EP0_SETUP_PHASE 1 /**< Setup Phase */ +#define XUSBPSU_EP0_DATA_PHASE 2 /**< Data Phase */ +#define XUSBPSU_EP0_STATUS_PHASE 3 /**< Status Pahse */ + +/* + * Link State + */ +#define XUSBPSU_LINK_STATE_U0 0x00 /**< in HS - ON */ +#define XUSBPSU_LINK_STATE_U1 0x01 +#define XUSBPSU_LINK_STATE_U2 0x02 /**< in HS - SLEEP */ +#define XUSBPSU_LINK_STATE_U3 0x03 /**< in HS - SUSPEND */ +#define XUSBPSU_LINK_STATE_SS_DIS 0x04 +#define XUSBPSU_LINK_STATE_RX_DET 0x05 +#define XUSBPSU_LINK_STATE_SS_INACT 0x06 +#define XUSBPSU_LINK_STATE_POLL 0x07 +#define XUSBPSU_LINK_STATE_RECOV 0x08 +#define XUSBPSU_LINK_STATE_HRESET 0x09 +#define XUSBPSU_LINK_STATE_CMPLY 0x0A +#define XUSBPSU_LINK_STATE_LPBK 0x0B +#define XUSBPSU_LINK_STATE_RESET 0x0E +#define XUSBPSU_LINK_STATE_RESUME 0x0F +#define XUSBPSU_LINK_STATE_MASK 0x0F + +/* + * Device States + */ +#define XUSBPSU_STATE_ATTACHED 0 +#define XUSBPSU_STATE_POWERED 1 +#define XUSBPSU_STATE_DEFAULT 2 +#define XUSBPSU_STATE_ADDRESS 3 +#define XUSBPSU_STATE_CONFIGURED 4 +#define XUSBPSU_STATE_SUSPENDED 5 + +/* + * Device Speeds + */ +#define XUSBPSU_SPEED_UNKNOWN 0 +#define XUSBPSU_SPEED_LOW 1 +#define XUSBPSU_SPEED_FULL 2 +#define XUSBPSU_SPEED_HIGH 3 +#define XUSBPSU_SPEED_SUPER 4 + + + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the XUSBPSU + * device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of controller */ + u32 BaseAddress; /**< Core register base address */ +} XUsbPsu_Config; + +/** + * Software Event buffer representation + */ +struct XUsbPsu_EvtBuffer { + void *BuffAddr; + u32 Offset; + u32 Count; + u32 Flags; +}; + +/** + * Transfer Request Block - Hardware format + */ +struct XUsbPsu_Trb { + u32 BufferPtrLow; + u32 BufferPtrHigh; + u32 Size; + u32 Ctrl; +} __attribute__((packed)); + + +/* + * Endpoint Parameters + */ +struct XUsbPsu_EpParams { + u32 Param2; /**< Parameter 2 */ + u32 Param1; /**< Parameter 1 */ + u32 Param0; /**< Parameter 0 */ +}; + +/** + * USB Standard Control Request + */ +typedef struct { + u8 bRequestType; + u8 bRequest; + u16 wValue; + u16 wIndex; + u16 wLength; +} __attribute__ ((packed)) SetupPacket; + +/** + * Endpoint representation + */ +struct XUsbPsu_Ep { + void (*Handler)(void *, u32, u32); + /** < User handler called + * when data is sent for IN Ep + * and received for OUT Ep + */ + struct XUsbPsu_Trb EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */ + u32 EpStatus; /**< Flags to represent Endpoint status */ + u32 RequestedBytes; /**< RequestedBytes for transfer */ + u32 BytesTxed; /**< Actual Bytes transferred */ + u32 Cmd; /**< command issued to EP lately */ + u16 MaxSize; /**< Size of endpoint */ + u8 *BufferPtr; /**< Buffer location */ + u8 ResourceIndex; /**< Resource Index assigned to + * Endpoint by core + */ + u8 PhyEpNum; /**< Physical Endpoint Number in core */ + u8 UsbEpNum; /**< USB Endpoint Number */ + u8 Type; /**< Type of Endpoint - + * Control/BULK/INTERRUPT/ISOC + */ + u8 Direction; /**< Direction - EP_DIR_OUT/EP_DIR_IN */ + u8 UnalignedTx; +}; + +/** + * USB Device Controller representation + */ +struct XUsbPsu { + SetupPacket SetupData ALIGNMENT_CACHELINE; + /**< Setup Packet buffer */ + struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE; + /**< TRB for control transfers */ + XUsbPsu_Config *ConfigPtr; /**< Configuration info pointer */ + struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */ + struct XUsbPsu_EvtBuffer Evt; + struct XUsbPsu_EpParams EpParams; + u32 BaseAddress; /**< Core register base address */ + u32 MaxSpeed; + u32 DevDescSize; + u32 ConfigDescSize; + void (*Chapter9)(struct XUsbPsu *, SetupPacket *); + void (*ClassHandler)(struct XUsbPsu *, SetupPacket *); + void *DevDesc; + void *ConfigDesc; + u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE] + __attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE))); + u8 NumOutEps; + u8 NumInEps; + u8 ControlDir; + u8 IsInTestMode; + u8 TestMode; + u8 Speed; + u8 State; + u8 Ep0State; + u8 LinkState; + u8 UnalignedTx; + u8 IsConfigDone; + u8 IsThreeStage; +}; + +struct XUsbPsu_Event_Type { + u32 Is_DevEvt:1; + u32 Type:7; + u32 Reserved8_31:24; +} __attribute__((packed)); + +/** + * struct XUsbPsu_event_depvt - Device Endpoint Events + * @Is_EpEvt: indicates this is an endpoint event + * @endpoint_number: number of the endpoint + * @endpoint_event: The event we have: + * 0x00 - Reserved + * 0x01 - XferComplete + * 0x02 - XferInProgress + * 0x03 - XferNotReady + * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) + * 0x05 - Reserved + * 0x06 - StreamEvt + * 0x07 - EPCmdCmplt + * @Reserved11_10: Reserved, don't use. + * @Status: Indicates the status of the event. Refer to databook for + * more information. + * @Parameters: Parameters of the current event. Refer to databook for + * more information. + */ +struct XUsbPsu_Event_Epevt { + u32 Is_EpEvt:1; + u32 Epnumber:5; + u32 Endpoint_Event:4; + u32 Reserved11_10:2; + u32 Status:4; + u32 Parameters:16; +} __attribute__((packed)); + +/** + * struct XUsbPsu_event_devt - Device Events + * @Is_DevEvt: indicates this is a non-endpoint event + * @Device_Event: indicates it's a device event. Should read as 0x00 + * @Type: indicates the type of device event. + * 0 - DisconnEvt + * 1 - USBRst + * 2 - ConnectDone + * 3 - ULStChng + * 4 - WkUpEvt + * 5 - Reserved + * 6 - EOPF + * 7 - SOF + * 8 - Reserved + * 9 - ErrticErr + * 10 - CmdCmplt + * 11 - EvntOverflow + * 12 - VndrDevTstRcved + * @Reserved15_12: Reserved, not used + * @Event_Info: Information about this event + * @Reserved31_25: Reserved, not used + */ +struct XUsbPsu_Event_Devt { + u32 Is_DevEvt:1; + u32 Device_Event:7; + u32 Type:4; + u32 Reserved15_12:4; + u32 Event_Info:9; + u32 Reserved31_25:7; +} __attribute__((packed)); + +/** + * struct XUsbPsu_event_gevt - Other Core Events + * @one_bit: indicates this is a non-endpoint event (not used) + * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. + * @phy_port_number: self-explanatory + * @reserved31_12: Reserved, not used. + */ +struct XUsbPsu_Event_Gevt { + u32 Is_GlobalEvt:1; + u32 Device_Event:7; + u32 Phy_Port_Number:4; + u32 Reserved31_12:20; +} __attribute__((packed)); + +/** + * union XUsbPsu_event - representation of Event Buffer contents + * @raw: raw 32-bit event + * @type: the type of the event + * @depevt: Device Endpoint Event + * @devt: Device Event + * @gevt: Global Event + */ +union XUsbPsu_Event { + u32 Raw; + struct XUsbPsu_Event_Type Type; + struct XUsbPsu_Event_Epevt Epevt; + struct XUsbPsu_Event_Devt Devt; + struct XUsbPsu_Event_Gevt Gevt; +}; + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + +#define roundup(x, y) ( \ +{ \ + const typeof(y) __y = y; \ + (((x) + (__y - 1)) / __y) * __y; \ +} \ +) + +#define DECLARE_DEV_DESC(Instance, desc) \ + (Instance).DevDesc = &(desc); \ + (Instance).DevDescSize = sizeof((desc)) + +#define DECLARE_CONFIG_DESC(Instance, desc) \ + (Instance).ConfigDesc = &(desc); \ + (Instance).ConfigDescSize = sizeof((desc)) + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xusbpsu.c + */ +int XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset, + u32 BitMask, u32 Timeout); +int XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset, + u32 BitMask, u32 Timeout); +void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 mode); +void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr); +void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr); +void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr); +void XUsbPsu_CoreNumEps(struct XUsbPsu *InstancePtr); +void XUsbPsu_cache_hwparams(struct XUsbPsu *InstancePtr); +int XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr); +void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask); +void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask); +int XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr, + XUsbPsu_Config *ConfigPtr, u32 BaseAddress); +int XUsbPsu_Start(struct XUsbPsu *InstancePtr); +int XUsbPsu_Stop(struct XUsbPsu *InstancePtr); +int XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, int mode); +u32 XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr); +int XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr, + u8 state); +int XUsbPsu_SendGenericCmd(struct XUsbPsu *InstancePtr, + int cmd, u32 param); +void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed); +int XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr); + +/* + * Functions in xusbpsu_endpoint.c + */ +struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr); +u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum, + u8 dir); +const char *XUsbPsu_EpCmdString(u8 cmd); +int XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 ep, u8 direction, + u32 cmd, struct XUsbPsu_EpParams *params); +int XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 ep, + u8 dir); +int XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 ep, u8 dir, + u16 size, u8 type); +int XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 ep, u8 dir); +int XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 dir, + u16 maxsize, u8 type); +int XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 dir); +int XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 size); +void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr); +void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 ep, u8 dir); +void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr); +int XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 EpNum, + u8 *BufferPtr, u32 BufferLen); +int XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 EpNum, + u8 *BufferPtr, u32 length); +void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 epnum, u8 Dir); +void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 epnum, u8 Dir); +void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 epnum, + u8 dir, void (*Handler)(void *, u32, u32)); +int XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir); + +/* + * Functions in xusbpsu_controltransfers.c + */ +int XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr); +void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr); +int XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr, + SetupPacket *ctrl); +void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *event); +void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *event); +void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *event); +int XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *event); +void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr, + struct XUsbPsu_Ep *dep); +void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *event); +void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *event); +int XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, + u32 BufferLen); +int XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length); + +/* + * Functions in xusbpsu_intr.c + */ +void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *event); +void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr); +void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr); +void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr); +void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr, + u32 evtinfo); +void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Devt *event); +void XUsbPsu_ProcessEvent(struct XUsbPsu *InstancePtr, + const union XUsbPsu_Event *event); +void XUsbPsu_ProcessEvtBuffer(struct XUsbPsu *InstancePtr); +void XUsbPsu_IntrHandler(void *XUsbPsu); + +/* + * Functions in xusbpsu_sinit.c + */ +XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xusbpsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xusbpsu_hw.h new file mode 100644 index 000000000..cd5cd33ec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xusbpsu_hw.h @@ -0,0 +1,457 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xusbpsu_hw.h +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    01/22/15 First release
+*
+*
+* +*****************************************************************************/ + +#ifndef XUSBPSU_HW_H /* Prevent circular inclusions */ +#define XUSBPSU_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +/************************** Constant Definitions ****************************/ + +/**@name Register offsets + * + * The following constants provide access to each of the registers of the + * USBPSU device. + * @{ + */ + +/* XUSBPSU registers memory space boundries */ +#define XUSBPSU_GLOBALS_REGS_START 0xc100 +#define XUSBPSU_GLOBALS_REGS_END 0xc6ff +#define XUSBPSU_DEVICE_REGS_START 0xc700 +#define XUSBPSU_DEVICE_REGS_END 0xcbff +#define XUSBPSU_OTG_REGS_START 0xcc00 +#define XUSBPSU_OTG_REGS_END 0xccff + +/* Global Registers */ +#define XUSBPSU_GSBUSCFG0 0xc100 +#define XUSBPSU_GSBUSCFG1 0xc104 +#define XUSBPSU_GTXTHRCFG 0xc108 +#define XUSBPSU_GRXTHRCFG 0xc10c +#define XUSBPSU_GCTL 0xc110 +#define XUSBPSU_GEVTEN 0xc114 +#define XUSBPSU_GSTS 0xc118 +#define XUSBPSU_GSNPSID 0xc120 +#define XUSBPSU_GGPIO 0xc124 +#define XUSBPSU_GUID 0xc128 +#define XUSBPSU_GUCTL 0xc12c +#define XUSBPSU_GBUSERRADDR0 0xc130 +#define XUSBPSU_GBUSERRADDR1 0xc134 +#define XUSBPSU_GPRTBIMAP0 0xc138 +#define XUSBPSU_GPRTBIMAP1 0xc13c +#define XUSBPSU_GHWPARAMS0_OFFSET 0xc140 +#define XUSBPSU_GHWPARAMS1_OFFSET 0xc144 +#define XUSBPSU_GHWPARAMS2_OFFSET 0xc148 +#define XUSBPSU_GHWPARAMS3_OFFSET 0xc14c +#define XUSBPSU_GHWPARAMS4_OFFSET 0xc150 +#define XUSBPSU_GHWPARAMS5_OFFSET 0xc154 +#define XUSBPSU_GHWPARAMS6_OFFSET 0xc158 +#define XUSBPSU_GHWPARAMS7_OFFSET 0xc15c +#define XUSBPSU_GDBGFIFOSPACE 0xc160 +#define XUSBPSU_GDBGLTSSM 0xc164 +#define XUSBPSU_GPRTBIMAP_HS0 0xc180 +#define XUSBPSU_GPRTBIMAP_HS1 0xc184 +#define XUSBPSU_GPRTBIMAP_FS0 0xc188 +#define XUSBPSU_GPRTBIMAP_FS1 0xc18c + +#define XUSBPSU_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) +#define XUSBPSU_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) + +#define XUSBPSU_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) + +#define XUSBPSU_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) + +#define XUSBPSU_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) +#define XUSBPSU_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) + +#define XUSBPSU_GEVNTADRLO(n) (0xc400 + (n * 0x10)) +#define XUSBPSU_GEVNTADRHI(n) (0xc404 + (n * 0x10)) +#define XUSBPSU_GEVNTSIZ(n) (0xc408 + (n * 0x10)) +#define XUSBPSU_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) + +#define XUSBPSU_GHWPARAMS8 0xc600 + +/* Device Registers */ +#define XUSBPSU_DCFG 0xc700 +#define XUSBPSU_DCTL 0xc704 +#define XUSBPSU_DEVTEN 0xc708 +#define XUSBPSU_DSTS 0xc70c +#define XUSBPSU_DGCMDPAR 0xc710 +#define XUSBPSU_DGCMD 0xc714 +#define XUSBPSU_DALEPENA 0xc720 +#define XUSBPSU_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) +#define XUSBPSU_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) +#define XUSBPSU_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) +#define XUSBPSU_DEPCMD(n) (0xc80c + (n * 0x10)) + +/* OTG Registers */ +#define XUSBPSU_OCFG 0xcc00 +#define XUSBPSU_OCTL 0xcc04 +#define XUSBPSU_OEVT 0xcc08 +#define XUSBPSU_OEVTEN 0xcc0C +#define XUSBPSU_OSTS 0xcc10 + +/* Bit fields */ + +/* Global Configuration Register */ +#define XUSBPSU_GCTL_PWRDNSCALE(n) ((n) << 19) +#define XUSBPSU_GCTL_U2RSTECN (1 << 16) +#define XUSBPSU_GCTL_RAMCLKSEL(x) (((x) & XUSBPSU_GCTL_CLK_MASK) << 6) +#define XUSBPSU_GCTL_CLK_BUS (0) +#define XUSBPSU_GCTL_CLK_PIPE (1) +#define XUSBPSU_GCTL_CLK_PIPEHALF (2) +#define XUSBPSU_GCTL_CLK_MASK (3) + +#define XUSBPSU_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) +#define XUSBPSU_GCTL_PRTCAPDIR(n) ((n) << 12) +#define XUSBPSU_GCTL_PRTCAP_HOST 1 +#define XUSBPSU_GCTL_PRTCAP_DEVICE 2 +#define XUSBPSU_GCTL_PRTCAP_OTG 3 + +#define XUSBPSU_GCTL_CORESOFTRESET (1 << 11) +#define XUSBPSU_GCTL_SOFITPSYNC (1 << 10) +#define XUSBPSU_GCTL_SCALEDOWN(n) ((n) << 4) +#define XUSBPSU_GCTL_SCALEDOWN_MASK XUSBPSU_GCTL_SCALEDOWN(3) +#define XUSBPSU_GCTL_DISSCRAMBLE (1 << 3) +#define XUSBPSU_GCTL_GBLHIBERNATIONEN (1 << 1) +#define XUSBPSU_GCTL_DSBLCLKGTNG (1 << 0) + +/* Global Status Register Device Interrupt Mask */ +#define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040 + +/* Global USB2 PHY Configuration Register */ +#define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define XUSBPSU_GUSB2PHYCFG_SUSPHY (1 << 6) + +/* Global USB3 PIPE Control Register */ +#define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST (1 << 31) +#define XUSBPSU_GUSB3PIPECTL_SUSPHY (1 << 17) + +/* Global TX Fifo Size Register */ +#define XUSBPSU_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) +#define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) + +/* Global Event Size Registers */ +#define XUSBPSU_GEVNTSIZ_INTMASK (1 << 31) +#define XUSBPSU_GEVNTSIZ_SIZE(n) ((n) & 0xffff) + +/* Global HWPARAMS1 Register */ +#define XUSBPSU_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) +#define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO 0 +#define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK 1 +#define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB 2 +#define XUSBPSU_GHWPARAMS1_PWROPT(n) ((n) << 24) +#define XUSBPSU_GHWPARAMS1_PWROPT_MASK XUSBPSU_GHWPARAMS1_PWROPT(3) + +/* Global HWPARAMS4 Register */ +#define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) +#define XUSBPSU_MAX_HIBER_SCRATCHBUFS 15 + +/* Device Configuration Register */ +#define XUSBPSU_DCFG_DEVADDR(addr) ((addr) << 3) +#define XUSBPSU_DCFG_DEVADDR_MASK XUSBPSU_DCFG_DEVADDR(0x7f) + +#define XUSBPSU_DCFG_SPEED_MASK 7 +#define XUSBPSU_DCFG_SUPERSPEED 4 +#define XUSBPSU_DCFG_HIGHSPEED 0 +#define XUSBPSU_DCFG_FULLSPEED2 1 +#define XUSBPSU_DCFG_LOWSPEED 2 +#define XUSBPSU_DCFG_FULLSPEED1 3 + +#define XUSBPSU_DCFG_LPM_CAP (1 << 22) + +/* Device Control Register */ +#define XUSBPSU_DCTL_RUN_STOP (1 << 31) +#define XUSBPSU_DCTL_CSFTRST (1 << 30) +#define XUSBPSU_DCTL_LSFTRST (1 << 29) + +#define XUSBPSU_DCTL_HIRD_THRES_MASK (0x1f << 24) +#define XUSBPSU_DCTL_HIRD_THRES(n) ((n) << 24) + +#define XUSBPSU_DCTL_APPL1RES (1 << 23) + +/* These apply for core versions 1.87a and earlier */ +#define XUSBPSU_DCTL_TRGTULST_MASK (0x0f << 17) +#define XUSBPSU_DCTL_TRGTULST(n) ((n) << 17) +#define XUSBPSU_DCTL_TRGTULST_U2 (XUSBPSU_DCTL_TRGTULST(2)) +#define XUSBPSU_DCTL_TRGTULST_U3 (XUSBPSU_DCTL_TRGTULST(3)) +#define XUSBPSU_DCTL_TRGTULST_SS_DIS (XUSBPSU_DCTL_TRGTULST(4)) +#define XUSBPSU_DCTL_TRGTULST_RX_DET (XUSBPSU_DCTL_TRGTULST(5)) +#define XUSBPSU_DCTL_TRGTULST_SS_INACT (XUSBPSU_DCTL_TRGTULST(6)) + +/* These apply for core versions 1.94a and later */ +#define XUSBPSU_DCTL_KEEP_CONNECT (1 << 19) +#define XUSBPSU_DCTL_L1_HIBER_EN (1 << 18) +#define XUSBPSU_DCTL_CRS (1 << 17) +#define XUSBPSU_DCTL_CSS (1 << 16) + +#define XUSBPSU_DCTL_INITU2ENA (1 << 12) +#define XUSBPSU_DCTL_ACCEPTU2ENA (1 << 11) +#define XUSBPSU_DCTL_INITU1ENA (1 << 10) +#define XUSBPSU_DCTL_ACCEPTU1ENA (1 << 9) +#define XUSBPSU_DCTL_TSTCTRL_MASK (0xf << 1) + +#define XUSBPSU_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) +#define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK) + +#define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION (XUSBPSU_DCTL_ULSTCHNGREQ(0)) +#define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED (XUSBPSU_DCTL_ULSTCHNGREQ(4)) +#define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT (XUSBPSU_DCTL_ULSTCHNGREQ(5)) +#define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE (XUSBPSU_DCTL_ULSTCHNGREQ(6)) +#define XUSBPSU_DCTL_ULSTCHNG_RECOVERY (XUSBPSU_DCTL_ULSTCHNGREQ(8)) +#define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE (XUSBPSU_DCTL_ULSTCHNGREQ(10)) +#define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK (XUSBPSU_DCTL_ULSTCHNGREQ(11)) + +/* Device Event Enable Register */ +#define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) +#define XUSBPSU_DEVTEN_EVNTOVERFLOWEN (1 << 11) +#define XUSBPSU_DEVTEN_CMDCMPLTEN (1 << 10) +#define XUSBPSU_DEVTEN_ERRTICERREN (1 << 9) +#define XUSBPSU_DEVTEN_SOFEN (1 << 7) +#define XUSBPSU_DEVTEN_EOPFEN (1 << 6) +#define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) +#define XUSBPSU_DEVTEN_WKUPEVTEN (1 << 4) +#define XUSBPSU_DEVTEN_ULSTCNGEN (1 << 3) +#define XUSBPSU_DEVTEN_CONNECTDONEEN (1 << 2) +#define XUSBPSU_DEVTEN_USBRSTEN (1 << 1) +#define XUSBPSU_DEVTEN_DISCONNEVTEN (1 << 0) + +/* Device Status Register */ +#define XUSBPSU_DSTS_DCNRD (1 << 29) + +/* This applies for core versions 1.87a and earlier */ +#define XUSBPSU_DSTS_PWRUPREQ (1 << 24) + +/* These apply for core versions 1.94a and later */ +#define XUSBPSU_DSTS_RSS (1 << 25) +#define XUSBPSU_DSTS_SSS (1 << 24) + +#define XUSBPSU_DSTS_COREIDLE (1 << 23) +#define XUSBPSU_DSTS_DEVCTRLHLT (1 << 22) + +#define XUSBPSU_DSTS_USBLNKST_MASK (0x0f << 18) +#define XUSBPSU_DSTS_USBLNKST(n) (((n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18) + +#define XUSBPSU_DSTS_RXFIFOEMPTY (1 << 17) + +#define XUSBPSU_DSTS_SOFFN_MASK (0x3fff << 3) +#define XUSBPSU_DSTS_SOFFN(n) (((n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3) + +#define XUSBPSU_DSTS_CONNECTSPD (7 << 0) + +#define XUSBPSU_DSTS_SUPERSPEED (4 << 0) +#define XUSBPSU_DSTS_HIGHSPEED (0 << 0) +#define XUSBPSU_DSTS_FULLSPEED2 (1 << 0) +#define XUSBPSU_DSTS_LOWSPEED (2 << 0) +#define XUSBPSU_DSTS_FULLSPEED1 (3 << 0) + +/* Device Generic Command Register */ +#define XUSBPSU_DGCMD_SET_LMP 0x01 +#define XUSBPSU_DGCMD_SET_PERIODIC_PAR 0x02 +#define XUSBPSU_DGCMD_XMIT_FUNCTION 0x03 + +/* These apply for core versions 1.94a and later */ +#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 +#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 + +#define XUSBPSU_DGCMD_SELECTED_FIFO_FLUSH 0x09 +#define XUSBPSU_DGCMD_ALL_FIFO_FLUSH 0x0a +#define XUSBPSU_DGCMD_SET_ENDPOINT_NRDY 0x0c +#define XUSBPSU_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 + +#define XUSBPSU_DGCMD_STATUS(n) (((n) >> 15) & 1) +#define XUSBPSU_DGCMD_CMDACT (1 << 10) +#define XUSBPSU_DGCMD_CMDIOC (1 << 8) + +/* Device Generic Command Parameter Register */ +#define XUSBPSU_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) +#define XUSBPSU_DGCMDPAR_FIFO_NUM(n) ((n) << 0) +#define XUSBPSU_DGCMDPAR_RX_FIFO (0 << 5) +#define XUSBPSU_DGCMDPAR_TX_FIFO (1 << 5) +#define XUSBPSU_DGCMDPAR_LOOPBACK_DIS (0 << 0) +#define XUSBPSU_DGCMDPAR_LOOPBACK_ENA (1 << 0) + +/* Device Endpoint Command Register */ +#define XUSBPSU_DEPCMD_PARAM_SHIFT 16 +#define XUSBPSU_DEPCMD_PARAM(x) ((x) << XUSBPSU_DEPCMD_PARAM_SHIFT) +#define XUSBPSU_DEPCMD_GET_RSC_IDX(x) (((x) >> XUSBPSU_DEPCMD_PARAM_SHIFT) & \ + 0x7f) +#define XUSBPSU_DEPCMD_STATUS(x) (((x) >> 12) & 0xF) +#define XUSBPSU_DEPCMD_HIPRI_FORCERM (1 << 11) +#define XUSBPSU_DEPCMD_CMDACT (1 << 10) +#define XUSBPSU_DEPCMD_CMDIOC (1 << 8) + +#define XUSBPSU_DEPCMD_DEPSTARTCFG 0x09 +#define XUSBPSU_DEPCMD_ENDTRANSFER 0x08 +#define XUSBPSU_DEPCMD_UPDATETRANSFER 0x07 +#define XUSBPSU_DEPCMD_STARTTRANSFER 0x06 +#define XUSBPSU_DEPCMD_CLEARSTALL 0x05 +#define XUSBPSU_DEPCMD_SETSTALL 0x04 +#define XUSBPSU_DEPCMD_GETEPSTATE 0x03 +#define XUSBPSU_DEPCMD_SETTRANSFRESOURCE 0x02 +#define XUSBPSU_DEPCMD_SETEPCONFIG 0x01 + +/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ +#define XUSBPSU_DALEPENA_EP(n) (1 << n) + +#define XUSBPSU_DEPCFG_INT_NUM(n) ((n) << 0) +#define XUSBPSU_DEPCFG_XFER_COMPLETE_EN (1 << 8) +#define XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9) +#define XUSBPSU_DEPCFG_XFER_NOT_READY_EN (1 << 10) +#define XUSBPSU_DEPCFG_FIFO_ERROR_EN (1 << 11) +#define XUSBPSU_DEPCFG_STREAM_EVENT_EN (1 << 13) +#define XUSBPSU_DEPCFG_BINTERVAL_M1(n) ((n) << 16) +#define XUSBPSU_DEPCFG_STREAM_CAPABLE (1 << 24) +#define XUSBPSU_DEPCFG_EP_NUMBER(n) ((n) << 25) +#define XUSBPSU_DEPCFG_BULK_BASED (1 << 30) +#define XUSBPSU_DEPCFG_FIFO_BASED (1 << 31) + +/* DEPCFG parameter 0 */ +#define XUSBPSU_DEPCFG_EP_TYPE(n) ((n) << 1) +#define XUSBPSU_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3) +#define XUSBPSU_DEPCFG_FIFO_NUMBER(n) ((n) << 17) +#define XUSBPSU_DEPCFG_BURST_SIZE(n) ((n) << 22) +#define XUSBPSU_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26) +/* This applies for core versions earlier than 1.94a */ +#define XUSBPSU_DEPCFG_IGN_SEQ_NUM (1 << 31) +/* These apply for core versions 1.94a and later */ +#define XUSBPSU_DEPCFG_ACTION_INIT (0 << 30) +#define XUSBPSU_DEPCFG_ACTION_RESTORE (1 << 30) +#define XUSBPSU_DEPCFG_ACTION_MODIFY (2 << 30) + +/* DEPXFERCFG parameter 0 */ +#define XUSBPSU_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff) + +#define XUSBPSU_DEPCMD_TYPE_BULK 2 +#define XUSBPSU_DEPCMD_TYPE_INTR 3 + +/* TRB Length, PCM and Status */ +#define XUSBPSU_TRB_SIZE_MASK (0x00ffffff) +#define XUSBPSU_TRB_SIZE_LENGTH(n) ((n) & XUSBPSU_TRB_SIZE_MASK) +#define XUSBPSU_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) +#define XUSBPSU_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) + +#define XUSBPSU_TRBSTS_OK 0 +#define XUSBPSU_TRBSTS_MISSED_ISOC 1 +#define XUSBPSU_TRBSTS_SETUP_PENDING 2 +#define XUSBPSU_TRB_STS_XFER_IN_PROG 4 + +/* TRB Control */ +#define XUSBPSU_TRB_CTRL_HWO (1 << 0) +#define XUSBPSU_TRB_CTRL_LST (1 << 1) +#define XUSBPSU_TRB_CTRL_CHN (1 << 2) +#define XUSBPSU_TRB_CTRL_CSP (1 << 3) +#define XUSBPSU_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) +#define XUSBPSU_TRB_CTRL_ISP_IMI (1 << 10) +#define XUSBPSU_TRB_CTRL_IOC (1 << 11) +#define XUSBPSU_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) + +#define XUSBPSU_TRBCTL_NORMAL XUSBPSU_TRB_CTRL_TRBCTL(1) +#define XUSBPSU_TRBCTL_CONTROL_SETUP XUSBPSU_TRB_CTRL_TRBCTL(2) +#define XUSBPSU_TRBCTL_CONTROL_STATUS2 XUSBPSU_TRB_CTRL_TRBCTL(3) +#define XUSBPSU_TRBCTL_CONTROL_STATUS3 XUSBPSU_TRB_CTRL_TRBCTL(4) +#define XUSBPSU_TRBCTL_CONTROL_DATA XUSBPSU_TRB_CTRL_TRBCTL(5) +#define XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST XUSBPSU_TRB_CTRL_TRBCTL(6) +#define XUSBPSU_TRBCTL_ISOCHRONOUS XUSBPSU_TRB_CTRL_TRBCTL(7) +#define XUSBPSU_TRBCTL_LINK_TRB XUSBPSU_TRB_CTRL_TRBCTL(8) + +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* Read a register of the USBPS8 device. This macro provides register +* access to all registers using the register offsets defined above. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Offset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset); +* +******************************************************************************/ +#define XUsbPsu_ReadReg(InstancePtr, Offset) \ + Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (Offset)) + +/*****************************************************************************/ +/** +* +* Write a register of the USBPS8 device. This macro provides +* register access to all registers using the register offsets defined above. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr, +* u32 Offset,u32 Data) +* +******************************************************************************/ +#define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \ + Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (Offset), (Data)) + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xwdtps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xwdtps.h new file mode 100644 index 000000000..498e60bee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xwdtps.h @@ -0,0 +1,219 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xwdtps.h +* +* The Xilinx watchdog timer driver supports the Xilinx watchdog timer hardware. +* +* The Xilinx watchdog timer (WDT) driver supports the following features: +* - Both Interrupt driven and Polled mode +* - enabling and disabling the watchdog timer +* - restarting the watchdog. +* - initializing the most significant digit of the counter restart value. +* - multiple individually enabling/disabling outputs +* +* It is the responsibility of the application to provide an interrupt handler +* for the watchdog timer and connect it to the interrupt system if interrupt +* driven mode is desired. +* +* If interrupt is enabled, the watchdog timer device generates an interrupt +* when the counter reaches zero. +* +* If the hardware interrupt signal is not connected/enabled, polled mode is the +* only option (using IsWdtExpired) for the watchdog. +* +* The outputs from the WDT are individually enabled/disabled using +* _EnableOutput()/_DisableOutput(). The clock divisor ratio and initial restart +* value of the count is configurable using _SetControlValues(). +* +* The reset condition of the hardware has the maximum initial count in the +* Counter Reset Value (CRV) and the WDT is disabled with the reset enable +* enabled and the reset length set to 32 clocks. i.e. +* 
+*     register ZMR = 0x1C2
+*     register CCR = 0x3FC
+*
+* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads +* or thread mutual exclusion, virtual memory, or cache control must be +* satisfied by the layer above this driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.01a asa    02/15/12 Added tcl file to generate xparameters
+* 1.02a  sg    07/15/12 Removed code/APIs related to  External Signal
+*						Length functionality for CR 658287
+*						Removed APIs XWdtPs_SetExternalSignalLength,
+*						XWdtPs_GetExternalSignalLength
+*						Modified the Self Test to use the Reset Length mask
+*						for CR 658287
+* 3.0	pkp	   12/09/14 Added support for Zynq Ultrascale Mp.Also
+*			modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ +#ifndef XWDTPS_H /* prevent circular inclusions */ +#define XWDTPS_H /* by using protection macros */ + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xwdtps_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * Choices for output selections for the device, used in + * XWdtPs_EnableOutput()/XWdtPs_DisableOutput() functions + */ +#define XWDTPS_RESET_SIGNAL 0x01U /**< Reset signal request */ +#define XWDTPS_IRQ_SIGNAL 0x02U /**< IRQ signal request */ + +/* + * Control value setting flags, used in + * XWdtPs_SetControlValues()/XWdtPs_GetControlValues() functions + */ +#define XWDTPS_CLK_PRESCALE 0x01U /**< Clock Prescale request */ +#define XWDTPS_COUNTER_RESET 0x02U /**< Counter Reset request */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ +} XWdtPs_Config; + + +/** + * The XWdtPs driver instance data. The user is required to allocate a + * variable of this type for every watchdog/timer device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XWdtPs_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device watchdog timer is running */ +} XWdtPs; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/** +* +* Check if the watchdog timer has expired. This function is used for polled +* mode and it is also used to check if the last reset was caused by the +* watchdog timer. +* +* @param InstancePtr is a pointer to the XWdtPs instance. +* +* @return +* - TRUE if the watchdog has expired. +* - FALSE if the watchdog has not expired. +* +* @note C-style signature: +* int XWdtPs_IsWdtExpired(XWdtPs *InstancePtr) +* +******************************************************************************/ +#define XWdtPs_IsWdtExpired(InstancePtr) \ +((XWdtPs_ReadReg((InstancePtr)->Config.BaseAddress, XWDTPS_SR_OFFSET) & \ + XWDTPS_SR_WDZ_MASK) == XWDTPS_SR_WDZ_MASK) + + +/****************************************************************************/ +/** +* +* Restart the watchdog timer. An application needs to call this function +* periodically to keep the timer from asserting the enabled output. +* +* @param InstancePtr is a pointer to the XWdtPs instance. +* +* @return None. +* +* @note C-style signature: +* void XWdtPs_RestartWdt(XWdtPs *InstancePtr) +* +******************************************************************************/ +#define XWdtPs_RestartWdt(InstancePtr) \ + XWdtPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XWDTPS_RESTART_OFFSET, XWDTPS_RESTART_KEY_VAL) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xwdtps_sinit.c. + */ +XWdtPs_Config *XWdtPs_LookupConfig(u16 DeviceId); + +/* + * Interface functions in xwdtps.c + */ +s32 XWdtPs_CfgInitialize(XWdtPs *InstancePtr, + XWdtPs_Config *ConfigPtr, u32 EffectiveAddress); + +void XWdtPs_Start(XWdtPs *InstancePtr); + +void XWdtPs_Stop(XWdtPs *InstancePtr); + +void XWdtPs_EnableOutput(XWdtPs *InstancePtr, u8 Signal); + +void XWdtPs_DisableOutput(XWdtPs *InstancePtr, u8 Signal); + +u32 XWdtPs_GetControlValue(XWdtPs *InstancePtr, u8 Control); + +void XWdtPs_SetControlValue(XWdtPs *InstancePtr, u8 Control, u32 Value); + +/* + * Self-test function in xwdttb_selftest.c. + */ +s32 XWdtPs_SelfTest(XWdtPs *InstancePtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xwdtps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xwdtps_hw.h new file mode 100644 index 000000000..2cd3b272b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xwdtps_hw.h @@ -0,0 +1,190 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xwdtps_hw.h +* +* This file contains the hardware interface to the System Watch Dog Timer (WDT). +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.02a  sg    07/15/12 Removed defines related to  External Signal
+*			Length functionality for CR 658287
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ +#ifndef XWDTPS_HW_H /* prevent circular inclusions */ +#define XWDTPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XWDTPS_ZMR_OFFSET 0x00000000U /**< Zero Mode Register */ +#define XWDTPS_CCR_OFFSET 0x00000004U /**< Counter Control Register */ +#define XWDTPS_RESTART_OFFSET 0x00000008U /**< Restart Register */ +#define XWDTPS_SR_OFFSET 0x0000000CU /**< Status Register */ +/* @} */ + + +/** @name Zero Mode Register + * This register controls how the time out is indicated and also contains + * the access code (0xABC) to allow writes to the register + * @{ + */ +#define XWDTPS_ZMR_WDEN_MASK 0x00000001U /**< enable the WDT */ +#define XWDTPS_ZMR_RSTEN_MASK 0x00000002U /**< enable the reset output */ +#define XWDTPS_ZMR_IRQEN_MASK 0x00000004U /**< enable the IRQ output */ + +#define XWDTPS_ZMR_RSTLN_MASK 0x00000070U /**< set length of reset pulse */ +#define XWDTPS_ZMR_RSTLN_SHIFT 4U /**< shift for reset pulse */ + +#define XWDTPS_ZMR_IRQLN_MASK 0x00000180U /**< set length of interrupt pulse */ +#define XWDTPS_ZMR_IRQLN_SHIFT 7U /**< shift for interrupt pulse */ + +#define XWDTPS_ZMR_ZKEY_MASK 0x00FFF000U /**< mask for writing access key */ +#define XWDTPS_ZMR_ZKEY_VAL 0x00ABC000U /**< access key, 0xABC << 12 */ + +/* @} */ + +/** @name Counter Control register + * This register controls how fast the timer runs and the reset value + * and also contains the access code (0x248) to allow writes to the + * register + * @{ + */ + +#define XWDTPS_CCR_CLKSEL_MASK 0x00000003U /**< counter clock prescale */ + +#define XWDTPS_CCR_CRV_MASK 0x00003FFCU /**< counter reset value */ +#define XWDTPS_CCR_CRV_SHIFT 2U /**< shift for writing value */ + +#define XWDTPS_CCR_CKEY_MASK 0x03FFC000U /**< mask for writing access key */ +#define XWDTPS_CCR_CKEY_VAL 0x00920000U /**< access key, 0x248 << 14 */ + +/* Bit patterns for Clock prescale divider values */ + +#define XWDTPS_CCR_PSCALE_0008 0x00000000U /**< divide clock by 8 */ +#define XWDTPS_CCR_PSCALE_0064 0x00000001U /**< divide clock by 64 */ +#define XWDTPS_CCR_PSCALE_0512 0x00000002U /**< divide clock by 512 */ +#define XWDTPS_CCR_PSCALE_4096 0x00000003U /**< divide clock by 4096 */ + +/* @} */ + +/** @name Restart register + * This register resets the timer preventing a timeout. Value is specific + * 0x1999 + * @{ + */ + +#define XWDTPS_RESTART_KEY_VAL 0x00001999U /**< valid key */ + +/*@}*/ + +/** @name Status register + * This register indicates timer reached zero count. + * @{ + */ +#define XWDTPS_SR_WDZ_MASK 0x00000001U /**< time out occurred */ + +/*@}*/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XWdtPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XWdtPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (u32)(RegOffset)) + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XWdtPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XWdtPs_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xzdma.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xzdma.h new file mode 100644 index 000000000..af8430e66 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xzdma.h @@ -0,0 +1,669 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* ZDMA is a general purpose DMA designed to support memory to memory and memory +* to IO buffer transfers. ALTO has two instance of general purpose ZDMA. +* One is located in FPD (full power domain) which is GDMA and other is located +* in LPD (low power domain) which is ADMA. +* +* GMDA & ADMA are configured each with 8 DMA channels and and each channel can +* be programmed secure or non-secure. +* Each channel is divided into two functional sides, Source (Read) and +* Destination (Write). Each DMA channel can be independently programmed +* in one of following DMA modes. +* - Simple DMA +* - Normal data transfer from source to destination. +* - Write Only mode. +* - Read Only mode. +* - Scatter Gather DMA +* - Only Normal mode it can't support other two modes. +* In Scatter gather descriptor can be of 3 types +* - Linear descriptor. +* - Linked list descriptor +* - Hybrid descriptor (Combination of both Linear and Linked list) +* Our driver will not support Hybrid type of descriptor. +* +* Initialization & Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the ZDMA core. +* +* XZDma_CfgInitialize() API is used to initialize the ZDMA core. +* The user needs to first call the XZDma_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to the +* XZDma_CfgInitialize() API. +* +* Interrupts +* The driver provides an interrupt handler XZDma_IntrHandler for handling +* the interrupt from the ZDMA core. The users of this driver have to +* register this handler with the interrupt system and provide the callback +* functions by using XZDma_SetCallBack API. In this version Descriptor done +* option is disabled. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XZDma driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* @file xzdma.h +* +* This header file contains identifiers and register-level driver functions (or +* macros), range macros, structure typedefs that can be used to access the +* Xilinx ZDMA core instance. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+*
+* +******************************************************************************/ +#ifndef XZDMA_H_ +#define XZDMA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xzdma_hw.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xil_cache.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/** @name ZDMA Handler Types + * @{ + */ +typedef enum { + XZDMA_HANDLER_DONE, /**< For Done Handler */ + XZDMA_HANDLER_ERROR, /**< For Error Handler */ +} XZDma_Handler; +/*@}*/ + +/** @name ZDMA Descriptors Types + * @{ + */ +typedef enum { + XZDMA_LINEAR, /**< Linear descriptor */ + XZDMA_LINKEDLIST, /**< Linked list descriptor */ +} XZDma_DscrType; +/*@}*/ + +/** @name ZDMA Operation modes + * @{ + */ +typedef enum { + XZDMA_NORMAL_MODE, /**< Normal transfer from source to + * destination*/ + XZDMA_WRONLY_MODE, /**< Write only mode */ + XZDMA_RDONLY_MODE /**< Read only mode */ +} XZDma_Mode; +/*@}*/ + +/** @name ZDMA state + * @{ + */ +typedef enum { + XZDMA_IDLE, /**< ZDMA is in Idle state */ + XZDMA_PAUSE, /**< Paused state */ + XZDMA_BUSY, /**< Busy state */ +} XZDmaState; +/*@}*/ + +/** @name ZDMA AXI Burst type + * @{ + */ +typedef enum { + XZDMA_FIXED_BURST = 0, /**< Fixed burst type */ + XZDMA_INCR_BURST /**< Increment burst type */ +} XZDma_BurstType; +/*@}*/ + +/******************************************************************************/ +/** +* This typedef contains scatter gather descriptor fields for ZDMA core. +*/ +typedef struct { + void *SrcDscrPtr; /**< Source Descriptor pointer */ + void *DstDscrPtr; /**< Destination Descriptor pointer */ + u32 DscrCount; /**< Count of descriptors available */ + XZDma_DscrType DscrType;/**< Type of descriptor either Linear or + * Linked list type */ +} XZDma_Descriptor; + +/******************************************************************************/ +/** +* This typedef contains scatter gather descriptor fields for ZDMA core. +*/ +typedef struct { + u64 Address; /**< Address */ + u32 Size; /**< Word2, Size of data */ + u32 Cntl; /**< Word3 Control data */ + u64 NextDscr; /**< Address of next descriptor */ + u64 Reserved; /**< Reserved address */ +} __attribute__ ((packed)) XZDma_LlDscr; + +/******************************************************************************/ +/** +* This typedef contains Linear descriptor fields for ZDMA core. +*/ +typedef struct { + u64 Address; /**< Address */ + u32 Size; /**< Word3, Size of data */ + u32 Cntl; /**< Word4, control data */ +} __attribute__ ((packed)) XZDma_LiDscr; + +/******************************************************************************/ +/** +* +* This typedef contains the data configurations of ZDMA core +*/ +typedef struct { + u8 OverFetch; /**< Enable Over fetch */ + u8 SrcIssue; /**< Outstanding transactions for Source */ + XZDma_BurstType SrcBurstType; + /**< Burst type for SRC */ + u8 SrcBurstLen; /**< AXI length for data read */ + XZDma_BurstType DstBurstType; + /**< Burst type for DST */ + u8 DstBurstLen; /**< AXI length for data write */ + u8 SrcCache; /**< AXI cache bits for data read */ + u8 SrcQos; /**< AXI QOS bits for data read */ + u8 DstCache; /**< AXI cache bits for data write */ + u8 DstQos; /**< AXI QOS bits for data write */ +} XZDma_DataConfig; + +/******************************************************************************/ +/** +* +* This typedef contains the descriptor configurations of ZDMA core +*/ +typedef struct{ + u8 AxCoherent; /**< AXI transactions are coherent or non-coherent */ + u8 AXCache; /**< AXI cache for DSCR fetch */ + u8 AXQos; /**< Qos bit for DSCR fetch */ +} XZDma_DscrConfig; + +/******************************************************************************/ +/** +* Callback type for Completion of all data transfers. +* +* @param CallBackRef is a callback reference passed in by the upper layer +* when setting the callback functions, and passed back to the +* upper layer when the callback is invoked. +*******************************************************************************/ +typedef void (*XZDma_DoneHandler) (void *CallBackRef); + +/******************************************************************************/ +/** +* Callback type for all error interrupts. +* +* @param CallBackRef is a callback reference passed in by the upper layer +* when setting the callback functions, and passed back to the +* upper layer when the callback is invoked. +* @param ErrorMask is a bit mask indicating the cause of the error. Its +* value equals 'OR'ing one or more XZDMA_IXR_* values defined in +* xzdma_hw.h +****************************************************************************/ +typedef void (*XZDma_ErrorHandler) (void *CallBackRef, u32 ErrorMask); + +/** +* This typedef contains configuration information for a ZDMA core +* Each ZDMA core should have a configuration structure associated. +*/ +typedef struct { + u16 DeviceId; /**< Device Id of ZDMA */ + u32 BaseAddress; /**< BaseAddress of ZDMA */ + u8 DmaType; /**< Type of DMA */ +} XZDma_Config; + +/******************************************************************************/ +/** +* +* The XZDma driver instance data structure. A pointer to an instance data +* structure is passed around by functions to refer to a specific driver +* instance. +*/ +typedef struct { + XZDma_Config Config; /**< Hardware configuration */ + u32 IsReady; /**< Device and the driver instance + * are initialized */ + u32 IntrMask; /**< Mask for enabling interrupts */ + + XZDma_Mode Mode; /**< Mode of ZDMA core to be operated */ + u8 IsSgDma; /**< Is ZDMA core is in scatter gather or + * not will be specified */ + XZDma_Descriptor Descriptor; /**< It contains information about + * descriptors */ + + XZDma_DoneHandler DoneHandler; /**< Call back for transfer + * done interrupt */ + void *DoneRef; /**< To be passed to the done + * interrupt callback */ + + XZDma_ErrorHandler ErrorHandler;/**< Call back for error + * interrupt */ + void *ErrorRef; /**< To be passed to the error + * interrupt callback */ + XZDma_DataConfig DataConfig; /**< Current configurations */ + XZDma_DscrConfig DscrConfig; /**< Current configurations */ + XZDmaState ChannelState; /**< ZDMA channel is busy */ + +} XZDma; + +/******************************************************************************/ +/** +* +* This typedef contains the fields for transfer of data. +*/ +typedef struct { + UINTPTR SrcAddr; /**< Source address */ + UINTPTR DstAddr; /**< Destination Address */ + u32 Size; /**< Size of the data to be transferred */ + u8 SrcCoherent; /**< Source coherent */ + u8 DstCoherent; /**< Destination coherent */ + u8 Pause; /**< Will pause data transmission after + * this transfer only for SG mode */ +} XZDma_Transfer; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* This function returns interrupt status read from Interrupt Status Register. +* Use the XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return The pending interrupts of the ZDMA core. +* Use the masks specified in xzdma_hw.h to interpret +* the returned value. +* @note +* C-style signature: +* void XZDma_IntrGetStatus(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_IntrGetStatus(InstancePtr) \ + XZDma_ReadReg((InstancePtr)->Config.BaseAddress, XZDMA_CH_ISR_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears interrupt(s). Every bit set in Interrupt Status +* Register indicates that a specific type of interrupt is occurring, and this +* function clears one or more interrupts by writing a bit mask to Interrupt +* Clear Register. +* +* @param InstancePtr is a pointer to the XZDma instance. +* @param Mask is the type of the interrupts to enable. Use OR'ing of +* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create +* this parameter value. +* +* @return None. +* +* @note +* C-style signature: +* void XZDma_IntrClear(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_IntrClear(InstancePtr, Mask) \ + XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_ISR_OFFSET, ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK)) + +/*****************************************************************************/ +/** +* +* This function returns interrupt mask to know which interrupts are +* enabled and which of them were disabled. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return The current interrupt mask. The mask indicates which interrupts +* are enabled/disabled. +* 0 bit represents .....corresponding interrupt is enabled. +* 1 bit represents .....Corresponding interrupt is disabled. +* +* @note +* C-style signature: +* void XZDma_GetIntrMask(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_GetIntrMask(InstancePtr) \ + XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + (u32)(XZDMA_CH_IMR_OFFSET)) + +/*****************************************************************************/ +/** +* +* This function enables individual interrupts of the ZDMA core by updating +* the Interrupt Enable register. +* +* @param InstancePtr is a pointer to the XZDma instance. +* @param Mask is the type of the interrupts to enable. Use OR'ing of +* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create +* this parameter value. +* +* @return None. +* +* @note The existing enabled interrupt(s) will remain enabled. +* C-style signature: +* void XZDma_EnableIntr(XZDma *InstancePtr, u32 Mask) +* +******************************************************************************/ +#define XZDma_EnableIntr(InstancePtr, Mask) \ + (InstancePtr)->IntrMask = ((InstancePtr)->IntrMask | (Mask)) + +/*****************************************************************************/ +/** +* +* This function disables individual interrupts of the ZDMA core by updating +* the Interrupt Disable register. +* +* @param InstancePtr is a pointer to the XZDma instance. +* @param Mask is the type of the interrupts to disable. Use OR'ing of +* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create +* this parameter value. +* +* @return None. +* +* @note The existing disabled interrupt(s) will remain disabled. +* C-style signature: +* void XZDma_DisableIntr(XZDma *InstancePtr, u32 Mask) +* +******************************************************************************/ +#define XZDma_DisableIntr(InstancePtr, Mask) \ + XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_IDS_OFFSET, \ + ((u32)XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_IDS_OFFSET) | ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK))) + +/*****************************************************************************/ +/** +* +* This function returns source current payload address under process +* of ZDMA core. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note This address may not be precise due to ZDMA pipeline structure +* C-style signature: +* u64 XZDma_SrcCurPyld(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_SrcCurPyld(InstancePtr) \ + ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET)) | \ + ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns destination current payload address under process +* of ZDMA core. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note This address may not be precise due to ZDMA pipeline structure +* C-style signature: +* u64 XZDma_DstCurPyld(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_DstCurPyld(InstancePtr) \ + ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET)) | \ + ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns source descriptor current payload address under +* process of ZDMA core. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note This address may not be precise due to ZDMA pipeline structure +* C-style signature: +* u64 XZDma_SrcDscrCurPyld(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_SrcDscrCurPyld(InstancePtr) \ + ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET)) | \ + ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT)) + + +/*****************************************************************************/ +/** +* +* This function returns destination descriptor current payload address under +* process of ZDMA core. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note This address may not be precise due to ZDMA pipeline structure +* C-style signature: +* u64 XZDma_DstDscrCurPyld(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_DstDscrCurPyld(InstancePtr) \ + ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET)) | \ + ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function gets the count of total bytes transferred through core +* since last clear in ZDMA core. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note +* C-style signature: +* void XZDma_GetTotalByte(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_GetTotalByte(InstancePtr) \ + XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_TOTAL_BYTE_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears the count of total bytes transferred in ZDMA core. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note +* C-style signature: +* void XZDma_TotalByteClear(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_TotalByteClear(InstancePtr) \ + XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_TOTAL_BYTE_OFFSET, \ + XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_TOTAL_BYTE_OFFSET)) + +/*****************************************************************************/ +/** +* +* This function gets the total number of Interrupt count for source after last +* call of this API. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note Once this API is called then count will become zero. +* C-style signature: +* void XZDma_GetSrcIntrCnt(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_GetSrcIntrCnt(InstancePtr) \ + XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_IRQ_SRC_ACCT_OFFSET) + +/*****************************************************************************/ +/** +* +* This function gets the total number of Interrupt count for destination +* after last call of this API. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note Once this API is called then count will become zero. +* C-style signature: +* void XZDma_GetDstIntrCnt(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_GetDstIntrCnt(InstancePtr) \ + XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \ + XZDMA_CH_IRQ_DST_ACCT_OFFSET) + +/*****************************************************************************/ +/** +* +* This function Enable's the ZDMA core for initiating the data transfer once the +* data transfer completes it will be automatically disabled. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note None. +* C-style signature: +* void XZDma_EnableCh(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_EnableCh(InstancePtr) \ + XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_EN_MASK)) + +/*****************************************************************************/ +/** +* +* This function Disable's the ZDMA core. +* +* @param InstancePtr is a pointer to the XZDma instance. +* +* @return None. +* +* @note None. +* C-style signature: +* void XZDma_DisableCh(XZDma *InstancePtr) +* +******************************************************************************/ +#define XZDma_DisableCh(InstancePtr) \ + XZDma_WriteReg((InstancePtr)->Config.BaseAddress,\ + (XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_DIS_MASK)) + +/************************ Prototypes of functions **************************/ + +XZDma_Config *XZDma_LookupConfig(u16 DeviceId); + +s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr, + u32 EffectiveAddr); +s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode); +u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr, + UINTPTR Dscr_MemPtr, u32 NoOfBytes); +s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure); +void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure); +s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure); +void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure); +s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num); +void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer); +void XZDma_Resume(XZDma *InstancePtr); +void XZDma_Reset(XZDma *InstancePtr); +XZDmaState XZDma_ChannelState(XZDma *InstancePtr); + +s32 XZDma_SelfTest(XZDma *InstancePtr); + +void XZDma_IntrHandler(void *Instance); +s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType, + void *CallBackFunc, void *CallBackRef); + +/*@}*/ + +#ifdef __cplusplus +} + +#endif + +#endif /* XZDMA_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xzdma_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xzdma_hw.h new file mode 100644 index 000000000..22a006e19 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xzdma_hw.h @@ -0,0 +1,380 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xzdma_hw.h +* +* This header file contains identifiers and register-level driver functions (or +* macros) that can be used to access the Xilinx ZDMA core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+*
+* +******************************************************************************/ +#ifndef XZDMA_HW_H_ +#define XZDMA_HW_H_ /**< Prevent circular inclusions + * by using protection macros */ +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Registers offsets + * @{ + */ +#define XZDMA_ERR_CTRL (0x000U) +#define XZDMA_CH_ECO (0x004U) +#define XZDMA_CH_ISR_OFFSET (0x100U) +#define XZDMA_CH_IMR_OFFSET (0x104U) +#define XZDMA_CH_IEN_OFFSET (0x108U) +#define XZDMA_CH_IDS_OFFSET (0x10CU) +#define XZDMA_CH_CTRL0_OFFSET (0x110U) +#define XZDMA_CH_CTRL1_OFFSET (0x114U) +#define XZDMA_CH_PERIF_OFFSET (0x118U) +#define XZDMA_CH_STS_OFFSET (0x11CU) +#define XZDMA_CH_DATA_ATTR_OFFSET (0x120U) +#define XZDMA_CH_DSCR_ATTR_OFFSET (0x124U) +#define XZDMA_CH_SRC_DSCR_WORD0_OFFSET (0x128U) +#define XZDMA_CH_SRC_DSCR_WORD1_OFFSET (0x12CU) +#define XZDMA_CH_SRC_DSCR_WORD2_OFFSET (0x130U) +#define XZDMA_CH_SRC_DSCR_WORD3_OFFSET (0x134U) +#define XZDMA_CH_DST_DSCR_WORD0_OFFSET (0x138U) +#define XZDMA_CH_DST_DSCR_WORD1_OFFSET (0x13CU) +#define XZDMA_CH_DST_DSCR_WORD2_OFFSET (0x140U) +#define XZDMA_CH_DST_DSCR_WORD3_OFFSET (0x144U) +#define XZDMA_CH_WR_ONLY_WORD0_OFFSET (0x148U) +#define XZDMA_CH_WR_ONLY_WORD1_OFFSET (0x14CU) +#define XZDMA_CH_WR_ONLY_WORD2_OFFSET (0x150U) +#define XZDMA_CH_WR_ONLY_WORD3_OFFSET (0x154U) +#define XZDMA_CH_SRC_START_LSB_OFFSET (0x158U) +#define XZDMA_CH_SRC_START_MSB_OFFSET (0x15CU) +#define XZDMA_CH_DST_START_LSB_OFFSET (0x160U) +#define XZDMA_CH_DST_START_MSB_OFFSET (0x164U) +#define XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET (0x168U) +#define XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET (0x16CU) +#define XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET (0x170U) +#define XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET (0x174U) +#define XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET (0x178U) +#define XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET (0x17CU) +#define XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET (0x180U) +#define XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET (0x184U) +#define XZDMA_CH_TOTAL_BYTE_OFFSET (0x188U) +#define XZDMA_CH_RATE_CNTL_OFFSET (0x18CU) +#define XZDMA_CH_IRQ_SRC_ACCT_OFFSET (0x190U) +#define XZDMA_CH_IRQ_DST_ACCT_OFFSET (0x194U) +#define XZDMA_CH_CTRL2_OFFSET (0x200U) +/*@}*/ + +/** @name Interrupt Enable/Disable/Mask/Status registers bit masks and shifts + * @{ + */ +#define XZDMA_IXR_DMA_PAUSE_MASK (0x00000800U) /**< IXR pause mask */ +#define XZDMA_IXR_DMA_DONE_MASK (0x00000400U) /**< IXR done mask */ +#define XZDMA_IXR_AXI_WR_DATA_MASK (0x00000200U) /**< IXR AXI write data + * error mask */ +#define XZDMA_IXR_AXI_RD_DATA_MASK (0x00000100U) /**< IXR AXI read data + * error mask */ +#define XZDMA_IXR_AXI_RD_DST_DSCR_MASK (0x00000080U) /**< IXR AXI read + * descriptor error + * mask */ +#define XZDMA_IXR_AXI_RD_SRC_DSCR_MASK (0x00000040U) /**< IXR AXI write + * descriptor error + * mask */ +#define XZDMA_IXR_DST_ACCT_ERR_MASK (0x00000020U) /**< IXR DST interrupt + * count overflow + * mask */ +#define XZDMA_IXR_SRC_ACCT_ERR_MASK (0x00000010U) /**< IXR SRC interrupt + * count overflow + * mask */ +#define XZDMA_IXR_BYTE_CNT_OVRFL_MASK (0x00000008U) /**< IXR byte count over + * flow mask */ +#define XZDMA_IXR_DST_DSCR_DONE_MASK (0x00000004U) /**< IXR destination + * descriptor done + * mask */ +#define XZDMA_IXR_SRC_DSCR_DONE_MASK (0x00000002U) /**< IXR source + * descriptor done + * mask */ +#define XZDMA_IXR_INV_APB_MASK (0x00000001U) /**< IXR invalid APB + * access mask */ +#define XZDMA_IXR_ALL_INTR_MASK (0x00000FFFU) /**< IXR OR of all the + * interrupts mask */ +#define XZDMA_IXR_DONE_MASK (0x00000400U) /**< IXR All done mask */ + +#define XZDMA_IXR_ERR_MASK (0x00000BF9U) /**< IXR all Error mask*/ + /**< Or of XZDMA_IXR_AXI_WR_DATA_MASK, + * XZDMA_IXR_AXI_RD_DATA_MASK, + * XZDMA_IXR_AXI_RD_DST_DSCR_MASK, + * XZDMA_IXR_AXI_RD_SRC_DSCR_MASK, + * XZDMA_IXR_INV_APB_MASK, + * XZDMA_IXR_DMA_PAUSE_MASK, + * XZDMA_IXR_BYTE_CNT_OVRFL_MASK, + * XZDMA_IXR_SRC_ACCT_ERR_MASK, + * XZDMA_IXR_DST_ACCT_ERR_MASK */ +/*@}*/ + +/** @name Channel Control0 register bit masks and shifts + * @{ + */ +#define XZDMA_CTRL0_OVR_FETCH_MASK (0x00000080U) /**< Over fetch mask */ +#define XZDMA_CTRL0_POINT_TYPE_MASK (0x00000040U) /**< Pointer type mask */ +#define XZDMA_CTRL0_MODE_MASK (0x00000030U) /**< Mode mask */ +#define XZDMA_CTRL0_WRONLY_MASK (0x00000010U) /**< Write only mask */ +#define XZDMA_CTRL0_RDONLY_MASK (0x00000020U) /**< Read only mask */ +#define XZDMA_CTRL0_RATE_CNTL_MASK (0x00000008U) /**< Rate control mask */ +#define XZDMA_CTRL0_CONT_ADDR_MASK (0x00000004U) /**< Continue address + * specified mask */ +#define XZDMA_CTRL0_CONT_MASK (0x00000002U) /**< Continue mask */ + +#define XZDMA_CTRL0_OVR_FETCH_SHIFT (7U) /**< Over fetch shift */ +#define XZDMA_CTRL0_POINT_TYPE_SHIFT (6U) /**< Pointer type shift */ +#define XZDMA_CTRL0_MODE_SHIFT (4U) /**< Mode type shift */ +#define XZDMA_CTRL0_RESET_VALUE (0x00000080U) /**< CTRL0 reset value */ + +/*@}*/ + +/** @name Channel Control1 register bit masks and shifts + * @{ + */ +#define XZDMA_CTRL1_SRC_ISSUE_MASK (0x0000001FU) /**< Source issue mask */ +#define XZDMA_CTRL1_RESET_VALUE (0x000003FFU) /**< CTRL1 reset value */ +/*@}*/ + +/** @name Channel Peripheral register bit masks and shifts + * @{ + */ +#define XZDMA_PERIF_PROG_CELL_CNT_MASK (0x0000003EU) /**< Peripheral program + * cell count */ +#define XZDMA_PERIF_SIDE_MASK (0x00000002U) /**< Interface attached + * the side mask */ +#define XZDMA_PERIF_EN_MASK (0x00000001U) /**< Peripheral flow + * control mask */ +/*@}*/ + +/** @name Channel Status register bit masks and shifts + * @{ + */ +#define XZDMA_STS_DONE_ERR_MASK (0x00000003U) /**< Done with errors mask */ +#define XZDMA_STS_BUSY_MASK (0x00000002U) /**< ZDMA is busy in transfer + * mask */ +#define XZDMA_STS_PAUSE_MASK (0x00000001U) /**< ZDMA is in Pause state + * mask */ +#define XZDMA_STS_DONE_MASK (0x00000000U) /**< ZDMA done mask */ +#define XZDMA_STS_ALL_MASK (0x00000003U) /**< ZDMA status mask */ + +/*@}*/ + +/** @name Channel Data Attribute register bit masks and shifts + * @{ + */ +#define XZDMA_DATA_ATTR_ARBURST_MASK (0x0C000000U) /**< Data ArBurst mask */ +#define XZDMA_DATA_ATTR_ARCACHE_MASK (0x03C00000U) /**< Data ArCache mask */ +#define XZDMA_DATA_ATTR_ARQOS_MASK (0x003C0000U) /**< Data ARQos masks */ +#define XZDMA_DATA_ATTR_ARLEN_MASK (0x0003C000U) /**< Data Arlen mask */ +#define XZDMA_DATA_ATTR_AWBURST_MASK (0x00003000U) /**< Data Awburst mask */ +#define XZDMA_DATA_ATTR_AWCACHE_MASK (0x00000F00U) /**< Data AwCache mask */ +#define XZDMA_DATA_ATTR_AWQOS_MASK (0x000000F0U) /**< Data AwQos mask */ +#define XZDMA_DATA_ATTR_AWLEN_MASK (0x0000000FU) /**< Data Awlen mask */ + +#define XZDMA_DATA_ATTR_ARBURST_SHIFT (26U) /**< Data Arburst shift */ +#define XZDMA_DATA_ATTR_ARCACHE_SHIFT (22U) /**< Data ArCache shift */ +#define XZDMA_DATA_ATTR_ARQOS_SHIFT (18U) /**< Data ARQos shift */ +#define XZDMA_DATA_ATTR_ARLEN_SHIFT (14U) /**< Data Arlen shift */ +#define XZDMA_DATA_ATTR_AWBURST_SHIFT (12U) /**< Data Awburst shift */ +#define XZDMA_DATA_ATTR_AWCACHE_SHIFT (8U) /**< Data Awcache shift */ +#define XZDMA_DATA_ATTR_AWQOS_SHIFT (4U) /**< Data Awqos shift */ +#define XZDMA_DATA_ATTR_RESET_VALUE (0x0483D20FU) /**< Data Attributes + * reset value */ + +/*@}*/ + +/** @name Channel DSCR Attribute register bit masks and shifts + * @{ + */ +#define XZDMA_DSCR_ATTR_AXCOHRNT_MASK (0x00000100U) /**< Descriptor coherent + * mask */ +#define XZDMA_DSCR_ATTR_AXCACHE_MASK (0x000000F0U) /**< Descriptor cache + * mask */ +#define XZDMA_DSCR_ATTR_AXQOS_MASK (0x0000000FU) /**< Descriptor AxQos + * mask */ + +#define XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT (8U) /**< Descriptor coherent shift */ +#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT (7U) /**< Descriptor cache shift */ +#define XZDMA_DSCR_ATTR_RESET_VALUE (0x00000000U) /**< Dscr Attributes + * reset value */ + +/*@}*/ + +/** @name Channel Source/Destination Word0 register bit mask + * @{ + */ +#define XZDMA_WORD0_LSB_MASK (0xFFFFFFFFU) /**< LSB Address mask */ +/*@}*/ + +/** @name Channel Source/Destination Word1 register bit mask + * @{ + */ +#define XZDMA_WORD1_MSB_MASK (0x0001FFFFU) /**< MSB Address mask */ +#define XZDMA_WORD1_MSB_SHIFT (32U) /**< MSB Address shift */ +/*@}*/ + +/** @name Channel Source/Destination Word2 register bit mask + * @{ + */ +#define XZDMA_WORD2_SIZE_MASK (0x3FFFFFFFU) /**< Size mask */ +/*@}*/ + +/** @name Channel Source/Destination Word3 register bit masks and shifts + * @{ + */ +#define XZDMA_WORD3_CMD_MASK (0x00000018U) /**< Cmd mask */ +#define XZDMA_WORD3_CMD_SHIFT (3U) /**< Cmd shift */ +#define XZDMA_WORD3_CMD_NXTVALID_MASK (0x00000000U) /**< Next Dscr is valid + * mask */ +#define XZDMA_WORD3_CMD_PAUSE_MASK (0x00000008U) /**< Pause after this + * dscr mask */ +#define XZDMA_WORD3_CMD_STOP_MASK (0x00000010U) /**< Stop after this + ..* dscr mask */ +#define XZDMA_WORD3_INTR_MASK (0x00000004U) /**< Interrupt + * enable or disable + * mask */ +#define XZDMA_WORD3_INTR_SHIFT (2U) /**< Interrupt enable + * disable + * shift */ +#define XZDMA_WORD3_TYPE_MASK (0x00000002U) /**< Type of Descriptor + * mask */ +#define XZDMA_WORD3_TYPE_SHIFT (1U) /**< Type of Descriptor + * Shift */ +#define XZDMA_WORD3_COHRNT_MASK (0x00000001U) /**< Coherence mask */ +/*@}*/ + +/** @name Channel Source/Destination start address or current payload + * MSB register bit mask + * @{ + */ +#define XZDMA_START_MSB_ADDR_MASK (0x0001FFFFU) /**< Start msb address + * mask */ +/*@}*/ + +/** @name Channel Rate control count register bit mask + * @{ + */ +#define XZDMA_CH_RATE_CNTL_MASK (0x00000FFFU) /**< Channel rate control + * mask */ +/*@}*/ + +/** @name Channel Source/Destination Interrupt account count register bit mask + * @{ + */ +#define XZDMA_CH_IRQ_ACCT_MASK (0x000000FFU) /**< Interrupt count + * mask */ +/*@}*/ + +/** @name Channel debug register 0/1 bit mask + * @{ + */ +#define XZDMA_CH_DBG_CMN_BUF_MASK (0x000001FFU) /**< Common buffer count + * mask */ +/*@}*/ + +/** @name Channel control2 register bit mask + * @{ + */ +#define XZDMA_CH_CTRL2_EN_MASK (0x00000001U) /**< Channel enable + * mask */ +#define XZDMA_CH_CTRL2_DIS_MASK (0x00000000U) /**< Channel disable + * mask */ +/*@}*/ + +/** @name Channel control2 register bit mask + * @{ + */ + #define XZDMA_WRITE_TO_CLEAR_MASK (0x00000000U) /**< Write to clear + * mask */ + /*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XZDma_In32 Xil_In32 /**< Input operation */ +#define XZDma_Out32 Xil_Out32 /**< Output operation */ + +/*****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the Xilinx base address of the ZDMA core. +* @param RegOffset is the register offset of the register. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XZDma_ReadReg(u32 BaseAddress, u32 RegOffset) +* +******************************************************************************/ +#define XZDma_ReadReg(BaseAddress, RegOffset) \ + XZDma_In32((BaseAddress) + (u32)(RegOffset)) + +/*****************************************************************************/ +/** +* +* This macro writes the value into the given register. +* +* @param BaseAddress is the Xilinx base address of the ZDMA core. +* @param RegOffset is the register offset of the register. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XZDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +******************************************************************************/ +#define XZDma_WriteReg(BaseAddress, RegOffset, Data) \ + XZDma_Out32(((BaseAddress) + (u32)(RegOffset)), (u32)(Data)) + +#ifdef __cplusplus +} + +#endif + +#endif /* XZDMA_HW_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/Makefile new file mode 100644 index 000000000..926b20c4e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/Makefile @@ -0,0 +1,27 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + + +libs: + echo "Compiling axipmon" + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OUTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon.c new file mode 100644 index 000000000..62c0b748b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon.c @@ -0,0 +1,2115 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xaxipmon.c +* +* This file contains the driver API functions that can be used to access +* the AXI Performance Monitor device. +* +* Refer to the xaxipmon.h header file for more information about this driver. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss   02/27/12  First release
+* 2.00a bss   06/23/12  Updated to support v2_00a version of IP.
+* 3.00a bss   09/03/12  Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
+*			to support v2_01a version of IP.
+* 3.01a bss   10/25/12  Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
+*			APIs (CR #683799).
+*			Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
+*			APIs (CR #683801).
+*			Added XAxiPmon_GetMetricName API (CR #683803).
+*			Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
+*			(CR #683746)
+*			Added XAxiPmon_EnableEventLog,
+*			XAxiPmon_DisableMetricsCounter,
+*			XAxiPmon_EnableMetricsCounter APIs to replace macros.
+*			Added XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs to support new
+*			version of IP.
+* 4.00a bss   01/17/13  To support new version of IP:
+* 			Added XAxiPmon_SetLogEnableRanges,
+*	  		XAxiPmon_GetLogEnableRanges,
+*			XAxiPmon_EnableMetricCounterTrigger,
+*			XAxiPmon_DisableMetricCounterTrigger,
+*			XAxiPmon_EnableEventLogTrigger,
+*			XAxiPmon_DisableEventLogTrigger,
+*			XAxiPmon_SetWriteLatencyId,
+*			XAxiPmon_SetReadLatencyId,
+*			XAxiPmon_GetWriteLatencyId,
+*			XAxiPmon_GetReadLatencyId APIs and removed
+*			XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs
+* 5.00a bss   08/26/13  To support new version of IP:
+*			Modified XAxiPmon_CfgInitialize to add Mode of APM and
+*			ScaleFactor parameter.
+*			Modified Assert functions depending on Mode.
+*			Modified XAxiPmon_GetMetricCounter and
+*			XAxiPmon_GetSampledMetricCounter to include
+*			new Counters.
+*			Modified XAxiPmon_SetSampleInterval and
+*			XAxiPmon_GetSampleInterval to remove higher 32 bit
+*			value of SampleInterval since Sample Interval Register
+*			is only 32 bit.
+*			Added XAxiPmon_SetWrLatencyStart,
+*			XAxiPmon_SetWrLatencyEnd, XAxiPmon_SetRdLatencyStart
+*			XAxiPmon_SetRdLatencyEnd, XAxiPmon_GetWrLatencyStart,
+*			XAxiPmon_GetWrLatencyEnd, XAxiPmon_GetRdLatencyStart,
+*			XAxiPmon_GetRdLatencyEnd, XAxiPmon_SetWriteIdMask,
+*			XAxiPmon_SetReadIdMask,
+*			XAxiPmon_GetWriteIdMask and
+*			XAxiPmon_GetReadIdMask APIs.
+*			Renamed:
+*			XAxiPmon_SetWriteLatencyId to XAxiPmon_SetWriteId
+*			XAxiPmon_SetReadLatencyId to XAxiPmon_SetReadId
+*			XAxiPmon_GetWriteLatencyId to XAxiPmon_GetWriteId
+*			XAxiPmon_SetReadLatencyId to XAxiPmon_GetReadId.
+* 6.2   bss  04/21/14   Updated XAxiPmon_CfgInitialize to Reset counters
+*			and FIFOs based on Modes(CR#782671). And if both
+*			profile and trace modes are present set mode as
+*			Advanced.
+* 6.2	bss  03/02/15	Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
+*						XAxiPmon_GetWriteId, XAxiPmon_GetReadId
+*						XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
+*						XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
+*						functions to support Zynq MP APM.
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xaxipmon.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* This function initializes a specific XAxiPmon device/instance. This function +* must be called prior to using the AXI Performance Monitor device. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param ConfigPtr points to the XAxiPmon device configuration structure. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. If the address translation is not used then the +* physical address is passed. +* Unexpected errors may occur if the address mapping is changed +* after this function is invoked. +* +* @return +* - XST_SUCCESS if successful. +* +* @note The user needs to first call the XAxiPmon_LookupConfig() API +* which returns the Configuration structure pointer which is +* passed as a parameter to the XAxiPmon_CfgInitialize() API. +* +******************************************************************************/ +int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr, + u32 EffectiveAddr) +{ + /* + * Assert the input arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * Set the values read from the device config and the base address. + */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddr; + InstancePtr->Config.GlobalClkCounterWidth = + ConfigPtr->GlobalClkCounterWidth; + InstancePtr->Config.MetricSampleCounterWidth = + ConfigPtr->MetricSampleCounterWidth; + InstancePtr->Config.IsEventCount = + ConfigPtr->IsEventCount; + InstancePtr->Config.NumberofSlots = + ConfigPtr->NumberofSlots; + InstancePtr->Config.NumberofCounters = + ConfigPtr->NumberofCounters; + InstancePtr->Config.HaveSampledCounters = + ConfigPtr->HaveSampledCounters; + InstancePtr->Config.IsEventLog = + ConfigPtr->IsEventLog; + InstancePtr->Config.FifoDepth = + ConfigPtr->FifoDepth; + InstancePtr->Config.FifoWidth = + ConfigPtr->FifoWidth; + InstancePtr->Config.TidWidth = + ConfigPtr->TidWidth; + InstancePtr->Config.Is32BitFiltering = ConfigPtr->Is32BitFiltering; + + InstancePtr->Config.ScaleFactor = ConfigPtr->ScaleFactor; + + if ((ConfigPtr->ModeProfile == ConfigPtr->ModeTrace) + || ConfigPtr->ModeAdvanced == 1) + { + InstancePtr->Mode = XAPM_MODE_ADVANCED; + } else if (ConfigPtr->ModeTrace == 1) { + InstancePtr->Mode = XAPM_MODE_TRACE; + } else { + InstancePtr->Mode = XAPM_MODE_PROFILE; + } + + /* + * Indicate the instance is now ready to use, initialized without error. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + /* + * Reset the Counters and FIFO based on Modes. + */ + + /* Advanced and Profile */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED || + InstancePtr->Mode == XAPM_MODE_PROFILE) + { + XAxiPmon_ResetMetricCounter(InstancePtr); + } + /* Advanced */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED) + { + XAxiPmon_ResetGlobalClkCounter(InstancePtr); + } + /* Advanced and Trace */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED || + InstancePtr->Mode == XAPM_MODE_TRACE) + { + XAxiPmon_ResetFifo(InstancePtr); + } + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function resets all Metric Counters and Sampled Metric Counters of +* AXI Performance Monitor. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return XST_SUCCESS +* +* +* @note None. +* +******************************************************************************/ +int XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr) +{ + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + /* + * Write the reset value to the Control register to reset + * Metric counters + */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue | XAPM_CR_MCNTR_RESET_MASK)); + /* + * Release from Reset + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue & ~(XAPM_CR_MCNTR_RESET_MASK))); + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/** +* +* This function resets Global Clock Counter of AXI Performance Monitor +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr) +{ + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + + /* + * Write the reset value to the Control register to reset + * Global Clock Counter + */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue | XAPM_CR_GCC_RESET_MASK)); + + /* + * Release from Reset + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue & ~(XAPM_CR_GCC_RESET_MASK))); + +} + +/*****************************************************************************/ +/** +* +* This function resets Streaming FIFO of AXI Performance Monitor +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return XST_SUCCESS +* +* @note None. +* +******************************************************************************/ +int XAxiPmon_ResetFifo(XAxiPmon *InstancePtr) +{ + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_PROFILE); + + /* Check Event Logging is enabled in Hardware */ + if((InstancePtr->Config.IsEventLog == 0) && + (InstancePtr->Mode == XAPM_MODE_ADVANCED)) + { + /*Event logging not enabled in Hardware*/ + return XST_SUCCESS; + } + /* + * Write the reset value to the Control register to reset + * FIFO + */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue | XAPM_CR_FIFO_RESET_MASK)); + /* + * Release from Reset + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue & ~(XAPM_CR_FIFO_RESET_MASK))); + + return XST_SUCCESS; + +} + +/****************************************************************************/ +/** +* +* This function sets Ranges for Incrementers depending on parameters passed. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param IncrementerNum specifies the Incrementer for which Ranges +* need to be set +* @param RangeUpper specifies the Upper limit in 32 bit Register +* @param RangeLower specifies the Lower limit in 32 bit Register +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 RangeUpper, u16 RangeLower) + { + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + Xil_AssertVoid(IncrementerNum < XAPM_MAX_COUNTERS); + + /* + * Write to the specified Range register + */ + RegValue = RangeUpper << 16; + RegValue |= RangeLower; + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + (XAPM_RANGE0_OFFSET + (IncrementerNum * 16)), + RegValue); + } + +/****************************************************************************/ +/** +* +* This function returns the Ranges of Incrementers Registers. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param IncrementerNum specifies the Incrementer for which Ranges +* need to be returned. +* @param RangeUpper specifies the user reference variable which returns +* the Upper Range Value of the specified Incrementer. +* @param RangeLower specifies the user reference variable which returns +* the Lower Range Value of the specified Incrementer. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 *RangeUpper, u16 *RangeLower) + { + + u32 RegValue; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + Xil_AssertVoid(IncrementerNum < XAPM_MAX_COUNTERS); + + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_RANGE0_OFFSET + (IncrementerNum * 16))); + + *RangeLower = RegValue & 0xFFFF; + *RangeUpper = (RegValue >> 16) & 0xFFFF; + } + +/****************************************************************************/ +/** +* +* This function sets the Sample Interval Register +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param SampleInterval is the Sample Interval value to be set +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval) +{ + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + /* + * Set Sample Interval Lower + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_SI_LOW_OFFSET, SampleInterval); + +} + +/****************************************************************************/ +/** +* +* This function returns the contents of Sample Interval Register +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param SampleInterval is a pointer where the Sample Interval +* Counter value is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + /* + * Set Sample Interval Lower + */ + *SampleInterval = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_SI_LOW_OFFSET); + +} + +/****************************************************************************/ +/** +* +* This function sets Metrics for specified Counter in the corresponding +* Metric Selector Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Slot is the slot ID for which specified counter has to +* be connected. +* @param Metrics is one of the Metric Sets. User has to use +* XAPM_METRIC_SET_* macros in xaxipmon.h for this parameter +* @param CounterNum is the Counter Number. +* The valid values are 0 to 9. +* +* @return XST_SUCCESS if Success +* XST_FAILURE if Failure +* +* @note None. +* +*****************************************************************************/ +int XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics, + u8 CounterNum) +{ + u32 RegValue; + u32 Mask; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + Xil_AssertNonvoid(Slot < XAPM_MAX_AGENTS); + Xil_AssertNonvoid((Metrics <= XAPM_METRIC_SET_22) || + (Metrics == XAPM_METRIC_SET_30)); + Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS); + + /* Find Mask value to force zero in counternum byte range */ + if (CounterNum == 0 || CounterNum == 4 || CounterNum == 8) { + Mask = 0xFFFFFF00; + } + else if (CounterNum == 1 || CounterNum == 5 || CounterNum == 9) { + Mask = 0xFFFF00FF; + } + else if (CounterNum == 2 || CounterNum == 6) { + Mask = 0xFF00FFFF; + } + else { + Mask = 0x00FFFFFF; + } + + if(CounterNum <= 3) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR0_OFFSET); + + RegValue = RegValue & Mask; + RegValue = RegValue | (Metrics << (CounterNum * 8)); + RegValue = RegValue | (Slot << (CounterNum * 8 + 5)); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_MSR0_OFFSET,RegValue); + } + else if((CounterNum >= 4) && (CounterNum <= 7)) { + CounterNum = CounterNum - 4; + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR1_OFFSET); + + RegValue = RegValue & Mask; + RegValue = RegValue | (Metrics << (CounterNum * 8)); + RegValue = RegValue | (Slot << (CounterNum * 8 + 5)); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_MSR1_OFFSET,RegValue); + } + else { + CounterNum = CounterNum - 8; + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR2_OFFSET); + + RegValue = RegValue & Mask; + RegValue = RegValue | (Metrics << (CounterNum * 8)); + RegValue = RegValue | (Slot << (CounterNum * 8 + 5)); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_MSR2_OFFSET,RegValue); + } + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function returns Metrics in the specified Counter from the corresponding +* Metric Selector Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the Counter Number. +* The valid values are 0 to 9. +* @param Metrics is a reference parameter from application where metrics +* of specified counter is filled. +* @praram Slot is a reference parameter in which slot Id of +* specified counter is filled +* @return XST_SUCCESS if Success +* XST_FAILURE if Failure +* +* @note None. +* +*****************************************************************************/ +int XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics, + u8 *Slot) +{ + u32 RegValue; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + Xil_AssertNonvoid(CounterNum <= XAPM_MAX_COUNTERS); + + if(CounterNum <= 3) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR0_OFFSET); + *Metrics = (RegValue >> (CounterNum * 8)) & 0x1F; + *Slot = (RegValue >> (CounterNum * 8 + 5)) & 0x7; + + } + else if((CounterNum >= 4) && (CounterNum <= 7)) { + CounterNum = CounterNum - 4; + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR1_OFFSET); + *Metrics = (RegValue >> (CounterNum * 8)) & 0x1F; + *Slot = (RegValue >> (CounterNum * 8 + 5)) & 0x7; + } + else { + CounterNum = CounterNum - 8; + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR2_OFFSET); + *Metrics = (RegValue >> (CounterNum * 8)) & 0x1F; + *Slot = (RegValue >> (CounterNum * 8 + 5)) & 0x7; + } + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Global Clock Counter Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CntHighValue is the user space pointer with which upper 32 bits +* of Global Clock Counter has to be filled +* @param CntLowValue is the user space pointer with which lower 32 bits +* of Global Clock Counter has to be filled +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue, + u32 *CntLowValue) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + + *CntHighValue = 0x0; + *CntLowValue = 0x0; + + /* + * If Counter width is 64 bit then Counter Value has to be + * filled at CntHighValue address also. + */ + if(InstancePtr->Config.GlobalClkCounterWidth == 64) { + + /* Bits[63:32] exists at XAPM_GCC_HIGH_OFFSET */ + *CntHighValue = XAxiPmon_ReadReg(InstancePtr-> + Config.BaseAddress, XAPM_GCC_HIGH_OFFSET); + } + /* Bits[31:0] exists at XAPM_GCC_LOW_OFFSET */ + *CntLowValue = XAxiPmon_ReadReg(InstancePtr-> + Config.BaseAddress, XAPM_GCC_LOW_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Metric Counter Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the number of the Metric Counter to be read. +* Use the XAPM_METRIC_COUNTER* defines for the counter number in +* xaxipmon.h. The valid values are 0 (XAPM_METRIC_COUNTER_0) to +* 47(XAPM_METRIC_COUNTER_47). +* @return RegValue is the content of specified Metric Counter. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum) +{ + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE); + Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE); + + if (CounterNum < 10 ) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_MC0_OFFSET + (CounterNum * 16))); + } + else if (CounterNum >= 10 && CounterNum < 12) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_MC10_OFFSET + ((CounterNum - 10) * 16))); + } + else if (CounterNum >= 12 && CounterNum < 24) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_MC12_OFFSET + ((CounterNum - 12) * 16))); + } + else if (CounterNum >= 24 && CounterNum < 36) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_MC24_OFFSET + ((CounterNum - 24) * 16))); + } + else + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_MC36_OFFSET + ((CounterNum - 36) * 16))); + + return RegValue; +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Sampled Metric Counter Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the number of the Sampled Metric Counter to read. +* Use the XAPM_METRIC_COUNTER* defines for the counter number in +* xaxipmon.h. The valid values are 0 (XAPM_METRIC_COUNTER_0) to +* 47(XAPM_METRIC_COUNTER_47). +* +* @return RegValue is the content of specified Sampled Metric Counter. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE); + Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_PROFILE || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.HaveSampledCounters == 1))); + + if (CounterNum < 10 ) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_SMC0_OFFSET + (CounterNum * 16))); + } + else if (CounterNum >= 10 && CounterNum < 12) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_SMC10_OFFSET + ((CounterNum - 10) * 16))); + } + else if (CounterNum >= 12 && CounterNum < 24) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_SMC12_OFFSET + ((CounterNum - 12) * 16))); + } + else if (CounterNum >= 24 && CounterNum < 36) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_SMC24_OFFSET + ((CounterNum - 24) * 16))); + } + else + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_SMC36_OFFSET + ((CounterNum - 36) * 16))); + + return RegValue; +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Incrementer Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param IncrementerNum is the number of the Incrementer register to +* read.Use the XAPM_INCREMENTER_* defines for the Incrementer +* number.The valid values are 0 (XAPM_INCREMENTER_0) to +* 9 (XAPM_INCREMENTER_9). +* @param IncrementerNum is the number of the specified Incrementer +* register +* @return RegValue is content of specified Metric Incrementer register. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED && + InstancePtr->Config.IsEventCount == 1); + Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS); + + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_INC0_OFFSET + (IncrementerNum * 16))); + + return RegValue; +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Sampled Incrementer Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param IncrementerNum is the number of the Sampled Incrementer +* register to read.Use the XAPM_INCREMENTER_* defines for the +* Incrementer number.The valid values are 0 (XAPM_INCREMENTER_0) +* to 9 (XAPM_INCREMENTER_9). +* @param IncrementerNum is the number of the specified Sampled +* Incrementer register +* @return RegValue is content of specified Sampled Incrementer register. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED && + InstancePtr->Config.IsEventCount == 1 && + InstancePtr->Config.HaveSampledCounters == 1); + Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS); + + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_SINC0_OFFSET + (IncrementerNum * 16))); + return RegValue; +} + +/****************************************************************************/ +/** +* +* This function sets Software-written Data Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param SwData is the Software written Data. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Set Software-written Data Register + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_SWD_OFFSET, + SwData); +} + +/****************************************************************************/ +/** +* +* This function returns contents of Software-written Data Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return SwData. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr) +{ + u32 SwData; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Set Metric Selector Register + */ + SwData = (u32)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_SWD_OFFSET); + return SwData; +} + +/*****************************************************************************/ +/** +* +* This function enables the following in the AXI Performance Monitor: +* - Event logging +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param FlagEnables is a value to write to the flag enables +* register defined by XAPM_FEC_OFFSET. It is recommended +* to use the XAPM_FEC_*_MASK mask bits to generate. +* A value of 0x0 will disable all events to the event +* log streaming FIFO. +* +* @return XST_SUCCESS +* +* @note None +* +******************************************************************************/ +int XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_TRACE || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventLog == 1))); + + /* Read current register value */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + /* Flag Enable register is present only in Advanced Mode */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED) + { + /* Now write to flag enables register */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_FEC_OFFSET, FlagEnables); + } + + /* Write the new value to the Control register to + * enable event logging */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegValue | XAPM_CR_EVENTLOG_ENABLE_MASK); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function disables the following in the AXI Performance Monitor: +* - Event logging +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return XST_SUCCESS +* +* @note None +* +******************************************************************************/ +int XAxiPmon_StopEventLog(XAxiPmon *InstancePtr) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_TRACE || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventLog == 1))); + + /* Read current register value */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + + /* Write the new value to the Control register to disable + * event logging */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegValue & ~XAPM_CR_EVENTLOG_ENABLE_MASK); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function enables the following in the AXI Performance Monitor: +* - Global clock counter +* - All metric counters +* - All sampled metric counters +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* SampleInterval is the sample interval for the sampled metric +* counters +* +* @return XST_SUCCESS +* +* @note None +******************************************************************************/ +int XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_PROFILE || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1))); + + /* Read current register value */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + /* Globlal Clock Counter is present in Advanced mode only */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED) + { + RegValue = RegValue | XAPM_CR_GCC_ENABLE_MASK; + } + + /* + * Write the new value to the Control register to enable + * global clock counter and metric counters + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegValue | XAPM_CR_MCNTR_ENABLE_MASK); + + /* Set, enable, and load sampled counters */ + XAxiPmon_SetSampleInterval(InstancePtr, SampleInterval); + XAxiPmon_LoadSampleIntervalCounter(InstancePtr); + XAxiPmon_EnableSampleIntervalCounter(InstancePtr); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function disables the following in the AXI Performance Monitor: +* - Global clock counter +* - All metric counters +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return XST_SUCCESS +* +* @note None +* +******************************************************************************/ +int XAxiPmon_StopCounters(XAxiPmon *InstancePtr) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_PROFILE || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1))); + + /* Read current register value */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + /* Globlal Clock Counter is present in Advanced mode only */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED) + { + RegValue = RegValue & ~XAPM_CR_GCC_ENABLE_MASK; + } + + /* + * Write the new value to the Control register to disable + * global clock counter and metric counters + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegValue & ~XAPM_CR_MCNTR_ENABLE_MASK); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function enables Metric Counters. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*******************************************************************************/ +void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_PROFILE || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1))); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal | XAPM_CR_MCNTR_ENABLE_MASK); +} +/****************************************************************************/ +/** +* +* This function disables the Metric Counters. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_PROFILE || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1))); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal & ~(XAPM_CR_MCNTR_ENABLE_MASK)); +} + +/****************************************************************************/ +/** +* +* This function sets the Upper and Lower Ranges for specified Metric Counter +* Log Enable Register.Event Logging starts when corresponding Metric Counter +* value falls in between these ranges +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the Metric Counter number for which +* Ranges are to be assigned.Use the XAPM_METRIC_COUNTER* +* defines for the counter number in xaxipmon.h. +* The valid values are 0 (XAPM_METRIC_COUNTER_0) to +* 9 (XAPM_METRIC_COUNTER_9). +* @param RangeUpper specifies the Upper limit in 32 bit Register +* @param RangeLower specifies the Lower limit in 32 bit Register +* @return None +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 RangeUpper, u16 RangeLower) +{ + u32 RegValue; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS); + Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1)); + + + /* + * Write the specified Ranges to corresponding Metric Counter Log + * Enable Register + */ + RegValue = RangeUpper << 16; + RegValue |= RangeLower; + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + (XAPM_MC0LOGEN_OFFSET + (CounterNum * 16)), RegValue); + +} + +/****************************************************************************/ +/** +* +* This function returns the Ranges of specified Metric Counter Log +* Enable Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the Metric Counter number for which +* Ranges are to be returned.Use the XAPM_METRIC_COUNTER* +* defines for the counter number in xaxipmon.h. +* The valid values are 0 (XAPM_METRIC_COUNTER_0) to +* 9 (XAPM_METRIC_COUNTER_9). +* +* @param RangeUpper specifies the user reference variable which returns +* the Upper Range Value of the specified Metric Counter +* Log Enable Register. +* @param RangeLower specifies the user reference variable which returns +* the Lower Range Value of the specified Metric Counter +* Log Enable Register. +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 *RangeUpper, u16 *RangeLower) +{ + u32 RegValue; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS); + Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1)); + + + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (XAPM_MC0LOGEN_OFFSET + (CounterNum * 16))); + + *RangeLower = RegValue & 0xFFFF; + *RangeUpper = (RegValue >> 16) & 0xFFFF; +} + +/*****************************************************************************/ +/** +* +* This function enables Event Logging. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*******************************************************************************/ +void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_TRACE || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventLog == 1))); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal | XAPM_CR_EVENTLOG_ENABLE_MASK); +} + +/*****************************************************************************/ +/** +* +* This function enables External trigger pulse so that Metric Counters can be +* started on external trigger pulse for a Slot. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*******************************************************************************/ +void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal | XAPM_CR_MCNTR_EXTTRIGGER_MASK); +} + +/****************************************************************************/ +/** +* +* This function disables the External trigger pulse used to start Metric +* Counters on external trigger pulse for a Slot. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal & ~(XAPM_CR_MCNTR_EXTTRIGGER_MASK)); +} + +/*****************************************************************************/ +/** +* +* This function enables External trigger pulse for Event Log +* so that Event Logging can be started on external trigger pulse for a Slot. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*******************************************************************************/ +void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_PROFILE); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal | XAPM_CR_EVTLOG_EXTTRIGGER_MASK); +} + +/****************************************************************************/ +/** +* +* This function disables the External trigger pulse used to start Event +* Log on external trigger pulse for a Slot. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_PROFILE); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal & ~(XAPM_CR_EVTLOG_EXTTRIGGER_MASK)); +} + +/****************************************************************************/ +/** +* +* This function returns a name for a given Metric. +* +* @param Metrics is one of the Metric Sets. User has to use +* XAPM_METRIC_SET_* macros in xaxipmon.h for this parameter +* +* @return const char * +* +* @note None +* +*****************************************************************************/ +const char * XAxiPmon_GetMetricName(u8 Metrics) +{ + if (Metrics == XAPM_METRIC_SET_0 ){ + return "Write Transaction Count"; + } + if (Metrics == XAPM_METRIC_SET_1 ){ + return "Read Transaction Count"; + } + if (Metrics == XAPM_METRIC_SET_2 ){ + return "Write Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_3 ){ + return "Read Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_4 ){ + return "Write Beat Count"; + } + if (Metrics == XAPM_METRIC_SET_5 ){ + return "Total Read Latency"; + } + if (Metrics == XAPM_METRIC_SET_6 ){ + return "Total Write Latency"; + } + if (Metrics == XAPM_METRIC_SET_7 ){ + return "Slv_Wr_Idle_Cnt"; + } + if (Metrics == XAPM_METRIC_SET_8 ){ + return "Mst_Rd_Idle_Cnt"; + } + if (Metrics == XAPM_METRIC_SET_9 ){ + return "Num_BValids"; + } + if (Metrics == XAPM_METRIC_SET_10){ + return "Num_WLasts"; + } + if (Metrics == XAPM_METRIC_SET_11){ + return "Num_RLasts"; + } + if (Metrics == XAPM_METRIC_SET_12){ + return "Minimum Write Latency"; + } + if (Metrics == XAPM_METRIC_SET_13){ + return "Maximum Write Latency"; + } + if (Metrics == XAPM_METRIC_SET_14){ + return "Minimum Read Latency"; + } + if (Metrics == XAPM_METRIC_SET_15){ + return "Maximum Read Latency"; + } + if (Metrics == XAPM_METRIC_SET_16){ + return "Transfer Cycle Count"; + } + if (Metrics == XAPM_METRIC_SET_17){ + return "Packet Count"; + } + if (Metrics == XAPM_METRIC_SET_18){ + return "Data Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_19){ + return "Position Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_20){ + return "Null Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_21){ + return "Slv_Idle_Cnt"; + } + if (Metrics == XAPM_METRIC_SET_22){ + return "Mst_Idle_Cnt"; + } + if (Metrics == XAPM_METRIC_SET_30){ + return "External event count"; + } + return "Unsupported"; +} + +/****************************************************************************/ +/** +* +* This function sets Write ID in ID register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param WriteId is the Write ID to be written in ID register. +* +* @return None. +* +* @note +* If ID filtering for write is of 32 bits(for Zynq MP APM) width then +* WriteID is written to XAPM_ID_OFFSET or if it is 16 bit width +* then lower 16 bits of WriteID are written to XAPM_ID_OFFSET. +* +*****************************************************************************/ +void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + RegVal = RegVal & ~(XAPM_ID_WID_MASK); + RegVal = RegVal | WriteId; + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET, RegVal); + } else { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET, WriteId); + } +} + +/****************************************************************************/ +/** +* +* This function sets Read ID in ID register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param ReadId is the Read ID to be written in ID register. +* +* @return None. +* +* @note +* If ID filtering for read is of 32 bits(for Zynq MP APM) width then +* ReadId is written to XAPM_RID_OFFSET or if it is 16 bit width +* then lower 16 bits of ReadId are written to XAPM_ID_OFFSET. +* +*****************************************************************************/ +void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + RegVal = RegVal & ~(XAPM_ID_RID_MASK); + RegVal = RegVal | (ReadId << 16); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET, RegVal); + } else { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_RID_OFFSET, ReadId); + } +} + +/****************************************************************************/ +/** +* +* This function returns Write ID in ID register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return WriteId is the required Write ID in ID register. +* +* @note None. +* If ID filtering for write is of 32 bits(for Zynq MP APM) width then +* 32 bit XAPM_ID_OFFSET contents are returned or if it is 16 bit +* width then lower 16 bits of XAPM_ID_OFFSET register are returned. +* +*****************************************************************************/ +u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr) +{ + + u32 WriteId; + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + WriteId = RegVal & XAPM_ID_WID_MASK; + } else { + WriteId = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + } + + return WriteId; +} + +/****************************************************************************/ +/** +* +* This function returns Read ID in ID register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return ReadId is the required Read ID in ID register. +* +* @note None. +* If ID filtering for write is of 32 bits(for Zynq MP APM) width then +* 32 bit XAPM_RID_OFFSET contents are returned or if it is 16 bit +* width then higher 16 bits of XAPM_ID_OFFSET register are returned. +* +*****************************************************************************/ +u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr) +{ + + u32 ReadId; + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + RegVal = RegVal & XAPM_ID_RID_MASK; + ReadId = RegVal >> 16; + } else { + ReadId = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_RID_OFFSET); + } + + return ReadId; +} + +/*****************************************************************************/ +/** +* +* This function sets Latency Start point to calculate write latency. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Param is XAPM_LATENCY_ADDR_ISSUE or XAPM_LATENCY_ADDR_ACCEPT +* in xaxipmon.h. +* @return None +* +* @note Param can be 0 - XAPM_LATENCY_ADDR_ISSUE +* or 1 - XAPM_LATENCY_ADDR_ACCEPT +* +*******************************************************************************/ +void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + if (Param == XAPM_LATENCY_ADDR_ACCEPT) { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET, RegVal | XAPM_CR_WRLATENCY_START_MASK); + } + else { + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET, + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET) & ~(XAPM_CR_WRLATENCY_START_MASK)); + } +} + +/*****************************************************************************/ +/** +* +* This function sets Latency End point to calculate write latency. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Param is XAPM_LATENCY_LASTWR or XAPM_LATENCY_FIRSTWR +* in xaxipmon.h. +* +* @return None +* +* @note Param can be 0 - XAPM_LATENCY_LASTWR +* or 1 - XAPM_LATENCY_FIRSTWR +* +*******************************************************************************/ +void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + if (Param == XAPM_LATENCY_FIRSTWR) { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET, RegVal | XAPM_CR_WRLATENCY_END_MASK); + } + else { + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET, + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET) & ~(XAPM_CR_WRLATENCY_END_MASK)); + } +} + +/*****************************************************************************/ +/** +* +* This function sets Latency Start point to calculate read latency. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Param is XAPM_LATENCY_ADDR_ISSUE or XAPM_LATENCY_ADDR_ACCEPT +* in xaxipmon.h. +* +* @return None +* +* @note Param can be 0 - XAPM_LATENCY_ADDR_ISSUE +* or 1 - XAPM_LATENCY_ADDR_ACCEPT +* +*******************************************************************************/ +void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + if (Param == XAPM_LATENCY_ADDR_ACCEPT) { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET, RegVal | XAPM_CR_RDLATENCY_START_MASK); + } + else { + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET, + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET) & ~(XAPM_CR_RDLATENCY_START_MASK)); + } +} + +/*****************************************************************************/ +/** +* +* This function sets Latency End point to calculate read latency. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Param is XAPM_LATENCY_LASTRD or XAPM_LATENCY_FIRSTRD +* in xaxipmon.h. +* +* @return None +* +* @note Param can be 0 - XAPM_LATENCY_LASTRD +* or 1 - XAPM_LATENCY_FIRSTRD +* +*******************************************************************************/ +void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + if (Param == XAPM_LATENCY_FIRSTRD) { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET, RegVal | XAPM_CR_RDLATENCY_END_MASK); + } + else { + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET, + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET) & ~(XAPM_CR_RDLATENCY_END_MASK)); + } +} + +/*****************************************************************************/ +/** +* +* This function returns Write Latency Start point. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Returns 0 - XAPM_LATENCY_ADDR_ISSUE or +* 1 - XAPM_LATENCY_ADDR_ACCEPT +* +* @note None +* +*******************************************************************************/ +u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr) +{ + u8 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + RegVal = RegVal & XAPM_CR_WRLATENCY_START_MASK; + if (RegVal != XAPM_LATENCY_ADDR_ISSUE) { + return XAPM_LATENCY_ADDR_ACCEPT; + } + else { + return XAPM_LATENCY_ADDR_ISSUE; + } +} + +/*****************************************************************************/ +/** +* +* This function returns Write Latency End point. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Returns 0 - XAPM_LATENCY_LASTWR or +* 1 - XAPM_LATENCY_FIRSTWR. +* +* @note None +* +*******************************************************************************/ +u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr) +{ + u8 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + RegVal = RegVal & XAPM_CR_WRLATENCY_END_MASK; + if (RegVal != XAPM_LATENCY_LASTWR) { + return XAPM_LATENCY_FIRSTWR; + } + else { + return XAPM_LATENCY_LASTWR; + } +} + +/*****************************************************************************/ +/** +* +* This function returns read Latency Start point. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Returns 0 - XAPM_LATENCY_ADDR_ISSUE or +* 1 - XAPM_LATENCY_ADDR_ACCEPT +* +* @note None +* +*******************************************************************************/ +u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr) +{ + u8 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + RegVal = RegVal & XAPM_CR_RDLATENCY_START_MASK; + + if (RegVal != XAPM_LATENCY_ADDR_ISSUE) { + return XAPM_LATENCY_ADDR_ACCEPT; + } + else { + return XAPM_LATENCY_ADDR_ISSUE; + } +} + +/*****************************************************************************/ +/** +* +* This function returns Read Latency End point. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Returns 0 - XAPM_LATENCY_LASTRD or +* 1 - XAPM_LATENCY_FIRSTRD. +* +* @note None +* +*******************************************************************************/ +u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr) +{ + u8 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + RegVal = RegVal & XAPM_CR_RDLATENCY_END_MASK; + if (RegVal != XAPM_LATENCY_LASTRD) { + return XAPM_LATENCY_FIRSTRD; + } + else { + return XAPM_LATENCY_LASTRD; + } + +} + +/****************************************************************************/ +/** +* +* This function sets Write ID Mask in ID Mask register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param WrMask is the Write ID mask to be written in ID register. +* +* @return None. +* +* @note +* If ID masking for write is of 32 bits(for Zynq MP APM) width then +* WrMask is written to XAPM_IDMASK_OFFSET or if it is 16 bit width +* then lower 16 bits of WrMask are written to XAPM_IDMASK_OFFSET. +* +*****************************************************************************/ +void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + RegVal = RegVal & ~(XAPM_MASKID_WID_MASK); + RegVal = RegVal | WrMask; + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET, RegVal); + } else { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET, WrMask); + } +} + +/****************************************************************************/ +/** +* +* This function sets Read ID Mask in ID Mask register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param RdMask is the Read ID mask to be written in ID Mask register. +* +* @return None. +* +* @note +* If ID masking for read is of 32 bits(for Zynq MP APM) width then +* RdMask is written to XAPM_RIDMASK_OFFSET or if it is 16 bit width +* then lower 16 bits of RdMask are written to XAPM_IDMASK_OFFSET. +* +*****************************************************************************/ +void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + RegVal = RegVal & ~(XAPM_MASKID_RID_MASK); + RegVal = RegVal | (RdMask << 16); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET, RegVal); + } else { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_RIDMASK_OFFSET, RdMask); + } +} + +/****************************************************************************/ +/** +* +* This function returns Write ID Mask in ID Mask register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return WrMask is the required Write ID Mask in ID Mask register. +* +* @note +* If ID masking for write is of 32 bits(for Zynq MP APM) width then +* 32 bit XAPM_IDMASK_OFFSET contents are returned or if it is 16 bit +* width then lower 16 bits of XAPM_IDMASK_OFFSET register +* are returned. +* +*****************************************************************************/ +u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr) +{ + + u32 WrMask; + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + WrMask = RegVal & XAPM_MASKID_WID_MASK; + } else { + WrMask = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + } + + return WrMask; +} + +/****************************************************************************/ +/** +* +* This function returns Read ID Mask in ID Mask register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return RdMask is the required Read ID Mask in ID Mask register. +* +* @note +* If ID masking for read is of 32 bits(for Zynq MP APM) width then +* 32 bit XAPM_RIDMASK_OFFSET contents are returned or if it is 16 bit +* width then higher 16 bits of XAPM_IDMASK_OFFSET register +* are returned. +* +*****************************************************************************/ +u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr) +{ + + u32 RdMask; + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + RegVal = RegVal & XAPM_MASKID_RID_MASK; + RdMask = RegVal >> 16; + } else { + RdMask = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_RIDMASK_OFFSET); + } + + return RdMask; +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon.h new file mode 100644 index 000000000..e21397108 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon.h @@ -0,0 +1,931 @@ +/****************************************************************************** +* +* Copyright (C) 2007 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xaxipmon.h +* +* The XAxiPmon driver supports the Xilinx AXI Performance Monitor device. +* +* The AXI Performance Monitor device provides following features: +* +* Configurable number of Metric Counters and Incrementers +* Computes performance metrics for Agents connected to +* monitor slots (Up to 8 slots) +* +* The following Metrics can be computed: +* +* Metrics computed for an AXI4 MM agent: +* Write Request Count: Total number of write requests by/to the agent. +* Read Request Count: Total number of read requests given by/to the +* agent. +* Read Latency: It is defined as the time from the start of read address +* transaction to the beginning of the read data service. +* Write Latency: It is defined as the period needed a master completes +* write data transaction, i.e. from write address +* transaction to write response from slave. +* Write Byte Count: Total number of bytes written by/to the agent. +* This metric is helpful when calculating the +* throughput of the system. +* Read Byte Count: Total number of bytes read from/by the agent. +* Average Write Latency: Average write latency seen by the agent. +* It can be derived from total write latency +* and the write request count. +* Average Read Latency: Average read latency seen by the agent. It can be +* derived from total read latency and the read +* request count. +* Master Write Idle Cycle Count: Number of idle cycles caused by the +* masters during write transactions to +* the slave. +* Slave Write Idle Cycle Count: Number of idle cycles caused by this slave +* during write transactions to the slave. +* Master Read Idle Cycle Count: Number of idle cycles caused by the +* master during read transactions to the +* slave. +* Slave Read Idle Cycle Count: Number of idle cycles caused by this slave +* during read transactions to the slave. +* +* Metrics computed for an AXI4-Stream agent: +* +* Transfer Cycle Count: Total number of writes by/to the agent. +* Data Byte Count: Total number of data bytes written by/to the agent. +* This metric helps in calculating the throughput +* of the system. +* Position Byte Count: Total number of position bytes transferred. +* Null Byte Count: Total number of null bytes transferred. +* Packet Count: Total number of packets transferred. +* +* There are three modes : Advanced, Profile and Trace. +* - Advanced mode has 10 Mertic Counters, Sampled Metric Counters, Incrementors +* and Sampled Incrementors. +* - Profile mode has only 47 Metric Counters and Sampled Metric Counters. +* - Trace mode has no Counters. +* User should refer to the hardware device specification for detailed +* information about the device. +* +* This header file contains the prototypes of driver functions that can +* be used to access the AXI Performance Monitor device. +* +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the AXI Performance Monitor device. +* +* XAxiPmon_CfgInitialize() API is used to initialize the AXI Performance Monitor +* device. The user needs to first call the XAxiPmon_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XAxiPmon_CfgInitialize() API. +* +* +* Interrupts +* +* The AXI Performance Monitor does not support Interrupts +* +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* +* Building the driver +* +* The XAxiPmon driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* Limitations of the driver +* +* +*

+* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    02/27/12 First release
+* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
+* 3.00a bss    09/03/12 To support v2_01_a version of IP:
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			added XAPM_FLAG_EVENT, XAPM_FLAG_EVNTSTAR,
+*			XAPM_FLAG_EVNTSTOP.
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
+*			in xaxipmon.c
+*			Deleted XAPM_AGENT_OFFSET Macro in xaxipmon_hw.h
+* 3.01a bss    10/25/12 To support new version of IP:
+*			Added XAPM_MCXLOGEN_OFFSET macros in xaxipmon_hw.h.
+*			Added XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
+*			Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
+*			(CR #683746) in xaxipmon.c
+*			Added XAxiPmon_EnableEventLog,
+*			XAxiPmon_DisableMetricsCounter,
+*			XAxiPmon_EnableMetricsCounter APIs in xaxipmon.c to
+*			replace macros in this file.
+*			Added XAPM_FLAG_XXX macros.
+*			Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
+*			APIs (CR #683799).
+*			Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
+*			APIs (CR #683801).
+*			Added XAxiPmon_GetMetricName API (CR #683803).
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent
+*			declarations (CR #677337)
+* 4.00a bss    01/17/13 To support new version of IP:
+*			Added XAPM_METRIC_SET_12 to XAPM_METRIC_SET_15 macros.
+*			Added XAxiPmon_SetLogEnableRanges,
+*	  		XAxiPmon_GetLogEnableRanges,
+*			XAxiPmon_EnableMetricCounterTrigger,
+*			XAxiPmon_DisableMetricCounterTrigger,
+*			XAxiPmon_EnableEventLogTrigger,
+*			XAxiPmon_DisableEventLogTrigger,
+*			XAxiPmon_SetWriteLatencyId,
+*			XAxiPmon_SetReadLatencyId,
+*			XAxiPmon_GetWriteLatencyId,
+*			XAxiPmon_GetReadLatencyId APIs and removed
+*			XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
+*			Added XAPM_LATENCYID_OFFSET,
+*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
+*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK in
+*			xaxipmon_hw.h
+* 5.00a bss   08/26/13  To support new version of IP:
+*			XAxiPmon_SampleMetrics Macro.
+*			Modified XAxiPmon_CfgInitialize, Assert functions
+*			Added XAxiPmon_GetMetricCounter,
+*			XAxiPmon_SetSampleInterval, XAxiPmon_GetSampleInterval,
+*			XAxiPmon_SetWrLatencyStart, XAxiPmon_SetWrLatencyEnd,
+*			XAxiPmon_SetRdLatencyStart, XAxiPmon_SetRdLatencyEnd,
+*			XAxiPmon_GetWrLatencyStart, XAxiPmon_GetWrLatencyEnd,
+*			XAxiPmon_GetRdLatencyStart, XAxiPmon_GetRdLatencyEnd,
+*			XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
+*			XAxiPmon_GetWriteIdMask and XAxiPmon_GetReadIdMask APIs
+*			Renamed :
+*			XAxiPmon_SetWriteLatencyId to
+*			XAxiPmon_SetWriteId, XAxiPmon_SetReadLatencyId to
+*			XAxiPmon_SetReadId, XAxiPmon_GetWriteLatencyId to
+*			XAxiPmon_GetWriteId and XAxiPmon_SetReadLatencyId to
+*			XAxiPmon_GetReadId. in xaxipmon.c
+*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
+*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET,
+*			XAPM_IDMASK_OFFSET, XAPM_CR_IDFILTER_ENABLE_MASK,
+*			XAPM_CR_WRLATENCY_START_MASK,
+*			XAPM_CR_WRLATENCY_END_MASK,
+*			XAPM_CR_RDLATENCY_START_MASK,
+*			XAPM_CR_RDLATENCY_END_MASK and
+*			XAPM_MAX_COUNTERS_PROFILE.
+*			Renamed:
+*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
+*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
+*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
+*			in xaxipmon_hw.h.
+*			Modified driver tcl to generate new parameters
+*			ScaleFactor, ModeProfile, ModeTrace and ModeAdvanced
+*			in Config structure.
+* 6.0   adk  19/12/13 Updated as per the New Tcl API's
+* 6.1   adk  16/04/14 Updated the driver tcl for the newly added parameters in
+* 		      The Axi pmon IP.
+* 6.2   bss  04/21/14   Updated XAxiPmon_CfgInitialize in xaxipmon.c to Reset
+*			counters and FIFOs based on Modes(CR#782671). And if
+*			both profile and trace modes are present set mode as
+*			Advanced.
+* 6.2	bss  03/02/15	To support Zynq MP APM:
+*						Added Is32BitFiltering in XAxiPmon_Config structure.
+*						Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
+*						XAxiPmon_GetWriteId, XAxiPmon_GetReadId
+*						XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask
+*						XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
+*						functions in xaxipmon.c.
+*						Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET in
+*						xaxipmon_hw.h
+*
+*
+* +*****************************************************************************/ +#ifndef XAXIPMON_H /* Prevent circular inclusions */ +#define XAXIPMON_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xaxipmon_hw.h" + +/************************** Constant Definitions ****************************/ + + +/** + * @name Macro for Maximum number of Counters + * + * @{ + */ +#define XAPM_MAX_COUNTERS 10 /**< Maximum number of Counters */ +#define XAPM_MAX_COUNTERS_PROFILE 48 /**< Maximum number of Counters */ + +/*@}*/ + + +/** + * @name Indices for Metric Counters and Sampled Metric Coounters used with + * XAxiPmon_GetMetricCounter and XAxiPmon_GetSampledMetricCounter APIs + * @{ + */ + +#define XAPM_METRIC_COUNTER_0 0 /**< Metric Counter 0 Register Index */ +#define XAPM_METRIC_COUNTER_1 1 /**< Metric Counter 1 Register Index */ +#define XAPM_METRIC_COUNTER_2 2 /**< Metric Counter 2 Register Index */ +#define XAPM_METRIC_COUNTER_3 3 /**< Metric Counter 3 Register Index */ +#define XAPM_METRIC_COUNTER_4 4 /**< Metric Counter 4 Register Index */ +#define XAPM_METRIC_COUNTER_5 5 /**< Metric Counter 5 Register Index */ +#define XAPM_METRIC_COUNTER_6 6 /**< Metric Counter 6 Register Index */ +#define XAPM_METRIC_COUNTER_7 7 /**< Metric Counter 7 Register Index */ +#define XAPM_METRIC_COUNTER_8 8 /**< Metric Counter 8 Register Index */ +#define XAPM_METRIC_COUNTER_9 9 /**< Metric Counter 9 Register Index */ + +/*@}*/ + +/** + * @name Indices for Incrementers and Sampled Incrementers used with + * XAxiPmon_GetIncrementer and XAxiPmon_GetSampledIncrementer APIs + * @{ + */ + +#define XAPM_INCREMENTER_0 0 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_1 1 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_2 2 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_3 3 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_4 4 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_5 5 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_6 6 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_7 7 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_8 8 /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_9 9 /**< Metric Counter 0 Register Index */ + +/*@}*/ + +/** + * @name Macros for Metric Selector Settings + * @{ + */ + +#define XAPM_METRIC_SET_0 0 /**< Write Transaction Count */ +#define XAPM_METRIC_SET_1 1 /**< Read Transaction Count */ +#define XAPM_METRIC_SET_2 2 /**< Write Byte Count */ +#define XAPM_METRIC_SET_3 3 /**< Read Byte Count */ +#define XAPM_METRIC_SET_4 4 /**< Write Beat Count */ +#define XAPM_METRIC_SET_5 5 /**< Total Read Latency */ +#define XAPM_METRIC_SET_6 6 /**< Total Write Latency */ +#define XAPM_METRIC_SET_7 7 /**< Slv_Wr_Idle_Cnt */ +#define XAPM_METRIC_SET_8 8 /**< Mst_Rd_Idle_Cnt */ +#define XAPM_METRIC_SET_9 9 /**< Num_BValids */ +#define XAPM_METRIC_SET_10 10 /**< Num_WLasts */ +#define XAPM_METRIC_SET_11 11 /**< Num_RLasts */ +#define XAPM_METRIC_SET_12 12 /**< Minimum Write Latency */ +#define XAPM_METRIC_SET_13 13 /**< Maximum Write Latency */ +#define XAPM_METRIC_SET_14 14 /**< Minimum Read Latency */ +#define XAPM_METRIC_SET_15 15 /**< Maximum Read Latency */ +#define XAPM_METRIC_SET_16 16 /**< Transfer Cycle Count */ +#define XAPM_METRIC_SET_17 17 /**< Packet Count */ +#define XAPM_METRIC_SET_18 18 /**< Data Byte Count */ +#define XAPM_METRIC_SET_19 19 /**< Position Byte Count */ +#define XAPM_METRIC_SET_20 20 /**< Null Byte Count */ +#define XAPM_METRIC_SET_21 21 /**< Slv_Idle_Cnt */ +#define XAPM_METRIC_SET_22 22 /**< Mst_Idle_Cnt */ +#define XAPM_METRIC_SET_30 30 /**< External event count */ + + +/*@}*/ + + +/** + * @name Macros for Maximum number of Agents + * @{ + */ + +#define XAPM_MAX_AGENTS 8 /**< Maximum number of Agents */ + +/*@}*/ + +/** + * @name Macros for Flags in Flag Enable Control Register + * @{ + */ + +#define XAPM_FLAG_WRADDR 0x00000001 /**< Write Address Flag */ +#define XAPM_FLAG_FIRSTWR 0x00000002 /**< First Write Flag */ +#define XAPM_FLAG_LASTWR 0x00000004 /**< Last Write Flag */ +#define XAPM_FLAG_RESPONSE 0x00000008 /**< Response Flag */ +#define XAPM_FLAG_RDADDR 0x00000010 /**< Read Address Flag */ +#define XAPM_FLAG_FIRSTRD 0x00000020 /**< First Read Flag */ +#define XAPM_FLAG_LASTRD 0x00000040 /**< Last Read Flag */ +#define XAPM_FLAG_SWDATA 0x00010000 /**< Software-written Data Flag */ +#define XAPM_FLAG_EVENT 0x00020000 /**< Last Read Flag */ +#define XAPM_FLAG_EVNTSTOP 0x00040000 /**< Last Read Flag */ +#define XAPM_FLAG_EVNTSTART 0x00080000 /**< Last Read Flag */ +#define XAPM_FLAG_GCCOVF 0x00100000 /**< Global Clock Counter Overflow + * Flag */ +#define XAPM_FLAG_SCLAPSE 0x00200000 /**< Sample Counter Lapse Flag */ +#define XAPM_FLAG_MC0 0x00400000 /**< Metric Counter 0 Flag */ +#define XAPM_FLAG_MC1 0x00800000 /**< Metric Counter 1 Flag */ +#define XAPM_FLAG_MC2 0x01000000 /**< Metric Counter 2 Flag */ +#define XAPM_FLAG_MC3 0x02000000 /**< Metric Counter 3 Flag */ +#define XAPM_FLAG_MC4 0x04000000 /**< Metric Counter 4 Flag */ +#define XAPM_FLAG_MC5 0x08000000 /**< Metric Counter 5 Flag */ +#define XAPM_FLAG_MC6 0x10000000 /**< Metric Counter 6 Flag */ +#define XAPM_FLAG_MC7 0x20000000 /**< Metric Counter 7 Flag */ +#define XAPM_FLAG_MC8 0x40000000 /**< Metric Counter 8 Flag */ +#define XAPM_FLAG_MC9 0x80000000 /**< Metric Counter 9 Flag */ + +/*@}*/ + +/** + * @name Macros for Read/Write Latency Start and End points + * @{ + */ +#define XAPM_LATENCY_ADDR_ISSUE 0 /**< Address Issue as start + point for Latency calculation*/ +#define XAPM_LATENCY_ADDR_ACCEPT 1 /**< Address Acceptance as start + point for Latency calculation*/ +#define XAPM_LATENCY_LASTRD 0 /**< Last Read as end point for + Latency calculation */ +#define XAPM_LATENCY_LASTWR 0 /**< Last Write as end point for + Latency calculation */ +#define XAPM_LATENCY_FIRSTRD 1 /**< First Read as end point for + Latency calculation */ +#define XAPM_LATENCY_FIRSTWR 1 /**< First Write as end point for + Latency calculation */ + +/*@}*/ + +/** + * @name Macros for Modes of APM + * @{ + */ + +#define XAPM_MODE_TRACE 2 /**< APM in Trace mode */ + +#define XAPM_MODE_PROFILE 1 /**< APM in Profile mode */ + +#define XAPM_MODE_ADVANCED 0 /**< APM in Advanced mode */ + +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the AXI Performance + * Monitor device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Device base address */ + int GlobalClkCounterWidth; /**< Global Clock Counter Width */ + int MetricSampleCounterWidth ; /**< Metric Sample Counters Width */ + u8 IsEventCount; /**< Event Count Enabled 1 - enabled + 0 - not enabled */ + u8 NumberofSlots; /**< Number of Monitor Slots */ + u8 NumberofCounters; /**< Number of Counters */ + u8 HaveSampledCounters; /**< Have Sampled Counters 1 - present + 0 - Not present */ + u8 IsEventLog; /**< Event Logging Enabled 1 - enabled + 0 - Not enabled */ + u32 FifoDepth; /**< Event Log FIFO Depth */ + u32 FifoWidth; /**< Event Log FIFO Width */ + u32 TidWidth; /**< Streaming Interface TID Width */ + u8 ScaleFactor; /**< Event Count Scaling factor */ + u8 ModeAdvanced; /**< Advanced Mode */ + u8 ModeProfile; /**< Profile Mode */ + u8 ModeTrace; /**< Trace Mode */ + u8 Is32BitFiltering; /**< 32 bit filtering enabled */ +} XAxiPmon_Config; + + +/** + * The driver's instance data. The user is required to allocate a variable + * of this type for every AXI Performance Monitor device in system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XAxiPmon_Config Config; /**< XAxiPmon_Config of current device */ + u32 IsReady; /**< Device is initialized and ready */ + u8 Mode; /**< APM Mode */ +} XAxiPmon; + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/****************************************************************************/ +/** +* +* This routine enables the Global Interrupt. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrGlobalEnable(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_IntrGlobalEnable(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \ + XAPM_GIE_OFFSET, 1) + + +/****************************************************************************/ +/** +* +* This routine disables the Global Interrupt. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrGlobalDisable(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_IntrGlobalDisable(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \ + XAPM_GIE_OFFSET, 0) + + +/****************************************************************************/ +/** +* +* This routine enables interrupt(s). Use the XAPM_IXR_* constants defined in +* xaxipmon_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Mask is the mask to enable. Bit positions of 1 will be enabled. +* Bit positions of 0 will keep the previous setting. This mask is +* formed by OR'ing XAPM_IXR__* bits defined in xaxipmon_hw.h. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XAxiPmon_IntrEnable(InstancePtr, Mask) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IE_OFFSET) | Mask); + + +/****************************************************************************/ +/** +* +* This routine disable interrupt(s). Use the XAPM_IXR_* constants defined in +* xaxipmon_hw.h to create the bit-mask to disable interrupts. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Mask is the mask to disable. Bit positions of 1 will be +* disabled. Bit positions of 0 will keep the previous setting. +* This mask is formed by OR'ing XAPM_IXR_* bits defined in +* xaxipmon_hw.h. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XAxiPmon_IntrDisable(InstancePtr, Mask) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IE_OFFSET) | Mask); + +/****************************************************************************/ +/** +* +* This routine clears the specified interrupt(s). +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* This mask is formed by OR'ing XAPM_IXR_* bits defined in +* xaxipmon_hw.h. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XAxiPmon_IntrClear(InstancePtr, Mask) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IS_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IS_OFFSET) | Mask); + +/****************************************************************************/ +/** +* +* This routine returns the Interrupt Status Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Interrupt Status Register contents +* +* @note C-Style signature: +* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_IntrGetStatus(InstancePtr) \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IS_OFFSET); + +/****************************************************************************/ +/** +* +* This function enables the Global Clock Counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableGlobalClkCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK); + +/****************************************************************************/ +/** +* +* This function disbles the Global Clock Counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableGlobalClkCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK)); + +/****************************************************************************/ +/** +* +* This function enables the specified flag in Flag Control Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableFlag(InstancePtr, Flag) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_FEC_OFFSET) | Flag); + +/****************************************************************************/ +/** +* +* This function disables the specified flag in Flag Control Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableFlag(InstancePtr, Flag) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_FEC_OFFSET) & ~(Flag)); + +/****************************************************************************/ +/** +* +* This function loads the sample interval register value into the sample +* interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_LoadSampleIntervalCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \ + XAPM_SICR_LOAD_MASK); + + + +/****************************************************************************/ +/** +* +* This enables the down count of the sample interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableSampleIntervalCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\ + XAPM_SICR_ENABLE_MASK); + + +/****************************************************************************/ +/** +* +* This disables the down count of the sample interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableSampleIntervalCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK)); + +/****************************************************************************/ +/** +* +* This enables Reset of Metric Counters when Sample Interval Counter lapses. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableMetricCounterReset(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\ + XAPM_SICR_MCNTR_RST_MASK); + +/****************************************************************************/ +/** +* +* This disables the down count of the sample interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableMetricCounterReset(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK)); + +/****************************************************************************/ +/** +* +* This function enables the ID Filter Masking. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_EnableIDFilter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK); + +/****************************************************************************/ +/** +* +* This function disbles the ID Filter masking. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_DisableIDFilter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK)); + +/****************************************************************************/ +/** +* +* This function samples Metric Counters to Sampled Metric Counters by +* reading Sample Register and also returns interval. i.e. the number of +* clocks in between previous read to the current read of sample register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Interval. i.e. the number of clocks in between previous +* read to the current read of sample register. +* +* @note C-Style signature: +* u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr); +* +*****************************************************************************/ +#define XAxiPmon_SampleMetrics(InstancePtr) \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, XAPM_SR_OFFSET); + + +/************************** Function Prototypes *****************************/ + +/** + * Functions in xaxipmon_sinit.c + */ +XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId); + +/** + * Functions in xaxipmon.c + */ +int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, + XAxiPmon_Config *ConfigPtr, u32 EffectiveAddr); + +int XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr); + +void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr); + +int XAxiPmon_ResetFifo(XAxiPmon *InstancePtr); + +void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 RangeUpper, u16 RangeLower); + +void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 *RangeUpper, u16 *RangeLower); + +void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval); + +void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval); + +int XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics, + u8 CounterNum); + +int XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics, + u8 *Slot); +void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue, + u32 *CntLowValue); + +u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum); + +u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum); + +u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum); + +u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum); + +void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData); + +u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr); + +int XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables); + +int XAxiPmon_StopEventLog(XAxiPmon *InstancePtr); + +int XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval); + +int XAxiPmon_StopCounters(XAxiPmon *InstancePtr); + +void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr); + +void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr); + +void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 RangeUpper, u16 RangeLower); + +void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 *RangeUpper, u16 *RangeLower); + +void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr); + +void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr); + +void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr); + +void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr); + +void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr); + +const char * XAxiPmon_GetMetricName(u8 Metrics); + +void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId); + +void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId); + +u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr); + +u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr); + +void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param); + +void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param); + +void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param); + +void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param); + +u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr); + +u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr); + +u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr); + +u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr); + +void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask); + +void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask); + +u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr); + +u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr); + + +/** + * Functions in xaxipmon_selftest.c + */ +int XAxiPmon_SelfTest(XAxiPmon *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_g.c new file mode 100644 index 000000000..4d55182e1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_g.c @@ -0,0 +1,127 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xaxipmon.h" + +/* +* The configuration table for devices +*/ + +XAxiPmon_Config XAxiPmon_ConfigTable[] = +{ + { + XPAR_PSU_APM_0_DEVICE_ID, + XPAR_PSU_APM_0_BASEADDR, + XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH, + XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH, + XPAR_PSU_APM_0_ENABLE_EVENT_COUNT, + XPAR_PSU_APM_0_NUM_MONITOR_SLOTS, + XPAR_PSU_APM_0_NUM_OF_COUNTERS, + XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT, + XPAR_PSU_APM_0_ENABLE_EVENT_LOG, + XPAR_PSU_APM_0_FIFO_AXIS_DEPTH, + XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH, + XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH, + XPAR_PSU_APM_0_METRIC_COUNT_SCALE, + XPAR_PSU_APM_0_ENABLE_ADVANCED, + XPAR_PSU_APM_0_ENABLE_PROFILE, + XPAR_PSU_APM_0_ENABLE_TRACE, + XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID + }, + { + XPAR_PSU_APM_1_DEVICE_ID, + XPAR_PSU_APM_1_BASEADDR, + XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH, + XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH, + XPAR_PSU_APM_1_ENABLE_EVENT_COUNT, + XPAR_PSU_APM_1_NUM_MONITOR_SLOTS, + XPAR_PSU_APM_1_NUM_OF_COUNTERS, + XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT, + XPAR_PSU_APM_1_ENABLE_EVENT_LOG, + XPAR_PSU_APM_1_FIFO_AXIS_DEPTH, + XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH, + XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH, + XPAR_PSU_APM_1_METRIC_COUNT_SCALE, + XPAR_PSU_APM_1_ENABLE_ADVANCED, + XPAR_PSU_APM_1_ENABLE_PROFILE, + XPAR_PSU_APM_1_ENABLE_TRACE, + XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID + }, + { + XPAR_PSU_APM_2_DEVICE_ID, + XPAR_PSU_APM_2_BASEADDR, + XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH, + XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH, + XPAR_PSU_APM_2_ENABLE_EVENT_COUNT, + XPAR_PSU_APM_2_NUM_MONITOR_SLOTS, + XPAR_PSU_APM_2_NUM_OF_COUNTERS, + XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT, + XPAR_PSU_APM_2_ENABLE_EVENT_LOG, + XPAR_PSU_APM_2_FIFO_AXIS_DEPTH, + XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH, + XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH, + XPAR_PSU_APM_2_METRIC_COUNT_SCALE, + XPAR_PSU_APM_2_ENABLE_ADVANCED, + XPAR_PSU_APM_2_ENABLE_PROFILE, + XPAR_PSU_APM_2_ENABLE_TRACE, + XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID + }, + { + XPAR_PSU_APM_5_DEVICE_ID, + XPAR_PSU_APM_5_BASEADDR, + XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH, + XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH, + XPAR_PSU_APM_5_ENABLE_EVENT_COUNT, + XPAR_PSU_APM_5_NUM_MONITOR_SLOTS, + XPAR_PSU_APM_5_NUM_OF_COUNTERS, + XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT, + XPAR_PSU_APM_5_ENABLE_EVENT_LOG, + XPAR_PSU_APM_5_FIFO_AXIS_DEPTH, + XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH, + XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH, + XPAR_PSU_APM_5_METRIC_COUNT_SCALE, + XPAR_PSU_APM_5_ENABLE_ADVANCED, + XPAR_PSU_APM_5_ENABLE_PROFILE, + XPAR_PSU_APM_5_ENABLE_TRACE, + XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_hw.h new file mode 100644 index 000000000..7fc4ae088 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_hw.h @@ -0,0 +1,566 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xaxipmon_hw.h +* +* This header file contains identifiers and basic driver functions (or +* macros) that can be used to access the AXI Performance Monitor. +* +* Refer to the device specification for more information about this driver. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    02/27/12 First release
+* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
+* 3.00a bss    09/03/12 Deleted XAPM_AGENT_OFFSET Macro to support
+*			v2_01a version of IP.
+* 3.01a bss    10/25/12 To support new version of IP:
+*			Added XAPM_MCXLOGEN_OFFSET and
+*			XAPM_CR_EXTERNAL_TRIGGER_MASK macros.
+* 4.00a bss    01/17/13 To support new version of IP:
+*			Added XAPM_LATENCYID_OFFSET,
+*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
+*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK
+* 5.00a bss   08/26/13  To support new version of IP:
+*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
+*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET.
+*			Added macro XAPM_IDMASK_OFFSET, XAPM_SR_OFFSET.
+*			Added XAPM_CR_IDFILTER_ENABLE_MASK,
+*			XAPM_CR_WRLATENCY_START_MASK,
+*			XAPM_CR_WRLATENCY_END_MASK,
+*			XAPM_CR_RDLATENCY_START_MASK,
+*			XAPM_CR_RDLATENCY_END_MASK, XAPM_MASKID_RID_MASK
+*			and XAPM_MASKID_WID_MASK macros.
+*			Renamed:
+*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
+*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
+*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
+*
+* 6.2  bss  03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
+*					 Zynq MP APM.
+*
+* +*****************************************************************************/ +#ifndef XAXIPMON_HW_H /* Prevent circular inclusions */ +#define XAXIPMON_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ + + +/**@name Register offsets of AXIMONITOR in the Device Config + * + * The following constants provide access to each of the registers of the + * AXI PERFORMANCE MONITOR device. + * @{ + */ + +#define XAPM_GCC_HIGH_OFFSET 0x0000 /**< Global Clock Counter + 32 to 63 bits */ +#define XAPM_GCC_LOW_OFFSET 0x0004 /**< Global Clock Counter Lower + 0-31 bits */ +#define XAPM_SI_HIGH_OFFSET 0x0020 /**< Sample Interval MSB */ +#define XAPM_SI_LOW_OFFSET 0x0024 /**< Sample Interval LSB */ +#define XAPM_SICR_OFFSET 0x0028 /**< Sample Interval Control + Register */ +#define XAPM_SR_OFFSET 0x002C /**< Sample Register */ +#define XAPM_GIE_OFFSET 0x0030 /**< Global Interrupt Enable + Register */ +#define XAPM_IE_OFFSET 0x0034 /**< Interrupt Enable Register */ +#define XAPM_IS_OFFSET 0x0038 /**< Interrupt Status Register */ + +#define XAPM_MSR0_OFFSET 0x0044 /**< Metric Selector 0 Register */ +#define XAPM_MSR1_OFFSET 0x0048 /**< Metric Selector 1 Register */ +#define XAPM_MSR2_OFFSET 0x004C /**< Metric Selector 2 Register */ + +#define XAPM_MC0_OFFSET 0x0100 /**< Metric Counter 0 Register */ +#define XAPM_INC0_OFFSET 0x0104 /**< Incrementer 0 Register */ +#define XAPM_RANGE0_OFFSET 0x0108 /**< Range 0 Register */ +#define XAPM_MC0LOGEN_OFFSET 0x010C /**< Metric Counter 0 + Log Enable Register */ +#define XAPM_MC1_OFFSET 0x0110 /**< Metric Counter 1 Register */ +#define XAPM_INC1_OFFSET 0x0114 /**< Incrementer 1 Register */ +#define XAPM_RANGE1_OFFSET 0x0118 /**< Range 1 Register */ +#define XAPM_MC1LOGEN_OFFSET 0x011C /**< Metric Counter 1 + Log Enable Register */ +#define XAPM_MC2_OFFSET 0x0120 /**< Metric Counter 2 Register */ +#define XAPM_INC2_OFFSET 0x0124 /**< Incrementer 2 Register */ +#define XAPM_RANGE2_OFFSET 0x0128 /**< Range 2 Register */ +#define XAPM_MC2LOGEN_OFFSET 0x012C /**< Metric Counter 2 + Log Enable Register */ +#define XAPM_MC3_OFFSET 0x0130 /**< Metric Counter 3 Register */ +#define XAPM_INC3_OFFSET 0x0134 /**< Incrementer 3 Register */ +#define XAPM_RANGE3_OFFSET 0x0138 /**< Range 3 Register */ +#define XAPM_MC3LOGEN_OFFSET 0x013C /**< Metric Counter 3 + Log Enable Register */ +#define XAPM_MC4_OFFSET 0x0140 /**< Metric Counter 4 Register */ +#define XAPM_INC4_OFFSET 0x0144 /**< Incrementer 4 Register */ +#define XAPM_RANGE4_OFFSET 0x0148 /**< Range 4 Register */ +#define XAPM_MC4LOGEN_OFFSET 0x014C /**< Metric Counter 4 + Log Enable Register */ +#define XAPM_MC5_OFFSET 0x0150 /**< Metric Counter 5 + Register */ +#define XAPM_INC5_OFFSET 0x0154 /**< Incrementer 5 Register */ +#define XAPM_RANGE5_OFFSET 0x0158 /**< Range 5 Register */ +#define XAPM_MC5LOGEN_OFFSET 0x015C /**< Metric Counter 5 + Log Enable Register */ +#define XAPM_MC6_OFFSET 0x0160 /**< Metric Counter 6 + Register */ +#define XAPM_INC6_OFFSET 0x0164 /**< Incrementer 6 Register */ +#define XAPM_RANGE6_OFFSET 0x0168 /**< Range 6 Register */ +#define XAPM_MC6LOGEN_OFFSET 0x016C /**< Metric Counter 6 + Log Enable Register */ +#define XAPM_MC7_OFFSET 0x0170 /**< Metric Counter 7 + Register */ +#define XAPM_INC7_OFFSET 0x0174 /**< Incrementer 7 Register */ +#define XAPM_RANGE7_OFFSET 0x0178 /**< Range 7 Register */ +#define XAPM_MC7LOGEN_OFFSET 0x017C /**< Metric Counter 7 + Log Enable Register */ +#define XAPM_MC8_OFFSET 0x0180 /**< Metric Counter 8 + Register */ +#define XAPM_INC8_OFFSET 0x0184 /**< Incrementer 8 Register */ +#define XAPM_RANGE8_OFFSET 0x0188 /**< Range 8 Register */ +#define XAPM_MC8LOGEN_OFFSET 0x018C /**< Metric Counter 8 + Log Enable Register */ +#define XAPM_MC9_OFFSET 0x0190 /**< Metric Counter 9 + Register */ +#define XAPM_INC9_OFFSET 0x0194 /**< Incrementer 9 Register */ +#define XAPM_RANGE9_OFFSET 0x0198 /**< Range 9 Register */ +#define XAPM_MC9LOGEN_OFFSET 0x019C /**< Metric Counter 9 + Log Enable Register */ +#define XAPM_SMC0_OFFSET 0x0200 /**< Sampled Metric Counter + 0 Register */ +#define XAPM_SINC0_OFFSET 0x0204 /**< Sampled Incrementer + 0 Register */ +#define XAPM_SMC1_OFFSET 0x0210 /**< Sampled Metric Counter + 1 Register */ +#define XAPM_SINC1_OFFSET 0x0214 /**< Sampled Incrementer + 1 Register */ +#define XAPM_SMC2_OFFSET 0x0220 /**< Sampled Metric Counter + 2 Register */ +#define XAPM_SINC2_OFFSET 0x0224 /**< Sampled Incrementer + 2 Register */ +#define XAPM_SMC3_OFFSET 0x0230 /**< Sampled Metric Counter + 3 Register */ +#define XAPM_SINC3_OFFSET 0x0234 /**< Sampled Incrementer + 3 Register */ +#define XAPM_SMC4_OFFSET 0x0240 /**< Sampled Metric Counter + 4 Register */ +#define XAPM_SINC4_OFFSET 0x0244 /**< Sampled Incrementer + 4 Register */ +#define XAPM_SMC5_OFFSET 0x0250 /**< Sampled Metric Counter + 5 Register */ +#define XAPM_SINC5_OFFSET 0x0254 /**< Sampled Incrementer + 5 Register */ +#define XAPM_SMC6_OFFSET 0x0260 /**< Sampled Metric Counter + 6 Register */ +#define XAPM_SINC6_OFFSET 0x0264 /**< Sampled Incrementer + 6 Register */ +#define XAPM_SMC7_OFFSET 0x0270 /**< Sampled Metric Counter + 7 Register */ +#define XAPM_SINC7_OFFSET 0x0274 /**< Sampled Incrementer + 7 Register */ +#define XAPM_SMC8_OFFSET 0x0280 /**< Sampled Metric Counter + 8 Register */ +#define XAPM_SINC8_OFFSET 0x0284 /**< Sampled Incrementer + 8 Register */ +#define XAPM_SMC9_OFFSET 0x0290 /**< Sampled Metric Counter + 9 Register */ +#define XAPM_SINC9_OFFSET 0x0294 /**< Sampled Incrementer + 9 Register */ + +#define XAPM_MC10_OFFSET 0x01A0 /**< Metric Counter 10 + Register */ +#define XAPM_MC11_OFFSET 0x01B0 /**< Metric Counter 11 + Register */ +#define XAPM_MC12_OFFSET 0x0500 /**< Metric Counter 12 + Register */ +#define XAPM_MC13_OFFSET 0x0510 /**< Metric Counter 13 + Register */ +#define XAPM_MC14_OFFSET 0x0520 /**< Metric Counter 14 + Register */ +#define XAPM_MC15_OFFSET 0x0530 /**< Metric Counter 15 + Register */ +#define XAPM_MC16_OFFSET 0x0540 /**< Metric Counter 16 + Register */ +#define XAPM_MC17_OFFSET 0x0550 /**< Metric Counter 17 + Register */ +#define XAPM_MC18_OFFSET 0x0560 /**< Metric Counter 18 + Register */ +#define XAPM_MC19_OFFSET 0x0570 /**< Metric Counter 19 + Register */ +#define XAPM_MC20_OFFSET 0x0580 /**< Metric Counter 20 + Register */ +#define XAPM_MC21_OFFSET 0x0590 /**< Metric Counter 21 + Register */ +#define XAPM_MC22_OFFSET 0x05A0 /**< Metric Counter 22 + Register */ +#define XAPM_MC23_OFFSET 0x05B0 /**< Metric Counter 23 + Register */ +#define XAPM_MC24_OFFSET 0x0700 /**< Metric Counter 24 + Register */ +#define XAPM_MC25_OFFSET 0x0710 /**< Metric Counter 25 + Register */ +#define XAPM_MC26_OFFSET 0x0720 /**< Metric Counter 26 + Register */ +#define XAPM_MC27_OFFSET 0x0730 /**< Metric Counter 27 + Register */ +#define XAPM_MC28_OFFSET 0x0740 /**< Metric Counter 28 + Register */ +#define XAPM_MC29_OFFSET 0x0750 /**< Metric Counter 29 + Register */ +#define XAPM_MC30_OFFSET 0x0760 /**< Metric Counter 30 + Register */ +#define XAPM_MC31_OFFSET 0x0770 /**< Metric Counter 31 + Register */ +#define XAPM_MC32_OFFSET 0x0780 /**< Metric Counter 32 + Register */ +#define XAPM_MC33_OFFSET 0x0790 /**< Metric Counter 33 + Register */ +#define XAPM_MC34_OFFSET 0x07A0 /**< Metric Counter 34 + Register */ +#define XAPM_MC35_OFFSET 0x07B0 /**< Metric Counter 35 + Register */ +#define XAPM_MC36_OFFSET 0x0900 /**< Metric Counter 36 + Register */ +#define XAPM_MC37_OFFSET 0x0910 /**< Metric Counter 37 + Register */ +#define XAPM_MC38_OFFSET 0x0920 /**< Metric Counter 38 + Register */ +#define XAPM_MC39_OFFSET 0x0930 /**< Metric Counter 39 + Register */ +#define XAPM_MC40_OFFSET 0x0940 /**< Metric Counter 40 + Register */ +#define XAPM_MC41_OFFSET 0x0950 /**< Metric Counter 41 + Register */ +#define XAPM_MC42_OFFSET 0x0960 /**< Metric Counter 42 + Register */ +#define XAPM_MC43_OFFSET 0x0970 /**< Metric Counter 43 + Register */ +#define XAPM_MC44_OFFSET 0x0980 /**< Metric Counter 44 + Register */ +#define XAPM_MC45_OFFSET 0x0990 /**< Metric Counter 45 + Register */ +#define XAPM_MC46_OFFSET 0x09A0 /**< Metric Counter 46 + Register */ +#define XAPM_MC47_OFFSET 0x09B0 /**< Metric Counter 47 + Register */ + +#define XAPM_SMC10_OFFSET 0x02A0 /**< Sampled Metric Counter + 10 Register */ +#define XAPM_SMC11_OFFSET 0x02B0 /**< Sampled Metric Counter + 11 Register */ +#define XAPM_SMC12_OFFSET 0x0600 /**< Sampled Metric Counter + 12 Register */ +#define XAPM_SMC13_OFFSET 0x0610 /**< Sampled Metric Counter + 13 Register */ +#define XAPM_SMC14_OFFSET 0x0620 /**< Sampled Metric Counter + 14 Register */ +#define XAPM_SMC15_OFFSET 0x0630 /**< Sampled Metric Counter + 15 Register */ +#define XAPM_SMC16_OFFSET 0x0640 /**< Sampled Metric Counter + 16 Register */ +#define XAPM_SMC17_OFFSET 0x0650 /**< Sampled Metric Counter + 17 Register */ +#define XAPM_SMC18_OFFSET 0x0660 /**< Sampled Metric Counter + 18 Register */ +#define XAPM_SMC19_OFFSET 0x0670 /**< Sampled Metric Counter + 19 Register */ +#define XAPM_SMC20_OFFSET 0x0680 /**< Sampled Metric Counter + 20 Register */ +#define XAPM_SMC21_OFFSET 0x0690 /**< Sampled Metric Counter + 21 Register */ +#define XAPM_SMC22_OFFSET 0x06A0 /**< Sampled Metric Counter + 22 Register */ +#define XAPM_SMC23_OFFSET 0x06B0 /**< Sampled Metric Counter + 23 Register */ +#define XAPM_SMC24_OFFSET 0x0800 /**< Sampled Metric Counter + 24 Register */ +#define XAPM_SMC25_OFFSET 0x0810 /**< Sampled Metric Counter + 25 Register */ +#define XAPM_SMC26_OFFSET 0x0820 /**< Sampled Metric Counter + 26 Register */ +#define XAPM_SMC27_OFFSET 0x0830 /**< Sampled Metric Counter + 27 Register */ +#define XAPM_SMC28_OFFSET 0x0840 /**< Sampled Metric Counter + 28 Register */ +#define XAPM_SMC29_OFFSET 0x0850 /**< Sampled Metric Counter + 29 Register */ +#define XAPM_SMC30_OFFSET 0x0860 /**< Sampled Metric Counter + 30 Register */ +#define XAPM_SMC31_OFFSET 0x0870 /**< Sampled Metric Counter + 31 Register */ +#define XAPM_SMC32_OFFSET 0x0880 /**< Sampled Metric Counter + 32 Register */ +#define XAPM_SMC33_OFFSET 0x0890 /**< Sampled Metric Counter + 33 Register */ +#define XAPM_SMC34_OFFSET 0x08A0 /**< Sampled Metric Counter + 34 Register */ +#define XAPM_SMC35_OFFSET 0x08B0 /**< Sampled Metric Counter + 35 Register */ +#define XAPM_SMC36_OFFSET 0x0A00 /**< Sampled Metric Counter + 36 Register */ +#define XAPM_SMC37_OFFSET 0x0A10 /**< Sampled Metric Counter + 37 Register */ +#define XAPM_SMC38_OFFSET 0x0A20 /**< Sampled Metric Counter + 38 Register */ +#define XAPM_SMC39_OFFSET 0x0A30 /**< Sampled Metric Counter + 39 Register */ +#define XAPM_SMC40_OFFSET 0x0A40 /**< Sampled Metric Counter + 40 Register */ +#define XAPM_SMC41_OFFSET 0x0A50 /**< Sampled Metric Counter + 41 Register */ +#define XAPM_SMC42_OFFSET 0x0A60 /**< Sampled Metric Counter + 42 Register */ +#define XAPM_SMC43_OFFSET 0x0A70 /**< Sampled Metric Counter + 43 Register */ +#define XAPM_SMC44_OFFSET 0x0A80 /**< Sampled Metric Counter + 44 Register */ +#define XAPM_SMC45_OFFSET 0x0A90 /**< Sampled Metric Counter + 45 Register */ +#define XAPM_SMC46_OFFSET 0x0AA0 /**< Sampled Metric Counter + 46 Register */ +#define XAPM_SMC47_OFFSET 0x0AB0 /**< Sampled Metric Counter + 47 Register */ + +#define XAPM_CTL_OFFSET 0x0300 /**< Control Register */ + +#define XAPM_ID_OFFSET 0x0304 /**< Latency ID Register */ + +#define XAPM_IDMASK_OFFSET 0x0308 /**< ID Mask Register */ + +#define XAPM_RID_OFFSET 0x030C /**< Latency Write ID Register */ + +#define XAPM_RIDMASK_OFFSET 0x0310 /**< Read ID Mask Register */ + +#define XAPM_FEC_OFFSET 0x0400 /**< Flag Enable + Control Register */ + +#define XAPM_SWD_OFFSET 0x0404 /**< Software-written + Data Register */ + +/* @} */ + +/** + * @name AXI Monitor Sample Interval Control Register mask(s) + * @{ + */ + +#define XAPM_SICR_MCNTR_RST_MASK 0x00000100 /**< Enable the Metric + Counter Reset */ +#define XAPM_SICR_LOAD_MASK 0x00000002 /**< Load the Sample Interval + * Register Value into the + * counter */ +#define XAPM_SICR_ENABLE_MASK 0x00000001 /**< Enable the downcounter */ + +/*@}*/ + + +/** @name Interrupt Status/Enable Register Bit Definitions and Masks + * @{ + */ + +#define XAPM_IXR_MC9_OVERFLOW_MASK 0x00001000 /**< Metric Counter 9 + * Overflow> */ +#define XAPM_IXR_MC8_OVERFLOW_MASK 0x00000800 /**< Metric Counter 8 + * Overflow> */ +#define XAPM_IXR_MC7_OVERFLOW_MASK 0x00000400 /**< Metric Counter 7 + * Overflow> */ +#define XAPM_IXR_MC6_OVERFLOW_MASK 0x00000200 /**< Metric Counter 6 + * Overflow> */ +#define XAPM_IXR_MC5_OVERFLOW_MASK 0x00000100 /**< Metric Counter 5 + * Overflow> */ +#define XAPM_IXR_MC4_OVERFLOW_MASK 0x00000080 /**< Metric Counter 4 + * Overflow> */ +#define XAPM_IXR_MC3_OVERFLOW_MASK 0x00000040 /**< Metric Counter 3 + * Overflow> */ +#define XAPM_IXR_MC2_OVERFLOW_MASK 0x00000020 /**< Metric Counter 2 + * Overflow> */ +#define XAPM_IXR_MC1_OVERFLOW_MASK 0x00000010 /**< Metric Counter 1 + * Overflow> */ +#define XAPM_IXR_MC0_OVERFLOW_MASK 0x00000008 /**< Metric Counter 0 + * Overflow> */ +#define XAPM_IXR_FIFO_FULL_MASK 0x00000004 /**< Event Log FIFO + * full> */ +#define XAPM_IXR_SIC_OVERFLOW_MASK 0x00000002 /**< Sample Interval + * Counter Overflow> */ +#define XAPM_IXR_GCC_OVERFLOW_MASK 0x00000001 /**< Global Clock Counter + * Overflow> */ +#define XAPM_IXR_ALL_MASK (XAPM_IXR_SIC_OVERFLOW_MASK | \ + XAPM_IXR_GCC_OVERFLOW_MASK | \ + XAPM_IXR_FIFO_FULL_MASK | \ + XAPM_IXR_MC0_OVERFLOW_MASK | \ + XAPM_IXR_MC1_OVERFLOW_MASK | \ + XAPM_IXR_MC2_OVERFLOW_MASK | \ + XAPM_IXR_MC3_OVERFLOW_MASK | \ + XAPM_IXR_MC4_OVERFLOW_MASK | \ + XAPM_IXR_MC5_OVERFLOW_MASK | \ + XAPM_IXR_MC6_OVERFLOW_MASK | \ + XAPM_IXR_MC7_OVERFLOW_MASK | \ + XAPM_IXR_MC8_OVERFLOW_MASK | \ + XAPM_IXR_MC9_OVERFLOW_MASK) +/* @} */ + +/** + * @name AXI Monitor Control Register mask(s) + * @{ + */ + +#define XAPM_CR_FIFO_RESET_MASK 0x02000000 + /**< FIFO Reset */ +#define XAPM_CR_GCC_RESET_MASK 0x00020000 + /**< Global Clk + Counter Reset */ +#define XAPM_CR_GCC_ENABLE_MASK 0x00010000 + /**< Global Clk + Counter Enable */ +#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK 0x00000200 + /**< Enable External trigger + to start event Log */ +#define XAPM_CR_EVENTLOG_ENABLE_MASK 0x00000100 + /**< Event Log Enable */ + +#define XAPM_CR_RDLATENCY_END_MASK 0x00000080 + /**< Write Latency + End point */ +#define XAPM_CR_RDLATENCY_START_MASK 0x00000040 + /**< Read Latency + Start point */ +#define XAPM_CR_WRLATENCY_END_MASK 0x00000020 + /**< Write Latency + End point */ +#define XAPM_CR_WRLATENCY_START_MASK 0x00000010 + /**< Write Latency + Start point */ +#define XAPM_CR_IDFILTER_ENABLE_MASK 0x00000008 + /**< ID Filter Enable */ + +#define XAPM_CR_MCNTR_EXTTRIGGER_MASK 0x00000004 + /**< Enable External + trigger to start + Metric Counters */ +#define XAPM_CR_MCNTR_RESET_MASK 0x00000002 + /**< Metrics Counter + Reset */ +#define XAPM_CR_MCNTR_ENABLE_MASK 0x00000001 + /**< Metrics Counter + Enable */ +/*@}*/ + +/** + * @name AXI Monitor ID Register mask(s) + * @{ + */ + +#define XAPM_ID_RID_MASK 0xFFFF0000 /**< Read ID */ + +#define XAPM_ID_WID_MASK 0x0000FFFF /**< Write ID */ + +/*@}*/ + +/** + * @name AXI Monitor ID Mask Register mask(s) + * @{ + */ + +#define XAPM_MASKID_RID_MASK 0xFFFF0000 /**< Read ID Mask */ + +#define XAPM_MASKID_WID_MASK 0x0000FFFF /**< Write ID Mask*/ + +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* Read a register of the AXI Performance Monitor device. This macro provides +* register access to all registers using the register offsets defined above. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XAxiPmon_ReadReg(u32 BaseAddress, u32 RegOffset); +* +******************************************************************************/ +#define XAxiPmon_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + +/*****************************************************************************/ +/** +* +* Write a register of the AXI Performance Monitor device. This macro provides +* register access to all registers using the register offsets defined above. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XAxiPmon_WriteReg(u32 BaseAddress, +* u32 RegOffset,u32 Data) +* +******************************************************************************/ +#define XAxiPmon_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32((BaseAddress) + (RegOffset), (Data))) + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_selftest.c new file mode 100644 index 000000000..5d5d2c007 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_selftest.c @@ -0,0 +1,148 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xaxipmon_selftest.c +* +* This file contains a diagnostic self test function for the XAxiPmon driver. +* The self test function does a simple read/write test of the Alarm Threshold +* Register. +* +* See XAxiPmon.h for more information. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss  02/24/12 First release
+* 2.00a bss  06/23/12 Updated to support v2_00a version of IP.
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xaxipmon.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constant defines the test value to be written + * to the Range Registers of Incrementers + */ + +#define XAPM_TEST_RANGEUPPER_VALUE 16 /**< Test Value for Upper Range */ +#define XAPM_TEST_RANGELOWER_VALUE 8 /**< Test Value for Lower Range */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/*****************************************************************************/ +/** +* +* Run a self-test on the driver/device. The test +* - Resets the device, +* - Writes a value into the Range Registers of Incrementer 0 and reads +* it back for comparison. +* - Resets the device again. +* +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return +* - XST_SUCCESS if the value read from the Range Register of +* Incrementer 0 is the same as the value written. +* - XST_FAILURE Otherwise +* +* @note This is a destructive test in that resets of the device are +* performed. Refer to the device specification for the +* device status after the reset operation. +* +******************************************************************************/ +int XAxiPmon_SelfTest(XAxiPmon *InstancePtr) +{ + int Status; + u16 RangeUpper; + u16 RangeLower; + + /* + * Assert the argument + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + /* + * Reset the device to get it back to its default state + */ + XAxiPmon_ResetMetricCounter(InstancePtr); + XAxiPmon_ResetGlobalClkCounter(InstancePtr); + + /* + * Write a value into the Incrementer register and + * read it back, and do the comparison + */ + XAxiPmon_SetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0, + XAPM_TEST_RANGEUPPER_VALUE, + XAPM_TEST_RANGELOWER_VALUE); + + XAxiPmon_GetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0, + &RangeUpper, &RangeLower); + + if ((RangeUpper == XAPM_TEST_RANGEUPPER_VALUE) && + (RangeLower == XAPM_TEST_RANGELOWER_VALUE)) { + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + + /* + * Reset the device again to its default state. + */ + XAxiPmon_ResetMetricCounter(InstancePtr); + XAxiPmon_ResetGlobalClkCounter(InstancePtr); + + /* + * Return the test result. + */ + return Status; +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_sinit.c new file mode 100644 index 000000000..06343dcd0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_2/src/xaxipmon_sinit.c @@ -0,0 +1,100 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xaxipmon_sinit.c +* +* This file contains the implementation of the XAxiPmon driver's static +* initialization functionality. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss  02/27/12 First release
+* 2.00a bss  06/23/12 Updated to support v2_00a version of IP.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xaxipmon.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +extern XAxiPmon_Config XAxiPmon_ConfigTable[]; + +/*****************************************************************************/ +/** +* +* This function looks up the device configuration based on the unique device ID. +* The table XAxiPmon_ConfigTable contains the configuration info for each device +* in the system. +* +* @param DeviceId contains the ID of the device for which the +* device configuration pointer is to be returned. +* +* @return +* - A pointer to the configuration found. +* - NULL if the specified device ID was not found. +* +* @note None. +* +******************************************************************************/ +XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId) +{ + XAxiPmon_Config *CfgPtr = NULL; + u32 Index; + + for (Index=0; Index < XPAR_XAXIPMON_NUM_INSTANCES; Index++) { + if (XAxiPmon_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XAxiPmon_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/Makefile new file mode 100644 index 000000000..55565709b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xcanps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling canps" + +xcanps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xcanps_includes + +xcanps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps.c new file mode 100644 index 000000000..d4ba8d893 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps.c @@ -0,0 +1,1202 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.c +* +* Functions in this file are the minimum required functions for the XCanPs +* driver. See xcanps.h for a detailed description of the driver. +* +* @note None. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +static void StubHandler(void); + +/*****************************************************************************/ +/* +* +* This function initializes a XCanPs instance/driver. +* +* The initialization entails: +* - Initialize all members of the XCanPs structure. +* - Reset the CAN device. The CAN device will enter Configuration Mode +* immediately after the reset is finished. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param ConfigPtr points to the XCanPs device configuration structure. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. If the address translation is not used then the +* physical address is passed. +* Unexpected errors may occur if the address mapping is changed +* after this function is invoked. +* +* @return XST_SUCCESS always. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * Set some default values for instance data, don't indicate the device + * is ready to use until everything has been initialized successfully. + */ + InstancePtr->IsReady = 0U; + InstancePtr->CanConfig.BaseAddr = EffectiveAddr; + InstancePtr->CanConfig.DeviceId = ConfigPtr->DeviceId; + + /* + * Set all handlers to stub values, let user configure this data later. + */ + InstancePtr->SendHandler = (XCanPs_SendRecvHandler) StubHandler; + InstancePtr->RecvHandler = (XCanPs_SendRecvHandler) StubHandler; + InstancePtr->ErrorHandler = (XCanPs_ErrorHandler) StubHandler; + InstancePtr->EventHandler = (XCanPs_EventHandler) StubHandler; + + /* + * Indicate the component is now ready to use. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + /* + * Reset the device to get it into its initial state. + */ + XCanPs_Reset(InstancePtr); + + Status = XST_SUCCESS; + return Status; +} + +/*****************************************************************************/ +/** +* +* This function resets the CAN device. Calling this function resets the device +* immediately, and any pending transmission or reception is terminated at once. +* Both Object Layer and Transfer Layer are reset. This function does not reset +* the Physical Layer. All registers are reset to the default values, and no +* previous status will be restored. TX FIFO, RX FIFO and TX High Priority +* Buffer are also reset. +* +* When a reset is required due to an internal error, the driver notifies the +* upper layer software of this need through the error status code or interrupts. +* The upper layer software is responsible for calling this Reset function and +* then re-configuring the device. +* +* The CAN device will be in Configuration Mode immediately after this function +* returns. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_Reset(XCanPs *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_SRR_OFFSET, \ + XCANPS_SRR_SRST_MASK); +} + +/****************************************************************************/ +/** +* +* This routine returns the current operation mode of the CAN device. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - XCANPS_MODE_CONFIG if the device is in Configuration Mode. +* - XCANPS_MODE_SLEEP if the device is in Sleep Mode. +* - XCANPS_MODE_NORMAL if the device is in Normal Mode. +* - XCANPS_MODE_LOOPBACK if the device is in Loop Back Mode. +* - XCANPS_MODE_SNOOP if the device is in Snoop Mode. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetMode(XCanPs *InstancePtr) +{ + u32 StatusReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + StatusReg = XCanPs_GetStatus(InstancePtr); + + if ((StatusReg & XCANPS_SR_CONFIG_MASK) != (u32)0) { + return (u8)XCANPS_MODE_CONFIG; + + } + else if ((StatusReg & XCANPS_SR_SLEEP_MASK) != (u32)0) { + return (u8)XCANPS_MODE_SLEEP; + + } + else if ((StatusReg & XCANPS_SR_NORMAL_MASK) != (u32)0) { + if ((StatusReg & XCANPS_SR_SNOOP_MASK) != (u32)0) { + return (u8)XCANPS_MODE_SNOOP; + } else { + return (u8)XCANPS_MODE_NORMAL; + } + } + else { + /* + * If this line is reached, the device is in Loop Back Mode. + */ + return (u8)XCANPS_MODE_LOOPBACK; + } +} + +/*****************************************************************************/ +/** +* +* This function allows the CAN device to enter one of the following operation +* modes: +* - Configuration Mode: Pass in parameter XCANPS_MODE_CONFIG +* - Sleep Mode: Pass in parameter XCANPS_MODE_SLEEP +* - Normal Mode: Pass in parameter XCANPS_MODE_NORMAL +* - Loop Back Mode: Pass in parameter XCANPS_MODE_LOOPBACK. +* - Snoop Mode: Pass in parameter XCANPS_MODE_SNOOP. +* +* Read the xcanps.h file and device specification for detailed description of +* each operation mode. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param OperationMode specify which operation mode to enter. Valid value +* is any of XCANPS_MODE_* defined in xcanps.h. Multiple modes +* can not be entered at the same time. +* +* @return None. +* +* @note +* +* This function does NOT ensure CAN device enters the specified operation mode +* before it returns the control to the caller. The caller is responsible for +* checking current operation mode using XCanPs_GetMode(). +* +******************************************************************************/ +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode) +{ + u8 CurrentMode; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((OperationMode == (u8)XCANPS_MODE_CONFIG) || + (OperationMode == (u8)XCANPS_MODE_SLEEP) || + (OperationMode == (u8)XCANPS_MODE_NORMAL) || + (OperationMode == (u8)XCANPS_MODE_LOOPBACK) || + (OperationMode == (u8)XCANPS_MODE_SNOOP)); + + CurrentMode = XCanPs_GetMode(InstancePtr); + + /* + * If current mode is Normal Mode and the mode to enter is Sleep Mode, + * or if current mode is Sleep Mode and the mode to enter is Normal + * Mode, no transition through Configuration Mode is needed. + */ + if ((CurrentMode == (u8)XCANPS_MODE_NORMAL) && + (OperationMode == (u8)XCANPS_MODE_SLEEP)) { + /* + * Normal Mode ---> Sleep Mode + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK); + return; + + } else if ((CurrentMode == (u8)XCANPS_MODE_SLEEP) && + (OperationMode == (u8)XCANPS_MODE_NORMAL)) { + /* + * Sleep Mode ---> Normal Mode + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, 0U); + return; + } + else { + /*This else was made for misra-c compliance*/ + ; + } + + /* + * If the mode transition is not any of the two cases above, CAN must + * enter Configuration Mode before switching into the target operation + * mode. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, 0U); + + /* + * Check if the device has entered Configuration Mode, if not, return to + * the caller. + */ + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + return; + } + + switch (OperationMode) { + case XCANPS_MODE_CONFIG: + /* + * As CAN is in Configuration Mode already. + * Nothing is needed to be done here. + */ + break; + + case XCANPS_MODE_SLEEP: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_NORMAL: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, 0U); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_LOOPBACK: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_LBACK_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_SNOOP: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SNOOP_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + default: + /*This default was made for misra-c compliance*/ + break; + + } +} + +/*****************************************************************************/ +/** +* +* This function returns Status value from Status Register (SR). Use the +* XCANPS_SR_* constants defined in xcanps_hw.h to interpret the returned +* value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The 32-bit value read from Status Register. +* +* @note None. +* +******************************************************************************/ +u32 XCanPs_GetStatus(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SR_OFFSET); +} + +/*****************************************************************************/ +/** +* +* This function reads Receive and Transmit error counters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param RxErrorCount is a pointer to data in which the Receive Error +* counter value is returned. +* @param TxErrorCount is a pointer to data in which the Transmit Error +* counter value is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount) +{ + u32 ErrorCount; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(RxErrorCount != NULL); + Xil_AssertVoid(TxErrorCount != NULL); + /* + * Read Error Counter Register and parse it. + */ + ErrorCount = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ECR_OFFSET); + *RxErrorCount = (u8)((ErrorCount & XCANPS_ECR_REC_MASK) >> + XCANPS_ECR_REC_SHIFT); + *TxErrorCount = (u8)(ErrorCount & XCANPS_ECR_TEC_MASK); +} + +/*****************************************************************************/ +/** +* +* This function reads Error Status value from Error Status Register (ESR). Use +* the XCANPS_ESR_* constants defined in xcanps_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The 32-bit value read from Error Status Register. +* +* @note None. +* +******************************************************************************/ +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ESR_OFFSET); +} + +/*****************************************************************************/ +/** +* +* This function clears Error Status bit(s) previously set in Error +* Status Register (ESR). Use the XCANPS_ESR_* constants defined in xcanps_hw.h +* to create the value to pass in. If a bit was cleared in Error Status Register +* before this function is called, it will not be modified. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @param Mask is he 32-bit mask used to clear bits in Error Status +* Register. Multiple XCANPS_ESR_* values can be 'OR'ed to clear +* multiple bits. +* +* @note None. +* +******************************************************************************/ +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ESR_OFFSET, Mask); +} + +/*****************************************************************************/ +/** +* +* This function sends a CAN Frame. If the TX FIFO is not full then the given +* frame is written into the the TX FIFO otherwise, it returns an error code +* immediately. +* This function does not wait for the given frame being sent to CAN bus. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer containing the +* CAN frame to be sent. +* +* @return +* - XST_SUCCESS if TX FIFO was not full and the given frame was +* written into the FIFO. +* - XST_FIFO_NO_ROOM if there is no room in the TX FIFO for the +* given frame. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsTxFifoFull(InstancePtr) == TRUE) { + Status = XST_FIFO_NO_ROOM; + } else { + + /* + * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DW1_OFFSET, FramePtr[2]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DW2_OFFSET, FramePtr[3]); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This function receives a CAN Frame. This function first checks if RX FIFO is +* empty, if not, it then reads a frame from the RX FIFO into the given buffer. +* This function returns error code immediately if there is no frame in the RX +* FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer where the CAN +* frame to be written. +* +* @return +* - XST_SUCCESS if RX FIFO was not empty and a frame was read from +* RX FIFO successfully and written into the given buffer. +* - XST_NO_DATA if there is no frame to be received from the FIFO. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsRxEmpty(InstancePtr) == TRUE) { + Status = XST_NO_DATA; + } else { + + /* + * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device. + */ + FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_ID_OFFSET); + FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DLC_OFFSET); + FramePtr[2] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DW1_OFFSET); + FramePtr[3] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DW2_OFFSET); + + /* + * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call + * returns correct RX FIFO occupancy/empty condition. + */ + XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine sends a CAN High Priority frame. This function first checks if +* TX High Priority Buffer is empty. If yes, it then writes the given frame into +* the Buffer. If not, this function returns immediately. This function does not +* wait for the given frame being sent to CAN bus. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer containing the +* CAN High Priority frame to be sent. +* +* @return +* - XST_SUCCESS if TX High Priority Buffer was not full and the +* given frame was written into the buffer. +* - XST_FIFO_NO_ROOM if there is no room in the TX High Priority +* Buffer for this frame. +* +* @note +* +* If the frame needs to be sent immediately and not delayed by processor's +* interrupt handling, the caller should disable interrupt at processor +* level before invoking this function. +* +******************************************************************************/ +s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsHighPriorityBufFull(InstancePtr) == TRUE) { + Status = XST_FIFO_NO_ROOM; + } else { + + /* + * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_ID_OFFSET, FramePtr[0]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DW1_OFFSET, FramePtr[2]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DW2_OFFSET, FramePtr[3]); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine enables individual acceptance filters. Up to 4 filters could +* be enabled. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndexes specifies which filter(s) to enable. Use +* any XCANPS_AFR_UAF*_MASK to enable one filter, and "Or" +* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need +* to be enabled. Any filter not specified in this parameter will +* keep its previous enable/disable setting. +* +* @return None. +* +* @note None. +* +* +******************************************************************************/ +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes) +{ + u32 EnabledFilters; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Calculate the new value and write to AFR. + */ + EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + EnabledFilters |= FilterIndexes; + EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET, + EnabledFilters); +} + +/*****************************************************************************/ +/** +* +* This routine disables individual acceptance filters. Up to 4 filters could +* be disabled. If all acceptance filters are disabled then all the received +* frames are stored in the RX FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndexes specifies which filter(s) to disable. Use +* any XCANPS_AFR_UAF*_MASK to disable one filter, and "Or" +* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need +* to be disabled. Any filter not specified in this parameter will +* keep its previous enable/disable setting. If all acceptance +* filters are disabled then all received frames are stored in the +* RX FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes) +{ + u32 EnabledFilters; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Calculate the new value and write to AFR. + */ + EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET, + EnabledFilters); +} + +/*****************************************************************************/ +/** +* +* This function returns enabled acceptance filters. Use XCANPS_AFR_UAF*_MASK +* defined in xcanps_hw.h to interpret the returned value. If no acceptance +* filters are enabled then all received frames are stored in the RX FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The value stored in Acceptance Filter Register. +* +* @note None. +* +* +******************************************************************************/ +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + +} + +/*****************************************************************************/ +/** +* +* This function sets values to the Acceptance Filter Mask Register (AFMR) and +* Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter. +* Use XCANPS_IDR_* defined in xcanps_hw.h to create the values to set the +* filter. Read the xcanps.h file and device specification for details. +* +* This function should be called only after: +* - The given filter is disabled by calling XCanPs_AcceptFilterDisable() +* - And the CAN device is ready to accept writes to AFMR and AFIR, i.e., +* XCanPs_IsAcceptFilterBusy() returns FALSE. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndex defines which Acceptance Filter Mask and ID Register +* to set. Use any single XCANPS_AFR_UAF*_MASK value. +* @param MaskValue is the value to write to the chosen Acceptance Filter +* Mask Register. +* @param IdValue is the value to write to the chosen Acceptance Filter +* ID Register. +* +* @return +* - XST_SUCCESS if the values were set successfully. +* - XST_FAILURE if the given filter was not disabled, or the CAN +* device was not ready to accept writes to AFMR and AFIR. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue) +{ + u32 EnabledFilters; + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((FilterIndex == XCANPS_AFR_UAF4_MASK) || + (FilterIndex == XCANPS_AFR_UAF3_MASK) || + (FilterIndex == XCANPS_AFR_UAF2_MASK) || + (FilterIndex == XCANPS_AFR_UAF1_MASK)); + + /* + * Return an error if the given filter is currently enabled. + */ + EnabledFilters = XCanPs_AcceptFilterGetEnabled(InstancePtr); + if ((EnabledFilters & FilterIndex) == FilterIndex) { + Status = XST_FAILURE; + } else { + + /* + * If the CAN device is not ready to accept writes to AFMR and AFIR, + * return error code. + */ + if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) { + Status = XST_FAILURE; + } else { + + /* + * Write to the AFMR and AFIR of the specified filter. + */ + switch (FilterIndex) { + case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */ + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR1_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR1_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR2_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR2_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR3_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR3_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR4_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR4_OFFSET, IdValue); + break; + + default: + /*This default was made for misra-c compliance*/ + break; + } + + Status = XST_SUCCESS; + } + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This function reads the values of the Acceptance Filter Mask and ID Register +* for the specified Acceptance Filter. Use XCANPS_IDR_* defined in xcanps_hw.h +* to interpret the values. Read the xcanps.h file and device specification for +* details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndex defines which Acceptance Filter Mask Register to get +* Mask and ID from. Use any single XCANPS_FILTER_* value. +* @param MaskValue is a pointer to the data in which the Mask value read +* from the chosen Acceptance Filter Mask Register is returned. +* @param IdValue is a pointer to the data in which the ID value read +* from the chosen Acceptance Filter ID Register is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((FilterIndex == XCANPS_AFR_UAF4_MASK) || + (FilterIndex == XCANPS_AFR_UAF3_MASK) || + (FilterIndex == XCANPS_AFR_UAF2_MASK) || + (FilterIndex == XCANPS_AFR_UAF1_MASK)); + Xil_AssertVoid(MaskValue != NULL); + Xil_AssertVoid(IdValue != NULL); + + /* + * Read from the AFMR and AFIR of the specified filter. + */ + switch (FilterIndex) { + case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR1_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR1_OFFSET); + break; + + case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR2_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR2_OFFSET); + break; + + case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR3_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR3_OFFSET); + break; + + case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR4_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR4_OFFSET); + break; + + default: + /*This default was made for misra-c compliance*/ + break; + } +} + +/*****************************************************************************/ +/** +* +* This routine sets Baud Rate Prescaler value. The system clock for the CAN +* controller is divided by (Prescaler + 1) to generate the quantum clock +* needed for sampling and synchronization. Read the device specification +* for details. +* +* Baud Rate Prescaler can be set only if the CAN device is in Configuration +* Mode. Call XCanPs_EnterMode() to enter Configuration Mode before using this +* function. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Prescaler is the value to set. Valid values are from 0 to 255. +* +* @return +* - XST_SUCCESS if the Baud Rate Prescaler value is set +* successfully. +* - XST_FAILURE if CAN device is not in Configuration Mode. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_BRPR_OFFSET, + (u32)Prescaler); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine gets Baud Rate Prescaler value. The system clock for the CAN +* controller is divided by (Prescaler + 1) to generate the quantum clock +* needed for sampling and synchronization. Read the device specification for +* details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return Current used Baud Rate Prescaler value. The value's range is +* from 0 to 255. +* +* @note None. +* +******************************************************************************/ +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr) +{ + u32 ReadValue; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + ReadValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BRPR_OFFSET); + return ((u8)ReadValue); +} + +/*****************************************************************************/ +/** +* +* This routine sets Bit time. Time segment 1, Time segment 2 and +* Synchronization Jump Width are set in this function. Device specification +* requires the values passed into this function be one less than the actual +* values of these fields. Read the device specification for details. +* +* Bit time can be set only if the CAN device is in Configuration Mode. +* Call XCanPs_EnterMode() to enter Configuration Mode before using this +* function. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param SyncJumpWidth is the Synchronization Jump Width value to set. +* Valid values are from 0 to 3. +* @param TimeSegment2 is the Time Segment 2 value to set. Valid values +* are from 0 to 7. +* @param TimeSegment1 is the Time Segment 1 value to set. Valid values +* are from 0 to 15. +* +* @return +* - XST_SUCCESS if the Bit time is set successfully. +* - XST_FAILURE if CAN device is not in Configuration Mode. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1) +{ + u32 Value; + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(SyncJumpWidth <= (u8)3U); + Xil_AssertNonvoid(TimeSegment2 <= (u8)7U); + Xil_AssertNonvoid(TimeSegment1 <= (u8)15U ); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + Value = ((u32) TimeSegment1) & XCANPS_BTR_TS1_MASK; + Value |= (((u32) TimeSegment2) << XCANPS_BTR_TS2_SHIFT) & + XCANPS_BTR_TS2_MASK; + Value |= (((u32) SyncJumpWidth) << XCANPS_BTR_SJW_SHIFT) & + XCANPS_BTR_SJW_MASK; + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BTR_OFFSET, Value); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine gets Bit time. Time segment 1, Time segment 2 and +* Synchronization Jump Width values are read in this function. According to +* device specification, the actual value of each of these fields is one +* more than the value read. Read the device specification for details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param SyncJumpWidth will store the Synchronization Jump Width value +* after this function returns. Its value ranges from 0 to 3. +* @param TimeSegment2 will store the Time Segment 2 value after this +* function returns. Its value ranges from 0 to 7. +* @param TimeSegment1 will store the Time Segment 1 value after this +* function returns. Its value ranges from 0 to 15. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1) +{ + u32 Value; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(SyncJumpWidth != NULL); + Xil_AssertVoid(TimeSegment2 != NULL); + Xil_AssertVoid(TimeSegment1 != NULL); + + Value = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BTR_OFFSET); + + *TimeSegment1 = (u8) (Value & XCANPS_BTR_TS1_MASK); + *TimeSegment2 = + (u8) ((Value & XCANPS_BTR_TS2_MASK) >> XCANPS_BTR_TS2_SHIFT); + *SyncJumpWidth = + (u8) ((Value & XCANPS_BTR_SJW_MASK) >> XCANPS_BTR_SJW_SHIFT); +} + + +/****************************************************************************/ +/** +* +* This routine sets the Rx Full threshold in the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Threshold is the threshold to be set. The valid values are +* from 1 to 63. +* +* @return +* - XST_FAILURE - If the CAN device is not in Configuration Mode. +* - XST_SUCCESS - If the Rx Full threshold is set in Watermark +* Interrupt Register. +* +* @note The threshold can only be set when the CAN device is in the +* configuration mode. +* +*****************************************************************************/ +s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold) +{ + + u32 ThrReg; + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Threshold <= (u8)63); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET); + + ThrReg &= XCANPS_WIR_EW_MASK; + ThrReg |= ((u32)Threshold & XCANPS_WIR_FW_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET, ThrReg); + + Status = XST_SUCCESS; + } + return Status; +} + +/****************************************************************************/ +/** +* +* This routine gets the Rx Full threshold from the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The Rx FIFO full watermark threshold value. The valid values +* are 1 to 63. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + return (u8) (XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET) & + XCANPS_WIR_FW_MASK); +} + + +/****************************************************************************/ +/** +* +* This routine sets the Tx Empty Threshold in the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Threshold is the threshold to be set. The valid values are +* from 1 to 63. +* +* @return +* - XST_FAILURE - If the CAN device is not in Configuration Mode. +* - XST_SUCCESS - If the threshold is set in Watermark +* Interrupt Register. +* +* @note The threshold can only be set when the CAN device is in the +* configuration mode. +* +*****************************************************************************/ +s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold) +{ + u32 ThrReg; + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Threshold <= (u8)63); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET); + + ThrReg &= XCANPS_WIR_FW_MASK; + ThrReg |= (((u32)Threshold << XCANPS_WIR_EW_SHIFT) + & XCANPS_WIR_EW_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET, ThrReg); + + Status = XST_SUCCESS; + } + return Status; +} + +/****************************************************************************/ +/** +* +* This routine gets the Tx Empty threshold from Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The Tx Empty FIFO threshold value. The valid values are 1 to 63. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + return (u8) ((XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET) & XCANPS_WIR_EW_MASK) >> + XCANPS_WIR_EW_SHIFT); +} + + + +/******************************************************************************/ +/* + * This routine is a stub for the asynchronous callbacks. The stub is here in + * case the upper layer forgot to set the handler(s). On initialization, all + * handlers are set to this callback. It is considered an error for this handler + * to be invoked. + * + ******************************************************************************/ +static void StubHandler(void) +{ + Xil_AssertVoidAlways(); +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps.h new file mode 100644 index 000000000..9c4c24211 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps.h @@ -0,0 +1,567 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.h +* +* The Xilinx CAN driver component. This component supports the Xilinx +* CAN Controller. +* +* The CAN Controller supports the following features: +* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards. +* - Supports both Standard (11 bit Identifier) and Extended (29 bit +* Identifier) frames. +* - Supports Bit Rates up to 1 Mbps. +* - Transmit message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Transmit prioritization through one TX High Priority Buffer. +* - Receive message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Watermark interrupts for Rx FIFO with configurable Watermark. +* - Acceptance filtering with 4 acceptance filters. +* - Sleep mode with automatic wake up. +* - Loop Back mode for diagnostic applications. +* - Snoop mode for diagnostic applications. +* - Maskable Error and Status Interrupts. +* - Readable Error Counters. +* - External PHY chip required. +* - Receive Timestamp. +* +* The device driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CAN. The driver handles transmission and reception of +* CAN frames, as well as configuration of the controller. The driver is simply a +* pass-through mechanism between a protocol stack and the CAN. A single device +* driver can support multiple CANs. +* +* Since the driver is a simple pass-through mechanism between a protocol stack +* and the CAN, no assembly or disassembly of CAN frames is done at the +* driver-level. This assumes that the protocol stack passes a correctly +* formatted CAN frame to the driver for transmission, and that the driver +* does not validate the contents of an incoming frame +* +* Operation Modes +* +* The CAN controller supports the following modes of operation: +* - Configuration Mode: In this mode the CAN timing parameters and +* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN +* controller loses synchronization with the CAN bus and drives a +* constant recessive bit on the bus line. The Error Counter Register are +* reset. The CAN controller does not receive or transmit any messages +* even if there are pending transmit requests from the TX FIFO or the TX +* High Priority Buffer. The Storage FIFOs and the CAN configuration +* registers are still accessible. +* - Normal Mode:In Normal Mode the CAN controller participates in bus +* communication, by transmitting and receiving messages. +* - Sleep Mode: In Sleep Mode the CAN Controller does not transmit any +* messages. However, if any other node transmits a message, then the CAN +* Controller receives the transmitted message and exits from Sleep Mode. +* If there are new transmission requests from either the TX FIFO or the +* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these +* requests are not serviced, and the CAN Controller continues to remain +* in Sleep Mode. Interrupts are generated when the CAN controller enters +* Sleep mode or Wakes up from Sleep mode. +* - Loop Back Mode: In Loop Back mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus. Any message that is transmitted +* is looped back to the �Rx� line and acknowledged. The CAN controller +* thus receives any message that it transmits. It does not participate in +* normal bus communication and does not receive any messages that are +* transmitted by other CAN nodes. This mode is used for diagnostic +* purposes. +* - Snoop Mode: In Snoop mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus and does not participate +* in normal bus communication but receives messages that are transmitted +* by other CAN nodes. This mode is used for diagnostic purposes. +* +* +* Buffer Alignment +* +* It is important to note that frame buffers passed to the driver must be +* 32-bit aligned. +* +* Receive Address Filtering +* +* The device can be set to accept frames whose Identifiers match any of the +* 4 filters set in the Acceptance Filter Mask/ID registers. +* +* The incoming Identifier is masked with the bits in the Acceptance Filter Mask +* Register. This value is compared with the result of masking the bits in the +* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If +* both these values are equal, the message will be stored in the RX FIFO. +* +* Acceptance Filtering is performed by each of the defined acceptance filters. +* If the incoming identifier passes through any acceptance filter then the +* frame is stored in the RX FIFO. +* +* If the Accpetance Filters are not set up then all the received messages are +* stroed in the RX FIFO. +* +* PHY Communication +* +* This driver does not provide any mechanism for directly programming PHY. +* +* Interrupts +* +* The driver has no dependencies on the interrupt controller. The driver +* provides an interrupt handler. User of this driver needs to provide +* callback functions. An interrupt handler example is available with +* the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Device Reset +* +* Bus Off interrupt that can occur in the device requires a device reset. +* The user is responsible for resetting the device and re-configuring it +* based on its needs (the driver does not save the current configuration). +* When integrating into an RTOS, these reset and re-configure obligations are +* taken care of by the OS adapter software if it exists for that RTOS. +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xcanps_g.c files. +* A table is defined where each entry contains configuration information +* for a CAN device. This information includes such things as the base address +* of the memory-mapped device. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCanPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+*			Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*			SDK claims a 40kbps baud rate but it's not.
+* 3.0 adk     09/12/14  Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ +#ifndef XCANPS_H /* prevent circular inclusions */ +#define XCANPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xcanps_hw.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +/** @name CAN operation modes + * @{ + */ +#define XCANPS_MODE_CONFIG 0x00000001U /**< Configuration mode */ +#define XCANPS_MODE_NORMAL 0x00000002U /**< Normal mode */ +#define XCANPS_MODE_LOOPBACK 0x00000004U /**< Loop Back mode */ +#define XCANPS_MODE_SLEEP 0x00000008U /**< Sleep mode */ +#define XCANPS_MODE_SNOOP 0x00000010U /**< Snoop mode */ +/* @} */ + +/** @name Callback identifiers used as parameters to XCanPs_SetHandler() + * @{ + */ +#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */ +#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/ +#define XCANPS_HANDLER_ERROR 3U /**< Handler type for error interrupt */ +#define XCANPS_HANDLER_EVENT 4U /**< Handler type for all other interrupts */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XCanPs_Config; + +/******************************************************************************/ +/** + * Callback type for frame sending and reception interrupts. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. +*******************************************************************************/ +typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef); + +/******************************************************************************/ +/** + * Callback type for error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param ErrorMask is a bit mask indicating the cause of the error. Its + * value equals 'OR'ing one or more XCANPS_ESR_* values defined in + * xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask); + +/******************************************************************************/ +/** + * Callback type for all kinds of interrupts except sending frame interrupt, + * receiving frame interrupt, and error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param Mask is a bit mask indicating the pending interrupts. Its value + * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask); + +/** + * The XCanPs driver instance data. The user is required to allocate a + * variable of this type for every CAN device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XCanPs_Config CanConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + + /** + * Callback and callback reference for TXOK interrupt. + */ + XCanPs_SendRecvHandler SendHandler; + void *SendRef; + + /** + * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts. + */ + XCanPs_SendRecvHandler RecvHandler; + void *RecvRef; + + /** + * Callback and callback reference for ERROR interrupt. + */ + XCanPs_ErrorHandler ErrorHandler; + void *ErrorRef; + + /** + * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/ + * Wakeup/Sleep/Bus off/ARBLST interrupts. + */ + XCanPs_EventHandler EventHandler; + void *EventRef; + +} XCanPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the transmission is complete. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the transmission is done. +* - FALSE if the transmission is not done. +* +* @note C-Style signature: +* int XCanPs_IsTxDone(XCanPs *InstancePtr) +* +*******************************************************************************/ +#define XCanPs_IsTxDone(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the transmission FIFO is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if TX FIFO is full. +* - FALSE if the TX FIFO is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsTxFifoFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the Transmission High Priority Buffer is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the TX High Priority Buffer is full. +* - FALSE if the TX High Priority Buffer is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsHighPriorityBufFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the receive FIFO is empty. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if RX FIFO is empty. +* - FALSE if the RX FIFO is NOT empty. +* +* @note C-Style signature: +* int XCanPs_IsRxEmpty(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsRxEmpty(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE) + + +/****************************************************************************/ +/** +* +* This macro checks if the CAN device is ready for the driver to change +* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask +* Registers (AFMR). +* +* AFIR and AFMR for a filter are changeable only after the filter is disabled +* and this routine returns FALSE. The filter can be disabled using the +* XCanPs_AcceptFilterDisable function. +* +* Use the XCanPs_Accept_* functions for configuring the acceptance filters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the device is busy and NOT ready to accept writes to +* AFIR and AFMR. +* - FALSE if the device is ready to accept writes to AFIR and +* AFMR. +* +* @note C-Style signature: +* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsAcceptFilterBusy(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro calculates CAN message identifier value given identifier field +* values. +* +* @param StandardId contains Standard Message ID value. +* @param SubRemoteTransReq contains Substitute Remote Transmission +* Request value. +* @param IdExtension contains Identifier Extension value. +* @param ExtendedId contains Extended Message ID value. +* @param RemoteTransReq contains Remote Transmission Request value. +* +* @return Message Identifier value. +* +* @note C-Style signature: +* u32 XCanPs_CreateIdValue(u32 StandardId, +* u32 SubRemoteTransReq, +* u32 IdExtension, u32 ExtendedId, +* u32 RemoteTransReq) +* +* Read the CAN specification for meaning of each parameter. +* +*****************************************************************************/ +#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \ + ExtendedId, RemoteTransReq) \ + ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \ + (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\ + (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \ + (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \ + ((RemoteTransReq) & XCANPS_IDR_RTR_MASK)) + + +/****************************************************************************/ +/** +* +* This macro calculates value for Data Length Code register given Data +* Length Code value. +* +* @param DataLengCode indicates Data Length Code value. +* +* @return Value that can be assigned to Data Length Code register. +* +* @note C-Style signature: +* u32 XCanPs_CreateDlcValue(u32 DataLengCode) +* +* Read the CAN specification for meaning of Data Length Code. +* +*****************************************************************************/ +#define XCanPs_CreateDlcValue(DataLengCode) \ + (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK) + + +/****************************************************************************/ +/** +* +* This macro clears the timestamp in the Timestamp Control Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XCanPs_ClearTimestamp(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_ClearTimestamp(InstancePtr) \ + XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \ + XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xcanps.c + */ +s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr); + +void XCanPs_Reset(XCanPs *InstancePtr); +u8 XCanPs_GetMode(XCanPs *InstancePtr); +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode); +u32 XCanPs_GetStatus(XCanPs *InstancePtr); +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount); +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr); +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask); +s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr); +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes); +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes); +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr); +s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue); +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue); + +s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler); +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr); +s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1); +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1); + +s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr); +s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr); + +/* + * Diagnostic functions in xcanps_selftest.c + */ +s32 XCanPs_SelfTest(XCanPs *InstancePtr); + +/* + * Functions in xcanps_intr.c + */ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask); +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr); +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr); +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrHandler(void *InstancePtr); +s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef); + +/* + * Functions in xcanps_sinit.c + */ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_g.c new file mode 100644 index 000000000..487b9d8a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_g.c @@ -0,0 +1,59 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xcanps.h" + +/* +* The configuration table for devices +*/ + +XCanPs_Config XCanPs_ConfigTable[] = +{ + { + XPAR_PSU_CAN_0_DEVICE_ID, + XPAR_PSU_CAN_0_BASEADDR + }, + { + XPAR_PSU_CAN_1_DEVICE_ID, + XPAR_PSU_CAN_1_BASEADDR + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_hw.c new file mode 100644 index 000000000..4fa95c6a0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_hw.c @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.c +* +* This file contains the implementation of the canps interface reset sequence +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.02a adk  08/08/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps_hw.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* This function resets the CAN device. Calling this function resets the device +* immediately, and any pending transmission or reception is terminated at once. +* Both Object Layer and Transfer Layer are reset. This function does not reset +* the Physical Layer. All registers are reset to the default values, and no +* previous status will be restored. TX FIFO, RX FIFO and TX High Priority +* Buffer are also reset. +* +* The CAN device will be in Configuration Mode immediately after this function +* returns. +* +* @param BaseAddr is the baseaddress of the interface. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_ResetHw(u32 BaseAddr) +{ + XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \ + XCANPS_SRR_SRST_MASK); +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_hw.h new file mode 100644 index 000000000..22f9b0725 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_hw.h @@ -0,0 +1,366 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.h +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xcanps.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a sbs    12/27/11 Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET  to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET  to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk   08/08/13  Updated for inclding the function prototype
+* 3.00  kvn   02/13/15  Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +#ifndef XCANPS_HW_H /* prevent circular inclusions */ +#define XCANPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the CAN. Each register is 32 bits. + * @{ + */ +#define XCANPS_SRR_OFFSET 0x00000000U /**< Software Reset Register */ +#define XCANPS_MSR_OFFSET 0x00000004U /**< Mode Select Register */ +#define XCANPS_BRPR_OFFSET 0x00000008U /**< Baud Rate Prescaler */ +#define XCANPS_BTR_OFFSET 0x0000000CU /**< Bit Timing Register */ +#define XCANPS_ECR_OFFSET 0x00000010U /**< Error Counter Register */ +#define XCANPS_ESR_OFFSET 0x00000014U /**< Error Status Register */ +#define XCANPS_SR_OFFSET 0x00000018U /**< Status Register */ + +#define XCANPS_ISR_OFFSET 0x0000001CU /**< Interrupt Status Register */ +#define XCANPS_IER_OFFSET 0x00000020U /**< Interrupt Enable Register */ +#define XCANPS_ICR_OFFSET 0x00000024U /**< Interrupt Clear Register */ +#define XCANPS_TCR_OFFSET 0x00000028U /**< Timestamp Control Register */ +#define XCANPS_WIR_OFFSET 0x0000002CU /**< Watermark Interrupt Reg */ + +#define XCANPS_TXFIFO_ID_OFFSET 0x00000030U /**< TX FIFO ID */ +#define XCANPS_TXFIFO_DLC_OFFSET 0x00000034U /**< TX FIFO DLC */ +#define XCANPS_TXFIFO_DW1_OFFSET 0x00000038U /**< TX FIFO Data Word 1 */ +#define XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU /**< TX FIFO Data Word 2 */ + +#define XCANPS_TXHPB_ID_OFFSET 0x00000040U /**< TX High Priority Buffer ID */ +#define XCANPS_TXHPB_DLC_OFFSET 0x00000044U /**< TX High Priority Buffer DLC */ +#define XCANPS_TXHPB_DW1_OFFSET 0x00000048U /**< TX High Priority Buf Data 1 */ +#define XCANPS_TXHPB_DW2_OFFSET 0x0000004CU /**< TX High Priority Buf Data Word 2 */ + +#define XCANPS_RXFIFO_ID_OFFSET 0x00000050U /**< RX FIFO ID */ +#define XCANPS_RXFIFO_DLC_OFFSET 0x00000054U /**< RX FIFO DLC */ +#define XCANPS_RXFIFO_DW1_OFFSET 0x00000058U /**< RX FIFO Data Word 1 */ +#define XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU /**< RX FIFO Data Word 2 */ + +#define XCANPS_AFR_OFFSET 0x00000060U /**< Acceptance Filter Register */ +#define XCANPS_AFMR1_OFFSET 0x00000064U /**< Acceptance Filter Mask 1 */ +#define XCANPS_AFIR1_OFFSET 0x00000068U /**< Acceptance Filter ID 1 */ +#define XCANPS_AFMR2_OFFSET 0x0000006CU /**< Acceptance Filter Mask 2 */ +#define XCANPS_AFIR2_OFFSET 0x00000070U /**< Acceptance Filter ID 2 */ +#define XCANPS_AFMR3_OFFSET 0x00000074U /**< Acceptance Filter Mask 3 */ +#define XCANPS_AFIR3_OFFSET 0x00000078U /**< Acceptance Filter ID 3 */ +#define XCANPS_AFMR4_OFFSET 0x0000007CU /**< Acceptance Filter Mask 4 */ +#define XCANPS_AFIR4_OFFSET 0x00000080U /**< Acceptance Filter ID 4 */ +/* @} */ + +/** @name Software Reset Register (SRR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SRR_CEN_MASK 0x00000002U /**< Can Enable */ +#define XCANPS_SRR_SRST_MASK 0x00000001U /**< Reset */ +/* @} */ + +/** @name Mode Select Register (MSR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_MSR_SNOOP_MASK 0x00000004U /**< Snoop Mode Select */ +#define XCANPS_MSR_LBACK_MASK 0x00000002U /**< Loop Back Mode Select */ +#define XCANPS_MSR_SLEEP_MASK 0x00000001U /**< Sleep Mode Select */ +/* @} */ + +/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BRPR_BRP_MASK 0x000000FFU /**< Baud Rate Prescaler */ +/* @} */ + +/** @name Bit Timing Register (BTR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BTR_SJW_MASK 0x00000180U /**< Synchronization Jump Width */ +#define XCANPS_BTR_SJW_SHIFT 7U +#define XCANPS_BTR_TS2_MASK 0x00000070U /**< Time Segment 2 */ +#define XCANPS_BTR_TS2_SHIFT 4U +#define XCANPS_BTR_TS1_MASK 0x0000000FU /**< Time Segment 1 */ +/* @} */ + +/** @name Error Counter Register (ECR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ECR_REC_MASK 0x0000FF00U /**< Receive Error Counter */ +#define XCANPS_ECR_REC_SHIFT 8U +#define XCANPS_ECR_TEC_MASK 0x000000FFU /**< Transmit Error Counter */ +/* @} */ + +/** @name Error Status Register (ESR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ESR_ACKER_MASK 0x00000010U /**< ACK Error */ +#define XCANPS_ESR_BERR_MASK 0x00000008U /**< Bit Error */ +#define XCANPS_ESR_STER_MASK 0x00000004U /**< Stuff Error */ +#define XCANPS_ESR_FMER_MASK 0x00000002U /**< Form Error */ +#define XCANPS_ESR_CRCER_MASK 0x00000001U /**< CRC Error */ +/* @} */ + +/** @name Status Register (SR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SR_SNOOP_MASK 0x00001000U /**< Snoop Mask */ +#define XCANPS_SR_ACFBSY_MASK 0x00000800U /**< Acceptance Filter busy */ +#define XCANPS_SR_TXFLL_MASK 0x00000400U /**< TX FIFO is full */ +#define XCANPS_SR_TXBFLL_MASK 0x00000200U /**< TX High Priority Buffer full */ +#define XCANPS_SR_ESTAT_MASK 0x00000180U /**< Error Status */ +#define XCANPS_SR_ESTAT_SHIFT 7U +#define XCANPS_SR_ERRWRN_MASK 0x00000040U /**< Error Warning */ +#define XCANPS_SR_BBSY_MASK 0x00000020U /**< Bus Busy */ +#define XCANPS_SR_BIDLE_MASK 0x00000010U /**< Bus Idle */ +#define XCANPS_SR_NORMAL_MASK 0x00000008U /**< Normal Mode */ +#define XCANPS_SR_SLEEP_MASK 0x00000004U /**< Sleep Mode */ +#define XCANPS_SR_LBACK_MASK 0x00000002U /**< Loop Back Mode */ +#define XCANPS_SR_CONFIG_MASK 0x00000001U /**< Configuration Mode */ +/* @} */ + +/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks + * @{ + */ +#define XCANPS_IXR_TXFEMP_MASK 0x00004000U /**< Tx Fifo Empty Interrupt */ +#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */ +#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */ +#define XCANPS_IXR_WKUP_MASK 0x00000800U /**< Wake up Interrupt */ +#define XCANPS_IXR_SLP_MASK 0x00000400U /**< Sleep Interrupt */ +#define XCANPS_IXR_BSOFF_MASK 0x00000200U /**< Bus Off Interrupt */ +#define XCANPS_IXR_ERROR_MASK 0x00000100U /**< Error Interrupt */ +#define XCANPS_IXR_RXNEMP_MASK 0x00000080U /**< RX FIFO Not Empty Interrupt */ +#define XCANPS_IXR_RXOFLW_MASK 0x00000040U /**< RX FIFO Overflow Interrupt */ +#define XCANPS_IXR_RXUFLW_MASK 0x00000020U /**< RX FIFO Underflow Interrupt */ +#define XCANPS_IXR_RXOK_MASK 0x00000010U /**< New Message Received Intr */ +#define XCANPS_IXR_TXBFLL_MASK 0x00000008U /**< TX High Priority Buf Full */ +#define XCANPS_IXR_TXFLL_MASK 0x00000004U /**< TX FIFO Full Interrupt */ +#define XCANPS_IXR_TXOK_MASK 0x00000002U /**< TX Successful Interrupt */ +#define XCANPS_IXR_ARBLST_MASK 0x00000001U /**< Arbitration Lost Interrupt */ +#define XCANPS_IXR_ALL ((u32)XCANPS_IXR_RXFWMFLL_MASK | \ + (u32)XCANPS_IXR_WKUP_MASK | \ + (u32)XCANPS_IXR_SLP_MASK | \ + (u32)XCANPS_IXR_BSOFF_MASK | \ + (u32)XCANPS_IXR_ERROR_MASK | \ + (u32)XCANPS_IXR_RXNEMP_MASK | \ + (u32)XCANPS_IXR_RXOFLW_MASK | \ + (u32)XCANPS_IXR_RXUFLW_MASK | \ + (u32)XCANPS_IXR_RXOK_MASK | \ + (u32)XCANPS_IXR_TXBFLL_MASK | \ + (u32)XCANPS_IXR_TXFLL_MASK | \ + (u32)XCANPS_IXR_TXOK_MASK | \ + (u32)XCANPS_IXR_ARBLST_MASK) +/* @} */ + +/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_TCR_CTS_MASK 0x00000001U /**< Clear Timestamp counter mask */ +/* @} */ + +/** @name CAN Watermark Register (WIR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_WIR_FW_MASK 0x0000003FU /**< Rx Full Threshold mask */ +#define XCANPS_WIR_EW_MASK 0x00003F00U /**< Tx Empty Threshold mask */ +#define XCANPS_WIR_EW_SHIFT 0x00000008U /**< Tx Empty Threshold shift */ + +/* @} */ + +/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter + Mask/Acceptance Filter ID) + * @{ + */ +#define XCANPS_IDR_ID1_MASK 0xFFE00000U /**< Standard Messg Identifier */ +#define XCANPS_IDR_ID1_SHIFT 21U +#define XCANPS_IDR_SRR_MASK 0x00100000U /**< Substitute Remote TX Req */ +#define XCANPS_IDR_SRR_SHIFT 20U +#define XCANPS_IDR_IDE_MASK 0x00080000U /**< Identifier Extension */ +#define XCANPS_IDR_IDE_SHIFT 19U +#define XCANPS_IDR_ID2_MASK 0x0007FFFEU /**< Extended Message Ident */ +#define XCANPS_IDR_ID2_SHIFT 1U +#define XCANPS_IDR_RTR_MASK 0x00000001U /**< Remote TX Request */ +/* @} */ + +/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DLCR_DLC_MASK 0xF0000000U /**< Data Length Code */ +#define XCANPS_DLCR_DLC_SHIFT 28U +#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU /**< Timestamp Mask (Rx only) */ + +/* @} */ + +/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW1R_DB0_MASK 0xFF000000U /**< Data Byte 0 */ +#define XCANPS_DW1R_DB0_SHIFT 24U +#define XCANPS_DW1R_DB1_MASK 0x00FF0000U /**< Data Byte 1 */ +#define XCANPS_DW1R_DB1_SHIFT 16U +#define XCANPS_DW1R_DB2_MASK 0x0000FF00U /**< Data Byte 2 */ +#define XCANPS_DW1R_DB2_SHIFT 8U +#define XCANPS_DW1R_DB3_MASK 0x000000FFU /**< Data Byte 3 */ +/* @} */ + +/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW2R_DB4_MASK 0xFF000000U /**< Data Byte 4 */ +#define XCANPS_DW2R_DB4_SHIFT 24U +#define XCANPS_DW2R_DB5_MASK 0x00FF0000U /**< Data Byte 5 */ +#define XCANPS_DW2R_DB5_SHIFT 16U +#define XCANPS_DW2R_DB6_MASK 0x0000FF00U /**< Data Byte 6 */ +#define XCANPS_DW2R_DB6_SHIFT 8U +#define XCANPS_DW2R_DB7_MASK 0x000000FFU /**< Data Byte 7 */ +/* @} */ + +/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_AFR_UAF4_MASK 0x00000008U /**< Use Acceptance Filter No.4 */ +#define XCANPS_AFR_UAF3_MASK 0x00000004U /**< Use Acceptance Filter No.3 */ +#define XCANPS_AFR_UAF2_MASK 0x00000002U /**< Use Acceptance Filter No.2 */ +#define XCANPS_AFR_UAF1_MASK 0x00000001U /**< Use Acceptance Filter No.1 */ +#define XCANPS_AFR_UAF_ALL_MASK ((u32)XCANPS_AFR_UAF4_MASK | \ + (u32)XCANPS_AFR_UAF3_MASK | \ + (u32)XCANPS_AFR_UAF2_MASK | \ + (u32)XCANPS_AFR_UAF1_MASK) +/* @} */ + +/** @name CAN frame length constants + * @{ + */ +#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */ +/* @} */ + +/* For backwards compatibilty */ +#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET +#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET +#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET +#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET + +#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK +#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET +#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK + + + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the CanPs interface + */ +void XCanPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_intr.c new file mode 100644 index 000000000..f3ad9d270 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_intr.c @@ -0,0 +1,416 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_intr.c +* +* This file contains functions related to CAN interrupt handling. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/****************************************************************************/ +/** +* +* This routine enables interrupt(s). Use the XCANPS_IXR_* constants defined in +* xcanps_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to enable. Bit positions of 1 will be enabled. +* Bit positions of 0 will keep the previous setting. This mask is +* formed by OR'ing XCANPS_IXR_* bits defined in xcanps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write to the IER to enable the specified interrupts. + */ + IntrValue = XCanPs_IntrGetEnabled(InstancePtr); + IntrValue |= Mask & XCANPS_IXR_ALL; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET, IntrValue); +} + +/****************************************************************************/ +/** +* +* This routine disables interrupt(s). Use the XCANPS_IXR_* constants defined in +* xcanps_hw.h to create the bit-mask to disable interrupt(s). +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to disable. Bit positions of 1 will be +* disabled. Bit positions of 0 will keep the previous setting. +* This mask is formed by OR'ing XCANPS_IXR_* bits defined in +* xcanps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write to the IER to disable the specified interrupts. + */ + IntrValue = XCanPs_IntrGetEnabled(InstancePtr); + IntrValue &= ~Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET, IntrValue); +} + +/****************************************************************************/ +/** +* +* This routine returns enabled interrupt(s). Use the XCANPS_IXR_* constants +* defined in xcanps_hw.h to interpret the returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return Enabled interrupt(s) in a 32-bit format. +* +* @note None. +* +*****************************************************************************/ +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET); +} + + +/****************************************************************************/ +/** +* +* This routine returns interrupt status read from Interrupt Status Register. +* Use the XCANPS_IXR_* constants defined in xcanps_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The value stored in Interrupt Status Register. +* +* @note None. +* +*****************************************************************************/ +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ISR_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function clears interrupt(s). Every bit set in Interrupt Status +* Register indicates that a specific type of interrupt is occurring, and this +* function clears one or more interrupts by writing a bit mask to Interrupt +* Clear Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* Bit positions of 0 will not change the previous interrupt +* status. This mask is formed by OR'ing XCANPS_IXR_* bits defined +* in xcanps_hw.h. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Clear the currently pending interrupts. + */ + IntrValue = XCanPs_IntrGetStatus(InstancePtr); + IntrValue &= Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_ICR_OFFSET, + IntrValue); +} + +/*****************************************************************************/ +/** +* +* This routine is the interrupt handler for the CAN driver. +* +* This handler reads the interrupt status from the ISR, determines the source of +* the interrupts, calls according callbacks, and finally clears the interrupts. +* +* Application beyond this driver is responsible for providing callbacks to +* handle interrupts and installing the callbacks using XCanPs_SetHandler() +* during initialization phase. An example delivered with this driver +* demonstrates how this could be done. +* +* @param InstancePtr is a pointer to the XCanPs instance that just +* interrupted. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_IntrHandler(void *InstancePtr) +{ + u32 PendingIntr; + u32 EventIntr; + XCanPs *CanPtr = (XCanPs *) ((void *)InstancePtr); + + Xil_AssertVoid(CanPtr != NULL); + Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY); + + PendingIntr = XCanPs_IntrGetStatus(CanPtr); + PendingIntr &= XCanPs_IntrGetEnabled(CanPtr); + + /* + * Clear all pending interrupts. + * Rising Edge interrupt + */ + XCanPs_IntrClear(CanPtr, PendingIntr); + + /* + * An error interrupt is occurring. + */ + if (((PendingIntr & XCANPS_IXR_ERROR_MASK) != (u32)0) && + (CanPtr->ErrorHandler != NULL)) { + CanPtr->ErrorHandler(CanPtr->ErrorRef, + XCanPs_GetBusErrorStatus(CanPtr)); + /* + * Clear Error Status Register. + */ + XCanPs_ClearBusErrorStatus(CanPtr, + XCanPs_GetBusErrorStatus(CanPtr)); + } + + /* + * Check if any following event interrupt is pending: + * - RX FIFO Overflow + * - RX FIFO Underflow + * - TX High Priority Buffer full + * - TX FIFO Full + * - Wake up from sleep mode + * - Enter sleep mode + * - Enter Bus off status + * - Arbitration is lost + * + * If so, call event callback provided by upper level. + */ + EventIntr = PendingIntr & ((u32)XCANPS_IXR_RXOFLW_MASK | + (u32)XCANPS_IXR_RXUFLW_MASK | + (u32)XCANPS_IXR_TXBFLL_MASK | + (u32)XCANPS_IXR_TXFLL_MASK | + (u32)XCANPS_IXR_WKUP_MASK | + (u32)XCANPS_IXR_SLP_MASK | + (u32)XCANPS_IXR_BSOFF_MASK | + (u32)XCANPS_IXR_ARBLST_MASK); + if ((EventIntr != (u32)0) && (CanPtr->EventHandler != NULL)) { + CanPtr->EventHandler(CanPtr->EventRef, EventIntr); + + if ((EventIntr & XCANPS_IXR_BSOFF_MASK) != (u32)0) { + /* + * Event callback should reset whole device if "Enter + * Bus Off Status" interrupt occurred. All pending + * interrupts are cleared and no further checking and + * handling of other interrupts is needed any more. + */ + return; + } else { + /*This else was made for misra-c compliance*/ + ; + } + } + + + if (((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK | + XCANPS_IXR_RXNEMP_MASK)) != (u32)0) && + (CanPtr->RecvHandler != NULL)) { + + /* + * This case happens when + * A number of frames depending on the Rx FIFO Watermark + * threshold are received. + * And also when frame was received and is sitting in RX FIFO. + * + * XCANPS_IXR_RXOK_MASK is not used because the bit is set + * just once even if there are multiple frames sitting + * in the RX FIFO. + * + * XCANPS_IXR_RXNEMP_MASK is used because the bit can be + * set again and again automatically as long as there is + * at least one frame in RX FIFO. + */ + CanPtr->RecvHandler(CanPtr->RecvRef); + } + + /* + * A frame was transmitted successfully. + */ + if (((PendingIntr & XCANPS_IXR_TXOK_MASK) != (u32)0) && + (CanPtr->SendHandler != NULL)) { + CanPtr->SendHandler(CanPtr->SendRef); + } +} + + +/*****************************************************************************/ +/** +* +* This routine installs an asynchronous callback function for the given +* HandlerType: +* +* 
+* HandlerType			Callback Function Type
+* -----------------------	------------------------
+* XCANPS_HANDLER_SEND		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_RECV		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_ERROR		XCanPs_ErrorHandler
+* XCANPS_HANDLER_EVENT		XCanPs_EventHandler
+*
+* HandlerType			Invoked by this driver when:
+* -------------------------------------------------------------------------
+* XCANPS_HANDLER_SEND		A frame transmitted by a call to
+*				XCanPs_Send() has been sent successfully.
+*
+* XCANPS_HANDLER_RECV		A frame(s) has been received and is sitting in
+*				the RX FIFO.
+*
+* XCANPS_HANDLER_ERROR		An error interrupt is occurring.
+*
+* XCANPS_HANDLER_EVENT		Any other kind of interrupt is occurring.
+*
+* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param HandlerType specifies which handler is to be attached. +* @param CallBackFunc is the address of the callback function. +* @param CallBackRef is a user data item that will be passed to the +* callback function when it is invoked. +* +* @return +* - XST_SUCCESS when handler is installed. +* - XST_INVALID_PARAM when HandlerType is invalid. +* +* @note +* Invoking this function for a handler that already has been installed replaces +* it with the new handler. +* +******************************************************************************/ +s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + switch (HandlerType) { + case XCANPS_HANDLER_SEND: + InstancePtr->SendHandler = + (XCanPs_SendRecvHandler) CallBackFunc; + InstancePtr->SendRef = CallBackRef; + Status = XST_SUCCESS; + break; + + case XCANPS_HANDLER_RECV: + InstancePtr->RecvHandler = + (XCanPs_SendRecvHandler) CallBackFunc; + InstancePtr->RecvRef = CallBackRef; + Status = XST_SUCCESS; + break; + + case XCANPS_HANDLER_ERROR: + InstancePtr->ErrorHandler = + (XCanPs_ErrorHandler) CallBackFunc; + InstancePtr->ErrorRef = CallBackRef; + Status = XST_SUCCESS; + break; + + case XCANPS_HANDLER_EVENT: + InstancePtr->EventHandler = + (XCanPs_EventHandler) CallBackFunc; + InstancePtr->EventRef = CallBackRef; + Status = XST_SUCCESS; + break; + + default: + Status = XST_INVALID_PARAM; + break; + } + return Status; +} + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_selftest.c new file mode 100644 index 000000000..c8a441ab8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_selftest.c @@ -0,0 +1,231 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_selftest.c +* +* This file contains a diagnostic self-test function for the XCanPs driver. +* +* Read xcanps.h file for more information. +* +* @note +* The Baud Rate Prescaler Register (BRPR) and Bit Timing Register(BTR) +* are setup such that CAN baud rate equals 40Kbps, given the CAN clock +* equal to 24MHz. These need to be changed based on the desired baudrate +* and CAN clock frequency. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*						 SDK claims a 40kbps baud rate but it's not.
+* 3.00  kvn    02/13/15 Modified code for MISRA_C:2012 compliance.
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xstatus.h" +#include "xcanps.h" + +/************************** Constant Definitions ****************************/ + +#define XCANPS_MAX_FRAME_SIZE_IN_WORDS ((XCANPS_MAX_FRAME_SIZE) / (sizeof(u32))) + +#define FRAME_DATA_LENGTH 8U /* Frame Data field length */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/* + * Buffers to hold frames to send and receive. These are declared as global so + * that they are not on the stack. + */ +static u32 TxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; +static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; + +/************************** Function Prototypes *****************************/ + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the CAN driver/device. The test resets +* the device, sets up the Loop Back mode, sends a standard frame, receives the +* frame, verifies the contents, and resets the device again. +* +* Note that this is a destructive test in that resets of the device are +* performed. Refer the device specification for the device status after +* the reset operation. +* +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - XST_SUCCESS if the self-test passed. i.e., the frame +* received via the internal loop back has the same contents as +* the frame sent. +* - XST_FAILURE Otherwise. +* +* @note +* +* If the CAN device does not work properly, this function may enter an +* infinite loop and will never return to the caller. +*

+* If XST_FAILURE is returned, the device is not reset so that the caller could +* have a chance to check reason(s) causing the failure. +* +******************************************************************************/ +s32 XCanPs_SelfTest(XCanPs *InstancePtr) +{ + u8 *FramePtr; + s32 Status; + u32 Index; + u8 GetModeResult; + u32 RxEmptyResult; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_Reset(InstancePtr); + + /* + * The device should enter Configuration Mode immediately after + * reset above is finished. Now check the mode and return error code if + * it is not Configuration Mode. + */ + if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + return Status; + } + + /* + * Setup Baud Rate Prescaler Register (BRPR) and Bit Timing Register + * (BTR) such that CAN baud rate equals 40Kbps, given the CAN clock + * equal to 24MHz. For more information see the CAN 2.0A, CAN 2.0B, + * ISO 11898-1 specifications. + */ + (void)XCanPs_SetBaudRatePrescaler(InstancePtr, (u8)29U); + (void)XCanPs_SetBitTiming(InstancePtr, (u8)3U, (u8)2U, (u8)15U); + + /* + * Enter the loop back mode. + */ + XCanPs_EnterMode(InstancePtr, XCANPS_MODE_LOOPBACK); + GetModeResult = XCanPs_GetMode(InstancePtr); + while (GetModeResult != ((u8)XCANPS_MODE_LOOPBACK)) { + GetModeResult = XCanPs_GetMode(InstancePtr); + } + + /* + * Create a frame to send with known values so we can verify them + * on receive. + */ + TxFrame[0] = (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U); + TxFrame[1] = (u32)XCanPs_CreateDlcValue((u32)8U); + + FramePtr = (u8 *)((void *)(&TxFrame[2])); + for (Index = 0U; Index < 8U; Index++) { + if(*FramePtr != 0U) { + *FramePtr = (u8)Index; + *FramePtr++; + } + } + + /* + * Send the frame. + */ + Status = XCanPs_Send(InstancePtr, TxFrame); + if (Status != (s32)XST_SUCCESS) { + Status = XST_FAILURE; + return Status; + } + + /* + * Wait until the frame arrives RX FIFO via internal loop back. + */ + RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK; + + while (RxEmptyResult == (u32)0U) { + RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK; + } + + /* + * Receive the frame. + */ + Status = XCanPs_Recv(InstancePtr, RxFrame); + if (Status != (s32)XST_SUCCESS) { + Status = XST_FAILURE; + return Status; + } + + /* + * Verify Identifier and Data Length Code. + */ + if (RxFrame[0] != + (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U)) { + Status = XST_FAILURE; + return Status; + } + + if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) { + Status = XST_FAILURE; + return Status; + } + + + for (Index = 2U; Index < (XCANPS_MAX_FRAME_SIZE_IN_WORDS); Index++) { + if (RxFrame[Index] != TxFrame[Index]) { + Status = XST_FAILURE; + return Status; + } + } + + /* + * Reset device again before returning to the caller. + */ + XCanPs_Reset(InstancePtr); + + Status = XST_SUCCESS; + return Status; +} + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_sinit.c new file mode 100644 index 000000000..3eed412e1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_0/src/xcanps_sinit.c @@ -0,0 +1,100 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_sinit.c +* +* This file contains the implementation of the XCanPs driver's static +* initialization functionality. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +extern XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES]; + +/*****************************************************************************/ +/** +* +* This function looks for the device configuration based on the unique device +* ID. The table XCanPs_ConfigTable[] contains the configuration information for +* each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId) +{ + XCanPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; Index < (u32)XPAR_XCANPS_NUM_INSTANCES; Index++) { + if (XCanPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XCanPs_ConfigTable[Index]; + break; + } + } + + return (XCanPs_Config *)CfgPtr; +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_0/src/Makefile new file mode 100644 index 000000000..747a7a10d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_0/src/Makefile @@ -0,0 +1,22 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES=*.c +INCLUDEFILES=*.h + +libs: + echo "Compiling cpu_cortexa53" + +.PHONY: include +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_0/src/xcpu_cortexa53.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_0/src/xcpu_cortexa53.h new file mode 100644 index 000000000..cbdfc1705 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_0/src/xcpu_cortexa53.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa53.h +* +* dummy file +* +******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/Makefile new file mode 100644 index 000000000..778797bcf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner csudma_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling csudma" + +csudma_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: csudma_includes + +csudma_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma.c new file mode 100644 index 000000000..186e3619a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma.c @@ -0,0 +1,764 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma.c +* +* This file contains the implementation of the interface functions for CSU_DMA +* driver. Refer to the header file xcsudma.h for more detailed information. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" + +/************************** Function Prototypes ******************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* This function initializes an CSU_DMA core. This function must be called +* prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting +* up the instance data and ensuring the hardware is in a quiescent state. +* +* @param InstancePtr is a pointer to the XCsuDma instance. +* @param CfgPtr is a reference to a structure containing information +* about a specific XCsuDma instance. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. The caller is responsible for keeping the +* address mapping from EffectiveAddr to the device physical +* base address unchanged once this function is invoked. +* Unexpected errors may occur if the address mapping changes +* after this function is called. If address translation is not +* used, pass in the physical address instead. +* +* @return +* - XST_SUCCESS if initialization was successful. +* +* @note None. +* +******************************************************************************/ +s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, + u32 EffectiveAddr) +{ + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(CfgPtr != NULL); + Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0)); + + /* Setup the instance */ + (void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr, + sizeof(XCsuDma_Config)); + InstancePtr->Config.BaseAddress = EffectiveAddr; + + XCsuDma_Reset(); + + InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY); + + return (XST_SUCCESS); + +} + +/*****************************************************************************/ +/** +* +* This function sets the starting address and amount(size) of the data to be +* transfered from/to the memory through the AXI interface. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Addr is a 64 bit variable which holds the starting address of +* data which needs to write into the memory(DST) (or read from +* the memory(SRC)). +* @param Size is a 32 bit variable which represents the number of 4 byte +* words needs to be transfered from starting address. +* @param EnDataLast is to trigger an end of message. It will enable or +* disable data_inp_last signal to stream interface when current +* command is completed. It is applicable only to source channel +* and neglected for destination channel. +* - 1 - Asserts data_inp_last signal. +* - 0 - data_inp_last will not be asserted. +* +* @return None. +* +* @note Data_inp_last signal is asserted simultaneously with the +* data_inp_valid signal associated with the final 32-bit word +* transfer. +* +******************************************************************************/ +void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + UINTPTR Addr, u32 Size, u8 EnDataLast) +{ + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(((Addr) & (u64)(XCSUDMA_ADDR_LSB_MASK)) == (u64)0x00); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX)); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + /* Flushing cache memory */ + if (Channel == (XCSUDMA_SRC_CHANNEL)) { + Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT)); + } + /* Invalidating cache memory */ + else { + Xil_DCacheInvalidateRange(Addr, Size << + (u32)(XCSUDMA_SIZE_SHIFT)); + } + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((u32)(Addr) & (u32)(XCSUDMA_ADDR_MASK))); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_MSB_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (((u64)Addr >> (u32)(XCSUDMA_MSB_ADDR_SHIFT)) & + (u32)(XCSUDMA_MSB_ADDR_MASK))); + + if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((Size << (u32)(XCSUDMA_SIZE_SHIFT)) | + (u32)(XCSUDMA_LAST_WORD_MASK))); + } + else { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Size << (u32)(XCSUDMA_SIZE_SHIFT))); + } +} + +/*****************************************************************************/ +/** +* +* This function returns the current address location of the memory, from where +* it has to read the data(SRC) or the location where it has to write the data +* (DST) based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Address is a 64 bit variable which holds the current address. +* - From this location data has to be read(SRC) +* - At this location data has to be written(DST) +* +* @note None. +* +******************************************************************************/ +u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + u64 FullAddr; + + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + FullAddr = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + FullAddr |= (u64)((u64)XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_MSB_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) << + (u64)(XCSUDMA_MSB_ADDR_SHIFT)); + + return FullAddr; +} + +/*****************************************************************************/ +/** +* +* This function returns the size of the data yet to be transfered from memory +* to CSU_DMA or CSU_DMA to memory based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Size is amount of data yet to be transfered. +* +* @note None. +* +******************************************************************************/ +u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + u32 Size; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + Size = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) >> + (u32)(XCSUDMA_SIZE_SHIFT); + + return Size; +} + +/*****************************************************************************/ +/** +* +* This function pause the Channel data tranfer to/from memory or to/from stream +* based on pause type. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Type is type of the pause to be enabled. +* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory +* - SRC Stops issuing of new read commands to memory. +* - DST Stops issuing of new write commands to memory. +* - XCSUDMA_PAUSE_STREAM(1) - Pause stream +* - SRC Stops transfer of data from FIFO to Stream. +* - DST Stops transfer of data from stream to FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) || + (Type == (XCSUDMA_PAUSE_STREAM))); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + /* Pause Memory Read/Write/Stream operations */ + if (Type == (XCSUDMA_PAUSE_MEMORY)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) | + (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK))); + } + if (Type == (XCSUDMA_PAUSE_STREAM)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + (Channel * (u32)XCSUDMA_OFFSET_DIFF))) | + (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK))); + } +} + +/*****************************************************************************/ +/** +* +* This functions checks whether Channel's memory or stream is paused or not +* based on the given pause type. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Type is type of the pause which needs to be checked. +* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory +* - SRC Stops issuing of new read commands to memory. +* - DST Stops issuing of new write commands to memory. +* - XCSUDMA_PAUSE_STREAM(1) - Pause stream +* - SRC Stops transfer of data from FIFO to Stream. +* - DST Stops transfer of data from stream to FIFO. +* +* @return Returns the pause status. +* - TRUE if it is in paused state. +* - FALSE if it is not in pause state. +* +* @note None. +* +******************************************************************************/ +s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type) +{ + + u32 Data; + s32 PauseState; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertNonvoid((Type == (XCSUDMA_PAUSE_MEMORY)) || + (Type == (XCSUDMA_PAUSE_STREAM))); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + /* To know Pause condition of Memory Read/Write/Stream operations */ + if (Type == (XCSUDMA_PAUSE_MEMORY)) { + if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)) == + (u32)0x00) { + PauseState = (s32)(FALSE); + } + else { + PauseState = (s32)(TRUE); + } + } + else { + if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)) == + (u32)0x00) { + PauseState = (s32)(FALSE); + } + else { + PauseState = (s32)(TRUE); + } + } + + return (s32)PauseState; + +} + +/*****************************************************************************/ +/** +* +* This function resumes the channel if it is in paused state and continues +* where it has left or no effect if it is not in paused state, based on the +* type of pause. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Type is type of the pause to be Resume if it is in pause +* state. +* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory +* - SRC Stops issuing of new read commands to memory. +* - DST Stops issuing of new write commands to memory. +* - XCSUDMA_PAUSE_STREAM(1) - Pause stream +* - SRC Stops transfer of data from FIFO to Stream. +* - DST Stops transfer of data from stream to FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type) +{ + u32 Data; + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) || + (Type == (XCSUDMA_PAUSE_STREAM))); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + if (Type == (XCSUDMA_PAUSE_MEMORY)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Data & + (~(XCSUDMA_CTRL_PAUSE_MEM_MASK)))); + } + if (Type == (XCSUDMA_PAUSE_STREAM)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + (((u32)Channel) * (u32)(XCSUDMA_OFFSET_DIFF))), + ( Data & + (~(XCSUDMA_CTRL_PAUSE_STRM_MASK)))); + } +} + +/*****************************************************************************/ +/** +* +* This function returns the sum of all the data read from AXI memory. It is +* valid only one we use CSU_DMA source channel. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* +* @return Returns the sum of all the data read from memory. +* +* @note Before start of the transfer need to clear this register to get +* correct sum otherwise it adds to previous value which results +* to wrong output. +* Valid only for source channel +* +******************************************************************************/ +u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr) +{ + u32 ChkSum; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == + (u32)(XIL_COMPONENT_IS_READY)); + + ChkSum = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CRC_OFFSET)); + + return ChkSum; + +} +/*****************************************************************************/ +/** +* +* This function clears the check sum of the data read from AXI memory. It is +* valid only for CSU_DMA source channel. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* +* @return Returns the sum of all the data read from memory. +* +* @note Before start of the transfer need to clear this register to get +* correct sum otherwise it adds to previous value which results +* to wrong output. +* +******************************************************************************/ +void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr) +{ + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CRC_OFFSET), (u32)(XCSUDMA_CRC_RESET_MASK)); +} + +/*****************************************************************************/ +/** +* This function cofigures all the values of CSU_DMA's Channels with the values +* of updated XCsuDma_Configure structure. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param ConfigurValues is a pointer to the structure XCsuDma_Configure +* whose values are used to configure CSU_DMA core. +* - SssFifoThesh When the DST FIFO level >= this value, +* the SSS interface signal, "data_out_fifo_level_hit" will be +* asserted. This mechanism can be used by the SSS to flow +* control data that is being looped back from the SRC DMA. +* - Range is (0x10 to 0x7A) threshold is 17 to 123 +* entries. +* - It is valid only for DST CSU_DMA IP. +* - ApbErr When accessed to invalid APB the resulting +* pslerr will be +* - 0 - 1'b0 +* - 1 - 1'b1 +* - EndianType Type of endianness +* - 0 doesn't change order +* - 1 will flip the order. +* - AxiBurstType....Type of the burst +* - 0 will issue INCR type burst +* - 1 will issue FIXED type burst +* - TimeoutValue Time out value for timers +* - 0x000 to 0xFFE are valid inputs +* - 0xFFF clears both timers +* - FifoThresh......Programmed watermark value +* - Range is 0x00 to 0x80 (0 to 128 entries). +* - Acache Sets the AXI CACHE bits on the AXI Write/Read +* channel. +* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] +* for DST channel are always 1, we need to configure +* remaining 3 signal support +* (Bufferable, Read allocate and Write allocate). +* Valid inputs are: +* - 0x000 - Cacheable, but do not allocate +* - 0x001 - Cacheable and bufferable, but do not allocate +* - 0x010 - Cacheable write-through, allocate on reads +* only +* - 0x011 - Cacheable write-back, allocate on reads only +* - 0x100 - Cacheable write-through, allocate on writes +* only +* - 0x101 - Cacheable write-back, allocate on writes only +* - 0x110 - Cacheable write-through, allocate on both +* reads and writes +* - 0x111 - Cacheable write-back, allocate on both reads +* and writes +* - RouteBit To select route +* - 0 : Command will be routed normally +* - 1 : Command will be routed to APU's cache controller +* - TimeoutEn To enable or disable time out counters +* - 0 : The 2 Timeout counters are disabled +* - 1 : The 2 Timeout counters are enabled +* - TimeoutPre Set the prescaler value for the timeout in +* clk (~2.5ns) cycles +* - Range is 0x000(Prescaler enables timer every cycles) +* to 0xFFF(Prescaler enables timer every 4096 cycles) +* - MaxOutCmds Controls the maximumum number of outstanding +* AXI read commands issued. +* - Range is 0x0(Up to 1 Outstanding Read command +* allowed) to 0x8 (Up to 9 Outstanding Read +* command allowed) +* +* @return None. +* +* @note To use timers timeout value Timeout enable field should be +* enabled. +* +******************************************************************************/ +void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues) +{ + u32 Data; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + Xil_AssertVoid(ConfigurValues != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(XCsuDma_IsBusy(InstancePtr, Channel) != (s32)(TRUE)); + + Data = (((ConfigurValues->EndianType << + (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) & + (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) | + ((ConfigurValues->ApbErr << + (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)) & + (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) | + ((ConfigurValues->AxiBurstType << + (u32)(XCSUDMA_CTRL_BURST_SHIFT)) & + (u32)(XCSUDMA_CTRL_BURST_MASK)) | + ((ConfigurValues->TimeoutValue << + (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)) & + (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) | + ((ConfigurValues->FifoThresh << + (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)) & + (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK))); + if(Channel == XCSUDMA_DST_CHANNEL) { + Data = Data | (u32)((ConfigurValues->SssFifoThesh << + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)) & + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)); + } + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); + + Data = (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL2_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) & + (u32)(XCSUDMA_CTRL2_RESERVED_MASK)); + Data |= (((ConfigurValues->Acache << + (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)) & + (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) | + ((ConfigurValues->RouteBit << + (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)) & + (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) | + ((ConfigurValues->TimeoutEn << + (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)) & + (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) | + ((ConfigurValues->TimeoutPre << + (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)) & + (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) | + ((ConfigurValues->MaxOutCmds) & + (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK))); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL2_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); +} + +/*****************************************************************************/ +/** +* +* This function updates XCsuDma_Configure structure members with the cofigured +* values of CSU_DMA's Channel. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param ConfigurValues is a pointer to the structure XCsuDma_Configure +* whose members are updated with configurations of CSU_DMA core. +* - SssFifoThesh When the DST FIFO level >= this value, +* the SSS interface signal, "data_out_fifo_level_hit" will be +* asserted. This mechanism can be used by the SSS to flow +* control data that is being looped back from the SRC DMA. +* - Range is (0x10 to 0x7A) threshold is 17 to 123 +* entries. +* - It is valid only for DST CSU_DMA IP. +* - ApbErr When accessed to invalid APB the resulting +* pslerr will be +* - 0 - 1'b0 +* - 1 - 1'b1 +* - EndianType Type of endianness +* - 0 doesn't change order +* - 1 will flip the order. +* - AxiBurstType....Type of the burst +* - 0 will issue INCR type burst +* - 1 will issue FIXED type burst +* - TimeoutValue Time out value for timers +* - 0x000 to 0xFFE are valid inputs +* - 0xFFF clears both timers +* - FifoThresh......Programmed watermark value +* - Range is 0x00 to 0x80 (0 to 128 entries). +* - Acache Sets the AXI CACHE bits on the AXI Write/Read +* channel. +* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] +* for DST channel are always 1, we need to configure +* remaining 3 signal support +* (Bufferable, Read allocate and Write allocate). +* Valid inputs are: +* - 0x000 - Cacheable, but do not allocate +* - 0x001 - Cacheable and bufferable, but do not allocate +* - 0x010 - Cacheable write-through, allocate on reads +* only +* - 0x011 - Cacheable write-back, allocate on reads only +* - 0x100 - Cacheable write-through, allocate on writes +* only +* - 0x101 - Cacheable write-back, allocate on writes only +* - 0x110 - Cacheable write-through, allocate on both +* reads and writes +* - 0x111 - Cacheable write-back, allocate on both reads +* and writes +* - RouteBit To select route +* - 0 : Command will be routed based normally +* - 1 : Command will be routed to APU's cache controller +* - TimeoutEn To enable or disable time out counters +* - 0 : The 2 Timeout counters are disabled +* - 1 : The 2 Timeout counters are enabled +* - TimeoutPre Set the prescaler value for the timeout in +* clk (~2.5ns) cycles +* - Range is 0x000(Prescaler enables timer every cycles) +* to 0xFFF(Prescaler enables timer every 4096 cycles) +* - MaxOutCmds Controls the maximumum number of outstanding +* AXI read commands issued. +* - Range is 0x0(Up to 1 Outstanding Read command +* allowed) to 0x8 (Up to 9 Outstanding Read command +* allowed) +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues) +{ + u32 Data; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(ConfigurValues != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + if (Channel == (XCSUDMA_DST_CHANNEL)) { + ConfigurValues->SssFifoThesh = + (u8)((Data & + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)) >> + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)); + } + ConfigurValues->ApbErr = + (u8)((Data & (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) >> + (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)); + ConfigurValues->EndianType = + (u8)((Data & (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) >> + (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)); + ConfigurValues->AxiBurstType = + (u8)((Data & (u32)(XCSUDMA_CTRL_BURST_MASK)) >> + (u32)(XCSUDMA_CTRL_BURST_SHIFT)); + ConfigurValues->TimeoutValue = + ((Data & (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) >> + (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)); + ConfigurValues->FifoThresh = + (u8)((Data & (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)) >> + (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL2_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + ConfigurValues->Acache = + (u8)((Data & (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) >> + (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)); + ConfigurValues->RouteBit = + (u8)((Data & (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) >> + (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)); + ConfigurValues->TimeoutEn = + (u8)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) >> + (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)); + ConfigurValues->TimeoutPre = + (u16)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) >> + (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)); + ConfigurValues->MaxOutCmds = + (u8)((Data & (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK))); + +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma.h new file mode 100644 index 000000000..831bcfccd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma.h @@ -0,0 +1,414 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* The CSU_DMA is present inside CSU (Configuration Security Unit) module which +* is located within the Low-Power Subsystem (LPS) internal to the PS. +* CSU_DMA allows the CSU to move data efficiently between the memory (32 bit +* AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure +* Stream Switch (SSS). +* +* The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC +* (read) channel and DST (write) channel. The DMA is effectively able to +* transfer data: +* - From PS-side to the SSS-side (SRC DMA only) +* - From SSS-side to the PS-side (DST DMA only) +* - Simultaneous PS-side to SSS_side and SSS-side to the PS-side +* +* Initialization & Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CSU_DMA core. +* +* XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core. +* The user needs to first call the XCsuDma_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to the +* XCsuDma_CfgInitialize() API. +* +* Interrupts +* This driver will not support handling of interrupts user should write handler +* to handle the interrupts. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCsuDma driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* @file xcsudma.h +* +* This header file contains identifiers and register-level driver functions (or +* macros), range macros, structure typedefs that can be used to access the +* Xilinx CSU_DMA core instance. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +#ifndef XCSUDMA_H_ +#define XCSUDMA_H_ /**< Prevent circular inclusions + * by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xcsudma_hw.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xil_cache.h" + +/************************** Constant Definitions *****************************/ + +/** @name CSU_DMA Channels + * @{ + */ +typedef enum { + XCSUDMA_SRC_CHANNEL = 0U, /**< Source Channel of CSU_DMA */ + XCSUDMA_DST_CHANNEL /**< Destination Channel of CSU_DMA */ +}XCsuDma_Channel; +/*@}*/ + +/** @name CSU_DMA pause types + * @{ + */ +typedef enum { + XCSUDMA_PAUSE_MEMORY, /**< Pauses memory data transfer + * to/from CSU_DMA */ + XCSUDMA_PAUSE_STREAM, /**< Pauses stream data transfer + * to/from CSU_DMA */ +}XCsuDma_PauseType; + +/*@}*/ + + +/** @name Ranges of Size + * @{ + */ +#define XCSUDMA_SIZE_MAX 0x07FFFFFF /**< Maximum allowed no of words */ + +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* This function resets the CSU_DMA core. +* +* @param None. +* +* @return None. +* +* @note None. +* C-style signature: +* void XCsuDma_Reset() +* +******************************************************************************/ +#define XCsuDma_Reset() \ + Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \ + (u32)(XCSUDMA_RESET_SET_MASK)); \ + Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \ + (u32)(XCSUDMA_RESET_UNSET_MASK)); + +/*****************************************************************************/ +/** +* This function will be in busy while loop until the data transfer is +* completed. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return None. +* +* @note This function should be called after XCsuDma_Transfer in polled +* mode to wait until the data gets transfered completely. +* C-style signature: +* void XCsuDma_WaitForDone(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_WaitForDone(InstancePtr,Channel) \ + while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_I_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK)) + +/*****************************************************************************/ +/** +* +* This function returns the number of completed SRC/DST DMA transfers that +* have not been acknowledged by software based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Count is number of completed DMA transfers but not acknowledged +* (Range is 0 to 7). +* - 000 - All finished transfers have been acknowledged. +* - Count - Count number of finished transfers are still +* outstanding. +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetDoneCount(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \ + (u32)(XCSUDMA_STS_DONE_CNT_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the current SRC/DST FIFO level in 32 bit words of the +* selected channel +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return FIFO level. (Range is 0 to 128) +* - 0 Indicates empty +* - Any number 1 to 128 indicates the number of entries in FIFO. +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetFIFOLevel(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \ + (u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the current number of read(src)/write(dst) outstanding +* commands based on the type of channel selected. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Count of outstanding commands. (Range is 0 to 9). +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetWROutstandCount(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \ + (u32)(XCUSDMA_STS_OUTSTDG_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the status of Channel either it is busy or not. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Returns the current status of the core. +* - TRUE represents core is currently busy. +* - FALSE represents core is not involved in any transfers. +* +* @note None. +* C-style signature: +* s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +* +******************************************************************************/ + +#define XCsuDma_IsBusy(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \ + (TRUE) : (FALSE) + + +/**************************** Type Definitions *******************************/ + +/** +* This typedef contains configuration information for a CSU_DMA core. +* Each CSU_DMA core should have a configuration structure associated. +*/ +typedef struct { + u16 DeviceId; /**< DeviceId is the unique ID of the + * device */ + u32 BaseAddress; /**< BaseAddress is the physical base address + * of the device's registers */ +} XCsuDma_Config; + + +/******************************************************************************/ +/** +* +* The XCsuDma driver instance data structure. A pointer to an instance data +* structure is passed around by functions to refer to a specific driver +* instance. +*/ +typedef struct { + XCsuDma_Config Config; /**< Hardware configuration */ + u32 IsReady; /**< Device and the driver instance + * are initialized */ +}XCsuDma; + + +/******************************************************************************/ +/** +* This typedef contains all the configuration feilds which needs to be set +* before the start of the data transfer. All these feilds of CSU_DMA can be +* configured by using XCsuDma_SetConfig API. +*/ +typedef struct { + u8 SssFifoThesh; /**< SSS FIFO threshold value */ + u8 ApbErr; /**< ABP invalid access error */ + u8 EndianType; /**< Type of endianess */ + u8 AxiBurstType; /**< Type of AXI bus */ + u32 TimeoutValue; /**< Time out value */ + u8 FifoThresh; /**< FIFO threshold value */ + u8 Acache; /**< AXI CACHE selection */ + u8 RouteBit; /**< Selection of Route */ + u8 TimeoutEn; /**< Enable of time out counters */ + u16 TimeoutPre; /**< Pre scaler value */ + u8 MaxOutCmds; /**< Maximum number of outstanding + * commands */ +}XCsuDma_Configure; + +/*****************************************************************************/ + + +/************************** Function Prototypes ******************************/ + +XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId); + +s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, + u32 EffectiveAddr); +void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + UINTPTR Addr, u32 Size, u8 EnDataLast); +void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr, + u32 Size); +u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel); +u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); +s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); +void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); + +u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr); +void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr); + +void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues); +void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues); +void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value); +u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr); + +/* Interrupt related APIs */ +u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel); +void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +s32 XCsuDma_SelfTest(XCsuDma *InstancePtr); + +/******************************************************************************/ + +#ifdef __cplusplus +} + +#endif + +#endif /* End of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c new file mode 100644 index 000000000..7157ccebf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c @@ -0,0 +1,55 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xcsudma.h" + +/* +* The configuration table for devices +*/ + +XCsuDma_Config XCsuDma_ConfigTable[] = +{ + { + XPAR_PSU_CSUDMA_DEVICE_ID, + XPAR_PSU_CSUDMA_BASEADDR + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_hw.h new file mode 100644 index 000000000..76e401c2b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_hw.h @@ -0,0 +1,308 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcsudma_hw.h +* +* This header file contains identifiers and register-level driver functions (or +* macros) that can be used to access the Xilinx CSU_DMA core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vnsld  22/10/14 First release
+*
+* +******************************************************************************/ + +#ifndef XCSUDMA_HW_H_ +#define XCSUDMA_HW_H_ /**< Prevent circular inclusions + * by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Registers offsets + * @{ + */ +#define XCSUDMA_ADDR_OFFSET 0x000 /**< Address Register Offset */ +#define XCSUDMA_SIZE_OFFSET 0x004 /**< Size Register Offset */ +#define XCSUDMA_STS_OFFSET 0x008 /**< Status Register Offset */ +#define XCSUDMA_CTRL_OFFSET 0x00C /**< Control Register Offset */ +#define XCSUDMA_CRC_OFFSET 0x010 /**< CheckSum Register Offset */ +#define XCSUDMA_I_STS_OFFSET 0x014 /**< Interrupt Status Register + * Offset */ +#define XCSUDMA_I_EN_OFFSET 0x018 /**< Interrupt Enable Register + * Offset */ +#define XCSUDMA_I_DIS_OFFSET 0x01C /**< Interrupt Disable Register + * Offset */ +#define XCSUDMA_I_MASK_OFFSET 0x020 /**< Interrupt Mask Register Offset */ +#define XCSUDMA_CTRL2_OFFSET 0x024 /**< Interrupt Control Register 2 + * Offset */ +#define XCSUDMA_ADDR_MSB_OFFSET 0x028 /**< Address's MSB Register Offset */ +#define XCSUDMA_SAFETY_CHK_OFFSET 0xFF8 /**< Safety Check Field Offset */ +#define XCSUDMA_FUTURE_ECO_OFFSET 0xFFC /**< Future potential ECO Offset */ +/*@}*/ + +/** @name CSU Base address and CSU_DMA reset offset + * @{ + */ +#define XCSU_BASEADDRESS 0xFFCA0000 + /**< CSU Base Address */ +#define XCSU_DMA_RESET_OFFSET 0x0000000CU /**< CSU_DMA Reset offset */ +/*@}*/ + +/** @name CSU_DMA Reset register bit masks + * @{ + */ +#define XCSUDMA_RESET_SET_MASK 0x00000001U /**< Reset set mask */ +#define XCSUDMA_RESET_UNSET_MASK 0x00000000U /**< Reset unset mask*/ +/*@}*/ + +/** @name Offset difference for Source and destination + * @{ + */ +#define XCSUDMA_OFFSET_DIFF 0x00000800U /**< Offset difference for + * source and + * destination channels */ +/*@}*/ + +/** @name Address register bit masks + * @{ + */ +#define XCSUDMA_ADDR_MASK 0xFFFFFFFCU /**< Address mask */ +#define XCSUDMA_ADDR_LSB_MASK 0x00000003U /**< Address alignment check + * mask */ +/*@}*/ + +/** @name Size register bit masks and shifts + * @{ + */ +#define XCSUDMA_SIZE_MASK 0x1FFFFFFCU /**< Mask for size */ +#define XCSUDMA_LAST_WORD_MASK 0x00000001U /**< Last word check bit mask*/ +#define XCSUDMA_SIZE_SHIFT 2U /**< Shift for size */ +/*@}*/ + +/** @name Status register bit masks and shifts + * @{ + */ +#define XCSUDMA_STS_DONE_CNT_MASK 0x0000E000U /**< Count done mask */ +#define XCSUDMA_STS_FIFO_LEVEL_MASK 0x00001FE0U /**< FIFO level mask */ +#define XCUSDMA_STS_OUTSTDG_MASK 0x0000001EU /**< No.of outstanding + * read/write + * commands mask */ +#define XCSUDMA_STS_BUSY_MASK 0x00000001U /**< Busy mask */ +#define XCSUDMA_STS_DONE_CNT_SHIFT 13U /**< Shift for Count + * done */ +#define XCSUDMA_STS_FIFO_LEVEL_SHIFT 5U /**< Shift for FIFO + * level */ +#define XCUSDMA_STS_OUTSTDG_SHIFT 1U /**< Shift for No.of + * outstanding + * read/write + * commands */ +/*@}*/ + +/** @name Control register bit masks and shifts + * @{ + */ +#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U /**< SSS FIFO threshold + * value mask */ +#define XCSUDMA_CTRL_APB_ERR_MASK 0x01000000U /**< APB register + * access error + * mask */ +#define XCSUDMA_CTRL_ENDIAN_MASK 0x00800000U /**< Endianess mask */ +#define XCSUDMA_CTRL_BURST_MASK 0x00400000U /**< AXI burst type + * mask */ +#define XCSUDMA_CTRL_TIMEOUT_MASK 0x003FFC00U /**< Time out value + * mask */ +#define XCSUDMA_CTRL_FIFO_THRESH_MASK 0x000003FCU /**< FIFO threshold + * mask */ +#define XCSUDMA_CTRL_PAUSE_MEM_MASK 0x00000001U /**< Memory pause + * mask */ +#define XCSUDMA_CTRL_PAUSE_STRM_MASK 0x00000002U /**< Stream pause + * mask */ +#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U /**< SSS FIFO threshold + * shift */ +#define XCSUDMA_CTRL_APB_ERR_SHIFT 24U /**< APB error shift */ +#define XCSUDMA_CTRL_ENDIAN_SHIFT 23U /**< Endianess shift */ +#define XCSUDMA_CTRL_BURST_SHIFT 22U /**< AXI burst type + * shift */ +#define XCSUDMA_CTRL_TIMEOUT_SHIFT 10U /**< Time out value + * shift */ +#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT 2U /**< FIFO thresh + * shift */ +/*@}*/ + +/** @name CheckSum register bit masks + * @{ + */ +#define XCSUDMA_CRC_RESET_MASK 0x00000000U /**< Mask to reset + * value of + * check sum */ +/*@}*/ + +/** @name Interrupt Enable/Disable/Mask/Status registers bit masks + * @{ + */ +#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK 0x00000001U /**< FIFO overflow + * mask, it is valid + * only to Destination + * Channel */ +#define XCSUDMA_IXR_INVALID_APB_MASK 0x00000040U /**< Invalid APB access + * mask */ +#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK 0x00000020U /**< FIFO threshold hit + * indicator mask */ +#define XCSUDMA_IXR_TIMEOUT_MEM_MASK 0x00000010U /**< Time out counter + * expired to access + * memory mask */ +#define XCSUDMA_IXR_TIMEOUT_STRM_MASK 0x00000008U /**< Time out counter + * expired to access + * stream mask */ +#define XCSUDMA_IXR_AXI_WRERR_MASK 0x00000004U /**< AXI Read/Write + * error mask */ +#define XCSUDMA_IXR_DONE_MASK 0x00000002U /**< Done mask */ +#define XCSUDMA_IXR_MEM_DONE_MASK 0x00000001U /**< Memory done + * mask, it is valid + * only for source + * channel*/ +#define XCSUDMA_IXR_SRC_MASK 0x0000007FU + /**< ((XCSUDMA_IXR_INVALID_APB_MASK)| + (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | + (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | + (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | + (XCSUDMA_IXR_AXI_WRERR_MASK) | + (XCSUDMA_IXR_DONE_MASK) | + (XCSUDMA_IXR_MEM_DONE_MASK)) */ + /**< All interrupt mask + * for source */ +#define XCSUDMA_IXR_DST_MASK 0x000000FEU + /**< ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) | + (XCSUDMA_IXR_INVALID_APB_MASK) | + (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | + (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | + (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | + (XCSUDMA_IXR_AXI_WRERR_MASK) | + (XCSUDMA_IXR_DONE_MASK)) */ + /**< All interrupt mask + * for destination */ +/*@}*/ + +/** @name Control register 2 bit masks and shifts + * @{ + */ +#define XCSUDMA_CTRL2_RESERVED_MASK 0x083F0000U /**< Reserved bits + * mask */ +#define XCSUDMA_CTRL2_ACACHE_MASK 0X07000000U /**< AXI CACHE mask */ +#define XCSUDMA_CTRL2_ROUTE_MASK 0x00800000U /**< Route mask */ +#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK 0x00400000U /**< Time out counters + * enable mask */ +#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK 0x0000FFF0U /**< Time out pre + * mask */ +#define XCSUDMA_CTRL2_MAXCMDS_MASK 0x0000000FU /**< Maximum commands + * mask */ +#define XCSUDMA_CTRL2_RESET_MASK 0x0000FFF8U /**< Reset mask */ +#define XCSUDMA_CTRL2_ACACHE_SHIFT 24U /**< Shift for + * AXI R/W CACHE */ +#define XCSUDMA_CTRL2_ROUTE_SHIFT 23U /**< Shift for route */ +#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT 22U /**< Shift for Timeout + * enable feild */ +#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT 4U /**< Shift for Timeout + * pre feild */ +/*@}*/ + +/** @name MSB Address register bit masks and shifts + * @{ + */ +#define XCSUDMA_MSB_ADDR_MASK 0x0001FFFFU /**< MSB bits of address + * mask */ +#define XCSUDMA_MSB_ADDR_SHIFT 32U /**< Shift for MSB bits of + * address */ +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XCsuDma_In32 Xil_In32 /**< Input operation */ +#define XCsuDma_Out32 Xil_Out32 /**< Output operation */ + +/*****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the Xilinx base address of the CSU_DMA core. +* @param RegOffset is the register offset of the register. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset) +* +******************************************************************************/ +#define XCsuDma_ReadReg(BaseAddress, RegOffset) \ + XCsuDma_In32((BaseAddress) + (u32)(RegOffset)) + +/*****************************************************************************/ +/** +* +* This macro writes the value into the given register. +* +* @param BaseAddress is the Xilinx base address of the CSU_DMA core. +* @param RegOffset is the register offset of the register. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +******************************************************************************/ +#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data) \ + XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + + +#ifdef __cplusplus +} + +#endif + + +#endif /* End of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_intr.c new file mode 100644 index 000000000..0f60da81f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_intr.c @@ -0,0 +1,271 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_intr.c +* +* This file contains interrupt related functions of Xilinx CSU_DMA core. +* Please see xcsudma.h for more details of the driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld  22/10/14  First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" + +/************************** Function Prototypes ******************************/ + + +/************************** Function Definitions *****************************/ + + +/*****************************************************************************/ +/** +* +* This function returns interrupt status read from Interrupt Status Register. +* Use the XCSUDMA_IXR_*_MASK constants defined in xcsudma_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return The pending interrupts of the CSU_DMA. Use th following masks +* to interpret the returned value. +* XCSUDMA_IXR_SRC_MASK - For Source channel +* XCSUDMA_IXR_DST_MASK - For Destination channel +* +* @note None. +* +******************************************************************************/ +u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + u32 Data; + + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_I_STS_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))); + + return Data; + +} + +/*****************************************************************************/ +/** +* +* This function clears interrupt(s). Every bit set in Interrupt Status +* Register indicates that a specific type of interrupt is occurring, and this +* function clears one or more interrupts by writing a bit mask to Interrupt +* Clear Register. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* Bit positions of 0 will not change the previous interrupt +* status. This mask is formed by OR'ing XCSUDMA_IXR_* bits +* defined in xcsudma_hw.h. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask) +{ + + + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + if (Channel == (XCSUDMA_SRC_CHANNEL)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_I_STS_OFFSET), + (Mask & (u32)(XCSUDMA_IXR_SRC_MASK))); + } + else { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_STS_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Mask & (u32)(XCSUDMA_IXR_DST_MASK))); + } +} + +/*****************************************************************************/ +/** +* +* This function enables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants +* defined in xcsudma_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Mask contains interrupts to be enabled. +* - Bit positions of 1 will be enabled. +* This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined +* in xcsudma_hw.h. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask) +{ + u32 Data; + + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + if (Channel == (XCSUDMA_SRC_CHANNEL)) { + Data = Mask & (u32)(XCSUDMA_IXR_SRC_MASK); + } + else { + Data = Mask & (u32)(XCSUDMA_IXR_DST_MASK); + } + /* + * Write the mask to the IER Register + */ + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_EN_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); + +} + +/*****************************************************************************/ +/** +* +* This function disables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants +* defined in xcsudma_hw.h to create the bit-mask to disable interrupts. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Mask contains interrupts to be disabled. +* - Bit positions of 1 will be disabled. +* This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined +* in xcsudma_hw.h. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask) +{ + u32 Data; + + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + if (Channel == XCSUDMA_SRC_CHANNEL) { + Data = (Mask) & (u32)(XCSUDMA_IXR_SRC_MASK); + } + else { + Data = (Mask) & (u32)(XCSUDMA_IXR_DST_MASK); + } + + /* + * Write the mask to the IDR Register + */ + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_DIS_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); + +} + +/*****************************************************************************/ +/** +* +* This function returns the interrupt mask to know which interrupts are +* enabled and which of them were disaled. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return The current interrupt mask. The mask indicates which interrupts +* are enabled/disabled. +* 0 bit represents .....corresponding interrupt is enabled. +* 1 bit represents .....Corresponding interrupt is disabled. +* To interpret returned mask use +* XCSUDMA_IXR_SRC_MASK........For source channel +* XCSUDMA_IXR_DST_MASK........For destination channel +* +* @note None. +* +******************************************************************************/ +u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + /* + * Read the Interrupt Mask register + */ + return (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_MASK_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))))); +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c new file mode 100644 index 000000000..dd0f5498f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c @@ -0,0 +1,122 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_selftest.c +* +* This file contains a diagnostic self-test function for the CSU_DMA driver. +* Refer to the header file xcsudma.h for more detailed information. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" + +/************************** Constant Definitions ****************************/ + + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Variable Definitions ****************************/ + + +/************************** Function Prototypes *****************************/ + + +/************************** Function Definitions *****************************/ + + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the driver and hardware device. Performs +* reset of both source and destination channels and checks if reset is working +* properly or not. +* +* @param InstancePtr is a pointer to the XCsuDma instance. +* +* @return +* - XST_SUCCESS if the self-test passed. +* - XST_FAILURE otherwise. +* +* @note None. +* +******************************************************************************/ +s32 XCsuDma_SelfTest(XCsuDma *InstancePtr) +{ + u32 Data; + s32 Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET)); + + /* Changing Endianess of Source channel */ + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET), + ((Data) | (u32)(XCSUDMA_CTRL_ENDIAN_MASK))); + + if ((XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET)) & + (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) == + (XCSUDMA_CTRL_ENDIAN_MASK)) { + Status = (s32)(XST_SUCCESS); + } + else { + Status = (s32)(XST_FAILURE); + } + + /* Changes made are being reverted back */ + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET), Data); + + return Status; + +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c new file mode 100644 index 000000000..f0301dac9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_sinit.c +* +* This file contains static initialization methods for Xilinx CSU_DMA core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/**************************** Type Definitions *******************************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* XCsuDma_LookupConfig returns a reference to an XCsuDma_Config structure +* based on the unique device id, DeviceId. The return value will refer +* to an entry in the device configuration table defined in the xcsudma_g.c +* file. +* +* @param DeviceId is the unique device ID of the device for the lookup +* operation. +* +* @return CfgPtr is a reference to a config record in the configuration +* table (in xcsudma_g.c) corresponding to DeviceId, or +* NULL if no match is found. +* +* @note None. +******************************************************************************/ +XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId) +{ + extern XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES]; + XCsuDma_Config *CfgPtr = NULL; + u32 Index; + + /* Checks all the instances */ + for (Index = (u32)0x0; Index < (u32)(XPAR_XCSUDMA_NUM_INSTANCES); + Index++) { + if (XCsuDma_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XCsuDma_ConfigTable[Index]; + break; + } + } + + return (XCsuDma_Config *)CfgPtr; +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/Makefile new file mode 100644 index 000000000..7002e6223 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xemacps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling emacps" + +xemacps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xemacps_includes + +xemacps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps.c new file mode 100644 index 000000000..40de3a064 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps.c @@ -0,0 +1,476 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps.c +* +* The XEmacPs driver. Functions in this file are the minimum required functions +* for this driver. See xemacps.h for a detailed description of the driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1  srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+*		      64-bit changes.
+* 3.00 kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   02/20/15 Added support for jumbo frames. Increase AHB burst.
+*                    Disable extended mode. Perform all 64 bit changes under
+*                    check for arch64.
+*
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xemacps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +void XEmacPs_StubHandler(void); /* Default handler routine */ + +/************************** Variable Definitions *****************************/ + + +/*****************************************************************************/ +/** +* Initialize a specific XEmacPs instance/driver. The initialization entails: +* - Initialize fields of the XEmacPs instance structure +* - Reset hardware and apply default options +* - Configure the DMA channels +* +* The PHY is setup independently from the device. Use the MII or whatever other +* interface may be present for setup. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param CfgPtr is the device configuration structure containing required +* hardware build data. +* @param EffectiveAddress is the base address of the device. If address +* translation is not utilized, this parameter can be passed in using +* CfgPtr->Config.BaseAddress to specify the physical base address. +* +* @return +* - XST_SUCCESS if initialization was successful +* +******************************************************************************/ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr, + UINTPTR EffectiveAddress) +{ + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(CfgPtr != NULL); + + /* Set device base address and ID */ + InstancePtr->Config.DeviceId = CfgPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddress; + + /* Set callbacks to an initial stub routine */ + InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler)); + InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler); + InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler); + + /* Reset the hardware and set default options */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + XEmacPs_Reset(InstancePtr); + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** +* Start the Ethernet controller as follows: +* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set +* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set +* - Start the SG DMA send and receive channels and enable the device +* interrupt +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return N/A +* +* @note +* Hardware is configured with scatter-gather DMA, the driver expects to start +* the scatter-gather channels and expects that the user has previously set up +* the buffer descriptor lists. +* +* This function makes use of internal resources that are shared between the +* Start, Stop, and Set/ClearOptions functions. So if one task might be setting +* device options while another is trying to start the device, the user is +* required to provide protection of this shared data (typically using a +* semaphore). +* +* This function must not be preempted by an interrupt that may service the +* device. +* +******************************************************************************/ +void XEmacPs_Start(XEmacPs *InstancePtr) +{ + u32 Reg; + + /* Assert bad arguments and conditions */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Start DMA */ + /* When starting the DMA channels, both transmit and receive sides + * need an initialized BD list. + */ + if (InstancePtr->Version == 2) { + Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0); + Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, + InstancePtr->RxBdRing.BaseBdAddr); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, + InstancePtr->TxBdRing.BaseBdAddr); + } + + /* clear any existed int status */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Enable transmitter if not already enabled */ + if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK); + } + } + + /* Enable receiver if not already enabled */ + if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK); + } + } + + /* Enable TX and RX interrupts */ + XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK | + XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK | + (u32)XEMACPS_IXR_TXCOMPL_MASK)); + + /* Enable TX Q1 Interrupts */ + if (InstancePtr->Version > 2) + XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK); + + /* Mark as started */ + InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED; + + return; +} + + +/*****************************************************************************/ +/** +* Gracefully stop the Ethernet MAC as follows: +* - Disable all interrupts from this device +* - Stop DMA channels +* - Disable the tansmitter and receiver +* +* Device options currently in effect are not changed. +* +* This function will disable all interrupts. Default interrupts settings that +* had been enabled will be restored when XEmacPs_Start() is called. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @note +* This function makes use of internal resources that are shared between the +* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be +* setting device options while another is trying to start the device, the user +* is required to provide protection of this shared data (typically using a +* semaphore). +* +* Stopping the DMA channels causes this function to block until the DMA +* operation is complete. +* +******************************************************************************/ +void XEmacPs_Stop(XEmacPs *InstancePtr) +{ + u32 Reg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Disable all interrupts */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Disable the receiver & transmitter */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK); + Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Mark as stopped */ + InstancePtr->IsStarted = 0U; +} + + +/*****************************************************************************/ +/** +* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the +* transmitter, and the receiver. +* +* Steps to reset +* - Stops transmit and receive channels +* - Stops DMA +* - Configure transmit and receive buffer size to default +* - Clear transmit and receive status register and counters +* - Clear all interrupt sources +* - Clear phy (if there is any previously detected) address +* - Clear MAC addresses (1-4) as well as Type IDs and hash value +* +* All options are placed in their default state. Any frames in the +* descriptor lists will remain in the lists. The side effect of doing +* this is that after a reset and following a restart of the device, frames +* were in the list before the reset may be transmitted or received. +* +* The upper layer software is responsible for re-configuring (if necessary) +* and restarting the MAC after the reset. Note also that driver statistics +* are not cleared on reset. It is up to the upper layer software to clear the +* statistics if needed. +* +* When a reset is required, the driver notifies the upper layer software of +* this need through the ErrorHandler callback and specific status codes. +* The upper layer software is responsible for calling this Reset function +* and then re-configuring the device. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +******************************************************************************/ +void XEmacPs_Reset(XEmacPs *InstancePtr) +{ + u32 Reg; + u8 i; + s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Stop the device and reset hardware */ + XEmacPs_Stop(InstancePtr); + InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS; + + InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC); + + InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF; + + InstancePtr->MaxMtuSize = XEMACPS_MTU; + InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE + + XEMACPS_TRL_SIZE; + InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize + + XEMACPS_HDR_VLAN_SIZE; + InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK; + + /* Setup hardware with default values */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + (XEMACPS_NWCTRL_STATCLR_MASK | + XEMACPS_NWCTRL_MDEN_MASK) & + (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK)); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCFG_OFFSET, + ((u32)XEMACPS_NWCFG_100_MASK | + (u32)XEMACPS_NWCFG_FDEN_MASK | + (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK)); + if (InstancePtr->Version > 2) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET, + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) | + XEMACPS_NWCFG_DWIDTH_64_MASK)); + } + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_DMACR_OFFSET, + (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) + + (((((u32)XEMACPS_RX_BUF_SIZE % + (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) << + (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) & + (u32)(XEMACPS_DMACR_RXBUF_MASK)) | + (u32)XEMACPS_DMACR_RXSIZE_MASK | + (u32)XEMACPS_DMACR_TXSIZE_MASK); + + + /* Single bursts */ + /* FIXME: Why Single bursts? */ + if (InstancePtr->Version > 2) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET, + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) | +#ifdef __aarch64__ + (u32)XEMACPS_DMACR_ADDR_WIDTH_64 | +#endif + (u32)XEMACPS_DMACR_INCR16_AHB_BURST)); + } + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXSR_OFFSET, 0x0U); + + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND); + if (InstancePtr->Version > 2) + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND); + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXSR_OFFSET, 0x0U); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_ISR_OFFSET); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + Reg); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_PHYMNTNC_OFFSET, 0x0U); + + XEmacPs_ClearHash(InstancePtr); + + for (i = 1U; i < 5U; i++) { + (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i); + (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i); + } + + /* clear all counters */ + for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U); + i++) { + (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4))); + } + + /* Disable the receiver */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Sync default options with hardware but leave receiver and + * transmitter disabled. They get enabled with XEmacPs_Start() if + * XEMACPS_TRANSMITTER_ENABLE_OPTION and + * XEMACPS_RECEIVER_ENABLE_OPTION are set. + */ + (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options & + ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | + (u32)XEMACPS_RECEIVER_ENABLE_OPTION)); + + (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options); +} + + +/******************************************************************************/ +/** + * This is a stub for the asynchronous callbacks. The stub is here in case the + * upper layer forgot to set the handler(s). On initialization, all handlers are + * set to this callback. It is considered an error for this handler to be + * invoked. + * + ******************************************************************************/ +void XEmacPs_StubHandler(void) +{ + Xil_AssertVoidAlways(); +} + +/*****************************************************************************/ +/** +* This function sets the start address of the transmit/receive buffer queue. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @QPtr Address of the Queue to be written +* @QueueNum Buffer Queue Index +* @Direction Transmit/Recive +* +* @note +* The buffer queue addresses has to be set before starting the transfer, so +* this function has to be called in prior to XEmacPs_Start() +* +******************************************************************************/ +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction) +{ + /* Assert bad arguments and conditions */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* If already started, then there is nothing to do */ + if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) { + return; + } + + if (QueueNum == 0x00U) { + if (Direction == XEMACPS_SEND) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } else { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } + } + else { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQ1BASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } +#ifdef __aarch64__ + /* Set the MSB of Queue start address */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_MSBBUF_QBASE_OFFSET, + (u32)((QPtr & (u32)ULONG64_HI_MASK) >> 32U)); +#endif +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps.h new file mode 100644 index 000000000..adb2f4b21 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps.h @@ -0,0 +1,783 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** + * + * @file xemacps.h + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not suppoted from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ *
+ * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001U +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002U +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004U +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020U +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040U +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400U +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800U +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U + +#define XEMACPS_DEFAULT_OPTIONS \ + ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ + (u32)XEMACPS_FCS_INSERT_OPTION | \ + (u32)XEMACPS_FCS_STRIP_OPTION | \ + (u32)XEMACPS_BROADCAST_OPTION | \ + (u32)XEMACPS_LENTYPE_ERR_OPTION | \ + (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ + (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1U +#define XEMACPS_HANDLER_DMARECV 2U +#define XEMACPS_HANDLER_ERROR 3U +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */ + +#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */ +#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ +#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 0x00000001 +#define XEMACPS_4BYTE_BURST 0x00000004 +#define XEMACPS_8BYTE_BURST 0x00000008 +#define XEMACPS_16BYTE_BURST 0x00000010 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * paramter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs_Instance { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + u32 Version; + u32 RxBufMask; + u32 MaxMtuSize; + u32 MaxFrameSize; + u32 MaxVlanFrameSize; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IER_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IDR_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/* + * Initialization functions in xemacps.c + */ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + UINTPTR EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction); + +/* + * Lookup configuration in xemacps_sinit.c + */ +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPointer, void *CallBackRef); +void XEmacPs_IntrHandler(void *XEmacPsPtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_bd.h new file mode 100644 index 000000000..41e0ab845 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_bd.h @@ -0,0 +1,799 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *
+ *
+ * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ +#ifdef __aarch64__ +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U +#else +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U +#endif + +/** + * The XEmacPs_Bd is the type for buffer descriptors (BDs). + */ +#define XEMACPS_BD_NUM_WORDS 2U +typedef UINTPTR XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * Zero out BD fields + * + * @param BdPtr is the BD pointer to operate on + * + * @return Nothing + * + * @note + * C-style signature: + * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClear(BdPtr) \ + memset((BdPtr), 0, sizeof(XEmacPs_Bd)) + +/****************************************************************************/ +/** +* +* Read the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to read +* @param Offset is the word offset to be read +* +* @return The 32-bit value of the field +* +* @note +* C-style signature: +* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset) +* +*****************************************************************************/ +#define XEmacPs_BdRead(BaseAddress, Offset) \ + (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset))) + +/****************************************************************************/ +/** +* +* Write the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to write +* @param Offset is the word offset to be written +* @param Data is the 32-bit value to write to the field +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data) +* +*****************************************************************************/ +#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ + (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data)) + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : + * + * C-style signature: + * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + (u32)((Addr) & ULONG64_LO_MASK)); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr)) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : Due to some bits are mixed within recevie BD's address field, + * read-modify-write is performed. + * + * C-style signature: + * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr))) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Status field (word 1). + * + * @param BdPtr is the BD pointer to operate on + * @param Data is the value to write to BD's status field. + * + * @note + * C-style signature: + * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data) + * + *****************************************************************************/ +#define XEmacPs_BdSetStatus(BdPtr, Data) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data)) + + +/*****************************************************************************/ +/** + * Retrieve the BD's Packet DMA transfer status word (word 1). + * + * @param BdPtr is the BD pointer to operate on + * + * @return Status word + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) + * + * Due to the BD bit layout differences in transmit and receive. User's + * caution is required. + *****************************************************************************/ +#define XEmacPs_BdGetStatus(BdPtr) \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) + + +/*****************************************************************************/ +/** + * Get the address (bits 0..31) of the BD's buffer address (word 0) + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U) +#else +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) +#endif + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + +/*****************************************************************************/ +/** + * Retrieve the BD length field. + * + * For Tx channels, the returned value is the same as that written with + * XEmacPs_BdSetLength(). + * + * For Rx channels, the returned value is the size of the received packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) + * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. + * + *****************************************************************************/ +#define XEmacPs_BdGetLength(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_LEN_MASK) + +/*****************************************************************************/ +/** + * Retrieve the RX frame size. + * + * The returned value is the size of the received packet. + * This API supports jumbo frame sizes if enabled. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr) + * RxBufMask is dependent on whether jumbo is enabled or not. + * + *****************************************************************************/ +#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + (InstancePtr)->RxBufMask) + +/*****************************************************************************/ +/** + * Test whether the given BD has been marked as the last BD of a packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsLast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the given transmit BD marks the end of the current + * packet to be processed. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the current packet does not end with the given + * BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Set this bit to mark the last descriptor in the receive buffer descriptor + * list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetRxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + XEMACPS_RXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the receive BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit to mark the last descriptor in the transmit buffer + * descriptor list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetTxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the transmit BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/* + * Must clear this bit to enable the MAC to write data to the receive + * buffer. Hardware sets this bit once it has successfully written a frame to + * memory. Once set, software has to clear the bit before the buffer can be + * used again. This macro clear the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearRxNew(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_NEW_MASK)) + + +/*****************************************************************************/ +/** + * Determine the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxNew(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Software sets this bit to disable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro sets this bit of transmit BD to avoid + * confusion. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Software clears this bit to enable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro clears this bit of transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Determine the used bit of the transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUsed(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to too many retries. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxRetry(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to data can not be + * feteched in time or buffers are exhausted. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUrun(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to buffer is exhausted + * mid-frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxExh(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit, no CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Clear this bit, CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Determine the broadcast bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxBcast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the multicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxMultiHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the unicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxUniHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame is a VLAN Tagged frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxVlan(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame has Type ID of 8100h and null VLAN + * identifier(Priority tag). + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxPri(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame's Concatenation Format Indicator (CFI) of + * the frames VLANTCI field was set. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxCFI(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the End Of Frame (EOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxEOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the Start Of Frame (SOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxSOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE) + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_bdring.c new file mode 100644 index 000000000..32a1e535f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_bdring.c @@ -0,0 +1,1072 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_bdring.c +* +* This file implements buffer descriptor ring related functions. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+*		      Earlier it used to search in "BdLimit" number of BDs to
+*		      know which BDs are processed. Now one more check is
+*		      added. It looks for BDs till the current BD pointer
+*		      reaches HwTail. By doing this processing time is saved.
+* 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+*		      xemacps_bdring.c is modified. Now start of packet is
+*		      searched for returning the number of BDs processed.
+* 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+*		      removed. It is expected that all BDs are allocated in
+*		      from uncached area. Fix for CR #663885.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_cache.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************************************************************** + * Compute the virtual address of a descriptor from its physical address + * + * @param BdPtr is the physical address of the BD + * + * @returns Virtual address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_PHYS_TO_VIRT(BdPtr) \ + ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Compute the physical address of a descriptor from its virtual address + * + * @param BdPtr is the physical address of the BD + * + * @returns Physical address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_VIRT_TO_PHYS(BdPtr) \ + ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around + * to the beginning of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is greater than + * the high address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \ + { \ + UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ + \ + Addr += ((RingPtr)->Separation * (NumBd)); \ + if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \ + { \ + Addr -= (RingPtr)->Length; \ + } \ + \ + (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \ + } + +/**************************************************************************** + * Move the BdPtr argument backwards an arbitrary number of BDs wrapping + * around to the end of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is less than + * the base address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \ + { \ + UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ + \ + Addr -= ((RingPtr)->Separation * (NumBd)); \ + if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \ + { \ + Addr += (RingPtr)->Length; \ + } \ + \ + (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \ + } + + +/************************** Function Prototypes ******************************/ + +static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr); +static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr); + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** + * Using a memory segment allocated by the caller, create and setup the BD list + * for the given DMA channel. + * + * @param RingPtr is the instance to be worked on. + * @param PhysAddr is the physical base address of user memory region. + * @param VirtAddr is the virtual base address of the user memory region. If + * address translation is not being utilized, then VirtAddr should be + * equivalent to PhysAddr. + * @param Alignment governs the byte alignment of individual BDs. This function + * will enforce a minimum alignment of 4 bytes with no maximum as long + * as it is specified as a power of 2. + * @param BdCount is the number of BDs to setup in the user memory region. It + * is assumed the region is large enough to contain the BDs. + * + * @return + * + * - XST_SUCCESS if initialization was successful + * - XST_NO_FEATURE if the provided instance is a non DMA type + * channel. + * - XST_INVALID_PARAM under any of the following conditions: + * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment + * parameter. + * 2) Alignment parameter does not meet minimum requirements or is not a + * power of 2 value. + * 3) BdCount is 0. + * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans + * over address 0x00000000 in virtual address space. + * + * @note + * Make sure to pass in the right alignment value. + *****************************************************************************/ +LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, u32 BdCount) +{ + u32 i; + UINTPTR BdVirtAddr; + UINTPTR BdPhyAddr; + UINTPTR VirtAddrLoc = VirtAddr; + + /* In case there is a failure prior to creating list, make sure the + * following attributes are 0 to prevent calls to other functions + * from doing anything. + */ + RingPtr->AllCnt = 0U; + RingPtr->FreeCnt = 0U; + RingPtr->HwCnt = 0U; + RingPtr->PreCnt = 0U; + RingPtr->PostCnt = 0U; + + /* Make sure Alignment parameter meets minimum requirements */ + if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Make sure Alignment is a power of 2 */ + if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Make sure PhysAddr and VirtAddr are on same Alignment */ + if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Is BdCount reasonable? */ + if (BdCount == 0x00000000U) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Figure out how many bytes will be between the start of adjacent BDs */ + RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd)); + + /* Must make sure the ring doesn't span address 0x00000000. If it does, + * then the next/prev BD traversal macros will fail. + */ + if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) { + return (LONG)(XST_DMA_SG_LIST_ERROR); + } + + /* Initial ring setup: + * - Clear the entire space + * - Setup each BD's BDA field with the physical address of the next BD + */ + (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount)); + + BdVirtAddr = VirtAddrLoc; + BdPhyAddr = PhysAddr + RingPtr->Separation; + for (i = 1U; i < BdCount; i++) { + BdVirtAddr += RingPtr->Separation; + BdPhyAddr += RingPtr->Separation; + } + + /* Setup and initialize pointers and counters */ + RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED); + RingPtr->BaseBdAddr = VirtAddrLoc; + RingPtr->PhysBaseAddr = PhysAddr; + RingPtr->HighBdAddr = BdVirtAddr; + RingPtr->Length = + ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation); + RingPtr->AllCnt = (u32)BdCount; + RingPtr->FreeCnt = (u32)BdCount; + RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc; + RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr; + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Clone the given BD into every BD in the list. + * every field of the source BD is replicated in every BD of the list. + * + * This function can be called only when all BDs are in the free group such as + * they are immediately after initialization with XEmacPs_BdRingCreate(). + * This prevents modification of BDs while they are in use by hardware or the + * user. + * + * @param RingPtr is the pointer of BD ring instance to be worked on. + * @param SrcBdPtr is the source BD template to be cloned into the list. This + * BD will be modified. + * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates + * which direction. + * + * @return + * - XST_SUCCESS if the list was modified. + * - XST_DMA_SG_NO_LIST if a list has not been created. + * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under + * hardware or user control. + * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped. + * + *****************************************************************************/ +LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction) +{ + u32 i; + UINTPTR CurBd; + + /* Can't do this function if there isn't a ring */ + if (RingPtr->AllCnt == 0x00000000U) { + return (LONG)(XST_DMA_SG_NO_LIST); + } + + /* Can't do this function with the channel running */ + if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) { + return (LONG)(XST_DEVICE_IS_STARTED); + } + + /* Can't do this function with some of the BDs in use */ + if (RingPtr->FreeCnt != RingPtr->AllCnt) { + return (LONG)(XST_DMA_SG_LIST_ERROR); + } + + if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Starting from the top of the ring, save BD.Next, overwrite the entire + * BD with the template, then restore BD.Next + */ + CurBd = RingPtr->BaseBdAddr; + for (i = 0U; i < RingPtr->AllCnt; i++) { + memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd)); + CurBd += RingPtr->Separation; + } + + CurBd -= RingPtr->Separation; + + if (Direction == XEMACPS_RECV) { + XEmacPs_BdSetRxWrap(CurBd); + } + else { + XEmacPs_BdSetTxWrap(CurBd); + } + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Reserve locations in the BD list. The set of returned BDs may be modified + * in preparation for future DMA transaction(s). Once the BDs are ready to be + * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same + * order which they were allocated here. Example: + * + * 
+ *        NumBd = 2,
+ *        Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ *        if (Status != XST_SUCCESS)
+ *        {
+ *            *Not enough BDs available for the request*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ * 
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ * 

+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ *     parameter.
+ *   - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ *       parameter. Doing so will lead to data corruption and system
+ *       instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr)
+{
+	LONG Status;
+	/* Enough free BDs available for the request? */
+	if (RingPtr->FreeCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead forward */
+	*BdSetPtr = RingPtr->FreeHead;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt -= NumBd;
+	RingPtr->PreCnt += NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ * 
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *        ...
+ *    if (Error)
+ *    {
+ *        Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ *    }
+ * 

+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ * 
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *    BdsLeft = 10,
+ *    CurBdPtr = BdPtr,
+ *
+ *    while (BdsLeft)
+ *    {
+ *       if (Error)
+ *       {
+ *          Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
+ *       }
+ *
+ *       CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
+ *       BdsLeft--,
+ *    }
+ * 

+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the BDs were unallocated.
+ *   - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ *     the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	(void *)BdSetPtr;
+	Xil_AssertNonvoid(RingPtr != NULL);
+	Xil_AssertNonvoid(BdSetPtr != NULL);
+
+	/* Enough BDs in the free state for the request? */
+	if (RingPtr->PreCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead backward */
+		XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PreCnt -= NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ *   - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ *     did not have its "last" bit set.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 i;
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	CurBdPtr = BdSetPtr;
+			for (i = 0U; i < NumBd; i++) {
+				CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+	}
+	/* Adjust ring pointers & counters */
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+	RingPtr->PreCnt -= NumBd;
+	RingPtr->HwTail = CurBdPtr;
+	RingPtr->HwCnt += NumBd;
+
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
+ *        NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ *        if (NumBd == 0)
+ *        {
+ *           * hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * 

+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Sop = 0U;
+	u32 Status;
+	u32 BdLimitLoc = BdLimit;
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+		if (BdLimitLoc > RingPtr->HwCnt){
+			BdLimitLoc = RingPtr->HwCnt;
+	}
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has not completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+		while (BdCount < BdLimitLoc) {
+		/* Read the status */
+			if(CurBdPtr != NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+
+			if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+				Sop = 1U;
+			}
+			if (Sop == 0x00000001U) {
+			BdCount++;
+			BdPartialCount++;
+		}
+
+		/* hardware has processed this BD so check the "last" bit.
+		 * If it is clear, then there are more BDs for the current
+		 * packet. Keep a count of these partial packet BDs.
+		 */
+			if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+				Sop = 0U;
+				BdPartialCount = 0U;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+        BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+		} else {
+			*BdSetPtr = NULL;
+			Status = 0U;
+	}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
+ *        NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ *        if (NumBd == 0)
+ *        {
+ *           *hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * 

+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Status;
+
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+	while (BdCount < BdLimit) {
+
+		/* Read the status */
+			if(CurBdPtr!=NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+			if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+			break;
+		}
+
+		BdCount++;
+
+		/* hardware has processed this BD so check the "last" bit. If
+                 * it is clear, then there are more BDs for the current packet.
+                 * Keep a count of these partial packet BDs.
+		 */
+			if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+				BdPartialCount = 0U;
+			} else {
+			BdPartialCount++;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+	BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+	}
+	else {
+		*BdSetPtr = NULL;
+			Status = 0U;
+	}
+}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0x00000000U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	/* Update pointers and counters */
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PostCnt -= NumBd;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ *   - Is the BD ring linked correctly in physical address space.
+ *   - Do the internal pointers point to BDs in the ring.
+ *   - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ *        which direction.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_NO_LIST if the list has not been created.
+ *   - XST_IS_STARTED if the channel is not stopped.
+ *   - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ *     structures. If this value is returned, the channel should be reset to
+ *     avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+	UINTPTR AddrV, AddrP;
+	u32 i;
+
+	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Is the list created */
+	if (RingPtr->AllCnt == 0x00000000U) {
+		return (LONG)(XST_DMA_SG_NO_LIST);
+	}
+
+	/* Can't check if channel is running */
+	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+		return (LONG)(XST_IS_STARTED);
+	}
+
+	/* RunState doesn't make sense */
+	if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal pointers point to correct memory space */
+	AddrV = (UINTPTR) RingPtr->FreeHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PreHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwTail;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PostHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal counters add up */
+	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+	     RingPtr->PostCnt) != RingPtr->AllCnt) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify BDs are linked correctly */
+	AddrV = RingPtr->BaseBdAddr;
+	AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+	for (i = 1U; i < RingPtr->AllCnt; i++) {
+		/* Check BDA for this BD. It should point to next physical addr */
+		if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+
+		/* Move on to next BD */
+		AddrV += RingPtr->Separation;
+		AddrP += RingPtr->Separation;
+	}
+
+	/* Last BD should have wrap bit set */
+	if (XEMACPS_SEND == Direction) {
+		if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+	else {			/* XEMACPS_RECV */
+		if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+
+	/* No problems found */
+	return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueRx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueRx = *TempPtr;
+		DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+		*TempPtr = DataValueRx;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueTx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueTx = *TempPtr;
+		DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+		*TempPtr = DataValueTx;
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_bdring.h
new file mode 100644
index 000000000..b678c5401
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_bdring.h
@@ -0,0 +1,235 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
+#define XEMACPS_BDRING_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+	UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+	UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
+	UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
+	u32 Length;	 /**< Total size of ring in bytes */
+	u32 RunState;	 /**< Flag to indicate DMA is started */
+	u32 Separation;	 /**< Number of bytes between the starting address
+                                  of adjacent BDs */
+	XEmacPs_Bd *FreeHead;
+			     /**< First BD in the free group */
+	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+	XEmacPs_Bd *HwHead; /**< First BD in the work group */
+	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+	XEmacPs_Bd *PostHead;
+			     /**< First BD in the post-work group */
+	XEmacPs_Bd *BdaRestart;
+			     /**< BDA to load when channel is started */
+
+	u32 HwCnt;	     /**< Number of BDs in work group */
+	u32 PreCnt;     /**< Number of BDs in pre-work group */
+	u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
+	u32 PostCnt;    /**< Number of BDs in post-work group */
+	u32 AllCnt;     /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+*        must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes)                    \
+    (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+*        parameter must be a power of 2 to get an accurate calculation (32, 64,
+*        128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+*         given memory constraints.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd)                    \
+    (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr)   ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr)                           \
+    (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ?                     \
+    (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) :                              \
+    (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr)                           \
+    (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
+    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
+    (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_control.c
new file mode 100644
index 000000000..69a6e4d7d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_control.c
@@ -0,0 +1,1158 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *					   register. Added a new API for setting the BURST length
+ *					   in DMACR register.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ * 

+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device.  The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	}
+	else{
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the MAC bits [31:0] in BOT */
+		MacAddr = *(Aptr);
+		MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+		MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+		MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+	/* There are reserved bits in TOP so don't affect them */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+		MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+	/* Set MAC bits [47:32] in TOP */
+		MacAddr |= (u32)(*(Aptr+4));
+		MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Aptr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+	IndexLoc--;
+
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*Aptr = (u8) MacAddr;
+	*(Aptr+1) = (u8) (MacAddr >> 8U);
+	*(Aptr+2) = (u8) (MacAddr >> 16U);
+	*(Aptr+3) = (u8) (MacAddr >> 24U);
+
+	/* Read MAC bits [47:32] in TOP */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*(Aptr+4) = (u8) MacAddr;
+	*(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ * 
+ * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
+ * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
+ * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
+ * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
+ * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
+ * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
+ * 

+ *
+ * da[0] represents the least significant bit of the first byte received,
+ * that is, the multicast/unicast indicator, and da[47] represents the most
+ * significant bit of the last byte received.
+ *
+ * If the hash index points to a bit that is set in the hash register then
+ * the frame will be matched according to whether the frame is multicast
+ * or unicast.
+ *
+ * A multicast match will be signaled if the multicast hash enable bit is
+ * set, da[0] is logic 1 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * A unicast match will be signaled if the unicast hash enable bit is set,
+ * da[0] is logic 0 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * To receive all multicast frames, the hash register should be set with
+ * all ones and the multicast hash enable bit should be set in the network
+ * configuration register.
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(AddressPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+				(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
+			Status = (LONG)(XST_INVALID_PARAM);
+		} else {
+
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr |= (u32)(0x00000001U << Result);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Delete 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was deleted successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+					(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
+			Status =  (LONG)(XST_INVALID_PARAM);
+		} else {
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << Result));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+/*****************************************************************************/
+/**
+ * Clear the Hash registers for the mac address pointed by AddressPtr.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ *****************************************************************************/
+void XEmacPs_ClearHash(XEmacPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET, 0x0U);
+
+	/* write bits [63:32] in TOP */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET, 0x0U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the Hash address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current HASH MAC address will be copied.
+ *
+ *****************************************************************************/
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 *Aptr = (u32 *)(void *)AddressPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(AddressPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	*(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET);
+
+	/* Read Hash bits [63:32] in TOP */
+	*(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the Type ID match for this driver/device.  The register is a 32-bit
+ * value. The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Id_Check is type ID to be configured.
+ * @param Index is a index to which Type ID (1-4).
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
+{
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the ID bits in MATCHx register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   ((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Set options for the driver/device. The driver should be stopped with
+ * XEmacPs_Stop() before changing options.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to set. Multiple options can be set by OR'ing
+ *        XTE_*_OPTIONS constants together. Options not specified are not
+ *        affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic register contents */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/*
+	 * It is configured to max 1536.
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn on VLAN packet only, only VLAN tagged will be accepted */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
+	}
+
+	/* Turn on FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
+	}
+
+	/* Turn on length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
+	}
+
+	/* Turn on flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
+	}
+
+	/* Turn on promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
+	}
+
+	/* Allow broadcast address reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
+	}
+
+	/* Allow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
+	}
+
+	/* enable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
+	}
+
+	/* Enable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Enable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+		Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Enable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_TXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Enable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_RXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * the option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options |= Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Clear options for the driver/device
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to clear. Multiple options can be cleared by
+ *        OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
+ *        are not affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/* There is only RX configuration!?
+	 * It is configured in two different length, upto 1536 and 10240 bytes
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn off VLAN packet only */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
+	}
+
+	/* Turn off FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
+	}
+
+	/* Turn off length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
+	}
+
+	/* Turn off flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
+	}
+
+	/* Turn off promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
+	}
+
+	/* Disallow broadcast address filtering => broadcast reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
+	}
+
+	/* Disallow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
+	}
+
+	/* Disable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
+	}
+
+	/* Disable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Disable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+			Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Disable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Disable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options &= ~Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get current option settings
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
+ * as a set opion.
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	return (InstancePtr->Options);
+}
+
+
+/*****************************************************************************/
+/**
+ * Send a pause packet
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * - XST_SUCCESS if pause frame transmission was initiated
+ * - XST_DEVICE_IS_STOPPED if the device has not been started.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Make sure device is ready for this operation */
+	if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STOPPED);
+	} else {
+	/* Send flow control frame */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
+ * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ *
+ * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
+ *         megabits per second.
+ *
+ * @note
+ *
+ *****************************************************************************/
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	u16 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+
+	if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
+		Status = (u16)(1000);
+	} else {
+		if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
+			Status = (u16)(100);
+		} else {
+			Status = (u16)(10);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
+ * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
+ * link speed.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
+ *        or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
+ *
+ * @note
+ *
+ *****************************************************************************/
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
+{
+        u32 Reg;
+	u16 Status;
+        Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
+
+        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+	Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
+
+	switch (Speed) {
+		case (u16)10:
+				Status = 0U;
+                break;
+
+        case (u16)100:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_100_MASK;
+                break;
+
+        case (u16)1000:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_1000_MASK;
+                break;
+
+        default:
+			Status = 1U;
+                break;
+    }
+	if(Status == (u16)1){
+                return;
+        }
+
+        /* Set register and return */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the MDIO clock divisor.
+ *
+ * Calculating the divisor:
+ *
+ * 
+ *              f[HOSTCLK]
+ *   f[MDC] = -----------------
+ *            (1 + Divisor) * 2
+ * 

+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ * 
+ * 000 : divide pclk by   8 (pclk up to  20 MHz)
+ * 001 : divide pclk by  16 (pclk up to  40 MHz)
+ * 010 : divide pclk by  32 (pclk up to  80 MHz)
+ * 011 : divide pclk by  48 (pclk up to 120 MHz)
+ * 100 : divide pclk by  64 (pclk up to 160 MHz)
+ * 101 : divide pclk by  96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ * 

+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+	u32 Reg;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCFG_OFFSET);
+	/* clear these three bits, could be done with mask */
+	Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+	Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+*        which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpReadTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+			IpReadTemp = Ipisr;
+		} while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+	/* Read data */
+		*PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_PHYMNTNC_OFFSET);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY.  Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+*   status from the MAC on a write, the user should read the PHY to verify the
+*   write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpWriteTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+				IpWriteTemp = Ipisr;
+		} while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+	u32 Reg;
+	u32 RegUpdateVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+					(BLength == XEMACPS_4BYTE_BURST) ||
+					(BLength == XEMACPS_8BYTE_BURST) ||
+					(BLength == XEMACPS_16BYTE_BURST));
+
+	switch (BLength) {
+		case XEMACPS_SINGLE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+			break;
+
+		case XEMACPS_4BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+			break;
+
+		case XEMACPS_8BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+			break;
+
+		case XEMACPS_16BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+			break;
+
+		default:
+			RegUpdateVal = 0x00000000U;
+			break;
+	}
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_DMACR_OFFSET);
+
+	Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+	Reg |= RegUpdateVal;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+																	Reg);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_g.c
new file mode 100644
index 000000000..2dbf8b924
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_g.c
@@ -0,0 +1,67 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_ETHERNET_0_DEVICE_ID,
+		XPAR_PSU_ETHERNET_0_BASEADDR
+	},
+	{
+		XPAR_PSU_ETHERNET_1_DEVICE_ID,
+		XPAR_PSU_ETHERNET_1_BASEADDR
+	},
+	{
+		XPAR_PSU_ETHERNET_2_DEVICE_ID,
+		XPAR_PSU_ETHERNET_2_BASEADDR
+	},
+	{
+		XPAR_PSU_ETHERNET_3_DEVICE_ID,
+		XPAR_PSU_ETHERNET_3_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_hw.c
new file mode 100644
index 000000000..db01faad3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_hw.c
@@ -0,0 +1,120 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc  28/06/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status registers
+*	Disable Rx and Tx engines
+*	Update the Tx and Rx descriptor queue registers with reset values
+*	Update the other relevant control registers with reset value
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+	u32 RegVal;
+
+	/* Disable the interrupts  */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+	/* Stop transmission,disable loopback and Stop tx and Rx engines */
+	RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+	RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+				(u32)XEMACPS_NWCTRL_RXEN_MASK|
+				(u32)XEMACPS_NWCTRL_HALTTX_MASK|
+				(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+	/* Clear the statistic registers, flush the packets in DPRAM*/
+	RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+				XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+	/* Clear the interrupt status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+	/* Clear the tx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+									(u32)XEMACPS_TXSR_TXCOMPL_MASK|
+									(u32)XEMACPS_TXSR_TXGO_MASK));
+	/* Clear the rx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+								XEMACPS_RXSR_FRAMERX_MASK);
+	/* Clear the tx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+	/* Clear the rx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+	/* Update the network config register with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+	/* Update the hash address registers with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_hw.h
new file mode 100644
index 000000000..4b8f582ce
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_hw.h
@@ -0,0 +1,647 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+* 

+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
+#define XEMACPS_HW_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR     4U   /**< Maxmum number of mac address
+                                           supported */
+#define XEMACPS_MAX_TYPE_ID      4U   /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT     64U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT     4U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U   /**< Minimum buffer alignment when using
+                                           options that impose alignment
+                                           restrictions on the buffer data on
+                                           the local bus */
+
+/** @name Direction identifiers
+ *
+ *  These are used by several functions and callbacks that need
+ *  to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND        1U	      /**< send direction */
+#define XEMACPS_RECV        2U	      /**< receive direction */
+/*@}*/
+
+/**  @name MDC clock division
+ *  currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+                                       bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT   64U /**< Number of receive buffer bytes as a
+                                       unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD     128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD     128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET        0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET         0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET          0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET         0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET          0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET       0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET       0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET          0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET           0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET           0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET           0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET           0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET      0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET       0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET       0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET   0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET         0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET         0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET       0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET       0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET       0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET       0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET       0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET       0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET       0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET       0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET        0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET        0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET        0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET        0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET       0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET        0x00000100U /**< Octects transmitted Low
+                                                      reg */
+#define XEMACPS_OCTTXH_OFFSET        0x00000104U /**< Octects transmitted High
+                                                      reg */
+
+#define XEMACPS_TXCNT_OFFSET         0x00000108U /**< Error-free Frmaes
+                                                      transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET       0x0000010CU /**< Error-free Broadcast
+                                                      Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET       0x00000110U /**< Error-free Multicast
+                                                      Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET    0x00000114U /**< Pause Frames Transmitted
+                                                      Counter */
+#define XEMACPS_TX64CNT_OFFSET       0x00000118U /**< Error-free 64 byte Frames
+                                                      Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET       0x0000011CU /**< Error-free 65-127 byte
+                                                      Frames Transmitted
+                                                      counter */
+#define XEMACPS_TX128CNT_OFFSET      0x00000120U /**< Error-free 128-255 byte
+                                                      Frames Transmitted
+                                                      counter*/
+#define XEMACPS_TX256CNT_OFFSET      0x00000124U /**< Error-free 256-511 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX512CNT_OFFSET      0x00000128U /**< Error-free 512-1023 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1024CNT_OFFSET     0x0000012CU /**< Error-free 1024-1518 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1519CNT_OFFSET     0x00000130U /**< Error-free larger than
+                                                      1519 byte Frames
+                                                      transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET     0x00000134U /**< TX under run error
+                                                      counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET   0x00000138U /**< Single Collision Frame
+                                                      Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET  0x0000013CU /**< Multiple Collision Frame
+                                                      Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+                                                      Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET   0x00000144U /**< Late Collision Frame
+                                                      Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET    0x00000148U /**< Deferred Transmission
+                                                      Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET   0x0000014CU /**< Transmit Carrier Sense
+                                                      Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET        0x00000150U /**< Octects Received register
+                                                      Low */
+#define XEMACPS_OCTRXH_OFFSET        0x00000154U /**< Octects Received register
+                                                      High */
+
+#define XEMACPS_RXCNT_OFFSET         0x00000158U /**< Error-free Frames
+                                                      Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET    0x0000015CU /**< Error-free Broadcast
+                                                      Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET    0x00000160U /**< Error-free Multicast
+                                                      Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET    0x00000164U /**< Pause Frames
+                                                      Received Counter */
+#define XEMACPS_RX64CNT_OFFSET       0x00000168U /**< Error-free 64 byte Frames
+                                                      Received Counter */
+#define XEMACPS_RX65CNT_OFFSET       0x0000016CU /**< Error-free 65-127 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET      0x00000170U /**< Error-free 128-255 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET      0x00000174U /**< Error-free 256-512 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET      0x00000178U /**< Error-free 512-1023 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET     0x0000017CU /**< Error-free 1024-1518 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET     0x00000180U /**< Error-free 1519-max byte
+                                                      Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET     0x00000184U /**< Undersize Frames Received
+                                                      Counter */
+#define XEMACPS_RXOVRCNT_OFFSET      0x00000188U /**< Oversize Frames Received
+                                                      Counter */
+#define XEMACPS_RXJABCNT_OFFSET      0x0000018CU /**< Jabbers Received
+                                                      Counter */
+#define XEMACPS_RXFCSCNT_OFFSET      0x00000190U /**< Frame Check Sequence
+                                                      Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET   0x00000194U /**< Length Field Error
+                                                      Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET     0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET    0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET   0x000001A0U /**< Receive Resource Error
+                                                      Counter */
+#define XEMACPS_RXORCNT_OFFSET       0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET      0x000001A8U /**< IP header Checksum Error
+                                                      Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET     0x000001ACU /**< TCP Checksum Error
+                                                      Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0U /**< UDP Checksum Error
+                                                      Counter */
+#define XEMACPS_LAST_OFFSET          0x000001B4U /**< Last statistic counter
+						      offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET      0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET      0x000001D8U /**< 1588 nanosecond
+						      adjustment counter */
+#define XEMACPS_1588_INC_OFFSET      0x000001DCU /**< 1588 nanosecond
+						      increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0U /**< 1588 PTP transmit second
+						      counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+						      nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8U /**< 1588 PTP receive second
+						      counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+						      nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0U /**< 1588 PTP peer transmit
+						      second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+						      nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8U /**< 1588 PTP peer receive
+						      second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+						      nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
+							reg */
+#define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
+							reg */
+#define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
+							reg */
+#define XEMACPS_MSBBUF_QBASE_OFFSET  0x000004C8U /**< MSB Buffer Q Base
+							reg */
+#define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
+							reg */
+#define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
+							reg */
+#define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
+							reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000U /**< Flush a packet from
+							Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+                                                         pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK      0x00000400U /**< Halt transmission
+                                                         after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK     0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK     0x00000080U /**< Enable writing to
+                                                         stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040U /**< Increment statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020U /**< Clear statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+                                                        non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000U /**< disable rejection of
+                                                        FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000U /**< enable RX checksum
+                                                        offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+                                                        Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK   0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U	   /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000U /**< Discard FCS from
+                                                        received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_1000_MASK        0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100U /**< Enable 1536 byte
+                                                        frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020U /**< Do not receive
+                                                        broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004U /**< Receive only VLAN
+                                                        frames */
+#define XEMACPS_NWCFG_FDEN_MASK        0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK         0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK       0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK         0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK        0x0000FFFFU /**< Address bits[47:32]
+                                                      bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64		0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
+													size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer
+												size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800U /**< enable/disable TX
+													    checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK        0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010U /**< Transmit buffs exhausted
+                                                       mid frame */
+#define XEMACPS_TXSR_TXGO_MASK        0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK       0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK      ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_TXSR_URUN_MASK | \
+                                       (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+                                       (u32)XEMACPS_TXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+                                       (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK       0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK      ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_RXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK	0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK	0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000U /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000U /**< PTP Pdelay_req
+						     transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK     0x00800000U /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000U /**< PTP Delay_req transmitted
+						*/
+#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000U /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000U /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK     0x00080000U /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
+                                                     zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U	/**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U	/**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK      0x00000400U	/**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U	/**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK      0x00000040U	/**< Transmit err occurred or
+                                                     no buffers*/
+#define XEMACPS_IXR_RETRY_MASK      0x00000020U	/**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK       0x00000010U	/**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK     0x00000008U	/**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK     0x00000004U	/**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U	/**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK      0x00000001U	/**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK        0x00007FFFU	/**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK    ((u32)XEMACPS_IXR_TXEXH_MASK |         \
+                                     (u32)XEMACPS_IXR_RETRY_MASK |         \
+                                     (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK    ((u32)XEMACPS_IXR_HRESPNOK_MASK |      \
+                                     (u32)XEMACPS_IXR_RXUSED_MASK |        \
+                                     (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U	/**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U	/**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U	/**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U	/**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U	/**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU	/**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U	/**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U	/**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET  0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET  0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET  0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process.  After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK  0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK  0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK  0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK   0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK   0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK  0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK   0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK     0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK       0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000U /**< Specific address
+                                                      matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK      0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK       0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK       0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK       0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK       0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK       0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK      0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK       0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32  Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+    XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+*         u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+    XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_intr.c
new file mode 100644
index 000000000..1c59e6c63
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_intr.c
@@ -0,0 +1,260 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
+*		      Rx errors. Under heavy Rx traffic, there will be a large
+*		      number of errors related to receive buffer not available.
+*		      Because of a HW bug (SI #692601), under such heavy errors,
+*		      the Rx data path can become unresponsive. To reduce the
+*		      probabilities for hitting this HW bug, the SW writes to
+*		      bit 18 to flush a packet from Rx DPRAM immediately. The
+*		      changes for it are done in the function
+*		      XEmacPs_IntrHandler.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+*		       and 64-bit changes.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ *        XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ *        when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPointer, void *CallBackRef)
+{
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FuncPointer != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	switch (HandlerType) {
+	case XEMACPS_HANDLER_DMASEND:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->SendRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_DMARECV:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->RecvRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_ERROR:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+		InstancePtr->ErrorRef = CallBackRef;
+		break;
+	default:
+		Status = (LONG)(XST_INVALID_PARAM);
+		break;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+*        interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+	u32 RegISR;
+	u32 RegSR;
+	u32 RegCtrl;
+	u32 RegQ1ISR = 0U;
+	XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* This ISR will try to handle as many interrupts as it can in a single
+	 * call. However, in most of the places where the user's error handler
+         * is called, this ISR exits because it is expected that the user will
+         * reset the device in nearly all instances.
+	 */
+	RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_ISR_OFFSET);
+
+	/* Read Transmit Q1 ISR */
+
+	if (InstancePtr->Version > 2)
+		RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET);
+
+	/* Clear the interrupt status register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   RegISR);
+
+	/* Receive complete interrupt */
+	if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+		/* Clear RX status register RX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET,
+				   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+				   (u32)XEMACPS_RXSR_BUFFNA_MASK));
+		InstancePtr->RecvHandler(InstancePtr->RecvRef);
+	}
+
+	/* Transmit Q1 complete interrupt */
+	if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET,
+				   XEMACPS_INTQ1SR_TXCOMPL_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Transmit complete interrupt */
+	if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Receive error conditions interrupt */
+	if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+		/* Clear RX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_RXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET, RegSR);
+
+		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
+		 * register to flush a packet out of Rx SRAM upon
+		 * an error for receive buffer not available. */
+		if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+			RegCtrl =
+			XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_NWCTRL_OFFSET);
+			RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET, RegCtrl);
+		}
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_RECV,
+					  RegSR);
+	}
+
+        /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+         * will be asserted the same time.
+         * Have to distinguish this bit to handle the real error condition.
+         */
+	/* Transmit Q1 error conditions interrupt */
+        if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+            ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+			/* Clear Interrupt Q1 status register */
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegQ1ISR);
+	   }
+
+	/* Transmit error conditions interrupt */
+        if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+            (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_TXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET, RegSR);
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegSR);
+	}
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_sinit.c
new file mode 100644
index 000000000..67822625e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_0/src/xemacps_sinit.c
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 New
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+	XEmacPs_Config *CfgPtr = NULL;
+	u32 i;
+
+	for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+		if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XEmacPs_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (XEmacPs_Config *)(CfgPtr);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/Makefile
new file mode 100644
index 000000000..8601ce4c7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xgpiops_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling gpiops"
+
+xgpiops_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xgpiops_includes
+
+xgpiops_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops.c
new file mode 100644
index 000000000..cc7910e59
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops.c
@@ -0,0 +1,620 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device. The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	ConfigPtr points to the XGpioPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address should be passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS always.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status = XST_SUCCESS;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+	/*
+	 * Set some default values for instance data, don't indicate the device
+	 * is ready to use until everything has been initialized successfully.
+	 */
+	InstancePtr->IsReady = 0U;
+	InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+	InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Handler = StubHandler;
+
+	/*
+	 * By default, interrupts are not masked in GPIO. Disable
+	 * interrupts for all pins in all the 4 banks.
+	 */
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(1) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(2) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(3) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+
+	/*
+	 * Indicate the component is now ready to use.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* @return	Current value of the Data register.
+*
+* @note		This function is used for reading the state of all the GPIO pins
+*		of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the data has to be read.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*		See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return	Current value of the Pin (0 or 1).
+*
+* @note		This function is used for reading the state of the specified
+*		GPIO pin.
+*
+*****************************************************************************/
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Data is the value to be written to the Data register.
+*
+* @return	None.
+*
+* @note		This function is used for writing to all the GPIO pins of
+*		the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+			  XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+* @param	Data is the data to be written to the specified pin (0 or 1).
+*
+* @return	None.
+*
+* @note		This function does a masked write to the specified pin of
+*		the specified GPIO bank. The previous state of other pins
+*		is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
+{
+	u32 RegOffset;
+	u32 Value;
+	u8 Bank;
+	u8 PinNumber;
+	u32 DataVar = Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	if (PinNumber > 15U) {
+		/*
+		 * There are only 16 data bits in bit maskable register.
+		 */
+		PinNumber -= (u8)16;
+		RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+	} else {
+		RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+	}
+
+	/*
+	 * Get the 32 bit value to be written to the Mask/Data register where
+	 * the upper 16 bits is the mask and lower 16 bits is the data.
+	 */
+	DataVar &= (u32)0x01;
+	Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+			  RegOffset, Value);
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Direction is the 32 bit mask of the Pin direction to be set for
+*		all the pins in the Bank. Bits with 0 are set to Input mode,
+*		bits with 1 are	set to Output Mode.
+*
+* @return	None.
+*
+* @note		This function is used for setting the direction of all the pins
+*		in the specified bank. The previous state of the pins is
+*		not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+* @param	Direction is the direction to be set for the specified pin.
+*		Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return	None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 DirModeReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+	Xil_AssertVoid(Direction <= (u32)1);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_DIRM_OFFSET);
+
+	if (Direction!=(u32)0) { /*  Output Direction */
+		DirModeReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Input Direction */
+		DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			 XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* return	Returns a 32 bit mask of the Direction register. Bits with 0 are
+*		in Input mode, bits with 1 are in Output Mode.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Direction is to be
+*		retrieved.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	Direction of the specified pin.
+*		- 0 for Input Direction
+*		- 1 for Output Direction
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	OpEnable is the 32 bit mask of the Output Enables to be set for
+*		all the pins in the Bank. The Output Enable of bits with 0 are
+*		disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return	None.
+*
+* @note		This function is used for setting the Output Enables of all the
+*		pins in the specified bank. The previous state of the Output
+*		Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+* @param	OpEnable specifies whether the Output Enable for the specified
+*		pin should be enabled.
+*		Valid values are 0 for Disabling Output Enable,
+*		1 for Enabling Output Enable.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 OpEnableReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+	Xil_AssertVoid(OpEnable <= (u32)1);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_OUTEN_OFFSET);
+
+	if (OpEnable != (u32)0) { /*  Enable Output Enable */
+		OpEnableReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Disable Output Enable */
+		OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* return	Returns a a 32 bit mask of the Output Enable register.
+*		Bits with 0 are in Disabled state, bits with 1 are in
+*		Enabled State.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Output Enable status is to
+*		be retrieved.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	Output Enable of the specified pin.
+*		- 0 if Output Enable is disabled for this pin
+*		- 1 if Output Enable is enabled for this pin
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param	PinNumber is the Pin number in the GPIO device.
+* @param	BankNumber returns the Bank in which this GPIO pin is present.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	PinNumberInBank returns the Pin Number within the Bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+{
+	/*
+	 * This structure defines the mapping of the pin numbers to the banks when
+	 * the driver APIs are used for working on the individual pins.
+	 */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+	u32 XGpioPsPinTable[] = {
+					(u32)25, /* 0 - 25, Bank 0 */
+					(u32)51, /* 26 - 51, Bank 1 */
+					(u32)77, /* 52 - 77, Bank 2 */
+					(u32)109, /* 78 - 109, Bank 3 */
+					(u32)141, /* 110 - 141, Bank 4 */
+					(u32)173 /* 142 - 173 Bank 5 */
+				};
+			*BankNumber = 0U;
+			while (*BankNumber < 6U) {
+				if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+					break;
+				}
+				(*BankNumber)++;
+			}
+#else
+	u32 XGpioPsPinTable[] = {
+		(u32)31, /* 0 - 31, Bank 0 */
+		(u32)53, /* 32 - 53, Bank 1 */
+		(u32)85, /* 54 - 85, Bank 2 */
+		(u32)117 /* 86 - 117 Bank 3 */
+	};
+	*BankNumber = 0U;
+	while (*BankNumber < 4U) {
+		if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+			break;
+		}
+		(*BankNumber)++;
+    }
+#endif
+	if (*BankNumber == (u8)0) {
+		*PinNumberInBank = PinNumber;
+	} else {
+		*PinNumberInBank = (u8)((u32)PinNumber %
+					(XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops.h
new file mode 100644
index 000000000..ef9a7f05a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops.h
@@ -0,0 +1,277 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+*	- 4 banks
+*	- Masked writes (There are no masked reads)
+*	- Bypass mode
+*	- Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* 


+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+#ifndef XGPIOPS_H		/* prevent circular inclusions */
+#define XGPIOPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ *  @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING	0x00U  /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING	0x01U  /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH	0x02U  /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	0x03U  /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW	0x04U  /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK0			0x00U  /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1			0x01U  /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2			0x02U  /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3			0x03U  /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4			0x04U  /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5			0x05U  /**< GPIO Bank 5 */
+
+#define XGPIOPS_MAX_BANKS		0x06U  /**< Max banks in a GPIO device */
+#define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)174 /*< Max pins in the ZynqMP GPIO device
+					      * 0 - 25,  Bank 0
+					      * 26 - 51, Bank 1
+					      *	52 - 77, Bank 2
+					      *	78 - 109, Bank 3
+					      *	110 - 141, Bank 4
+					      *	142 - 173, Bank 5
+					      */
+#else
+
+#define XGPIOPS_MAX_BANKS		0x04U  /**< Max banks in a GPIO device */
+#define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /*< Max pins in the GPIO device
+					      * 0 - 31,  Bank 0
+					      * 32 - 53, Bank 1
+					      *	54 - 85, Bank 2
+					      *	86 - 117, Bank 3
+					      */
+
+
+#endif
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions for a GPIO bank. It is
+ *		passed back to the upper layer when the callback is invoked. Its
+ *		type is not important to the driver component, so it is a void
+ *		pointer.
+ * @param	Bank is the bank for which the interrupt status has changed.
+ * @param	Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XGpioPs_Config GpioConfig;	/**< Device configuration */
+	u32 IsReady;			/**< Device is initialized and ready */
+	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
+	void *CallBackRef; 		/**< Callback ref for bank handlers */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xgpiops.c
+ */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+			   u32 EffectiveAddr);
+
+/*
+ * Bank APIs in xgpiops.c
+ */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber,	u8 *BankNumber, u8 *PinNumberInBank);
+
+/*
+ * Pin APIs in xgpiops.c
+ */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/*
+ * Diagnostic functions in xgpiops_selftest.c
+ */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/*
+ * Functions in xgpiops_intr.c
+ */
+/*
+ * Bank APIs in xgpiops_intr.c
+ */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+			     XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/*
+ * Pin APIs in xgpiops_intr.c
+ */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/*
+ * Functions in xgpiops_sinit.c
+ */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_g.c
new file mode 100644
index 000000000..0ac9ce911
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_GPIO_0_DEVICE_ID,
+		XPAR_PSU_GPIO_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_hw.c
new file mode 100644
index 000000000..dfa99c02f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_hw.c
@@ -0,0 +1,175 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+*
+* This file contains low level GPIO functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk   08/22/13 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param	Base address of GPIO module
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+	u32 BankCount;
+
+	/*
+	 * Write reset values to all mask data registers
+	 */
+	for(BankCount = 2U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+	}
+	/*
+	 * Write reset values to all output data registers
+	 */
+	for(BankCount = 2U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_OFFSET), 0x0U);
+	}
+
+	/*
+	 * Reset all registers of all 4 banks
+	 */
+	for(BankCount = 0U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTMASK_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTDIS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTSTS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTPOL_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTANY_OFFSET), 0x0U);
+	}
+
+	/*
+	 * Bank 0 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+			XGPIOPS_INTTYPE_BANK0_RESET);
+	/*
+	 * Bank 1 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress,
+			((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK1_RESET);
+	/*
+	 * Bank 2 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK2_RESET);
+	/*
+	 * Bank 3 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK3_RESET);
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+	/*
+	 * Bank 4 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK4_RESET);
+	/*
+	 * Bank 5 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK5_RESET);
+#endif
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_hw.h
new file mode 100644
index 000000000..2f4ea8041
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_hw.h
@@ -0,0 +1,161 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
+#define XGPIOPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ *  @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ *  @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U  /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U  /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET  0x00000040U  /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ *  @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET  0x3FFFFFFFU
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x3FFFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0x3FFFFFFFU
+#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU
+#define XGPIOPS_INTTYPE_BANK4_RESET  0xFFFFFFFFU
+#define XGPIOPS_INTTYPE_BANK5_RESET  0xFFFFFFFFU
+#else
+
+#define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFFU
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x3FFFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFFU
+#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU
+#endif
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
+		Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the offset of the register to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
+		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_intr.c
new file mode 100644
index 000000000..83c4c6254
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_intr.c
@@ -0,0 +1,745 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to API's. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Mask is the bit mask of the pins for which interrupts are to
+*		be enabled. Bit positions of 1 will be enabled. Bit positions
+*		of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be enabled.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Mask is the bit mask of the pins for which interrupts are
+*		to be disabled. Bit positions of 1 will be disabled. Bit
+*		positions of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be disabled.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg =  ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* @return	Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+*		indicate that the interrupt for that pin is enabled, bit
+*		positions with 0 indicate that the interrupt for that pin is
+*		disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
+{
+	u32 IntrMask;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+	return (~IntrMask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return
+*		- TRUE if the interrupt is enabled.
+*		- FALSE if the interrupt is disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg  = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* @return	The value read from Interrupt Status Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return
+*		- TRUE if the interrupt has occurred.
+*		- FALSE if the interrupt has not occurred.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Mask is the mask of the interrupts to be cleared. Bit positions
+*		of 1 will be cleared. Bit positions of 0 will not change the
+*		previous interrupt status.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	/*
+	 * Clear the currently pending interrupts.
+	 */
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt status is to be
+*		cleared. Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	/*
+	 * Clear the specified pending interrupts.
+	 */
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	IntrReg &= ((u32)1 << PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	IntrType is the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity is the 32 bit mask of the interrupt polarity.
+*		0 means Active Low or Falling Edge and 1 means Active High or
+*		Rising Edge.
+* @param	IntrOnAny is the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means  trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		This function is used for setting the interrupt related
+*		properties of all the pins in the specified bank. The previous
+*		state of the pins is not maintained.
+*		To change the Interrupt properties of a single GPIO pin, use the
+*		function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	IntrType returns the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity returns the 32 bit mask of the interrupt
+*		polarity. 0 means Active Low or Falling Edge and 1 means
+*		Active High or Rising Edge.
+* @param	IntrOnAny returns the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTTYPE_OFFSET);
+
+	*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					 XGPIOPS_INTPOL_OFFSET);
+
+	*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be set.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+* @param	IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+*		defined in xgpiops.h to specify the IRQ type.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
+{
+	u32 IntrTypeReg;
+	u32 IntrPolReg;
+	u32 IntrOnAnyReg;
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+	Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_INTTYPE_OFFSET);
+
+	IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTPOL_OFFSET);
+
+	IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					XGPIOPS_INTANY_OFFSET);
+
+	switch (IrqType) {
+		case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		default:
+			/**< Default statement is added for MISRA C compliance. */
+			break;
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be obtained.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	None.
+*
+* @note		Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+*		returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u32 IntrType;
+	u32 IntrPol;
+	u32 IntrOnAny;
+	u8 Bank;
+	u8 PinNumber;
+	u8 IrqType;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+
+	if (IntrType == ((u32)1 << PinNumber)) {
+
+		IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+
+		if (IntrOnAny == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+		} else if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+		}
+	} else {
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+		if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+		}
+	}
+
+	return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the  XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+*
+* @return	None.
+*
+* @note		The handler is called within interrupt context, so it should do
+*		its work quickly and queue potentially time-consuming work to a
+*		task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+				 XGpioPs_Handler FuncPointer)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPointer != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPointer;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return	None.
+*
+* @note		This function does not save and restore the processor context
+*		such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
+{
+	u8 Bank;
+	u32 IntrStatus;
+	u32 IntrEnabled;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (Bank = 0U; Bank < XGPIOPS_MAX_BANKS; Bank++) {
+		IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+		if (IntrStatus != (u32)0) {
+			IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
+							      Bank);
+			XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
+							(IntrStatus & IntrEnabled));
+			InstancePtr->Handler(InstancePtr->
+					     CallBackRef, Bank,
+					     (IntrStatus & IntrEnabled));
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	Bank is the GPIO Bank in which an interrupt occurred.
+* @param	Status is the Interrupt status of the GPIO bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
+{
+	(void*) CallBackRef;
+	(void) Bank;
+	(void) Status;
+
+	Xil_AssertVoidAlways();
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_selftest.c
new file mode 100644
index 000000000..9dcca8c12
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+*		- XST_SUCCESS if the self-test passed.
+* 		- XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrEnabled;
+	u32 CurrentIntrType = 0U;
+	u32 CurrentIntrPolarity = 0U;
+	u32 CurrentIntrOnAny = 0U;
+	u32 IntrType = 0U;
+	u32 IntrPolarity = 0U;
+	u32 IntrOnAny = 0U;
+	u32 IntrTestValue = 0x22U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the Interrupts for Bank 0 .
+	 */
+	IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+	XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	/*
+	 * Get the Current Interrupt properties for Bank 0.
+	 * Set them to a known value, read it back and compare.
+	 */
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+			     &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+			     IntrTestValue, IntrTestValue);
+
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+			     &IntrPolarity, &IntrOnAny);
+
+	if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+	    (IntrOnAny != IntrTestValue)) {
+
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Restore the contents of all the interrupt registers modified in this
+	 * test.
+	 */
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+			     CurrentIntrPolarity, CurrentIntrOnAny);
+
+	XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_sinit.c
new file mode 100644
index 000000000..d6fd4cb26
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_0/src/xgpiops_sinit.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+	XGpioPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+		if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XGpioPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XGpioPs_Config *)CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/Makefile
new file mode 100644
index 000000000..8c16c35ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xiicps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling iicps"
+
+xiicps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xiicps_includes
+
+xiicps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps.c
new file mode 100644
index 000000000..6ea477bae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps.c
@@ -0,0 +1,329 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.c
+*
+* Contains implementation of required functions for the XIicPs driver.
+* See xiicps.h for detailed description of the device and driver.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.00a sdm     09/21/11 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+* 2.1   hk      04/25/14 Explicitly reset CR and clear FIFO in Abort function
+*                        and state the same in the comments. CR# 784254.
+*                        Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk		10/07/14 Repeated start feature removed.
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+* 						 in XIicPs_Reset.
+*				12/06/14 Implemented Repeated start feature.
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef, u32 StatusEvent);
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XIicPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Device is disabled
+*   - Slave mode
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific IIC device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return	The return value is XST_SUCCESS if successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
+				  u32 EffectiveAddr)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->StatusHandler = StubHandler;
+	InstancePtr->CallBackRef = NULL;
+
+	InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the IIC device to get it into its initial state. It is expected
+	 * that device configuration will take place after this initialization
+	 * is done, but before the device is started.
+	 */
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	/* Initialize repeated start flag to 0 */
+	InstancePtr->IsRepeatedStart = 0;
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Check whether the I2C bus is busy
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+* 		- TRUE if the bus is busy.
+*		- FALSE if the bus is not busy.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	s32	Status;
+
+	StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_SR_OFFSET);
+	if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
+		Status = (s32)TRUE;
+	}else {
+		Status = (s32)FALSE;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference.
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef, u32 StatusEvent)
+{
+	(void) ((void *)CallBackRef);
+	(void) StatusEvent;
+	Xil_AssertVoidAlways();
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by resetting the FIFOs. The byte counts are
+* cleared.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Abort(XIicPs *InstancePtr)
+{
+	u32 IntrMaskReg;
+	u32 IntrStatusReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enter a critical section, so disable the interrupts while we clear
+	 * the FIFO and the status register.
+	 */
+	IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_IMR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+
+	/*
+	 * Reset the settings in config register and clear the FIFOs.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  XIICPS_CR_RESET_VALUE | XIICPS_CR_CLR_FIFO_MASK);
+
+	/*
+	 * Read, then write the interrupt status to make sure there are no
+	 * pending interrupts.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Restore the interrupt state.
+	 */
+	IntrMaskReg = XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IER_OFFSET, IntrMaskReg);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the IIC device. Reset must only be called after the driver has been
+* initialized. The configuration of the device after reset is the same as its
+* configuration after initialization.  Any data transfer that is in progress is
+* aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and reenabling interrupts for the IIC device after the reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Reset(XIicPs *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress.
+	 */
+	XIicPs_Abort(InstancePtr);
+
+	/*
+	 * Reset any values so the software state matches the hardware device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  XIICPS_CR_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
+			  XIICPS_IXR_ALL_INTR_MASK);
+
+}
+/*****************************************************************************/
+/**
+* Put more data into the transmit FIFO, number of bytes is ether expected
+* number of bytes for this transfer or available space in FIFO, which ever
+* is less.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes left for this instance.
+*
+* @note		This is function is shared by master and slave.
+*
+******************************************************************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr)
+{
+	u8 AvailBytes;
+	s32 LoopCnt;
+	s32 NumBytesToSend;
+
+	/*
+	 * Determine number of bytes to write to FIFO.
+	 */
+	AvailBytes = (u8)XIICPS_FIFO_DEPTH -
+		(u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_TRANS_SIZE_OFFSET);
+
+	if (InstancePtr->SendByteCount > (s32)AvailBytes) {
+		NumBytesToSend = (s32)AvailBytes;
+	} else {
+		NumBytesToSend = InstancePtr->SendByteCount;
+	}
+
+	/*
+	 * Fill FIFO with amount determined above.
+	 */
+	for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
+		XIicPs_SendByte(InstancePtr);
+	}
+
+	return InstancePtr->SendByteCount;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps.h
new file mode 100644
index 000000000..9c6dc10eb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps.h
@@ -0,0 +1,416 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.h
+*
+* This is an implementation of IIC driver in the PS block. The device can
+* be either a master or a slave on the IIC bus. This implementation supports
+* both interrupt mode transfer and polled mode transfer. Only 7-bit address
+* is used in the driver, although the hardware also supports 10-bit address.
+*
+* IIC is a 2-wire serial interface.  The master controls the clock, so it can
+* regulate when it wants to send or receive data. The slave is under control of
+* the master, it must respond quickly since it has no control of the clock and
+* must send/receive data as fast or as slow as the master does.
+*
+* The higher level software must implement a higher layer protocol to inform
+* the slave what to send to the master.
+*
+* Initialization & Configuration
+*
+* The XIicPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*    - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
+*      the static configuration structure defined in xiicps_g.c. This is
+*      setup by the tools. For some operating systems the config structure
+*      will be initialized by the software and this call is not needed.
+*
+*   - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a
+*     system with address translation, the provided virtual memory base
+*     address replaces the physical address in the configuration
+*     structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, bus arbitration is defined in the IIC
+* standard. Lost of arbitration causes arbitration loss interrupt on the device.
+*
+* Multiple Slaves
+*
+* Multiple slaves are supported by selecting them with unique addresses. It is
+* up to the system designer to be sure all devices on the IIC bus have
+* unique addresses.
+*
+* Addressing
+*
+* The IIC hardware can use 7 or 10 bit addresses.  The driver provides the
+* ability to control which address size is sent in messages as a master to a
+* slave device.
+*
+* FIFO Size 
+* The hardware FIFO is 32 bytes deep. The user must know the limitations of
+* other IIC devices on the bus. Some are only able to receive a limited number
+* of bytes in a single transfer.
+*
+* Data Rates
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+*
+* When the device is configured as a slave, the slck setting controls the
+* sample rate and so must be set to be at least as fast as the fastest scl
+* expected to be seen in the system.
+*
+* Polled Mode Operation
+*
+* This driver supports polled mode transfers.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XIicPs_InterruptHandler to an interrupt system such that it will be called
+* when an interrupt occurs. This function does not save and restore the
+* processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Transfer complete
+* - More Data
+* - Transfer not Acknowledged
+* - Transfer Time out
+* - Monitored slave ready - master mode only
+* - Receive Overflow
+* - Transmit FIFO overflow
+* - Receive FIFO underflow
+* - Arbitration lost
+*
+* Bus Busy
+*
+* Bus busy is checked before the setup of a master mode device, to avoid
+* unnecessary arbitration loss interrupt.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied by
+* the layer above this driver.
+*
+*Repeated Start
+*
+* The I2C controller does not indicate completion of a receive transfer if HOLD
+* bit is set. Due to this errata, repeated start cannot be used if a receive
+* transfer is followed by any other transfer.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk  08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                    read mode and clear transfer size register.
+*                    Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	10/07/14 Repeated start feature deleted.
+* 3.0	sk	11/03/14 Modified TimeOut Register value to 0xFF
+* 					 in XIicPs_Reset.
+* 			12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XIICPS_H       /* prevent circular inclusions */
+#define XIICPS_H       /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xiicps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options may be specified or retrieved for the device and
+ * enable/disable additional features of the IIC.  Each of the options
+ * are bit fields, so more than one may be specified.
+ *
+ * @{
+ */
+#define XIICPS_7_BIT_ADDR_OPTION	0x01U  /**< 7-bit address mode */
+#define XIICPS_10_BIT_ADDR_OPTION	0x02U  /**< 10-bit address mode */
+#define XIICPS_SLAVE_MON_OPTION		0x04U  /**< Slave monitor mode */
+#define XIICPS_REP_START_OPTION		0x08U  /**< Repeated Start */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to an application
+ * event handler from the driver.  These constants are bit masks such that
+ * more than one event can be passed to the handler.
+ *
+ * @{
+ */
+#define XIICPS_EVENT_COMPLETE_SEND	0x0001U  /**< Transmit Complete Event*/
+#define XIICPS_EVENT_COMPLETE_RECV	0x0002U  /**< Receive Complete Event*/
+#define XIICPS_EVENT_TIME_OUT		0x0004U  /**< Transfer timed out */
+#define XIICPS_EVENT_ERROR			0x0008U  /**< Receive error */
+#define XIICPS_EVENT_ARB_LOST		0x0010U  /**< Arbitration lost */
+#define XIICPS_EVENT_NACK			0x0020U  /**< NACK Received */
+#define XIICPS_EVENT_SLAVE_RDY		0x0040U  /**< Slave ready */
+#define XIICPS_EVENT_RX_OVR			0x0080U  /**< RX overflow */
+#define XIICPS_EVENT_TX_OVR			0x0100U  /**< TX overflow */
+#define XIICPS_EVENT_RX_UNF			0x0200U  /**< RX underflow */
+/*@}*/
+
+/** @name Role constants
+ *
+ * These constants are used to pass into the device setup routines to
+ * set up the device according to transfer direction.
+ */
+#define SENDING_ROLE		1  /**< Transfer direction is sending */
+#define RECVING_ROLE		0  /**< Transfer direction is receiving */
+
+/* Maximum transfer size */
+#define XIICPS_MAX_TRANSFER_SIZE	(u32)(255U - 3U)
+
+/**************************** Type Definitions *******************************/
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		not important to the driver, so it is a void pointer.
+* @param	StatusEvent indicates one or more status events that occurred.
+*/
+typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;     /**< Unique ID  of device */
+	u32 BaseAddress;  /**< Base address of the device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XIicPs_Config;
+
+/**
+ * The XIicPs driver instance data. The user is required to allocate a
+ * variable of this type for each IIC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIicPs_Config Config;	/* Configuration structure */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Options set in the device */
+
+	u8 *SendBufferPtr;	/* Pointer to send buffer */
+	u8 *RecvBufferPtr;	/* Pointer to recv buffer */
+	s32 SendByteCount;	/* Number of bytes still expected to send */
+	s32 RecvByteCount;	/* Number of bytes still expected to receive */
+	s32 CurrByteCount;	/* No. of bytes expected in current transfer */
+
+	s32 UpdateTxSize;	/* If tx size register has to be updated */
+	s32 IsSend;		/* Whether master is sending or receiving */
+	s32 IsRepeatedStart;	/* Indicates if user set repeated start */
+
+	XIicPs_IntrHandler StatusHandler;  /* Event handler function */
+	void *CallBackRef;	/* Callback reference for event handler */
+} XIicPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Place one byte into the transmit FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_SendByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_SendByte(InstancePtr)					\
+{									\
+	u8 Data;							\
+	Data = *((InstancePtr)->SendBufferPtr);				\
+	 XIicPs_Out32((InstancePtr)->Config.BaseAddress			\
+			 + (u32)(XIICPS_DATA_OFFSET), 			\
+					(u32)(Data));			\
+	(InstancePtr)->SendBufferPtr += 1;				\
+	(InstancePtr)->SendByteCount -= 1;\
+}
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		u8 XIicPs_RecvByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_RecvByte(InstancePtr)					\
+{									\
+	u8 *Data, Value;						\
+	Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress	\
+		  + (u32)XIICPS_DATA_OFFSET));  			\
+	Data = &Value;							\
+	*(InstancePtr)->RecvBufferPtr = *Data;				\
+	(InstancePtr)->RecvBufferPtr += 1;				\
+	 (InstancePtr)->RecvByteCount --; 				\
+}
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Function for configuration lookup, in xiicps_sinit.c
+ */
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions for general setup, in xiicps.c
+ */
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
+				  u32 EffectiveAddr);
+
+void XIicPs_Abort(XIicPs *InstancePtr);
+void XIicPs_Reset(XIicPs *InstancePtr);
+
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+/*
+ * Functions for interrupts, in xiicps_intr.c
+ */
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr);
+
+/*
+ * Functions for device as master, in xiicps_master.c
+ */
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for device as slave, in xiicps_slave.c
+ */
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xiicps_selftest.c
+ */
+s32 XIicPs_SelfTest(XIicPs *InstancePtr);
+
+/*
+ * Functions for setting and getting data rate, in xiicps_options.c
+ */
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
+u32 XIicPs_GetOptions(XIicPs *InstancePtr);
+
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
+u32 XIicPs_GetSClk(XIicPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_g.c
new file mode 100644
index 000000000..51db30170
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_g.c
@@ -0,0 +1,61 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xiicps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIicPs_Config XIicPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_I2C_0_DEVICE_ID,
+		XPAR_PSU_I2C_0_BASEADDR,
+		XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_I2C_1_DEVICE_ID,
+		XPAR_PSU_I2C_1_BASEADDR,
+		XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_hw.c
new file mode 100644
index 000000000..e45101b8d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_hw.c
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.c
+*
+* Contains implementation of required functions for providing the reset sequence
+* to the i2c interface
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.04a kpc     11/07/13 First release
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given I2c interface by
+* configuring the appropriate control bits in the I2c specifc registers
+* the i2cps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status
+*	Clear FIFO's and disable hold bit
+*	Clear the line status
+*	Update relevant config registers with reset values
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* I2c controller
+******************************************************************************/
+void XIicPs_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+
+	/* Disable all the interrupts */
+	XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+	/* Clear the interrupt status */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
+	/* Clear the hold bit,master enable bit and ack bit */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
+	RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
+	/* Clear the fifos */
+	RegVal |= XIICPS_CR_CLR_FIFO_MASK;
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
+	/* Clear the timeout register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	/* Clear the transfer size register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+	/* Clear the status register */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
+	/* Update the configuraqtion register with reset value */
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_hw.h
new file mode 100644
index 000000000..71b770ce4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_hw.h
@@ -0,0 +1,380 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.h
+*
+* This header file contains the hardware definition for an IIC device.
+* It includes register definitions and interface functions to read/write
+* the registers.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype.
+* 3.0	sk		11/03/14 Modified the TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 

+*
+******************************************************************************/
+#ifndef XIICPS_HW_H		/* prevent circular inclusions */
+#define XIICPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the IIC.
+ * @{
+ */
+#define XIICPS_CR_OFFSET			0x00U  /**< 32-bit Control */
+#define XIICPS_SR_OFFSET			0x04U  /**< Status */
+#define XIICPS_ADDR_OFFSET			0x08U  /**< IIC Address */
+#define XIICPS_DATA_OFFSET			0x0CU  /**< IIC FIFO Data */
+#define XIICPS_ISR_OFFSET			0x10U  /**< Interrupt Status */
+#define XIICPS_TRANS_SIZE_OFFSET	0x14U  /**< Transfer Size */
+#define XIICPS_SLV_PAUSE_OFFSET		0x18U  /**< Slave monitor pause */
+#define XIICPS_TIME_OUT_OFFSET		0x1CU  /**< Time Out */
+#define XIICPS_IMR_OFFSET			0x20U  /**< Interrupt Enabled Mask */
+#define XIICPS_IER_OFFSET			0x24U  /**< Interrupt Enable */
+#define XIICPS_IDR_OFFSET			0x28U  /**< Interrupt Disable */
+/* @} */
+
+/** @name Control Register
+ *
+ * This register contains various control bits that
+ * affects the operation of the IIC controller. Read/Write.
+ * @{
+ */
+
+#define XIICPS_CR_DIV_A_MASK	0x0000C000U /**< Clock Divisor A */
+#define XIICPS_CR_DIV_A_SHIFT			14U /**< Clock Divisor A shift */
+#define XIICPS_DIV_A_MAX				 4U /**< Maximum value of Divisor A */
+#define XIICPS_CR_DIV_B_MASK	0x00003F00U /**< Clock Divisor B */
+#define XIICPS_CR_DIV_B_SHIFT			 8U /**< Clock Divisor B shift */
+#define XIICPS_CR_CLR_FIFO_MASK	0x00000040U /**< Clear FIFO, auto clears*/
+#define XIICPS_CR_SLVMON_MASK	0x00000020U /**< Slave monitor mode */
+#define XIICPS_CR_HOLD_MASK		0x00000010U /**<  Hold bus 1=Hold scl,
+												0=terminate transfer */
+#define XIICPS_CR_ACKEN_MASK	0x00000008U /**< Enable TX of ACK when
+												Master receiver*/
+#define XIICPS_CR_NEA_MASK		0x00000004U /**< Addressing Mode 1=7 bit,
+												0=10 bit */
+#define XIICPS_CR_MS_MASK		0x00000002U /**< Master mode bit 1=Master,
+												0=Slave */
+#define XIICPS_CR_RD_WR_MASK	0x00000001U /**< Read or Write Master
+												transfer  0=Transmitter,
+												1=Receiver*/
+#define XIICPS_CR_RESET_VALUE			 0U /**< Reset value of the Control
+												register */
+/* @} */
+
+/** @name IIC Status Register
+ *
+ * This register is used to indicate status of the IIC controller. Read only
+ * @{
+ */
+#define XIICPS_SR_BA_MASK		0x00000100U  /**< Bus Active Mask */
+#define XIICPS_SR_RXOVF_MASK	0x00000080U  /**< Receiver Overflow Mask */
+#define XIICPS_SR_TXDV_MASK		0x00000040U  /**< Transmit Data Valid Mask */
+#define XIICPS_SR_RXDV_MASK		0x00000020U  /**< Receiver Data Valid Mask */
+#define XIICPS_SR_RXRW_MASK		0x00000008U  /**< Receive read/write Mask */
+/* @} */
+
+/** @name IIC Address Register
+ *
+ * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
+ * A write access to this register always initiates a transfer if the IIC is in
+ * master mode. Read/Write
+ * @{
+ */
+#define XIICPS_ADDR_MASK	0x000003FF  /**< IIC Address Mask */
+/* @} */
+
+/** @name IIC Data Register
+ *
+ * When written to, the data register sets data to transmit. When read from, the
+ * data register reads the last received byte of data. Read/Write
+ * @{
+ */
+#define XIICPS_DATA_MASK	0x000000FF  /**< IIC Data Mask */
+/* @} */
+
+/** @name IIC Interrupt Registers
+ *
+ * IIC Interrupt Status Register
+ *
+ * This register holds the interrupt status flags for the IIC controller. Some
+ * of the flags are level triggered
+ * - i.e. are set as long as the interrupt condition exists.  Other flags are
+ *   edge triggered, which means they are set one the interrupt condition occurs
+ *   then remain set until they are cleared by software.
+ *   The interrupts are cleared by writing a one to the interrupt bit position
+ *   in the Interrupt Status Register. Read/Write.
+ *
+ * IIC Interrupt Enable Register
+ *
+ * This register is used to enable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * IIC Interrupt Mask register.  Write only.
+ *
+ * IIC Interrupt Disable Register 
+ *
+ * This register is used to disable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * IIC Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled status of each IIC controller
+ * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
+ * the status register. A bit set to 0 means the interrupt is enabled.
+ * All mask bits are set and all interrupts are disabled after reset. Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Interrupt Status Register
+ * @{
+ */
+
+#define XIICPS_IXR_ARB_LOST_MASK  0x00000200U	 /**< Arbitration Lost Interrupt
+													mask */
+#define XIICPS_IXR_RX_UNF_MASK    0x00000080U	 /**< FIFO Recieve Underflow
+													Interrupt mask */
+#define XIICPS_IXR_TX_OVR_MASK    0x00000040U	 /**< Transmit Overflow
+													Interrupt mask */
+#define XIICPS_IXR_RX_OVR_MASK    0x00000020U	 /**< Receive Overflow Interrupt
+													mask */
+#define XIICPS_IXR_SLV_RDY_MASK   0x00000010U	 /**< Monitored Slave Ready
+													Interrupt mask */
+#define XIICPS_IXR_TO_MASK        0x00000008U	 /**< Transfer Time Out
+													Interrupt mask */
+#define XIICPS_IXR_NACK_MASK      0x00000004U	 /**< NACK Interrupt mask */
+#define XIICPS_IXR_DATA_MASK      0x00000002U	 /**< Data Interrupt mask */
+#define XIICPS_IXR_COMP_MASK      0x00000001U	 /**< Transfer Complete
+													Interrupt mask */
+#define XIICPS_IXR_DEFAULT_MASK   0x000002FFU	 /**< Default ISR Mask */
+#define XIICPS_IXR_ALL_INTR_MASK  0x000002FFU	 /**< All ISR Mask */
+/* @} */
+
+
+/** @name IIC Transfer Size Register
+*
+* The register's meaning varies according to the operating mode as follows:
+*   - Master transmitter mode: number of data bytes still not transmitted minus
+*     one
+*   - Master receiver mode: number of data bytes that are still expected to be
+*     received
+*   - Slave transmitter mode: number of bytes remaining in the FIFO after the
+*     master terminates the transfer
+*   - Slave receiver mode: number of valid data bytes in the FIFO
+*
+* This register is cleared if CLR_FIFO bit in the control register is set.
+* Read/Write
+* @{
+*/
+#define XIICPS_TRANS_SIZE_MASK  0x0000003F /**< IIC Transfer Size Mask */
+#define XIICPS_FIFO_DEPTH          16	  /**< Number of bytes in the FIFO */
+#define XIICPS_DATA_INTR_DEPTH     14    /**< Number of bytes at DATA intr */
+/* @} */
+
+
+/** @name IIC Slave Monitor Pause Register
+*
+* This register is associated with the slave monitor mode of the I2C interface.
+* It is meaningful only when the module is in master mode and bit SLVMON in the
+* control register is set.
+*
+* This register defines the pause interval between consecutive attempts to
+* address the slave once a write to an I2C address register is done by the
+* host. It represents the number of sclk cycles minus one between two attempts.
+*
+* The reset value of the register is 0, which results in the master repeatedly
+* trying to access the slave immediately after unsuccessful attempt.
+* Read/Write
+* @{
+*/
+#define XIICPS_SLV_PAUSE_MASK    0x0000000F  /**< Slave monitor pause mask */
+/* @} */
+
+
+/** @name IIC Time Out Register
+*
+* The value of time out register represents the time out interval in number of
+* sclk cycles minus one.
+*
+* When the accessed slave holds the sclk line low for longer than the time out
+* period, thus prohibiting the I2C interface in master mode to complete the
+* current transfer, an interrupt is generated and TO interrupt flag is set.
+*
+* The reset value of the register is 0x1f.
+* Read/Write
+* @{
+ */
+#define XIICPS_TIME_OUT_MASK    0x000000FFU    /**< IIC Time Out mask */
+#define XIICPS_TO_RESET_VALUE   0x000000FFU    /**< IIC Time Out reset value */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XIicPs_In32 Xil_In32
+#define XIicPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XIicPs_ReadReg(BaseAddress, RegOffset) \
+	XIicPs_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
+*
+******************************************************************************/
+#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/***************************************************************************/
+/**
+* Read the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	Current bit mask that represents currently enabled interrupts.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadIER(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_ReadIER(BaseAddress) \
+	XIicPs_ReadReg((BaseAddress),  XIICPS_IER_OFFSET)
+
+/***************************************************************************/
+/**
+* Write to the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be enabled.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
+
+/***************************************************************************/
+/**
+* Disable all interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableAllInterrupts(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_DisableAllInterrupts(BaseAddress) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		XIICPS_IXR_ALL_INTR_MASK)
+
+/***************************************************************************/
+/**
+* Disable selected interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be disabled.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		(IntrMask))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the I2c interface
+ */
+void XIicPs_ResetHw(u32 BaseAddress);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_intr.c
new file mode 100644
index 000000000..b1c604f9a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_intr.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_intr.c
+*
+* Contains functions of the XIicPs driver for interrupt-driven transfers.
+* See xiicps.h for a detailed description of the device and driver.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 3.00	sk		01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function, the status handler, which the
+* driver calls when it encounters conditions that should be reported to the
+* higher layer software. The handler executes in an interrupt context, so
+* the amount of processing should be minimized
+*
+* Refer to the xiicps.h file for a list of the Callback events. The events are
+* defined to start with XIICPS_EVENT_*.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FunctionPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should finish its
+* work quickly.
+*
+******************************************************************************/
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FunctionPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FunctionPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_master.c
new file mode 100644
index 000000000..249de73d7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_master.c
@@ -0,0 +1,985 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_master.c
+*
+* Handles master mode transfers.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---  -------- ---------------------------------------------
+* 1.00a jz   01/30/10 First release
+* 1.00a sdm  09/21/11 Updated the XIicPs_SetupMaster to not check for
+*		      Bus Busy condition when the Hold Bit is set.
+* 1.01a sg   03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*		      check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 2.0   hk   03/07/14 Added check for error status in the while loop that
+*                     checks for completion. CR# 762244, 764875.
+* 2.1   hk   04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                     Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk   08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                     read mode and clear transfer size register.
+*                     Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	 10/06/14 Fill transmit fifo before address register when sending.
+* 					  Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
+* 					  Repeated start feature removed.
+* 3.0	sk	 12/06/14 Implemented Repeated start feature.
+*			 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			 02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
+static void MasterSendData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven send in master mode.
+*
+* It tries to send the first FIFO-full of data, then lets the interrupt
+* handler to handle the rest of the data if there is any.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+ ****************************************************************************/
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->IsSend = 1;
+
+	/*
+	 * Set repeated start if sending more than FIFO of data.
+	 */
+	if (((InstancePtr->IsRepeatedStart) != 0)||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+				(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Setup as a master sending role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	(void)TransmitFifoFill(InstancePtr);
+
+	/*
+	 * Do the address transfer to notify the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven receive in master mode.
+*
+* It sets the transfer size register so the slave can send data to us.
+* The rest of the work is managed by interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note		This receive routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->CurrByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->IsSend = 0;
+	InstancePtr->UpdateTxSize = 0;
+
+	if ((ByteCount > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Initialize for a master receiving role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+	/*
+	 * Do the address transfer to signal the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	/*
+	 * Setup the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		InstancePtr->UpdateTxSize = 1;
+	}else {
+		XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
+			 (u32)ByteCount);
+	}
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode send in master mode.
+*
+* It sends data to the FIFO and waits for the slave to pick them up.
+* If slave fails to remove data from FIFO, the send fails with
+* time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+		 s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	u32 Intrs;
+	u32 Value;
+	s32 Status;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	if (((InstancePtr->IsRepeatedStart) != 0) ||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
+		(u32)XIICPS_IXR_NACK_MASK;
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Transmit first FIFO full of data.
+	 */
+	(void)TransmitFifoFill(InstancePtr);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Continue sending as long as there is more data and
+	 * there are no errors.
+	 */
+	Value = ((InstancePtr->SendByteCount > (s32)0) &&
+		((IntrStatusReg & Intrs) == (u32)0U));
+	while (Value != (u32)0x00U) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		/*
+		 * Wait until transmit FIFO is empty.
+		 */
+		if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_ISR_OFFSET);
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
+				((IntrStatusReg & Intrs) == (u32)0U));
+			continue;
+		}
+
+		/*
+		 * Send more data out through transmit FIFO.
+		 */
+		(void)TransmitFifoFill(InstancePtr);
+		Value = ((InstancePtr->SendByteCount > (s32)0) &&
+			((IntrStatusReg & Intrs) == (u32)0U));
+	}
+
+	/*
+	 * Check for completion of transfer.
+	 */
+	while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		/*
+		 * If there is an error, tell the caller.
+		 */
+		if ((IntrStatusReg & Intrs) != 0U) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode receive in master mode.
+*
+* It repeatedly sets the transfer size register so the slave can
+* send data to us. It polls the data register for data to come in.
+* If slave fails to send us data, it fails with time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+				s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 Intrs;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 BytesToRecv;
+	s32 BytesToRead;
+	s32 TransSize;
+	s32 Tmp = 0;
+	u32 Status_Rcv;
+	u32 Status;
+	s32 Result;
+	s32 IsHold = 0;
+	s32 UpdateTxSize = 0;
+	s32 ByteCountVar = ByteCount;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCountVar;
+
+	Platform = XGetPlatform_Info();
+
+	if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+		IsHold = 1;
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Set up the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCountVar > XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		UpdateTxSize = 1;
+	}else {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+			 ByteCountVar);
+	}
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
+			(u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
+	/*
+	 * Poll the interrupt status register to find the errors.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	while ((InstancePtr->RecvByteCount > 0) &&
+			((IntrStatusReg & Intrs) == 0U)) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	    while ((StatusReg & XIICPS_SR_RXDV_MASK) != 0U) {
+		    if (((InstancePtr->RecvByteCount <
+			    XIICPS_DATA_INTR_DEPTH) != 0U) && (IsHold != 0) &&
+			    ((!InstancePtr->IsRepeatedStart) != 0) &&
+			    (UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+		    ByteCountVar --;
+
+			if (Platform == XPLAT_ZYNQ) {
+			    if ((UpdateTxSize != 0) &&
+				    ((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				    break;
+				}
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		}
+		if (Platform == XPLAT_ZYNQ) {
+			if ((UpdateTxSize != 0) &&
+				((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+			    /*  wait while fifo is full */
+			    while (XIicPs_ReadReg(BaseAddr,
+				    XIICPS_TRANS_SIZE_OFFSET) !=
+				    (u32)(ByteCountVar - XIICPS_FIFO_DEPTH)) { ;
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+		    if ((InstancePtr->RecvByteCount > 0) && (ByteCountVar == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		}
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+	if ((IntrStatusReg & Intrs) != 0x0U) {
+		Result = (s32)XST_FAILURE;
+	}
+	else {
+		Result =  (s32)XST_SUCCESS;
+	}
+
+	return Result;
+}
+
+/*****************************************************************************/
+/**
+* This function enables the slave monitor mode.
+*
+* It enables slave monitor in the control register and enables
+* slave ready interrupt. It then does an address transfer to slave.
+* Interrupt handler will signal the caller if slave responds to
+* the address transfer.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we want to contact.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 BaseAddr;
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/* Clear transfer size register */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+
+	/*
+	 * Enable slave monitor mode in control register.
+	 */
+	ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
+	ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
+			(u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
+	ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Set up interrupt flag for slave monitor interrupt.
+	 * Dont enable NACK.
+	 */
+	XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
+
+	/*
+	 * Initialize the slave monitor register.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
+
+	/*
+	 * Set the slave address to start the slave address transmission.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function disables slave monitor mode.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
+{
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Clear slave monitor control bit.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+		XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+			& (~XIICPS_CR_SLVMON_MASK));
+
+	/*
+	 * Clear interrupt flag for slave monitor interrupt.
+	 */
+	XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the master mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper handling.
+*
+* 
+* The interrupts that are handled are:
+* - DATA
+*	This case is handled only for master receive data.
+*	The master has to request for more data (if there is more data to
+*	receive) and read the data from the FIFO .
+*
+* - COMP
+*	If the Master is transmitting data and there is more data to be
+*	sent then the data is written to the FIFO. If there is no more data to
+*	be transmitted then a completion event is signalled to the upper layer
+*	by calling the callback handler.
+*
+*	If the Master is receiving data then the data is read from the FIFO and
+*	the Master has to request for more data (if there is more data to
+*	receive). If all the data has been received then a completion event
+*	is signalled to the upper layer by calling the callback handler.
+*	It is an error if the amount of received data is more than expected.
+*
+* - NAK and SLAVE_RDY
+*	This is signalled to the upper layer by calling the callback handler.
+*
+* - All Other interrupts
+*	These interrupts are marked as error. This is signalled to the upper
+*	layer by calling the callback handler.
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 StatusEvent = 0U;
+	u32 BaseAddr;
+	u16 SlaveAddr;
+	s32 ByteCnt;
+	s32 IsHold;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	Platform = XGetPlatform_Info();
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					 (u32)XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are
+	 * missed while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
+
+	ByteCnt = InstancePtr->CurrByteCount;
+
+	IsHold = 0;
+	if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
+		IsHold = 1;
+	}
+
+	/*
+	 * Send
+	 */
+	if (((InstancePtr->IsSend) != 0) &&
+		((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
+		if (InstancePtr->SendByteCount > 0) {
+			MasterSendData(InstancePtr);
+		} else {
+			StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+		}
+	}
+
+
+	/*
+	 * Receive
+	 */
+	if (((!(InstancePtr->IsSend))!= 0) &&
+		((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
+		(0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
+
+		while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) &
+				XIICPS_SR_RXDV_MASK) != 0U) {
+			if (((InstancePtr->RecvByteCount <
+				XIICPS_DATA_INTR_DEPTH)!= 0U)  && (IsHold != 0)  &&
+				((!InstancePtr->IsRepeatedStart)!= 0) &&
+				(InstancePtr->UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+			ByteCnt--;
+
+			if (Platform == XPLAT_ZYNQ) {
+			    if ((InstancePtr->UpdateTxSize != 0) &&
+				    ((ByteCnt == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				    break;
+				}
+			}
+		}
+
+		if (Platform == XPLAT_ZYNQ) {
+			if ((InstancePtr->UpdateTxSize != 0) &&
+				((ByteCnt == (XIICPS_FIFO_DEPTH + 1))!= 0U)) {
+				/* wait while fifo is full */
+				while (XIicPs_ReadReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET) !=
+					(u32)(ByteCnt - XIICPS_FIFO_DEPTH)) {
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+			if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				SlaveAddr = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+				XIicPs_EnableInterrupts(BaseAddr,
+					(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+					(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+					(u32)XIICPS_IXR_ARB_LOST_MASK);
+			}
+		}
+		InstancePtr->CurrByteCount = ByteCnt;
+	}
+
+	if (((!(InstancePtr->IsSend)) != 0) &&
+		(0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
+		/*
+		 * If all done, tell the application.
+		 */
+		if (InstancePtr->RecvByteCount == 0){
+			if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+		}
+	}
+
+
+	/*
+	 * Slave ready interrupt, it is only meaningful for master mode.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
+		StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
+	}
+
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0 ) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * Arbitration lost interrupt
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) {
+		StatusEvent |= XIICPS_EVENT_ARB_LOST;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
+			XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK |
+			XIICPS_IXR_RX_OVR_MASK))) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if (StatusEvent != 0U) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+
+}
+
+/*****************************************************************************/
+/*
+* This function prepares a device to transfers as a master.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @param	Role specifies whether the device is sending or receiving.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if bus is busy.
+*
+* @note		Interrupts are always disabled, device which needs to use
+*		interrupts needs to setup interrupts after this call.
+*
+****************************************************************************/
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+	u32 EnabledIntr = 0x0U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
+
+
+	/*
+	 * Only check if bus is busy when repeated start option is not set.
+	 */
+	if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
+		if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
+			(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
+
+	if (Role == RECVING_ROLE) {
+		ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
+		EnabledIntr = (u32)XIICPS_IXR_DATA_MASK |(u32)XIICPS_IXR_RX_OVR_MASK;
+	}else {
+		ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+	}
+	EnabledIntr |= (u32)XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_ARB_LOST_MASK;
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+* This function handles continuation of sending data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+static void MasterSendData(XIicPs *InstancePtr)
+{
+	(void)TransmitFifoFill(InstancePtr);
+
+	/*
+	 * Clear hold bit if done, so stop can be sent out.
+	 */
+	if (InstancePtr->SendByteCount == 0) {
+
+		/*
+		 * If user has enabled repeated start as an option,
+		 * do not disable it.
+		 */
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+
+			XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
+		}
+	}
+
+	return;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_options.c
new file mode 100644
index 000000000..a26bacac9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_options.c
@@ -0,0 +1,493 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_options.c
+*
+* Contains functions for the configuration of the XIccPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error.
+*			 This is a fix for CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk	10/07/14 Repeated start feature removed.
+* 3.0	sk	12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+		u32 Option;
+		u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+		{XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
+		{XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
+};
+
+#define XIICPS_NUM_OPTIONS      (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the IIC device driver. The options control
+* how the device behaves relative to the IIC bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is requested, set the flag.
+	 * The hold bit in CR will be written by driver when the next transfer
+	 * is initiated.
+	 */
+	if ((OptionsVar & XIICPS_REP_START_OPTION) != 0U ) {
+		InstancePtr->IsRepeatedStart = 1;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table, turning the option on.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so turning it on means
+			 * turning 7-bit option off.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			} else {
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+	/*
+	 * Now write to the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears the options for the IIC device driver. The options
+* control how the device behaves relative to the IIC bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be cleared. This is a
+*		bit mask where a 1 means to turn the option off. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is cleared, set the flag.
+	 * The hold bit in CR will be cleared by driver when the
+	 * following transfer ends.
+	 */
+	if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
+		InstancePtr->IsRepeatedStart = 0;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table and clear the specified options.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so clearing it means turning
+			 * 7-bit option on.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			} else {
+
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the IIC device. The options control how
+* the device behaves relative to the IIC bus.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	32 bit mask of the options, where a 1 means the option is on,
+*		and a 0 means to the option is off. One or more bit values may
+*		be contained in the mask. See the bit definitions named
+* 		XIICPS_*_OPTION in the file xiicps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetOptions(XIicPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 ControlReg;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read control register to find which options are currently set.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to determine which options are set.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+		if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
+			OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
+		}
+	}
+
+	if (InstancePtr->IsRepeatedStart != 0 ) {
+		OptionsFlag |= XIICPS_REP_START_OPTION;
+	}
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+* See the hardware data sheet for a full explanation of setting the serial
+* clock rate.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	FsclHz is the clock frequency in Hz. The two most common clock
+*		rates are 100KHz and 400KHz.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*		- XST_FAILURE if the Fscl frequency can not be set.
+*
+* @note		The clock can not be faster than the input clock divide by 22.
+*
+******************************************************************************/
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
+{
+	u32 Div_a;
+	u32 Div_b;
+	u32 ActualFscl;
+	u32 Temp;
+	u32 TempLimit;
+	u32 LastError;
+	u32 BestError;
+	u32 CurrentError;
+	u32 ControlReg;
+	u32 CalcDivA;
+	u32 CalcDivB;
+	u32 BestDivA = 0;
+	u32 BestDivB = 0;
+	u32 FsclHzVar = FsclHz;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FsclHzVar > 0U);
+
+	if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
+					XIICPS_TRANS_SIZE_OFFSET)) {
+		return (s32)XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
+	 */
+	Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
+
+	/*
+	 * If the answer is negative or 0, the Fscl input is out of range.
+	 */
+	if ((u32)(0U) == Temp) {
+		return (s32)XST_FAILURE;
+	}
+
+	/*
+	 * If frequency 400KHz is selected, 384.6KHz should be set.
+	 * If frequency 100KHz is selected, 90KHz should be set.
+	 * This is due to a hardware limitation.
+	 */
+	if(FsclHzVar > 384600U) {
+		FsclHzVar = 384600U;
+	}
+
+	if((FsclHzVar <= 100000U) && (FsclHzVar > 90000U)) {
+		FsclHzVar = 90000U;
+	}
+
+	/*
+	 * TempLimit helps in iterating over the consecutive value of Temp to
+	 * find the closest clock rate achievable with divisors.
+	 * Iterate over the next value only if fractional part is involved.
+	 */
+	TempLimit = (((InstancePtr->Config.InputClockHz) %
+			((u32)22 * FsclHzVar)) != 	(u32)0x0U) ?
+						Temp + (u32)1U : Temp;
+	BestError = FsclHzVar;
+
+	BestDivA = 0U;
+	BestDivB = 0U;
+	for ( ; Temp <= TempLimit ; Temp++)
+	{
+		LastError = FsclHzVar;
+		CalcDivA = 0U;
+		CalcDivB = 0U;
+
+		for (Div_b = 0U; Div_b < 64U; Div_b++) {
+
+			Div_a = Temp / (Div_b + 1U);
+
+			if (Div_a != 0U){
+				Div_a = Div_a - (u32)1U;
+			}
+			if (Div_a > 3U){
+				continue;
+			}
+			ActualFscl = (InstancePtr->Config.InputClockHz) /
+						(22U * (Div_a + 1U) * (Div_b + 1U));
+
+			if (ActualFscl > FsclHzVar){
+				CurrentError = (ActualFscl - FsclHzVar);}
+			else{
+				CurrentError = (FsclHzVar - ActualFscl);}
+
+			if (LastError > CurrentError) {
+				CalcDivA = Div_a;
+				CalcDivB = Div_b;
+				LastError = CurrentError;
+			}
+		}
+
+		/*
+		 * Used to capture the best divisors.
+		 */
+		if (LastError < BestError) {
+			BestError = LastError;
+			BestDivA = CalcDivA;
+			BestDivB = CalcDivB;
+		}
+	}
+
+
+	/*
+	 * Read the control register and mask the Divisors.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  (u32)XIICPS_CR_OFFSET);
+	ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
+	ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
+		(BestDivB << XIICPS_CR_DIV_B_SHIFT);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	The value of the IIC clock to the nearest Hz based on the
+*		control register settings. The actual value may not be exact to
+*		to integer math rounding errors.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetSClk(XIicPs *InstancePtr)
+{
+	u32 ControlReg;
+	u32 ActualFscl;
+	u32 Div_a;
+	u32 Div_b;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XIICPS_CR_OFFSET);
+
+	Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
+	Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
+
+	ActualFscl = (InstancePtr->Config.InputClockHz) /
+		(22U * (Div_a + 1U) * (Div_b + 1U));
+
+	return ActualFscl;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_selftest.c
new file mode 100644
index 000000000..0a3cf27e6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_selftest.c
@@ -0,0 +1,129 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_selftest.c
+*
+* This component contains the implementation of selftest functions for the
+* XIicPs driver component.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.00a sdm    09/22/11 Removed unused code
+* 3.0	sk	   11/03/14 Removed TimeOut Register value check
+*			   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+#define REG_TEST_VALUE    0x00000005U
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SelfTest(XIicPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the IIC registers should be in their default state right now.
+	 */
+	if ((XIICPS_CR_RESET_VALUE !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_CR_OFFSET)) ||
+		(XIICPS_IXR_ALL_INTR_MASK !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_IMR_OFFSET))) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Write, Read then write a register
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
+
+	if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XIICPS_SLV_PAUSE_OFFSET)) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, 0U);
+
+	XIicPs_Reset(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_sinit.c
new file mode 100644
index 000000000..726694062
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_sinit.c
+*
+* The implementation of the XIicPs component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 3.00	sk	   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return	A pointer to the configuration found or NULL if the specified
+*		device ID was not found. See xiicps.h for the definition of
+*		XIicPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
+{
+	XIicPs_Config *CfgPtr = NULL;
+	s32 Index;
+
+	for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
+		if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIicPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XIicPs_Config *)CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_slave.c
new file mode 100644
index 000000000..e1551a7a5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_0/src/xiicps_slave.c
@@ -0,0 +1,587 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xiicps_slave.c
+*
+* Handles slave transfers
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --  -------- ---------------------------------------------
+* 1.00a jz  01/30/10 First release
+* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
+* 3.00	sk	01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 SlaveRecvData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function sets up the device to be a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note
+*	Interrupt is always enabled no matter the tranfer is interrupt-
+*	driven or polled mode. Whether device will be interrupted or not
+*	depends on whether the device is connected to an interrupt
+*	controller and interrupt for the device is enabled.
+*
+****************************************************************************/
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
+	ControlReg |= (u32)XIICPS_CR_NEA_MASK;
+	ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven send. It set the repeated
+* start for the device is the tranfer size is larger than FIFO depth.
+* Data processing for the send is initiated by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(BaseAddr,
+			(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+			(u32)XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK |
+			(u32)XIICPS_IXR_TX_OVR_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven receive.
+* Data processing for the receive is handled by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return	None.
+*
+* @note		This routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
+		(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_RX_UNF_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+* This function sends  a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if master sends us data or master terminates the
+*		transfer before all data has sent out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Tmp;
+	s32 BytesToSend;
+	s32 Error = 0;
+	s32 Status = (s32)XST_SUCCESS;
+	u32 Value;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	/*
+	 * Use RXRW bit in status register to wait master to start a read.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0U) &&
+				((!Error) != 0)) {
+
+		/*
+		 * If master tries to send us data, it is an error.
+		 */
+		if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
+			Error = 1;
+		}
+
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	}
+
+	if (Error != 0) {
+		Status = (s32)XST_FAILURE;
+	} else {
+
+		/*
+		 * Clear the interrupt status register.
+		 */
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+		/*
+		 * Send data as long as there is more data to send and
+		 * there are no errors.
+		 */
+		Value = (InstancePtr->SendByteCount > (s32)0) &&
+						((!Error) != 0);
+		while (Value != (u32)0x00U) {
+
+			/*
+			 * Find out how many can be sent.
+			 */
+			BytesToSend = InstancePtr->SendByteCount;
+			if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
+				BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
+			}
+
+			for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
+				XIicPs_SendByte(InstancePtr);
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * Wait for master to read the data out of fifo.
+			 */
+			while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
+							((!Error) != 0)) {
+
+				/*
+				 * If master terminates the transfer before all data is
+				 * sent, it is an error.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_ISR_OFFSET);
+				if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
+					Error = 1;
+				}
+
+				/* Clear ISR.
+				 */
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+							IntrStatusReg);
+
+				StatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_SR_OFFSET);
+			}
+			Value = (InstancePtr->SendByteCount > (s32)0U) &&
+							((!Error) != 0);
+		}
+	}
+	if (Error != 0) {
+	Status = (s32)XST_FAILURE;
+	}
+
+	return Status;
+}
+/*****************************************************************************/
+/**
+* This function receives a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Count;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	/*
+	 * Clear the interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Clear the status register.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	Count = InstancePtr->RecvByteCount;
+	while (Count > (s32)0) {
+
+		/* Wait for master to put data */
+		while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
+		    StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * If master terminates the transfer before we get all
+			 * the data or the master tries to read from us,
+			 * it is an error.
+			 */
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_ISR_OFFSET);
+			if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
+					XIICPS_IXR_COMP_MASK))!=0x0U) &&
+				((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
+				((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+
+				return (s32)XST_FAILURE;
+			}
+
+			/*
+			 * Clear the interrupt status register.
+			 */
+			XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+			IntrStatusReg);
+		}
+
+		/*
+		 * Read all data from FIFO.
+		 */
+		while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			 ((InstancePtr->RecvByteCount > 0) != 0x0U)){
+
+			XIicPs_RecvByte(InstancePtr);
+
+			StatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_SR_OFFSET);
+		}
+		Count = InstancePtr->RecvByteCount;
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for slave mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper
+* handling.
+*
+* 
+*
+* The interrupts that are handled are:
+* - DATA
+*	If the instance is sending, it means that the master wants to read more
+*	data from us. Send more data, and check whether we are done with this
+*	send.
+*
+*	If the instance is receiving, it means that the master has writen
+* 	more data to us. Receive more data, and check whether we are done with
+*	with this receive.
+*
+* - COMP
+*	This marks that stop sequence has been sent from the master, transfer
+*	is about to terminate. However, for receiving, the master may have
+*	written us some data, so receive that first.
+*
+*	It is an error if the amount of transfered data is less than expected.
+*
+* - NAK
+*	This marks that master does not want our data. It is for send only.
+*
+* - Other interrupts
+*	These interrupts are marked as error.
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 IsSend = 0U;
+	u32 StatusEvent = 0U;
+	s32 LeftOver;
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are missed
+	 * while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
+
+	/*
+	 * Determine whether the device is sending.
+	 */
+	if (InstancePtr->RecvBufferPtr == NULL) {
+		IsSend = 1U;
+	}
+
+	/* Data interrupt
+	 *
+	 * This means master wants to do more data transfers.
+	 * Also check for completion of transfer, signal upper layer if done.
+	 */
+	if ((u32)0U != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
+		if (IsSend != 0x0U) {
+			LeftOver = TransmitFifoFill(InstancePtr);
+				/*
+				 * We may finish send here
+				 */
+				if (LeftOver == 0) {
+					StatusEvent |=
+						XIICPS_EVENT_COMPLETE_SEND;
+				}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+
+			/* We may finish the receive here */
+			if (LeftOver == 0) {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Complete interrupt.
+	 *
+	 * In slave mode, it means the master has done with this transfer, so
+	 * we signal the application using completion event.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
+		if (IsSend != 0x0U) {
+			if (InstancePtr->SendByteCount > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			}else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+			}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+			if (LeftOver > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			} else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Nack interrupt, pass this information to application.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
+				XIICPS_IXR_RX_UNF_MASK |
+				XIICPS_IXR_TX_OVR_MASK |
+				XIICPS_IXR_RX_OVR_MASK))){
+
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if (0U != StatusEvent) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This function handles continuation of receiving data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes still expected by the instance.
+*
+* @note		None.
+*
+****************************************************************************/
+static s32 SlaveRecvData(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	u32 BaseAddr;
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+		XIicPs_RecvByte(InstancePtr);
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	}
+
+	return InstancePtr->RecvByteCount;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/Makefile
new file mode 100644
index 000000000..3e1fc71f7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xipipsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ipipsu"
+
+xipipsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xipipsu_includes
+
+xipipsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu.c
new file mode 100644
index 000000000..42ea2b583
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu.c
@@ -0,0 +1,347 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xipipsu.c
+*
+* This file contains the implementation of the interface functions for XIpiPsu
+* driver. Refer to the header file xipipsu.h for more detailed information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who	Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	mjr	03/15/15	First Release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xipipsu.h"
+#include "xipipsu_hw.h"
+
+/****************************************************************************/
+/**
+ * Initialize the Instance pointer based on a given Config Pointer
+ *
+ * @param	InstancePtr is a pointer to the instance to be worked on
+ * @param	CfgPtr is the device configuration structure containing required
+ *		  	hardware build data
+ * @param	EffectiveAddress is the base address of the device. If address
+ *        	translation is not utilized, this parameter can be passed in using
+ *        	CfgPtr->Config.BaseAddress to specify the physical base address.
+ * @return	XST_SUCCESS if initialization was successful
+ * 			XST_FAILURE in case of failure
+ *
+ */
+
+XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
+		UINTPTR EffectiveAddress)
+{
+	u32 Index;
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr != NULL);
+	/* Set device base address and ID */
+	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddress;
+	InstancePtr->Config.BitMask = CfgPtr->BitMask;
+	InstancePtr->Config.IntId = CfgPtr->IntId;
+
+	InstancePtr->Config.TargetCount = CfgPtr->TargetCount;
+
+	for (Index = 0; Index < CfgPtr->TargetCount; Index++) {
+		InstancePtr->Config.TargetList[Index].Mask =
+				CfgPtr->TargetList[Index].Mask;
+		InstancePtr->Config.TargetList[Index].BufferIndex =
+				CfgPtr->TargetList[Index].BufferIndex;
+	}
+
+	/* Mark the component as Ready */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	return (XST_SUCCESS);
+}
+
+/**
+ * @brief	Reset the given IPI register set.
+ *        	This function can be called to disable the IPIs from all
+ *        	the sources and clear any pending IPIs in status register
+ *
+ * @param 	InstancePtr is the pointer to current IPI instance
+ *
+ */
+
+void XIpiPsu_Reset(XIpiPsu *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/**************Disable***************/
+
+	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_IDR_OFFSET,
+			XIPIPSU_ALL_MASK);
+
+	/**************Clear***************/
+	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_ISR_OFFSET,
+			XIPIPSU_ALL_MASK);
+
+}
+
+/**
+ * @brief	Trigger an IPI to a Destination CPU
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	DestCpuMask is the Mask of the CPU to which IPI is to be triggered
+ *
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if an error occurred
+ */
+
+XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Trigger an IPI to the Target */
+	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_TRIG_OFFSET,
+			DestCpuMask);
+	return XST_SUCCESS;
+
+}
+
+/**
+ * @brief Poll for an acknowledgement using Observation Register
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	DestCpuMask is the Mask of the destination CPU from which ACK is expected
+ * @param	TimeOutCount is the Count after which the routines returns failure
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if a timeout occurred
+ */
+
+XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
+		u32 TimeOutCount)
+{
+	u32 Flag, PollCount;
+	XStatus Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PollCount = 0;
+	/* Poll the OBS register until the corresponding DestCpu bit is cleared */
+	do {
+		Flag = (XIpiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XIPIPSU_OBS_OFFSET)) & (DestCpuMask);
+		PollCount++;
+		/* Check if the IPI was Acknowledged by the Target or we Timed Out*/
+	} while ((0x00000000U != Flag) && (PollCount < TimeOutCount));
+
+	if (PollCount >= TimeOutCount) {
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/**
+ * @brief	Get the Buffer Index for a CPU specified by Mask
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	CpuMask is the Mask of the CPU form which Index is required
+ *
+ * @return	Buffer Index value if CPU Mask is valid
+ * 			XIPIPSU_MAX_BUFF_INDEX+1 if not valid
+ *
+ * @note	Static function used only by XIpiPsu_GetBufferAddress
+ *
+ */
+static u32 XIpiPsu_GetBufferIndex(XIpiPsu *InstancePtr, u32 CpuMask)
+{
+	u32 BufferIndex;
+	u32 Index;
+	/* Init Index with an invalid value */
+	BufferIndex = XIPIPSU_MAX_BUFF_INDEX + 1;
+
+	/*Search for CPU in the List */
+	for (Index = 0; Index < InstancePtr->Config.TargetCount; Index++) {
+		/*If we find the CPU , then set the Index and break the loop*/
+		if (InstancePtr->Config.TargetList[Index].Mask == CpuMask) {
+			BufferIndex = InstancePtr->Config.TargetList[Index].BufferIndex;
+			break;
+		}
+	}
+
+	/* Return the Index */
+	return BufferIndex;
+}
+
+/**
+ * @brief	Get the Buffer Address for a given pair of CPUs
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	SrcCpuMask is the Mask for Source CPU
+ * @param	DestCpuMask is the Mask for Destination CPU
+ * @param	BufferType is either XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP
+ *
+ * @return	Valid Buffer Address if no error
+ * 			NULL if an error occurred in calculating Address
+ *
+ */
+
+static u32* XIpiPsu_GetBufferAddress(XIpiPsu *InstancePtr, u32 SrcCpuMask,
+		u32 DestCpuMask, u32 BufferType)
+{
+#ifdef __aarch64__
+	u64 BufferAddr;
+#else
+	u32 BufferAddr;
+#endif
+
+	u32 SrcIndex;
+	u32 DestIndex;
+	/* Get the buffer indices */
+	SrcIndex = XIpiPsu_GetBufferIndex(InstancePtr, SrcCpuMask);
+	DestIndex = XIpiPsu_GetBufferIndex(InstancePtr, DestCpuMask);
+
+	/* If we got an invalid buffer index, then return NULL pointer, else valid address */
+	if ((SrcIndex > XIPIPSU_MAX_BUFF_INDEX)
+			|| (DestIndex > XIPIPSU_MAX_BUFF_INDEX)) {
+		BufferAddr = 0U;
+	} else {
+
+		if (XIPIPSU_BUF_TYPE_MSG == BufferType) {
+			BufferAddr = XIPIPSU_MSG_RAM_BASE
+					+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
+					+ (DestIndex * XIPIPSU_BUFFER_OFFSET_TARGET);
+		} else if (XIPIPSU_BUF_TYPE_RESP == BufferType) {
+			BufferAddr = XIPIPSU_MSG_RAM_BASE
+					+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
+					+ (DestIndex * XIPIPSU_BUFFER_OFFSET_TARGET)
+					+ (XIPIPSU_BUFFER_OFFSET_RESPONSE);
+		} else {
+			BufferAddr = 0U;
+		}
+
+	}
+
+	return (u32 *) BufferAddr;
+}
+
+/**
+ * @brief	Read an Incoming Message from a Source
+ *
+ * @param 	InstancePtr is the pointer to current IPI instance
+ * @param 	SrcCpuMask is the Device Mask for the CPU which has sent the message
+ * @param 	MsgPtr is the pointer to Buffer to which the read message needs to be stored
+ * @param 	MsgLength is the length of the buffer/message
+ * @param 	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if an error occurred
+ */
+
+XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufferType)
+{
+	u32 *BufferPtr;
+	u32 Index;
+	u32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
+
+	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr, TargetMask,
+			InstancePtr->Config.BitMask, BufferType);
+	if (BufferPtr != NULL) {
+		/* Copy the IPI Buffer contents into Users's Buffer*/
+		for (Index = 0; Index < MsgLength; Index++) {
+			MsgPtr[Index] = BufferPtr[Index];
+		}
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	return Status;
+}
+
+
+/**
+ * @brief	Send a Message to Destination
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	DestCpuMask is the Device Mask for the destination CPU
+ * @param	MsgPtr is the pointer to Buffer which contains the message to be sent
+ * @param	MsgLength is the length of the buffer/message
+ * @param	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if an error occurred
+ */
+
+XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufferType)
+{
+	u32 *BufferPtr;
+	u32 Index;
+	u32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
+
+	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr,
+			InstancePtr->Config.BitMask, TargetMask, BufferType);
+	if (BufferPtr != NULL) {
+		/* Copy the Message to IPI Buffer */
+		for (Index = 0; Index < MsgLength; Index++) {
+			BufferPtr[Index] = MsgPtr[Index];
+		}
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu.h
new file mode 100644
index 000000000..81edd534d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu.h
@@ -0,0 +1,277 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ * @file xipipsu.h
+ *
+ * This is the header file for implementation of IPIPSU driver.
+ * Inter Processor Interrupt (IPI) is used for communication between
+ * different processors on ZynqMP SoC. Each IPI register set has Trigger, Status
+ * and Observation registers for communication between processors. Each IPI path
+ * has a 32 byte buffer associated with it and these buffers are located in the
+ * XPPU RAM. This driver supports the following operations:
+ *
+ * - Trigger IPIs to CPUs on the SoC
+ * - Write and Read Message buffers
+ * - Read the status of Observation Register to get status of Triggered IPI
+ * - Enable/Disable IPIs from selected Masters
+ * - Read the Status register to get the source of an incoming IPI
+ *
+ * Initialization
+ * The config data for the driver is loaded and is based on the HW build. The
+ * XIpiPsu_Config data structure contains all the data related to the
+ * IPI driver instance and also teh available Target CPUs.
+ *
+ * Sending an IPI
+ * The following steps can be followed to send an IPI:
+ * - Write the Message into Message Buffer using XIpiPsu_WriteMessage()
+ * - Trigger IPI using XIpiPsu_TriggerIpi()
+ * - Wait for Ack using XIpiPsu_PollForAck()
+ * - Read response using XIpiPsu_ReadMessage()
+ *
+ * @note	XIpiPsu_GetObsStatus() before sending an IPI to ensure that the
+ * previous IPI was serviced by the target
+ *
+ * Receiving an IPI
+ * To receive an IPI, the following sequence can be followed:
+ * - Register an interrupt handler for the IPIs interrupt ID
+ * - Enable the required sources using XIpiPsu_InterruptEnable()
+ * - In the interrupt handler, Check for source using XIpiPsu_GetInterruptStatus
+ * - Read the message form source using XIpiPsu_ReadMessage()
+ * - Write the response using XIpiPsu_WriteMessage()
+ * - Ack the IPI using XIpiPsu_ClearInterruptStatus()
+ *
+ * @note	XIpiPsu_Reset can be used at startup to clear the status and
+ * disable all sources
+ *
+ */
+/*****************************************************************************/
+#ifndef XIPIPSU_H_
+#define XIPIPSU_H_
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xstatus.h"
+#include "xipipsu_hw.h"
+
+/************************** Constant Definitions *****************************/
+#define XIPIPSU_BUF_TYPE_MSG	(0x00000001U)
+#define XIPIPSU_BUF_TYPE_RESP	(0x00000002U)
+#define XIPIPSU_MAX_MSG_LEN		XIPIPSU_MSG_BUF_SIZE
+/**************************** Type Definitions *******************************/
+/**
+ * Data structure used to refer IPI Targets
+ */
+typedef struct {
+	u32 Mask; /**< Bit Mask for the target */
+	u32 BufferIndex; /**< Buffer Index used for calculating buffer address */
+} XIpiPsu_Target;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u32 DeviceId; /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of the device */
+	u32 BitMask; /**< BitMask to be used to identify this CPU */
+	u32 BufferIndex; /**< Index of the IPI Message Buffer */
+	u32 IntId; /**< Interrupt ID on GIC **/
+	u32 TargetCount; /**< Number of available IPI Targets */
+	XIpiPsu_Target TargetList[XIPIPSU_MAX_TARGETS] ; /** < List of IPI Targets */
+} XIpiPsu_Config;
+
+/**
+ * The XIpiPsu driver instance data. The user is required to allocate a
+ * variable of this type for each IPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIpiPsu_Config Config; /**< Configuration structure */
+	u32 IsReady; /**< Device is initialized and ready */
+	u32 Options; /**< Options set in the device */
+} XIpiPsu;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/**
+*
+* Read the register specified by the base address and offset
+*
+* @param	BaseAddress is the base address of the IPI instance
+* @param	RegOffset is the offset of the register relative to base
+*
+* @return	Value of the specified register
+* @note
+* C-style signature
+*	u32 XIpiPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+
+#define XIpiPsu_ReadReg(BaseAddress, RegOffset) \
+		Xil_In32((BaseAddress) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write a value into a register specified by base address and offset
+*
+* @param BaseAddress is the base address of the IPI instance
+* @param RegOffset is the offset of the register relative to base
+* @param Data is a 32-bit value that is to be written into the specified register
+*
+* @note
+* C-style signature
+*	void XIpiPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+
+#define XIpiPsu_WriteReg(BaseAddress, RegOffset, Data) \
+		Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Mask contains a bit mask of interrupts to enable. The mask can
+*			be formed using a set of bitwise or'd values of individual CPU masks
+*
+* @note
+* C-style signature
+*	void XIpiPsu_InterruptEnable(XIpiPsu *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XIpiPsu_InterruptEnable(InstancePtr, Mask) \
+	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_IER_OFFSET, \
+		((Mask) & XIPIPSU_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be disabled.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Mask contains a bit mask of interrupts to disable. The mask can
+*			be formed using a set of bitwise or'd values of individual CPU masks
+*
+* @note
+* C-style signature
+*	void XIpiPsu_InterruptDisable(XIpiPsu *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XIpiPsu_InterruptDisable(InstancePtr, Mask)  \
+	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_IDR_OFFSET, \
+		((Mask) & XIPIPSU_ALL_MASK));
+/****************************************************************************/
+/**
+*
+* Get the STATUS REGISTER of the current IPI instance.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @return Returns the Interrupt Status register(ISR) contents
+* @note User needs to parse this 32-bit value to check the source CPU
+* C-style signature
+*	u32 XIpiPsu_GetInterruptStatus(XIpiPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XIpiPsu_GetInterruptStatus(InstancePtr)  \
+	XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_ISR_OFFSET)
+/****************************************************************************/
+/**
+*
+* Clear the STATUS REGISTER of the current IPI instance.
+* The corresponding interrupt status for
+* each bit set to 1 in Mask, will be cleared
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask corresponding to the source CPU*
+*
+* @note This function should be used after handling the IPI.
+* Clearing the status will automatically clear the corresponding bit in
+* OBSERVATION register of Source CPU
+* C-style signature
+*	void XIpiPsu_ClearInterruptStatus(XIpiPsu *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+
+#define XIpiPsu_ClearInterruptStatus(InstancePtr, Mask)  \
+	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_ISR_OFFSET, \
+		((Mask) & XIPIPSU_ALL_MASK));
+/****************************************************************************/
+/**
+*
+* Get the OBSERVATION REGISTER of the current IPI instance.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @return	Returns the Observation register(OBS) contents
+* @note		User needs to parse this 32-bit value to check the status of
+*			individual CPUs
+* C-style signature
+*	u32 XIpiPsu_GetObsStatus(XIpiPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XIpiPsu_GetObsStatus(InstancePtr)  \
+	XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_OBS_OFFSET)
+/****************************************************************************/
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xipipsu_sinit.c */
+
+XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId);
+
+/* Interface Functions implemented in xipipsu.c */
+
+XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
+		UINTPTR EffectiveAddress);
+
+void XIpiPsu_Reset(XIpiPsu *InstancePtr);
+
+XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask);
+
+XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
+		u32 TimeOutCount);
+
+XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufType);
+
+XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufType);
+
+#endif /* XIPIPSU_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu_g.c
new file mode 100644
index 000000000..d4fc2eb2e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu_g.c
@@ -0,0 +1,105 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xipipsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIpiPsu_Config XIpiPsu_ConfigTable[] =
+{
+
+	{
+		XPAR_PSU_IPI_0_DEVICE_ID,
+		XPAR_PSU_IPI_0_BASE_ADDRESS,
+		XPAR_PSU_IPI_0_BIT_MASK,
+		XPAR_PSU_IPI_0_BUFFER_INDEX,
+		XPAR_PSU_IPI_0_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
+	}
+};
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu_hw.h
new file mode 100644
index 000000000..2f3fb0830
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu_hw.h
@@ -0,0 +1,76 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/**
+*
+* @file xipipsu_hw.h
+*
+* This file contains macro definitions for low level HW related params
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   mjr  03/15/15 First release
+*
+* 

+*
+******************************************************************************/
+#ifndef XIPIPSU_HW_H_	/* prevent circular inclusions */
+#define XIPIPSU_HW_H_	/* by using protection macros */
+
+/************************** Constant Definitions *****************************/
+/* Message RAM related params */
+#define XIPIPSU_MSG_RAM_BASE 0xFF990000U
+#define XIPIPSU_MSG_BUF_SIZE 8U	/* Size in Words */
+#define XIPIPSU_MAX_BUFF_INDEX	7
+
+/* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
+#define XIPIPSU_BUFFER_OFFSET_GROUP	(8U * 2U * 32U)
+#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U)
+#define XIPIPSU_BUFFER_OFFSET_RESPONSE		(32U)
+
+/* Max Number of IPI slots on the device */
+#define XIPIPSU_MAX_TARGETS	11
+
+/* Register Offsets for each member  of IPI Register Set */
+#define XIPIPSU_TRIG_OFFSET 0x00U
+#define XIPIPSU_OBS_OFFSET 0x04U
+#define XIPIPSU_ISR_OFFSET 0x10U
+#define XIPIPSU_IMR_OFFSET 0x14U
+#define XIPIPSU_IER_OFFSET 0x18U
+#define XIPIPSU_IDR_OFFSET 0x1CU
+
+/* MASK of all valid IPI bits in above registers */
+#define XIPIPSU_ALL_MASK	0x0F0F0301U
+
+#endif /* XIPIPSU_HW_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu_sinit.c
new file mode 100644
index 000000000..b09bf7b98
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v1_0/src/xipipsu_sinit.c
@@ -0,0 +1,87 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/**
+*
+* @file xipipsu_sinit.c
+*
+* The implementation of the XIpiPsu component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   mjr  03/15/15 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xparameters.h"
+#include "xipipsu.h"
+
+/************************** Variable Definitions *****************************/
+extern XIpiPsu_Config XIpiPsu_ConfigTable[];
+
+/*****************************************************************************/
+
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*			configuration for.
+*
+* @return	A pointer to the configuration found or NULL if the specified
+*			device ID was not found. See xipipsu.h for the definition of
+*			XIpiPsu_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId)
+{
+	XIpiPsu_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
+		if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIpiPsu_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/Makefile
new file mode 100644
index 000000000..2e3955048
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/Makefile
@@ -0,0 +1,83 @@
+#/******************************************************************************
+#*
+#* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+#*
+#* This file contains confidential and proprietary information  of Xilinx, Inc.
+#* and is protected under U.S. and  international copyright and other
+#* intellectual property  laws.
+#*
+#* DISCLAIMER
+#* This disclaimer is not a license and does not grant any  rights to the
+#* materials distributed herewith. Except as  otherwise provided in a valid
+#* license issued to you by  Xilinx, and to the maximum extent permitted by
+#* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL
+#* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS,
+#* IMPLIED, OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF
+#* MERCHANTABILITY, NON-  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+#* and
+#* (2) Xilinx shall not be liable (whether in contract or tort,  including
+#* negligence, or under any other theory of liability) for any loss or damage
+#* of any kind or nature  related to, arising under or in connection with these
+#* materials, including for any direct, or any indirect,  special, incidental,
+#* or consequential loss or damage  (including loss of data, profits,
+#* goodwill, or any type of  loss or damage suffered as a result of any
+#* action brought  by a third party) even if such damage or loss was
+#* reasonably foreseeable or Xilinx had been advised of the  possibility
+#* of the same.
+#*
+#* CRITICAL APPLICATIONS
+#* Xilinx products are not designed or intended to be fail-  safe, or for use
+#* in any application requiring fail-safe  performance, such as life-support
+#* or safety devices or  systems, Class III medical devices, nuclear
+#* facilities,  applications related to the deployment of airbags, or any
+#* other applications that could lead to death, personal  injury, or severe
+#* property or environmental damage  (individually and collectively,
+#* "Critical  Applications"). Customer assumes the sole risk and  liability
+#* of any use of Xilinx products in Critical  Applications, subject only to
+#* applicable laws and  regulations governing limitations on product liability.
+#*
+#* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS  PART
+#* OF THIS FILE AT ALL TIMES.
+#*
+#******************************************************************************/
+
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xuartps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling nandpsu"
+
+xuartps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xuartps_includes
+
+xuartps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandps_g.c
new file mode 100644
index 000000000..dd3a3d3fc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xnandpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XNandPsu_Config XNandPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_NAND_0_DEVICE_ID,
+		XPAR_PSU_NAND_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu.c
new file mode 100644
index 000000000..5c0346cc1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu.c
@@ -0,0 +1,4195 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu.c
+*
+* This file contains the implementation of the interface functions for
+* XNandPsu driver. Refer to the header file xnandpsu.h for more detailed
+* information.
+*
+* This module supports for NAND flash memory devices that conform to the
+* "Open NAND Flash Interface" (ONFI) 3.0 Specification. This modules
+* implements basic flash operations like read, write and erase.
+*
+* @note		Driver has been renamed to nandpsu after change in
+*		naming convention.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 2.0   sb     01/12/2015  Removed Null checks for Buffer passed
+*			   as parameter to Read API's
+*			   - XNandPsu_Read()
+*			   - XNandPsu_ReadPage
+*			   Modified
+*			   - XNandPsu_SetFeature()
+*			   - XNandPsu_GetFeature()
+*			   and made them public.
+*			   Removed Failure Return for BCF Error check in
+*			   XNandPsu_ReadPage() and added BCH_Error counter
+*			   in the instance pointer structure.
+* 			   Added XNandPsu_Prepare_Cmd API
+*			   Replaced
+*			   - XNandPsu_IntrStsEnable
+*			   - XNandPsu_IntrStsClear
+*			   - XNandPsu_IntrClear
+*			   - XNandPsu_SetProgramReg
+*			   with XNandPsu_WriteReg call
+*			   Modified xnandpsu.c file API's with above changes.
+*  			   Corrected the program command for Set Feature API.
+*			   Modified
+*			   - XNandPsu_OnfiReadStatus
+*			   - XNandPsu_GetFeature
+*			   - XNandPsu_SetFeature
+*			   to add support for DDR mode.
+*			   Changed Convention for SLC/MLC
+*			   SLC --> HAMMING
+*			   MLC --> BCH
+*			   SlcMlc --> IsBCH
+*			   Removed extra DMA mode initialization from
+*			   the XNandPsu_CfgInitialize API.
+*			   Modified
+*			   - XNandPsu_SetEccAddrSize
+*			   ECC address now is calculated based upon the
+*			   size of spare area
+*			   Modified Block Erase API, removed clearing of
+*			   packet register before erase.
+*			   Clearing Data Interface Register before
+*			   XNandPsu_OnfiReset call.
+*			   Modified XNandPsu_ChangeTimingMode API supporting
+*			   SDR and NVDDR interface for timing modes 0 to 5.
+*			   Modified Bbt Signature and Version Offset value for
+*			   Oob and No-Oob region.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xnandpsu.h"
+#include "xnandpsu_bbm.h"
+/************************** Constant Definitions *****************************/
+
+const XNandPsu_EccMatrix EccMatrix[] = {
+	/*
+	 * 512 byte page
+	 */
+	{XNANDPSU_PAGE_SIZE_512, 9U, 1U, XNANDPSU_HAMMING, 0x20DU, 0x3U},
+	{XNANDPSU_PAGE_SIZE_512, 9U, 4U, XNANDPSU_BCH, 0x209U, 0x7U},
+	{XNANDPSU_PAGE_SIZE_512, 9U, 8U, XNANDPSU_BCH, 0x203U, 0xDU},
+	/*
+	 * 2K byte page
+	 */
+	{XNANDPSU_PAGE_SIZE_2K, 9U, 1U, XNANDPSU_HAMMING, 0x834U, 0xCU},
+	{XNANDPSU_PAGE_SIZE_2K, 9U, 4U, XNANDPSU_BCH, 0x826U, 0x1AU},
+	{XNANDPSU_PAGE_SIZE_2K, 9U, 8U, XNANDPSU_BCH, 0x80cU, 0x34U},
+	{XNANDPSU_PAGE_SIZE_2K, 9U, 12U, XNANDPSU_BCH, 0x822U, 0x4EU},
+	{XNANDPSU_PAGE_SIZE_2K, 10U, 24U, XNANDPSU_BCH, 0x81cU, 0x54U},
+	/*
+	 * 4K byte page
+	 */
+	{XNANDPSU_PAGE_SIZE_4K, 9U, 1U, XNANDPSU_HAMMING, 0x1068U, 0x18U},
+	{XNANDPSU_PAGE_SIZE_4K, 9U, 4U, XNANDPSU_BCH, 0x104cU, 0x34U},
+	{XNANDPSU_PAGE_SIZE_4K, 9U, 8U, XNANDPSU_BCH, 0x1018U, 0x68U},
+	{XNANDPSU_PAGE_SIZE_4K, 9U, 12U, XNANDPSU_BCH, 0x1044U, 0x9CU},
+	{XNANDPSU_PAGE_SIZE_4K, 10U, 24U, XNANDPSU_BCH, 0x1038U, 0xA8U},
+	/*
+	 * 8K byte page
+	 */
+	{XNANDPSU_PAGE_SIZE_8K, 9U, 1U, XNANDPSU_HAMMING, 0x20d0U, 0x30U},
+	{XNANDPSU_PAGE_SIZE_8K, 9U, 4U, XNANDPSU_BCH, 0x2098U, 0x68U},
+	{XNANDPSU_PAGE_SIZE_8K, 9U, 8U, XNANDPSU_BCH, 0x2030U, 0xD0U},
+	{XNANDPSU_PAGE_SIZE_8K, 9U, 12U, XNANDPSU_BCH, 0x2088U, 0x138U},
+	{XNANDPSU_PAGE_SIZE_8K, 10U, 24U, XNANDPSU_BCH, 0x2070U, 0x150U},
+	/*
+	 * 16K byte page
+	 */
+	{XNANDPSU_PAGE_SIZE_16K, 9U, 1U, XNANDPSU_HAMMING, 0x4460U, 0x60U},
+	{XNANDPSU_PAGE_SIZE_16K, 9U, 4U, XNANDPSU_BCH, 0x43f0U, 0xD0U},
+	{XNANDPSU_PAGE_SIZE_16K, 9U, 8U, XNANDPSU_BCH, 0x4320U, 0x1A0U},
+	{XNANDPSU_PAGE_SIZE_16K, 9U, 12U, XNANDPSU_BCH, 0x4250U, 0x270U},
+	{XNANDPSU_PAGE_SIZE_16K, 10U, 24U, XNANDPSU_BCH, 0x4220U, 0x2A0U}
+};
+
+/**************************** Type Definitions *******************************/
+static u8 isQemuPlatform = 0U;
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr);
+
+static void XNandPsu_InitGeometry(XNandPsu *InstancePtr, OnfiParamPage *Param);
+
+static void XNandPsu_InitFeatures(XNandPsu *InstancePtr, OnfiParamPage *Param);
+
+static s32 XNandPsu_PollRegTimeout(XNandPsu *InstancePtr, u32 RegOffset,
+					u32 Mask, u32 Timeout);
+
+static void XNandPsu_SetPktSzCnt(XNandPsu *InstancePtr, u32 PktSize,
+						u32 PktCount);
+
+static void XNandPsu_SetPageColAddr(XNandPsu *InstancePtr, u32 Page, u16 Col);
+
+static void XNandPsu_SetPageSize(XNandPsu *InstancePtr);
+
+static void XNandPsu_SetBusWidth(XNandPsu *InstancePtr);
+
+static void XNandPsu_SelectChip(XNandPsu *InstancePtr, u32 Target);
+
+static s32 XNandPsu_OnfiReset(XNandPsu *InstancePtr, u32 Target);
+
+static s32 XNandPsu_OnfiReadStatus(XNandPsu *InstancePtr, u32 Target,
+							u16 *OnfiStatus);
+
+static s32 XNandPsu_OnfiReadId(XNandPsu *InstancePtr, u32 Target, u8 IdAddr,
+							u32 IdLen, u8 *Buf);
+
+static s32 XNandPsu_OnfiReadParamPage(XNandPsu *InstancePtr, u32 Target,
+						u8 *Buf);
+
+static s32 XNandPsu_ProgramPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
+							u32 Col, u8 *Buf);
+
+static s32 XNandPsu_ReadPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
+							u32 Col, u8 *Buf);
+
+static s32 XNandPsu_CheckOnDie(XNandPsu *InstancePtr, OnfiParamPage *Param);
+
+static void XNandPsu_SetEccAddrSize(XNandPsu *InstancePtr);
+
+static s32 XNandPsu_ChangeReadColumn(XNandPsu *InstancePtr, u32 Target,
+					u32 Col, u32 PktSize, u32 PktCount,
+					u8 *Buf);
+
+static s32 XNandPsu_ChangeWriteColumn(XNandPsu *InstancePtr, u32 Target,
+					u32 Col, u32 PktSize, u32 PktCount,
+					u8 *Buf);
+
+static s32 XNandPsu_InitExtEcc(XNandPsu *InstancePtr, OnfiExtPrmPage *ExtPrm);
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XNandPsu instance. This function must
+* be called prior to using the NAND flash device to read or write any data.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	ConfigPtr points to XNandPsu device configuration structure.
+* @param	EffectiveAddr is the base address of NAND flash controller.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		The user needs to first call the XNandPsu_LookupConfig() API
+*		which returns the Configuration structure pointer which is
+*		passed as a parameter to the XNandPsu_CfgInitialize() API.
+*
+******************************************************************************/
+s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status = XST_FAILURE;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Initialize InstancePtr Config structure
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	/*
+	 * Operate in Polling Mode
+	 */
+	InstancePtr->Mode = XNANDPSU_POLLING;
+	/*
+	 * Enable MDMA mode by default
+	 */
+	InstancePtr->DmaMode = XNANDPSU_MDMA;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Temporary hack for disabling the ecc on qemu as currently there
+	 * is no support in the utility for writing images with ecc enabled.
+	 */
+	#define CSU_VER_REG 0xFFCA0044U
+	#define CSU_VER_PLATFORM_MASK 0xF000U
+	#define CSU_VER_PLATFORM_QEMU_VAL 0x3000U
+	if ((*(u32 *)CSU_VER_REG & CSU_VER_PLATFORM_MASK) ==
+					CSU_VER_PLATFORM_QEMU_VAL) {
+		isQemuPlatform = 1U;
+	}
+	/*
+	 * Initialize the NAND flash targets
+	 */
+	Status = XNandPsu_FlashInit(InstancePtr);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Flash init failed\r\n",__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Set ECC mode
+	 */
+	if (InstancePtr->Features.EzNand != 0U) {
+		InstancePtr->EccMode = XNANDPSU_EZNAND;
+	} else if (InstancePtr->Features.OnDie != 0U) {
+		InstancePtr->EccMode = XNANDPSU_ONDIE;
+	} else {
+		InstancePtr->EccMode = XNANDPSU_HWECC;
+	}
+
+	if (isQemuPlatform != 0U) {
+		InstancePtr->EccMode = XNANDPSU_NONE;
+		goto Out;
+	}
+
+	/*
+	 * Initialize Ecc Error flip counters
+	 */
+	 InstancePtr->Ecc_Stat_PerPage_flips = 0U;
+	 InstancePtr->Ecc_Stats_total_flips = 0U;
+
+	/*
+	 * Scan for the bad block table(bbt) stored in the flash & load it in
+	 * memory(RAM).  If bbt is not found, create bbt by scanning factory
+	 * marked bad blocks and store it in last good blocks of flash.
+	 */
+	XNandPsu_InitBbtDesc(InstancePtr);
+	Status = XNandPsu_ScanBbt(InstancePtr);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: BBT scan failed\r\n",__func__);
+#endif
+		goto Out;
+	}
+
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the NAND flash and gets the geometry information.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr)
+{
+	u32 Target;
+	u8 Id[ONFI_SIG_LEN] = {0U};
+	OnfiParamPage Param = {0U};
+	s32 Status = XST_FAILURE;
+	u32 Index;
+	u32 Crc;
+	u32 PrmPgOff;
+	u32 PrmPgLen;
+	OnfiExtPrmPage ExtParam __attribute__ ((aligned(64)));
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Clear Data Interface Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_DATA_INTF_OFFSET, 0U);
+
+	/* Clear DMA Buffer Boundary Register */
+	XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XNANDPSU_DMA_BUF_BND_OFFSET, 0U);
+
+	for (Target = 0U; Target < XNANDPSU_MAX_TARGETS; Target++) {
+		/*
+		 * Reset the Target
+		 */
+		Status = XNandPsu_OnfiReset(InstancePtr, Target);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+		/*
+		 * Read ONFI ID
+		 */
+		Status = XNandPsu_OnfiReadId(InstancePtr, Target,
+						ONFI_READ_ID_ADDR,
+						ONFI_SIG_LEN,
+						(u8 *)&Id[0]);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+
+		if (!IS_ONFI(Id)) {
+			if (Target == 0U) {
+#ifdef XNANDPSU_DEBUG
+				xil_printf("%s: ONFI ID doesn't match\r\n",
+								__func__);
+#endif
+				Status = XST_FAILURE;
+				goto Out;
+			}
+		}
+
+		/* Read Parameter Page */
+		for(Index = 0U; Index < ONFI_MND_PRM_PGS; Index++) {
+			if (Index == 0U) {
+				Status = XNandPsu_OnfiReadParamPage(InstancePtr,
+							Target, (u8 *)&Param);
+			} else {
+				PrmPgOff = Index * ONFI_PRM_PG_LEN;
+				PrmPgLen = ONFI_PRM_PG_LEN;
+				Status = XNandPsu_ChangeReadColumn(InstancePtr,
+							Target,PrmPgOff,
+							ONFI_PRM_PG_LEN, 1U,
+							(u8 *) &Param);
+			}
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+			/* Check CRC */
+			Crc = XNandPsu_OnfiParamPageCrc((u8*)&Param, 0U,
+								ONFI_CRC_LEN);
+			if (Crc != Param.Crc) {
+#ifdef XNANDPSU_DEBUG
+				xil_printf("%s: ONFI parameter page (%d) crc check failed\r\n",
+							__func__, Index);
+#endif
+				continue;
+			} else {
+				break;
+			}
+		}
+		if (Index >= ONFI_MND_PRM_PGS) {
+			Status = XST_FAILURE;
+			goto Out;
+		}
+		/* Fill Geometry for the first target */
+		if (Target == 0U) {
+			XNandPsu_InitGeometry(InstancePtr, &Param);
+			XNandPsu_InitFeatures(InstancePtr, &Param);
+			if ((!InstancePtr->Features.EzNand) != 0U) {
+				Status =XNandPsu_CheckOnDie(InstancePtr,&Param);
+				if (Status != XST_SUCCESS) {
+					InstancePtr->Features.OnDie = 0U;
+				}
+			}
+			if (isQemuPlatform != 0U) {
+				InstancePtr->Geometry.NumTargets++;
+				break;
+			}
+			if ((InstancePtr->Geometry.NumBitsECC == 0xFFU) &&
+				(InstancePtr->Features.ExtPrmPage != 0U)) {
+				/* ONFI 3.1 section 5.7.1.6 & 5.7.1.7 */
+				PrmPgLen = (u32)Param.ExtParamPageLen * 16U;
+					PrmPgOff = (u32)((u32)Param.NumOfParamPages *
+							ONFI_PRM_PG_LEN) +
+							(Index * (u32)PrmPgLen);
+					Status = XNandPsu_ChangeReadColumn(
+							InstancePtr,
+							Target,
+							PrmPgOff,
+							PrmPgLen, 1U,
+							(u8 *)(void *)&ExtParam);
+					if (Status != XST_SUCCESS) {
+						goto Out;
+					}
+					/*
+					 * Check CRC
+					 */
+					Crc = XNandPsu_OnfiParamPageCrc(
+							(u8 *)&ExtParam,
+							2U,
+							PrmPgLen);
+					if (Crc != ExtParam.Crc) {
+#ifdef XNANDPSU_DEBUG
+	xil_printf("%s: ONFI extended parameter page (%d) crc check failed\r\n",
+							__func__, Index);
+#endif
+						Status = XST_FAILURE;
+						goto Out;
+					}
+					/*
+					 * Initialize Extended ECC info
+					 */
+					Status = XNandPsu_InitExtEcc(
+							InstancePtr,
+							&ExtParam);
+					if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+	xil_printf("%s: Init extended ecc failed\r\n",__func__);
+#endif
+						goto Out;
+				}
+			}
+			/* Configure ECC settings */
+			XNandPsu_SetEccAddrSize(InstancePtr);
+		}
+		InstancePtr->Geometry.NumTargets++;
+	}
+	/*
+	 * Calculate total number of blocks and total size of flash
+	 */
+	InstancePtr->Geometry.NumPages = InstancePtr->Geometry.NumTargets *
+					InstancePtr->Geometry.NumTargetPages;
+	InstancePtr->Geometry.NumBlocks = InstancePtr->Geometry.NumTargets *
+					InstancePtr->Geometry.NumTargetBlocks;
+	InstancePtr->Geometry.DeviceSize =
+					(u64)InstancePtr->Geometry.NumTargets *
+					InstancePtr->Geometry.TargetSize;
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the geometry information from ONFI parameter page.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Param is pointer to the ONFI parameter page.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_InitGeometry(XNandPsu *InstancePtr, OnfiParamPage *Param)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertVoid(Param != NULL);
+
+	InstancePtr->Geometry.BytesPerPage = Param->BytesPerPage;
+	InstancePtr->Geometry.SpareBytesPerPage = Param->SpareBytesPerPage;
+	InstancePtr->Geometry.PagesPerBlock = Param->PagesPerBlock;
+	InstancePtr->Geometry.BlocksPerLun = Param->BlocksPerLun;
+	InstancePtr->Geometry.NumLuns = Param->NumLuns;
+	InstancePtr->Geometry.RowAddrCycles = Param->AddrCycles & 0xFU;
+	InstancePtr->Geometry.ColAddrCycles = (Param->AddrCycles >> 4U) & 0xFU;
+	InstancePtr->Geometry.NumBitsPerCell = Param->BitsPerCell;
+	InstancePtr->Geometry.NumBitsECC = Param->EccBits;
+	InstancePtr->Geometry.BlockSize = (Param->PagesPerBlock *
+						Param->BytesPerPage);
+	InstancePtr->Geometry.NumTargetBlocks = (Param->BlocksPerLun *
+						(u32)Param->NumLuns);
+	InstancePtr->Geometry.NumTargetPages = (Param->BlocksPerLun *
+						(u32)Param->NumLuns *
+						Param->PagesPerBlock);
+	InstancePtr->Geometry.TargetSize = ((u64)Param->BlocksPerLun *
+						(u64)Param->NumLuns *
+						(u64)Param->PagesPerBlock *
+						(u64)Param->BytesPerPage);
+	InstancePtr->Geometry.EccCodeWordSize = 9U; /* 2 power of 9 = 512 */
+
+#ifdef XNANDPSU_DEBUG
+	xil_printf("Manufacturer: %s\r\n", Param->DeviceManufacturer);
+	xil_printf("Device Model: %s\r\n", Param->DeviceModel);
+	xil_printf("Jedec ID: 0x%x\r\n", Param->JedecManufacturerId);
+	xil_printf("Bytes Per Page: 0x%x\r\n", Param->BytesPerPage);
+	xil_printf("Spare Bytes Per Page: 0x%x\r\n", Param->SpareBytesPerPage);
+	xil_printf("Pages Per Block: 0x%x\r\n", Param->PagesPerBlock);
+	xil_printf("Blocks Per LUN: 0x%x\r\n", Param->BlocksPerLun);
+	xil_printf("Number of LUNs: 0x%x\r\n", Param->NumLuns);
+	xil_printf("Number of bits per cell: 0x%x\r\n", Param->BitsPerCell);
+	xil_printf("Number of ECC bits: 0x%x\r\n", Param->EccBits);
+	xil_printf("Block Size: 0x%x\r\n", InstancePtr->Geometry.BlockSize);
+
+	xil_printf("Number of Target Blocks: 0x%x\r\n",
+					InstancePtr->Geometry.NumTargetBlocks);
+	xil_printf("Number of Target Pages: 0x%x\r\n",
+					InstancePtr->Geometry.NumTargetPages);
+
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the feature list from ONFI parameter page.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Param is pointer to ONFI parameter page buffer.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_InitFeatures(XNandPsu *InstancePtr, OnfiParamPage *Param)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertVoid(Param != NULL);
+
+	InstancePtr->Features.BusWidth = ((Param->Features & (1U << 0U)) != 0U) ?
+						XNANDPSU_BUS_WIDTH_16 :
+						XNANDPSU_BUS_WIDTH_8;
+	InstancePtr->Features.NvDdr = ((Param->Features & (1U << 5)) != 0U) ?
+								1U : 0U;
+	InstancePtr->Features.EzNand = ((Param->Features & (1U << 9)) != 0U) ?
+								1U : 0U;
+	InstancePtr->Features.ExtPrmPage = ((Param->Features & (1U << 7)) != 0U) ?
+								1U : 0U;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks if the flash supports on-die ECC.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Param is pointer to ONFI parameter page.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_CheckOnDie(XNandPsu *InstancePtr, OnfiParamPage *Param)
+{
+	s32 Status = XST_FAILURE;
+	u8 JedecId[2] = {0U};
+	u8 EccSetFeature[4] = {0x08U, 0x00U, 0x00U, 0x00U};
+	u8 EccGetFeature[4] ={0U};
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Param != NULL);
+
+	/*
+	 * Check if this flash supports On-Die ECC.
+	 * For more information, refer to Micron TN2945.
+	 * Micron Flash: MT29F1G08ABADA, MT29F1G08ABBDA
+	 *		 MT29F1G16ABBDA,
+	 *		 MT29F2G08ABBEA, MT29F2G16ABBEA,
+	 *		 MT29F2G08ABAEA, MT29F2G16ABAEA,
+	 *		 MT29F4G08ABBDA, MT29F4G16ABBDA,
+	 *		 MT29F4G08ABADA, MT29F4G16ABADA,
+	 *		 MT29F8G08ADBDA, MT29F8G16ADBDA,
+	 *		 MT29F8G08ADADA, MT29F8G16ADADA
+	 */
+
+	/*
+	 * Read JEDEC ID
+	 */
+	Status = XNandPsu_OnfiReadId(InstancePtr, 0U, 0x00U, 2U, &JedecId[0]);
+	if (Status != XST_SUCCESS) {
+		goto Out;
+	}
+
+	if ((JedecId[0] == 0x2CU) &&
+	/*
+	 * 1 Gb flash devices
+	 */
+	((JedecId[1] == 0xF1U) ||
+	(JedecId[1] == 0xA1U) ||
+	(JedecId[1] == 0xB1U) ||
+	/*
+	 * 2 Gb flash devices
+	 */
+	(JedecId[1] == 0xAAU) ||
+	(JedecId[1] == 0xBAU) ||
+	(JedecId[1] == 0xDAU) ||
+	(JedecId[1] == 0xCAU) ||
+	/*
+	 * 4 Gb flash devices
+	 */
+	(JedecId[1] == 0xACU) ||
+	(JedecId[1] == 0xBCU) ||
+	(JedecId[1] == 0xDCU) ||
+	(JedecId[1] == 0xCCU) ||
+	/*
+	 * 8 Gb flash devices
+	 */
+	(JedecId[1] == 0xA3U) ||
+	(JedecId[1] == 0xB3U) ||
+	(JedecId[1] == 0xD3U) ||
+	(JedecId[1] == 0xC3U))) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Ondie flash detected, jedec id 0x%x 0x%x\r\n",
+					__func__, JedecId[0], JedecId[1]);
+#endif
+		/*
+		 * On-Die Set Feature
+		 */
+		Status = XNandPsu_SetFeature(InstancePtr, 0U, 0x90U,
+						&EccSetFeature[0]);
+		if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: Ondie set_feature failed\r\n",
+								__func__);
+#endif
+			goto Out;
+		}
+		/*
+		 * Check to see if ECC feature is set
+		 */
+		Status = XNandPsu_GetFeature(InstancePtr, 0U, 0x90U,
+						&EccGetFeature[0]);
+		if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: Ondie get_feature failed\r\n",
+								__func__);
+#endif
+			goto Out;
+		}
+		if ((EccGetFeature[0] & 0x08U) != 0U) {
+			InstancePtr->Features.OnDie = 1U;
+			Status = XST_SUCCESS;
+		}
+	} else {
+		/*
+		 * On-Die flash not found
+		 */
+		Status = XST_FAILURE;
+	}
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables DMA mode of controller operation.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->DmaMode = XNANDPSU_MDMA;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables DMA mode of driver/controller operation.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->DmaMode = XNANDPSU_PIO;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables ECC mode of driver/controller operation.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+void XNandPsu_EnableEccMode(XNandPsu *InstancePtr)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->EccMode = XNANDPSU_HWECC;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables ECC mode of driver/controller operation.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+void XNandPsu_DisableEccMode(XNandPsu *InstancePtr)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->EccMode = XNANDPSU_NONE;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables storing bbt version in oob area.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*			None
+*
+* @note		None
+*
+******************************************************************************/
+void XNandPsu_EnableBbtOobMode(XNandPsu *InstancePtr)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	InstancePtr->BbtDesc.Option = XNANDPSU_BBT_OOB;
+	InstancePtr->BbtMirrorDesc.Option = XNANDPSU_BBT_OOB;
+	/*
+	 * Setting the Signature and Version Offset
+	 */
+	InstancePtr->BbtDesc.SigOffset = XNANDPSU_BBT_DESC_SIG_OFFSET;
+	InstancePtr->BbtMirrorDesc.SigOffset = XNANDPSU_BBT_DESC_SIG_OFFSET;
+	InstancePtr->BbtDesc.VerOffset = XNANDPSU_BBT_DESC_VER_OFFSET;
+	InstancePtr->BbtMirrorDesc.VerOffset = XNANDPSU_BBT_DESC_VER_OFFSET;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables storing bbt version in no oob area i.e. page memory.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*			None
+*
+* @note		None
+*
+******************************************************************************/
+void XNandPsu_DisableBbtOobMode(XNandPsu *InstancePtr)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	InstancePtr->BbtDesc.Option = XNANDPSU_BBT_NO_OOB;
+	InstancePtr->BbtMirrorDesc.Option = XNANDPSU_BBT_NO_OOB;
+	/*
+	 * Setting the Signature and Version Offset
+	 */
+	InstancePtr->BbtDesc.SigOffset = XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET;
+	InstancePtr->BbtMirrorDesc.SigOffset =
+					XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET;
+	InstancePtr->BbtDesc.VerOffset = XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET;
+	InstancePtr->BbtMirrorDesc.VerOffset =
+					XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function polls for a register bit set status till the timeout.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	RegOffset is the offset of register.
+* @param	Mask is the bitmask.
+* @param	Timeout is the timeout value.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_PollRegTimeout(XNandPsu *InstancePtr, u32 RegOffset,
+					u32 Mask, u32 Timeout)
+{
+	s32 Status = XST_FAILURE;
+	volatile u32 RegVal;
+	u32 TimeoutVar = Timeout;
+
+	while (TimeoutVar > 0U) {
+		RegVal = XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
+						RegOffset);
+		if ((RegVal & Mask) != 0U) {
+			break;
+		}
+		TimeoutVar--;
+	}
+
+	if (TimeoutVar <= 0U) {
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets packet size and packet count values in packet register.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	PktSize is the packet size.
+* @param	PktCount is the packet count.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_SetPktSzCnt(XNandPsu *InstancePtr, u32 PktSize,
+						u32 PktCount)
+{
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertVoid(PktSize <= XNANDPSU_MAX_PKT_SIZE);
+	Xil_AssertVoid(PktCount <= XNANDPSU_MAX_PKT_COUNT);
+
+	/*
+	 * Update Packet Register with pkt size and count
+	 */
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_PKT_OFFSET,
+				((u32)XNANDPSU_PKT_PKT_SIZE_MASK |
+				(u32)XNANDPSU_PKT_PKT_CNT_MASK),
+				((PktSize & XNANDPSU_PKT_PKT_SIZE_MASK) |
+				((PktCount << XNANDPSU_PKT_PKT_CNT_SHIFT) &
+				XNANDPSU_PKT_PKT_CNT_MASK)));
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets Page and Column values in the Memory address registers.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Page is the page value.
+* @param	Col is the column value.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_SetPageColAddr(XNandPsu *InstancePtr, u32 Page, u16 Col)
+{
+	/*
+	 * Program Memory Address Register 1
+	 */
+	XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_MEM_ADDR1_OFFSET,
+				((Col & XNANDPSU_MEM_ADDR1_COL_ADDR_MASK) |
+				((Page << (u32)XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT) &
+				XNANDPSU_MEM_ADDR1_PG_ADDR_MASK)));
+	/*
+	 * Program Memory Address Register 2
+	 */
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_MEM_ADDR2_OFFSET,
+				XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK,
+				((Page >> XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT) &
+				XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK));
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the size of page in Command Register.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_SetPageSize(XNandPsu *InstancePtr)
+{
+	u32 PageSizeMask = 0;
+	u32 PageSize = InstancePtr->Geometry.BytesPerPage;
+
+	/*
+	 * Calculate page size mask
+	 */
+	switch(PageSize) {
+		case XNANDPSU_PAGE_SIZE_512:
+			PageSizeMask = (0U << XNANDPSU_CMD_PG_SIZE_SHIFT);
+			break;
+		case XNANDPSU_PAGE_SIZE_2K:
+			PageSizeMask = (1U << XNANDPSU_CMD_PG_SIZE_SHIFT);
+			break;
+		case XNANDPSU_PAGE_SIZE_4K:
+			PageSizeMask = (2U << XNANDPSU_CMD_PG_SIZE_SHIFT);
+			break;
+		case XNANDPSU_PAGE_SIZE_8K:
+			PageSizeMask = (3U << XNANDPSU_CMD_PG_SIZE_SHIFT);
+			break;
+		case XNANDPSU_PAGE_SIZE_16K:
+			PageSizeMask = (4U << XNANDPSU_CMD_PG_SIZE_SHIFT);
+			break;
+		case XNANDPSU_PAGE_SIZE_1K_16BIT:
+			PageSizeMask = (5U << XNANDPSU_CMD_PG_SIZE_SHIFT);
+			break;
+		default:
+			/*
+			 * Not supported
+			 */
+			break;
+	}
+	/*
+	 * Update Command Register
+	 */
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_CMD_OFFSET,
+				XNANDPSU_CMD_PG_SIZE_MASK, PageSizeMask);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function setup the Ecc Register.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_SetEccAddrSize(XNandPsu *InstancePtr)
+{
+	u32 PageSize = InstancePtr->Geometry.BytesPerPage;
+	u32 CodeWordSize = InstancePtr->Geometry.EccCodeWordSize;
+	u32 NumEccBits = InstancePtr->Geometry.NumBitsECC;
+	u32 Index;
+	u32 Found = 0U;
+	u8 BchModeVal = 0U;
+
+	for (Index = 0U; Index < (sizeof(EccMatrix)/sizeof(XNandPsu_EccMatrix));
+						Index++) {
+		if ((EccMatrix[Index].PageSize == PageSize) &&
+			(EccMatrix[Index].CodeWordSize >= CodeWordSize)) {
+			if (EccMatrix[Index].NumEccBits >= NumEccBits) {
+				Found = Index;
+				break;
+			}
+			else {
+				Found = Index;
+			}
+		}
+	}
+
+	if (Found != 0U) {
+		if(InstancePtr->Geometry.SpareBytesPerPage < 64U) {
+			InstancePtr->EccCfg.EccAddr = PageSize;
+		}
+		else {
+			InstancePtr->EccCfg.EccAddr = PageSize +
+				(InstancePtr->Geometry.SpareBytesPerPage
+						- EccMatrix[Found].EccSize);
+		}
+		InstancePtr->EccCfg.EccSize = EccMatrix[Found].EccSize;
+		InstancePtr->EccCfg.NumEccBits = EccMatrix[Found].NumEccBits;
+		InstancePtr->EccCfg.CodeWordSize =
+						EccMatrix[Found].CodeWordSize;
+#ifdef XNANDPSU_DEBUG
+		xil_printf("ECC: addr 0x%x size 0x%x numbits %d "
+				   "codesz %d\r\n",
+				   InstancePtr->EccCfg.EccAddr,
+				   InstancePtr->EccCfg.EccSize,
+				   InstancePtr->EccCfg.NumEccBits,
+				   InstancePtr->EccCfg.CodeWordSize);
+#endif
+		if (EccMatrix[Found].IsBCH == XNANDPSU_HAMMING) {
+			InstancePtr->EccCfg.IsBCH = 0U;
+		} else {
+			InstancePtr->EccCfg.IsBCH = 1U;
+		}
+		/*
+		 * Write ECC register
+		 */
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				(u32)XNANDPSU_ECC_OFFSET,
+				((u32)InstancePtr->EccCfg.EccAddr |
+				((u32)InstancePtr->EccCfg.EccSize << (u32)16) |
+				((u32)InstancePtr->EccCfg.IsBCH << (u32)27)));
+
+		if (EccMatrix[Found].IsBCH == XNANDPSU_BCH) {
+			/*
+			 * Write memory address register 2
+			 */
+			switch(InstancePtr->EccCfg.NumEccBits) {
+				case 16U:
+					BchModeVal = 0x0U;
+					break;
+				case 12U:
+					BchModeVal = 0x1U;
+					break;
+				case 8U:
+					BchModeVal = 0x2U;
+					break;
+				case 4U:
+					BchModeVal = 0x3U;
+					break;
+				case 24U:
+					BchModeVal = 0x4U;
+					break;
+				default:
+					BchModeVal = 0x0U;
+			}
+			XNandPsu_ReadModifyWrite(InstancePtr,
+				XNANDPSU_MEM_ADDR2_OFFSET,
+				XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK,
+				(BchModeVal <<
+				(u32)XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT));
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function setup the Ecc Spare Command Register.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_SetEccSpareCmd(XNandPsu *InstancePtr, u16 SpareCmd,
+								u8 AddrCycles)
+{
+	XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				(u32)XNANDPSU_ECC_SPR_CMD_OFFSET,
+				(u32)SpareCmd | ((u32)AddrCycles << 28U));
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the flash bus width in memory address2 register.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_SetBusWidth(XNandPsu *InstancePtr)
+{
+	/*
+	 * Update Memory Address2 register with bus width
+	 */
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_MEM_ADDR2_OFFSET,
+				XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK,
+				(InstancePtr->Features.BusWidth <<
+				XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT));
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the chip select value in memory address2 register.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_SelectChip(XNandPsu *InstancePtr, u32 Target)
+{
+	/*
+	 * Update Memory Address2 register with chip select
+	 */
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_MEM_ADDR2_OFFSET,
+			XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK,
+			((Target << XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT) &
+			XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK));
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends ONFI Reset command to the flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_OnfiReset(XNandPsu *InstancePtr, u32 Target)
+{
+	s32 Status = XST_FAILURE;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
+
+	/*
+	 * Enable Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+	/*
+	 * Program Command Register
+	 */
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RST, ONFI_CMD_INVALID, 0U,
+			0U, 0U);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Set Reset in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_PROG_OFFSET, XNANDPSU_PROG_RST_MASK);
+
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		(XNANDPSU_INTR_STS_EN_OFFSET), 0U);
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends ONFI Read Status command to the flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	OnfiStatus is the ONFI status value to return.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_OnfiReadStatus(XNandPsu *InstancePtr, u32 Target,
+							u16 *OnfiStatus)
+{
+	s32 Status = XST_FAILURE;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
+	Xil_AssertNonvoid(OnfiStatus != NULL);
+	/*
+	 * Enable Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+	/*
+	 * Program Command Register
+	 */
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_STS, ONFI_CMD_INVALID,
+				0U, 0U, 0U);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	if(InstancePtr->DataInterface == XNANDPSU_SDR){
+		XNandPsu_SetPktSzCnt(InstancePtr, 1U, 1U);
+	}
+	else{
+		XNandPsu_SetPktSzCnt(InstancePtr, 2U, 1U);
+	}
+
+	/*
+	 * Set Read Status in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_STS_MASK);
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	/*
+	 * Read Flash Status
+	 */
+	*OnfiStatus = (u8) XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
+						XNANDPSU_FLASH_STS_OFFSET);
+
+Out:
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends ONFI Read ID command to the flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Buf is the ONFI ID value to return.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_OnfiReadId(XNandPsu *InstancePtr, u32 Target, u8 IdAddr,
+							u32 IdLen, u8 *Buf)
+{
+	s32 Status = XST_FAILURE;
+	u32 Index;
+	u32 Rem;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+	u32 RegVal;
+	u32 RemIdx;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
+	Xil_AssertNonvoid(Buf != NULL);
+
+	/*
+	 * Enable Buffer Read Ready Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+	/*
+	 * Program Command
+	 */
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_ID, ONFI_CMD_INVALID, 0U,
+					0U, ONFI_READ_ID_ADDR_CYCLES);
+
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, 0U, IdAddr);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, IdLen, 1U);
+	/*
+	 * Set Read ID in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_ID_MASK);
+
+	/*
+	 * Poll for Buffer Read Ready event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+		InstancePtr,
+		XNANDPSU_INTR_STS_OFFSET,
+		XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+		XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for buf read ready timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Enable Transfer Complete Interrupt in Interrupt
+	 * Status Enable Register
+	 */
+
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+
+	/*
+	 * Clear Buffer Read Ready Interrupt in Interrupt Status
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+	/*
+	 * Read Packet Data from Data Port Register
+	 */
+	for (Index = 0U; Index < (IdLen/4); Index++) {
+		BufPtr[Index] = XNandPsu_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
+	}
+	Rem = IdLen % 4;
+	if (Rem != 0U) {
+		RegVal = XNandPsu_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
+		for (RemIdx = 0U; RemIdx < Rem; RemIdx++) {
+			Buf[(Index * 4U) + RemIdx] = (u8) (RegVal >>
+						(RemIdx * 8U)) & 0xFFU;
+		}
+	}
+
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,0U);
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends the ONFI Read Parameter Page command to flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	PrmIndex is the index of parameter page.
+* @param	Buf is the parameter page information to return.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_OnfiReadParamPage(XNandPsu *InstancePtr, u32 Target,
+						u8 *Buf)
+{
+	s32 Status = XST_FAILURE;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+	u32 Index;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
+	Xil_AssertNonvoid(Buf != NULL);
+
+	/*
+	 * Enable Buffer Read Ready Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+	/*
+	 * Program Command
+	 */
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_PRM_PG, ONFI_CMD_INVALID,
+					0U, 0U, ONFI_PRM_PG_ADDR_CYCLES);
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, 0U, 0U);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, ONFI_PRM_PG_LEN, 1U);
+	/*
+	 * Set Read Parameter Page in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_PRM_PG_MASK);
+
+	/*
+	 * Poll for Buffer Read Ready event
+	 */
+	 Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	 if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: Poll for buf read ready timeout\r\n",
+							__func__);
+#endif
+			goto Out;
+		}
+
+
+			/*
+			 * Enable Transfer Complete Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				(XNANDPSU_INTR_STS_EN_OFFSET),
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+		/*
+		 * Clear Buffer Read Ready Interrupt in Interrupt Status
+		 * Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+		/*
+		 * Read Packet Data from Data Port Register
+		 */
+		for (Index = 0U; Index < (ONFI_PRM_PG_LEN/4); Index++) {
+			BufPtr[Index] = XNandPsu_ReadReg(
+					InstancePtr->Config.BaseAddress,
+						XNANDPSU_BUF_DATA_PORT_OFFSET);
+		}
+
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the length including bad blocks from a given offset and
+* length.
+*
+* @param	InstancePtr is the pointer to the XNandPsu instance.
+* @param	Offset is the flash data address to read from.
+* @param	Length is number of bytes to read.
+*
+* @return
+*		- Return actual length including bad blocks.
+*
+* @note		None.
+*
+******************************************************************************/
+static s32 XNandPsu_CalculateLength(XNandPsu *InstancePtr, u64 Offset,
+							u64 Length)
+{
+	s32 Status;
+	u32 BlockSize;
+	u32 BlockLen;
+	u32 Block;
+	u32 TempLen = 0;
+	u64 OffsetVar = Offset;
+
+	BlockSize = InstancePtr->Geometry.BlockSize;
+
+	while (TempLen < Length) {
+		Block = (u32) ((u32)OffsetVar/BlockSize);
+		BlockLen = BlockSize - ((u32)OffsetVar % BlockSize);
+		/*
+		 * Check if the block is bad
+		 */
+		Status = XNandPsu_IsBlockBad(InstancePtr, Block);
+		if (Status != XST_SUCCESS) {
+			/*
+			 * Good block
+			 */
+			TempLen += BlockLen;
+		}
+		if (OffsetVar >= InstancePtr->Geometry.DeviceSize) {
+			Status = XST_FAILURE;
+			goto Out;
+		}
+		OffsetVar += BlockLen;
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes to the flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Offset is the starting offset of flash to write.
+* @param	Length is the number of bytes to write.
+* @param	SrcBuf is the source data buffer to write.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
+{
+	s32 Status = XST_FAILURE;
+	u32 Page;
+	u32 Col;
+	u32 Target;
+	u32 Block;
+	u32 PartialBytes = 0;
+	u32 NumBytes;
+	u32 RemLen;
+	u8 *BufPtr;
+	u8 *Ptr = (u8 *)SrcBuf;
+	u16 OnfiStatus;
+	u64 OffsetVar = Offset;
+	u64 LengthVar = Length;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(SrcBuf != NULL);
+	Xil_AssertNonvoid(LengthVar != 0U);
+	Xil_AssertNonvoid((OffsetVar + LengthVar) <
+				InstancePtr->Geometry.DeviceSize);
+
+	/*
+	 * Check if write operation exceeds flash size when including
+	 * bad blocks.
+	 */
+	Status = XNandPsu_CalculateLength(InstancePtr, OffsetVar, LengthVar);
+	if (Status != XST_SUCCESS) {
+		goto Out;
+	}
+
+	while (LengthVar > 0U) {
+		Block = (u32) (OffsetVar/InstancePtr->Geometry.BlockSize);
+		/*
+		 * Skip the bad blocks. Increment the offset by block size.
+		 * For better results, always program the flash starting at
+		 * a block boundary.
+		 */
+		if (XNandPsu_IsBlockBad(InstancePtr, Block) == XST_SUCCESS) {
+			OffsetVar += (u64)InstancePtr->Geometry.BlockSize;
+			continue;
+		}
+		/*
+		 * Calculate Page and Column address values
+		 */
+		Page = (u32) (OffsetVar/InstancePtr->Geometry.BytesPerPage);
+		Col = (u32) (OffsetVar &
+				(InstancePtr->Geometry.BytesPerPage - 1U));
+		PartialBytes = 0U;
+		/*
+		 * Check if partial write.
+		 * If column address is > 0 or Length is < page size
+		 */
+		if ((Col > 0U) ||
+			(LengthVar < InstancePtr->Geometry.BytesPerPage)) {
+			RemLen = InstancePtr->Geometry.BytesPerPage - Col;
+			PartialBytes = (RemLen < (u32)LengthVar) ?
+					RemLen : (u32)LengthVar;
+		}
+
+		Target = (u32) (OffsetVar/InstancePtr->Geometry.TargetSize);
+		if (Page > InstancePtr->Geometry.NumTargetPages) {
+			Page %= InstancePtr->Geometry.NumTargetPages;
+		}
+
+		/*
+		 * Check if partial write
+		 */
+		if (PartialBytes > 0U) {
+			BufPtr = &InstancePtr->PartialDataBuf[0];
+			memset(BufPtr, 0xFF,
+					InstancePtr->Geometry.BytesPerPage);
+			memcpy(BufPtr + Col, Ptr, PartialBytes);
+
+			NumBytes = PartialBytes;
+		} else {
+			BufPtr = (u8 *)Ptr;
+			NumBytes = (InstancePtr->Geometry.BytesPerPage <
+					(u32)LengthVar) ?
+					InstancePtr->Geometry.BytesPerPage :
+					(u32)LengthVar;
+		}
+		/*
+		 * Program page
+		 */
+		Status = XNandPsu_ProgramPage(InstancePtr, Target, Page, 0U,
+								BufPtr);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+		/*
+		 * ONFI ReadStatus
+		 */
+		do {
+			Status = XNandPsu_OnfiReadStatus(InstancePtr, Target,
+								&OnfiStatus);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+			if ((OnfiStatus & (1U << 6U)) != 0U) {
+				if ((OnfiStatus & (1U << 0U)) != 0U) {
+					Status = XST_FAILURE;
+					goto Out;
+				}
+			}
+		} while (((OnfiStatus >> 6U) & 0x1U) == 0U);
+
+		Ptr += NumBytes;
+		OffsetVar += NumBytes;
+		LengthVar -= NumBytes;
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reads from the flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Offset is the starting offset of flash to read.
+* @param	Length is the number of bytes to read.
+* @param	DestBuf is the destination data buffer to fill in.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
+{
+	s32 Status = XST_FAILURE;
+	u32 Page;
+	u32 Col;
+	u32 Target;
+	u32 Block;
+	u32 PartialBytes = 0U;
+	u32 RemLen;
+	u32 NumBytes;
+	u8 *BufPtr;
+	u8 *Ptr = (u8 *)DestBuf;
+	u64 OffsetVar = Offset;
+	u64 LengthVar = Length;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(LengthVar != 0U);
+	Xil_AssertNonvoid((OffsetVar + LengthVar) <
+				InstancePtr->Geometry.DeviceSize);
+
+	/*
+	 * Check if read operation exceeds flash size when including
+	 * bad blocks.
+	 */
+	Status = XNandPsu_CalculateLength(InstancePtr, OffsetVar, LengthVar);
+	if (Status != XST_SUCCESS) {
+		goto Out;
+	}
+
+	while (LengthVar > 0U) {
+		Block = (u32) (OffsetVar/InstancePtr->Geometry.BlockSize);
+		/*
+		 * Skip the bad block. Increment the offset by block size.
+		 * The flash programming utility must make sure to start
+		 * writing always at a block boundary and skip blocks if any.
+		 */
+		if (XNandPsu_IsBlockBad(InstancePtr, Block) == XST_SUCCESS) {
+			OffsetVar += (u64)InstancePtr->Geometry.BlockSize;
+			continue;
+		}
+		/*
+		 * Calculate Page and Column address values
+		 */
+		Page = (u32) (OffsetVar/InstancePtr->Geometry.BytesPerPage);
+		Col = (u32) (OffsetVar &
+				(InstancePtr->Geometry.BytesPerPage - 1U));
+		PartialBytes = 0U;
+		/*
+		 * Check if partial write.
+		 * If column address is > 0 or Length is < page size
+		 */
+		if ((Col > 0U) ||
+			(LengthVar < InstancePtr->Geometry.BytesPerPage)) {
+			RemLen = InstancePtr->Geometry.BytesPerPage - Col;
+			PartialBytes = ((u32)RemLen < (u32)LengthVar) ?
+						(u32)RemLen : (u32)LengthVar;
+		}
+
+		Target = (u32) (OffsetVar/InstancePtr->Geometry.TargetSize);
+		if (Page > InstancePtr->Geometry.NumTargetPages) {
+			Page %= InstancePtr->Geometry.NumTargetPages;
+		}
+		/*
+		 * Check if partial read
+		 */
+		if (PartialBytes > 0U) {
+			BufPtr = &InstancePtr->PartialDataBuf[0];
+			NumBytes = PartialBytes;
+		} else {
+			BufPtr = Ptr;
+			NumBytes = (InstancePtr->Geometry.BytesPerPage <
+					(u32)LengthVar) ?
+					InstancePtr->Geometry.BytesPerPage :
+					(u32)LengthVar;
+		}
+		/*
+		 * Read page
+		 */
+		Status = XNandPsu_ReadPage(InstancePtr, Target, Page, 0U,
+								BufPtr);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+		if (PartialBytes > 0U) {
+			memcpy(Ptr, BufPtr + Col, NumBytes);
+		}
+		Ptr += NumBytes;
+		OffsetVar += NumBytes;
+		LengthVar -= NumBytes;
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function erases the flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Offset is the starting offset of flash to erase.
+* @param	Length is the number of bytes to erase.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note
+*		The Offset and Length should be aligned to block size boundary
+*		to get better results.
+*
+******************************************************************************/
+s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length)
+{
+	s32 Status = XST_FAILURE;
+	u32 Target = 0;
+	u32 StartBlock;
+	u32 NumBlocks = 0;
+	u32 Block;
+	u32 AlignOff;
+	u32 EraseLen;
+	u32 BlockRemLen;
+	u16 OnfiStatus;
+	u64 OffsetVar = Offset;
+	u64 LengthVar = Length;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(LengthVar != 0U);
+	Xil_AssertNonvoid((OffsetVar + LengthVar) <
+			InstancePtr->Geometry.DeviceSize);
+
+	/*
+	 * Check if erase operation exceeds flash size when including
+	 * bad blocks.
+	 */
+	Status = XNandPsu_CalculateLength(InstancePtr, OffsetVar, LengthVar);
+	if (Status != XST_SUCCESS) {
+		goto Out;
+	}
+	/*
+	 * Calculate number of blocks to erase
+	 */
+	StartBlock = (u32) (OffsetVar/InstancePtr->Geometry.BlockSize);
+
+	while (LengthVar > 0U) {
+		Block = (u32) (OffsetVar/InstancePtr->Geometry.BlockSize);
+		if (XNandPsu_IsBlockBad(InstancePtr, Block) ==
+							XST_SUCCESS) {
+			OffsetVar += (u64)InstancePtr->Geometry.BlockSize;
+			NumBlocks++;
+			continue;
+		}
+
+		AlignOff = (u32)OffsetVar &
+				(InstancePtr->Geometry.BlockSize - (u32)1);
+		if (AlignOff > 0U) {
+			BlockRemLen = InstancePtr->Geometry.BlockSize -
+								AlignOff;
+			EraseLen = (BlockRemLen < (u32)LengthVar) ?
+						BlockRemLen :(u32)LengthVar;
+		} else {
+			EraseLen = (InstancePtr->Geometry.BlockSize <
+						(u32)LengthVar) ?
+					InstancePtr->Geometry.BlockSize:
+						(u32)LengthVar;
+		}
+		NumBlocks++;
+		OffsetVar += EraseLen;
+		LengthVar -= EraseLen;
+	}
+
+	for (Block = StartBlock; Block < (StartBlock + NumBlocks); Block++) {
+		Target = Block/InstancePtr->Geometry.NumTargetBlocks;
+		Block %= InstancePtr->Geometry.NumTargetBlocks;
+		if (XNandPsu_IsBlockBad(InstancePtr, Block) ==
+							XST_SUCCESS) {
+			/*
+			 * Don't erase bad block
+			 */
+			continue;
+		}
+		/*
+		 * Block Erase
+		 */
+		Status = XNandPsu_EraseBlock(InstancePtr, Target, Block);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+		/*
+		 * ONFI ReadStatus
+		 */
+		do {
+			Status = XNandPsu_OnfiReadStatus(InstancePtr, Target,
+								&OnfiStatus);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+			if ((OnfiStatus & (1U << 6U)) != 0U) {
+				if ((OnfiStatus & (1U << 0U)) != 0U) {
+					Status = XST_FAILURE;
+					goto Out;
+				}
+			}
+		} while (((OnfiStatus >> 6U) & 0x1U) == 0U);
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends ONFI Program Page command to flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Page is the page address value to program.
+* @param	Col is the column address value to program.
+* @param	Buf is the data buffer to program.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_ProgramPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
+							u32 Col, u8 *Buf)
+{
+	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles +
+				InstancePtr->Geometry.ColAddrCycles;
+	u32 PktSize;
+	u32 PktCount;
+	u32 BufWrCnt = 0U;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+	s32 Status = XST_FAILURE;
+	u32 Index;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Page < InstancePtr->Geometry.NumPages);
+	Xil_AssertNonvoid(Buf != NULL);
+
+	if (InstancePtr->EccCfg.CodeWordSize > 9U) {
+		PktSize = 1024U;
+	} else {
+		PktSize = 512U;
+	}
+	PktCount = InstancePtr->Geometry.BytesPerPage/PktSize;
+
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_PG_PROG1, ONFI_CMD_PG_PROG2,
+					1U, 1U, (u8)AddrCycles);
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+
+		/*
+		 * Enable DMA boundary Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
+			XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK);
+	} else {
+		/*
+		 * Enable Buffer Write Ready Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+	}
+	/*
+	 * Program Page Size
+	 */
+	XNandPsu_SetPageSize(InstancePtr);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	/*
+	 * Program DMA system address and DMA buffer boundary
+	 */
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		/*
+		 * Flush the Data Cache
+		 */
+		Xil_DCacheFlushRange((INTPTR)Buf, (PktSize * PktCount));
+
+#ifdef __aarch64__
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
+				(u32) (((INTPTR)Buf >> 32) & 0xFFFFFFFFU));
+#endif
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
+				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
+	}
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, Page, (u16)Col);
+	/*
+	 * Set Bus Width
+	 */
+	XNandPsu_SetBusWidth(InstancePtr);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Set ECC
+	 */
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
+		XNandPsu_SetEccSpareCmd(InstancePtr, ONFI_CMD_CHNG_WR_COL,
+					InstancePtr->Geometry.ColAddrCycles);
+	}
+	/*
+	 * Set Page Program in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_PG_PROG_MASK);
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		goto WriteDmaDone;
+	}
+
+	while (BufWrCnt < PktCount) {
+		/*
+		 * Poll for Buffer Write Ready event
+		 */
+		Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+		if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: Poll for buf write ready timeout\r\n",
+							__func__);
+#endif
+			goto Out;
+		}
+		/*
+		 * Increment Buffer Write Interrupt Count
+		 */
+		BufWrCnt++;
+
+		if (BufWrCnt == PktCount) {
+			/*
+			 * Enable Transfer Complete Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+		} else {
+			/*
+			 * Clear Buffer Write Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+		}
+		/*
+		 * Clear Buffer Write Ready Interrupt in Interrupt Status
+		 * Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
+		/*
+		 * Write Packet Data to Data Port Register
+		 */
+		for (Index = 0U; Index < (PktSize/4U); Index++) {
+			XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+						XNANDPSU_BUF_DATA_PORT_OFFSET,
+						BufPtr[Index]);
+		}
+		BufPtr += (PktSize/4U);
+
+		if (BufWrCnt < PktCount) {
+			/*
+			 * Enable Buffer Write Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+		} else {
+			break;
+		}
+	}
+WriteDmaDone:
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends ONFI Program Page command to flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Page is the page address value to program.
+* @param	Col is the column address value to program.
+* @param	Buf is the data buffer to program.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
+{
+	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles +
+				InstancePtr->Geometry.ColAddrCycles;
+	u32 Col = InstancePtr->Geometry.BytesPerPage;
+	u32 Target = Page/InstancePtr->Geometry.NumTargetPages;
+	u32 PktSize = InstancePtr->Geometry.SpareBytesPerPage;
+	u32 PktCount = 1U;
+	u32 BufWrCnt = 0U;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+	u16 PreEccSpareCol = 0U;
+	u16 PreEccSpareWrCnt = 0U;
+	u16 PostEccSpareCol = 0U;
+	u16 PostEccSpareWrCnt = 0U;
+	u32 PostWrite = 0U;
+	OnfiCmdFormat Cmd;
+	s32 Status = XST_FAILURE;
+	u32 Index;
+	u32 PageVar = Page;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(PageVar < InstancePtr->Geometry.NumPages);
+	Xil_AssertNonvoid(Buf != NULL);
+
+	PageVar %= InstancePtr->Geometry.NumTargetPages;
+
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
+		/*
+		 * Calculate ECC free positions before and after ECC code
+		 */
+		PreEccSpareCol = 0x0U;
+		PreEccSpareWrCnt = InstancePtr->EccCfg.EccAddr -
+				(u16)InstancePtr->Geometry.BytesPerPage;
+
+		PostEccSpareCol = PreEccSpareWrCnt +
+					InstancePtr->EccCfg.EccSize;
+		PostEccSpareWrCnt = InstancePtr->Geometry.SpareBytesPerPage -
+					PostEccSpareCol;
+
+		PreEccSpareWrCnt = (PreEccSpareWrCnt/4U) * 4U;
+		PostEccSpareWrCnt = (PostEccSpareWrCnt/4U) * 4U;
+
+		if (PreEccSpareWrCnt > 0U) {
+			PktSize = PreEccSpareWrCnt;
+			PktCount = 1U;
+			Col = InstancePtr->Geometry.BytesPerPage +
+							PreEccSpareCol;
+			BufPtr = (u32 *)(void *)Buf;
+			if (PostEccSpareWrCnt > 0U) {
+				PostWrite = 1U;
+			}
+		} else if (PostEccSpareWrCnt > 0U) {
+			PktSize = PostEccSpareWrCnt;
+			PktCount = 1U;
+			Col = InstancePtr->Geometry.BytesPerPage +
+							PostEccSpareCol;
+			BufPtr = (u32 *)(void *)&Buf[Col];
+		} else {
+			/*
+			 * No free spare bytes available for writing
+			 */
+			Status = XST_FAILURE;
+			goto Out;
+		}
+	}
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		/*
+		 * Enable Transfer Complete Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+
+	} else {
+		/*
+		 * Enable Buffer Write Ready Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+
+	}
+	/*
+	 * Program Command hack for change write column
+	 */
+	if (PostWrite > 0U) {
+		Cmd.Command1 = 0x80U;
+		Cmd.Command2 = 0x00U;
+		XNandPsu_Prepare_Cmd(InstancePtr, Cmd.Command1, Cmd.Command2,
+				0U , 1U, (u8)AddrCycles);
+
+	} else {
+		XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_PG_PROG1,
+				ONFI_CMD_PG_PROG2, 0U , 1U, (u8)AddrCycles);
+	}
+	/*
+	 * Program Page Size
+	 */
+	XNandPsu_SetPageSize(InstancePtr);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	/*
+	 * Program DMA system address and DMA buffer boundary
+	 */
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		/*
+		 * Flush the Data Cache
+		 */
+		Xil_DCacheFlushRange((INTPTR)BufPtr, (PktSize * PktCount));
+
+#ifdef __aarch64__
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
+				(u32) (((INTPTR)BufPtr >> 32) & 0xFFFFFFFFU));
+#endif
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
+				(u32) ((INTPTR)(void *)BufPtr & 0xFFFFFFFFU));
+
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_BUF_BND_OFFSET,
+				XNANDPSU_DMA_BUF_BND_512K);
+	}
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, PageVar, (u16)Col);
+	/*
+	 * Set Bus Width
+	 */
+	XNandPsu_SetBusWidth(InstancePtr);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Set Page Program in Program Register
+	 */
+	if (PostWrite > 0U) {
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,((u32)XNANDPSU_PROG_PG_PROG_MASK |
+				(u32)XNANDPSU_PROG_CHNG_ROW_ADDR_MASK));
+	} else {
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_PG_PROG_MASK);
+	}
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		goto WriteDmaDone;
+	}
+
+	while (BufWrCnt < PktCount) {
+		/*
+		 * Poll for Buffer Write Ready event
+		 */
+		Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+		if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: Poll for buf write ready timeout\r\n",
+							__func__);
+#endif
+			goto Out;
+		}
+		/*
+		 * Increment Buffer Write Interrupt Count
+		 */
+		BufWrCnt++;
+
+		if (BufWrCnt == PktCount) {
+			/*
+			 * Enable Transfer Complete Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+
+		} else {
+			/*
+			 * Clear Buffer Write Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+		}
+		/*
+		 * Clear Buffer Write Ready Interrupt in Interrupt Status
+		 * Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
+		/*
+		 * Write Packet Data to Data Port Register
+		 */
+		for (Index = 0U; Index < (PktSize/4U); Index++) {
+			XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+						XNANDPSU_BUF_DATA_PORT_OFFSET,
+						BufPtr[Index]);
+		}
+		BufPtr += (PktSize/4U);
+
+		if (BufWrCnt < PktCount) {
+			/*
+			 * Enable Buffer Write Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+		} else {
+			break;
+		}
+	}
+WriteDmaDone:
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
+		if (PostWrite > 0U) {
+			BufPtr = (u32 *)(void *)&Buf[PostEccSpareCol];
+			Status = XNandPsu_ChangeWriteColumn(InstancePtr,
+					Target,
+					PostEccSpareCol, PostEccSpareWrCnt, 1U,
+					(u8 *)(void *)BufPtr);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+		}
+	}
+Out:
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends ONFI Read Page command to flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Page is the page address value to read.
+* @param	Col is the column address value to read.
+* @param	Buf is the data buffer to fill in.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_ReadPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
+							u32 Col, u8 *Buf)
+{
+	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles +
+				InstancePtr->Geometry.ColAddrCycles;
+	u32 PktSize;
+	u32 PktCount;
+	u32 BufRdCnt = 0U;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+	s32 Status = XST_FAILURE;
+	u32 Index, RegVal;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Page < InstancePtr->Geometry.NumPages);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
+
+	if (InstancePtr->EccCfg.CodeWordSize > 9U) {
+		PktSize = 1024U;
+	} else {
+		PktSize = 512U;
+	}
+	PktCount = InstancePtr->Geometry.BytesPerPage/PktSize;
+
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD1, ONFI_CMD_RD2,
+					1U, 1U, (u8)AddrCycles);
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+
+		/*
+		 * Enable DMA boundary Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
+			XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK);
+
+	} else {
+		/*
+		 * Enable Buffer Read Ready Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+
+	}
+	/*
+	 * Enable Single bit error and Multi bit error
+	 */
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
+		/*
+		 * Interrupt Status Enable Register
+		 */
+		XNandPsu_IntrStsEnable(InstancePtr,
+			(XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK |
+			XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK));
+	}
+	/*
+	 * Program Page Size
+	 */
+	XNandPsu_SetPageSize(InstancePtr);
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, Page, (u16)Col);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	/*
+	 * Program DMA system address and DMA buffer boundary
+	 */
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		/*
+		 * Invalidate the Data Cache
+		 */
+		Xil_DCacheInvalidateRange((INTPTR)Buf, (PktSize * PktCount));
+
+#ifdef __aarch64__
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
+				(u32) (((INTPTR)(void *)Buf >> 32) &
+				0xFFFFFFFFU));
+#endif
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
+				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
+	}
+	/*
+	 * Set Bus Width
+	 */
+	XNandPsu_SetBusWidth(InstancePtr);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Set ECC
+	 */
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
+		XNandPsu_SetEccSpareCmd(InstancePtr,
+					(ONFI_CMD_CHNG_RD_COL1 |
+					(ONFI_CMD_CHNG_RD_COL2 << (u8)8U)),
+					InstancePtr->Geometry.ColAddrCycles);
+	}
+
+	/*
+	 * Set Read command in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_MASK);
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		goto ReadDmaDone;
+	}
+
+	while (BufRdCnt < PktCount) {
+		/*
+		 * Poll for Buffer Read Ready event
+		 */
+		Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+		if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: Poll for buf read ready timeout\r\n",
+							__func__);
+#endif
+			goto CheckEccError;
+		}
+		/*
+		 * Increment Buffer Read Interrupt Count
+		 */
+		BufRdCnt++;
+
+		if (BufRdCnt == PktCount) {
+			/*
+			 * Enable Transfer Complete Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			RegVal = XNandPsu_ReadReg(
+					(InstancePtr)->Config.BaseAddress,
+					XNANDPSU_INTR_STS_EN_OFFSET);
+			RegVal &= ~XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK;
+			RegVal |= XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK;
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, RegVal);
+		} else {
+			/*
+			 * Clear Buffer Read Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			RegVal = XNandPsu_ReadReg(
+					(InstancePtr)->Config.BaseAddress,
+					XNANDPSU_INTR_STS_EN_OFFSET);
+			RegVal &= ~XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK;
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+					XNANDPSU_INTR_STS_EN_OFFSET, RegVal);
+		}
+		/*
+		 * Clear Buffer Read Ready Interrupt in Interrupt Status
+		 * Register
+		 */
+		RegVal = XNandPsu_ReadReg(
+				(InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET);
+		RegVal |= XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK;
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET, RegVal);
+		/*
+		 * Read Packet Data from Data Port Register
+		 */
+		for (Index = 0U; Index < (PktSize/4); Index++) {
+			BufPtr[Index] = XNandPsu_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
+		}
+		BufPtr += (PktSize/4);
+
+		if (BufRdCnt < PktCount) {
+			/*
+			 * Enable Buffer Read Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			RegVal = XNandPsu_ReadReg(
+					(InstancePtr)->Config.BaseAddress,
+					XNANDPSU_INTR_STS_EN_OFFSET);
+			RegVal |= XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK;
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, RegVal);
+		} else {
+			break;
+		}
+	}
+ReadDmaDone:
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto CheckEccError;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+CheckEccError:
+	/*
+	 * Check ECC Errors
+	 */
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
+		/*
+		 * Hamming Multi Bit Errors
+		 */
+		if (((u32)XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET) &
+			(u32)XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK) != 0U) {
+
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK);
+
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: ECC Hamming multi bit error\r\n",
+							__func__);
+#endif
+			InstancePtr->Ecc_Stat_PerPage_flips =
+					((XNandPsu_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XNANDPSU_ECC_ERR_CNT_OFFSET) &
+					0x1FF00U) >> 8U);
+			InstancePtr->Ecc_Stats_total_flips +=
+					InstancePtr->Ecc_Stat_PerPage_flips;
+			Status = XST_FAILURE;
+		}
+		/*
+		 * Hamming Single Bit or BCH Errors
+		 */
+		if (((u32)XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET) &
+			(u32)XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK) != 0U) {
+
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+					XNANDPSU_INTR_STS_OFFSET,
+					XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK);
+
+			if (InstancePtr->EccCfg.IsBCH == 1U) {
+				InstancePtr->Ecc_Stat_PerPage_flips =
+						((XNandPsu_ReadReg(
+						InstancePtr->Config.BaseAddress,
+						XNANDPSU_ECC_ERR_CNT_OFFSET)&
+						0x1FF00U) >> 8U);
+				InstancePtr->Ecc_Stats_total_flips +=
+					InstancePtr->Ecc_Stat_PerPage_flips;
+				Status = XST_SUCCESS;
+			}
+		}
+	}
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reads spare bytes from flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Page is the page address value to read.
+* @param	Buf is the data buffer to fill in.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
+{
+	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles +
+				InstancePtr->Geometry.ColAddrCycles;
+	u32 Col = InstancePtr->Geometry.BytesPerPage;
+	u32 Target = Page/InstancePtr->Geometry.NumTargetPages;
+	u32 PktSize = InstancePtr->Geometry.SpareBytesPerPage;
+	u32 PktCount = 1U;
+	u32 BufRdCnt = 0U;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+	s32 Status = XST_FAILURE;
+	u32 Index;
+	u32 PageVar = Page;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(PageVar < InstancePtr->Geometry.NumPages);
+	Xil_AssertNonvoid(Buf != NULL);
+
+	PageVar %= InstancePtr->Geometry.NumTargetPages;
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		/*
+		 * Enable Transfer Complete Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+	} else {
+		/*
+		 * Enable Buffer Read Ready Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+	}
+	/*
+	 * Program Command
+	 */
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD1, ONFI_CMD_RD2, 0U,
+						1U, (u8)AddrCycles);
+	/*
+	 * Program Page Size
+	 */
+	XNandPsu_SetPageSize(InstancePtr);
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, PageVar, (u16)Col);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	/*
+	 * Program DMA system address and DMA buffer boundary
+	 */
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+
+		/*
+		 * Invalidate the Data Cache
+		 */
+		Xil_DCacheInvalidateRange((INTPTR)Buf, (PktSize * PktCount));
+#ifdef __aarch64__
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
+				(u32) (((INTPTR)(void *)Buf >> 32) &
+				0xFFFFFFFFU));
+#endif
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
+				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
+	}
+	/*
+	 * Set Bus Width
+	 */
+	XNandPsu_SetBusWidth(InstancePtr);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Set Read command in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_MASK);
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		goto ReadDmaDone;
+	}
+
+	while (BufRdCnt < PktCount) {
+		/*
+		 * Poll for Buffer Read Ready event
+		 */
+		Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+		if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: Poll for buf read ready timeout\r\n",
+							__func__);
+#endif
+			goto Out;
+		}
+		/*
+		 * Increment Buffer Read Interrupt Count
+		 */
+		BufRdCnt++;
+
+		if (BufRdCnt == PktCount) {
+			/*
+			 * Enable Transfer Complete Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+
+		} else {
+			/*
+			 * Clear Buffer Read Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+					XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+		}
+		/*
+		 * Clear Buffer Read Ready Interrupt in Interrupt Status
+		 * Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+		/*
+		 * Read Packet Data from Data Port Register
+		 */
+		for (Index = 0U; Index < (PktSize/4); Index++) {
+			BufPtr[Index] = XNandPsu_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
+		}
+		BufPtr += (PktSize/4);
+
+		if (BufRdCnt < PktCount) {
+			/*
+			 * Enable Buffer Read Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+		} else {
+			break;
+		}
+	}
+ReadDmaDone:
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+Out:
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends ONFI block erase command to the flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Block is the block to erase.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block)
+{
+	s32 Status = XST_FAILURE;
+	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles;
+	u32 Page;
+	u32 ErasePage;
+	u32 EraseCol;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
+	Xil_AssertNonvoid(Block < InstancePtr->Geometry.NumBlocks);
+
+	Page = Block * InstancePtr->Geometry.PagesPerBlock;
+	ErasePage = (Page >> 16U) & 0xFFFFU;
+	EraseCol = Page & 0xFFFFU;
+
+	/*
+	 * Enable Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+
+	/*
+	 * Program Command
+	 */
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_BLK_ERASE1,
+			ONFI_CMD_BLK_ERASE2, 0U , 0U, (u8)AddrCycles);
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, ErasePage, (u16)EraseCol);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Set Block Erase in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_BLK_ERASE_MASK);
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends ONFI Get Feature command to flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Feature is the feature selector.
+* @param	Buf is the buffer to fill feature value.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
+								u8 *Buf)
+{
+	s32 Status;
+	u32 Index;
+	u32 PktSize = 4;
+	u32 PktCount = 1;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Buf != NULL);
+
+	if (InstancePtr->DataInterface == XNANDPSU_NVDDR) {
+		PktSize = 8U;
+	}
+
+	/*
+	 * Enable Buffer Read Ready Interrupt in Interrupt Status
+	 * Enable Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+	/*
+	 * Program Command
+	 */
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_GET_FEATURES,
+				ONFI_CMD_INVALID, 0U, 0U, 1U);
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, 0x0U, Feature);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	/*
+	 * Set Read Parameter Page in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_GET_FEATURES_MASK);
+	/*
+	 * Poll for Buffer Read Ready event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+		InstancePtr,
+		XNANDPSU_INTR_STS_OFFSET,
+		XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+		XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for buf read ready timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Buffer Read Ready Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Buffer Read Ready Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+	/*
+	 * Enable Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+
+	/*
+	 * Read Data from Data Port Register
+	 */
+	for (Index = 0U; Index < (PktSize/4U); Index++) {
+		BufPtr[Index] = XNandPsu_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
+	}
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends ONFI Set Feature command to flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Feature is the feature selector.
+* @param	Buf is the feature value to send.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
+								u8 *Buf)
+{
+	s32 Status;
+	u32 Index;
+	u32 PktSize = 4U;
+	u32 PktCount = 1U;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Buf != NULL);
+	if (InstancePtr->DataInterface == XNANDPSU_NVDDR) {
+		PktSize = 8U;
+	}
+
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Enable Buffer Write Ready Interrupt in Interrupt Status
+	 * Enable Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+
+	/*
+	 * Program Command
+	 */
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_SET_FEATURES,
+				ONFI_CMD_INVALID, 0U , 0U, 1U);
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, 0x0U, Feature);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	/*
+	 * Set Read Parameter Page in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_SET_FEATURES_MASK);
+	/*
+	 * Poll for Buffer Write Ready event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+		InstancePtr,
+		XNANDPSU_INTR_STS_OFFSET,
+		XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
+		XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for buf write ready timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Buffer Write Ready Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Buffer Write Ready Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
+	/*
+	 * Enable Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			(XNANDPSU_INTR_STS_EN_OFFSET),
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+	/*
+	 * Write Data to Data Port Register
+	 */
+	for (Index = 0U; Index < (PktSize/4U); Index++) {
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+					XNANDPSU_BUF_DATA_PORT_OFFSET,
+					BufPtr[Index]);
+	}
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function changes clock frequency of flash controller.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	ClockFreq is the clock frequency to change.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+static void XNandPsu_ChangeClockFreq(XNandPsu *InstancePtr, u32 ClockFreq)
+{
+	/*
+	 * Not implemented
+	 */
+}
+/*****************************************************************************/
+/**
+*
+* This function changes the data interface and timing mode.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	NewIntf is the new data interface.
+* @param	NewMode is the new timing mode.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
+				XNandPsu_DataInterface NewIntf,
+				XNandPsu_TimingMode NewMode)
+{
+	s32 Status;
+	u32 Target;
+	u32 Index;
+	u32 Found = 0U;
+	u32 RegVal;
+	u8 Buf[4] = {0U};
+	u32 *Feature = (u32 *)(void *)&Buf[0];
+	u32 SetFeature = 0U;
+	u32 NewModeVar = NewMode;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check for valid input arguments
+	 */
+	if((NewIntf != XNANDPSU_SDR && NewIntf != XNANDPSU_NVDDR) ||
+			(NewModeVar > 5U)){
+		Status = XST_FAILURE;
+		goto Out;
+	}
+
+	if(NewIntf == XNANDPSU_NVDDR){
+		NewModeVar = NewModeVar | 0x10U;
+	}
+	/*
+	 * Get current data interface type and timing mode
+	 */
+	XNandPsu_DataInterface CurIntf = InstancePtr->DataInterface;
+	XNandPsu_TimingMode CurMode = InstancePtr->TimingMode;
+
+	/*
+	 * Check if the flash is in same mode
+	 */
+	if ((CurIntf == NewIntf) && (CurMode == NewModeVar)) {
+		Status = XST_SUCCESS;
+		goto Out;
+	}
+
+	if ((CurIntf == XNANDPSU_NVDDR) && (NewIntf == XNANDPSU_SDR)) {
+
+		NewModeVar = XNANDPSU_SDR0;
+
+		/*
+		 * Change the clock frequency
+		 */
+		XNandPsu_ChangeClockFreq(InstancePtr, XNANDPSU_SDR_CLK);
+
+		/*
+		 * Update Data Interface Register
+		 */
+		RegVal = ((NewModeVar % 6U) << ((NewIntf == XNANDPSU_NVDDR) ? 3U : 0U)) |
+				((u32)NewIntf << XNANDPSU_DATA_INTF_DATA_INTF_SHIFT);
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+					XNANDPSU_DATA_INTF_OFFSET, RegVal);
+
+		for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
+							Target++) {
+			Status = XNandPsu_OnfiReset(InstancePtr, Target);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+		}
+
+		/*
+		 * Set Feature
+		 */
+		for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
+								Target++) {
+			Status = XNandPsu_SetFeature(InstancePtr, Target, 0x01U,
+							(u8 *)&NewModeVar);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+		}
+
+		InstancePtr->DataInterface = NewIntf;
+		InstancePtr->TimingMode = NewModeVar;
+
+		for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
+								Target++) {
+			Status = XNandPsu_GetFeature(InstancePtr, Target, 0x01U,
+								&Buf[0]);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+			/*
+			 * Check if set_feature was successful
+			 */
+			if ((u32)*Feature != (u32)NewModeVar) {
+				Status = XST_FAILURE;
+				goto Out;
+			}
+		}
+
+		goto Out;
+	}
+
+	SetFeature = NewModeVar;
+	if(CurIntf == XNANDPSU_NVDDR && NewIntf == XNANDPSU_NVDDR){
+		SetFeature |= SetFeature << 8U;
+	}
+	/*
+	 * Set Feature
+	 */
+	for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
+							Target++) {
+		Status = XNandPsu_SetFeature(InstancePtr, Target, 0x01U,
+						(u8 *)&SetFeature);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+	}
+
+	InstancePtr->DataInterface = NewIntf;
+	InstancePtr->TimingMode = NewModeVar;
+	/*
+	 * Update Data Interface Register
+	 */
+	RegVal = ((NewMode % 6U) << ((NewIntf == XNANDPSU_NVDDR) ? 3U : 0U)) |
+			((u32)NewIntf << XNANDPSU_DATA_INTF_DATA_INTF_SHIFT);
+	XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DATA_INTF_OFFSET, RegVal);
+
+	/*
+	 * Get Feature
+	 */
+	for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
+							Target++) {
+		Status = XNandPsu_GetFeature(InstancePtr, Target, 0x01U,
+							&Buf[0]);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+
+		/*
+		 * Check if set_feature was successful
+		 */
+		if (*Feature != NewModeVar) {
+			Status = XST_FAILURE;
+			goto Out;
+		}
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function issues change read column and reads the data into buffer
+* specified by user.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Col is the coulmn address.
+* @param	PktSize is the number of bytes to read.
+* @param	PktCount is the number of transactions to read.
+* @param	Buf is the data buffer to fill in.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_ChangeReadColumn(XNandPsu *InstancePtr, u32 Target,
+					u32 Col, u32 PktSize, u32 PktCount,
+					u8 *Buf)
+{
+	u32 AddrCycles = InstancePtr->Geometry.ColAddrCycles;
+	u32 BufRdCnt = 0U;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+	s32 Status = XST_FAILURE;
+	u32 Index;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
+	Xil_AssertNonvoid(Buf != NULL);
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		/*
+		 * Enable DMA boundary Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
+				XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK);
+	} else {
+		/*
+		 * Enable Buffer Read Ready Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+	}
+	/*
+	 * Program Command
+	 */
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_CHNG_RD_COL1,
+			ONFI_CMD_CHNG_RD_COL2, 0U , 1U, (u8)AddrCycles);
+	/*
+	 * Program Page Size
+	 */
+	XNandPsu_SetPageSize(InstancePtr);
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, 0U, (u16)Col);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	/*
+	 * Program DMA system address and DMA buffer boundary
+	 */
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		/*
+		 * Invalidate the Data Cache
+		 */
+		Xil_DCacheInvalidateRange((INTPTR)Buf, (PktSize * PktCount));
+#ifdef __aarch64__
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
+				(u32) (((INTPTR)Buf >> 32) & 0xFFFFFFFFU));
+#endif
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
+				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
+	}
+	/*
+	 * Set Bus Width
+	 */
+	XNandPsu_SetBusWidth(InstancePtr);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Set Read command in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_MASK);
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		goto ReadDmaDone;
+	}
+
+	while (BufRdCnt < PktCount) {
+		/*
+		 * Poll for Buffer Read Ready event
+		 */
+		Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+		if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: Poll for buf read ready timeout\r\n",
+							__func__);
+#endif
+			goto Out;
+		}
+		/*
+		 * Increment Buffer Read Interrupt Count
+		 */
+		BufRdCnt++;
+
+		if (BufRdCnt == PktCount) {
+			/*
+			 * Enable Transfer Complete Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+		} else {
+			/*
+			 * Clear Buffer Read Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+		}
+		/*
+		 * Clear Buffer Read Ready Interrupt in Interrupt Status
+		 * Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+		/*
+		 * Read Packet Data from Data Port Register
+		 */
+		for (Index = 0U; Index < (PktSize/4); Index++) {
+			BufPtr[Index] = XNandPsu_ReadReg(
+						InstancePtr->Config.BaseAddress,
+						XNANDPSU_BUF_DATA_PORT_OFFSET);
+		}
+		BufPtr += (PktSize/4U);
+
+		if (BufRdCnt < PktCount) {
+			/*
+			 * Enable Buffer Read Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+		} else {
+			break;
+		}
+	}
+ReadDmaDone:
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function issues change read column and reads the data into buffer
+* specified by user.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Target is the chip select value.
+* @param	Col is the coulmn address.
+* @param	PktSize is the number of bytes to read.
+* @param	PktCount is the number of transactions to read.
+* @param	Buf is the data buffer to fill in.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_ChangeWriteColumn(XNandPsu *InstancePtr, u32 Target,
+					u32 Col, u32 PktSize, u32 PktCount,
+					u8 *Buf)
+{
+	u32 AddrCycles = InstancePtr->Geometry.ColAddrCycles;
+	u32 BufWrCnt = 0U;
+	u32 *BufPtr = (u32 *)(void *)Buf;
+	s32 Status = XST_FAILURE;
+	OnfiCmdFormat OnfiCommand;
+	u32 Index;
+
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
+	Xil_AssertNonvoid(Buf != NULL);
+
+	if (PktCount == 0U) {
+		return XST_SUCCESS;
+	}
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		/*
+		 * Enable DMA boundary Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
+				XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK);
+	} else {
+		/*
+		 * Enable Buffer Write Ready Interrupt in Interrupt Status
+		 * Enable Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+	}
+	/*
+	 * Change write column hack
+	 */
+	OnfiCommand.Command1 = 0x85U;
+	OnfiCommand.Command2 = 0x10U;
+	XNandPsu_Prepare_Cmd(InstancePtr, OnfiCommand.Command1,
+				OnfiCommand.Command2, 0U , 0U, (u8)AddrCycles);
+
+	/*
+	 * Program Page Size
+	 */
+	XNandPsu_SetPageSize(InstancePtr);
+	/*
+	 * Program Column, Page, Block address
+	 */
+	XNandPsu_SetPageColAddr(InstancePtr, 0U, (u16)Col);
+	/*
+	 * Program Packet Size and Packet Count
+	 */
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	/*
+	 * Program DMA system address and DMA buffer boundary
+	 */
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+#ifdef __aarch64__
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
+				(u32) (((INTPTR)Buf >> 32U) & 0xFFFFFFFFU));
+#endif
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
+				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
+	}
+	/*
+	 * Set Bus Width
+	 */
+	XNandPsu_SetBusWidth(InstancePtr);
+	/*
+	 * Program Memory Address Register2 for chip select
+	 */
+	XNandPsu_SelectChip(InstancePtr, Target);
+	/*
+	 * Set Page Program in Program Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK);
+
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+		goto WriteDmaDone;
+	}
+
+	while (BufWrCnt < PktCount) {
+		/*
+		 * Poll for Buffer Write Ready event
+		 */
+		Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+		if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+			xil_printf("%s: Poll for buf write ready timeout\r\n",
+							__func__);
+#endif
+			goto Out;
+		}
+		/*
+		 * Increment Buffer Write Interrupt Count
+		 */
+		BufWrCnt++;
+
+		if (BufWrCnt == PktCount) {
+			/*
+			 * Enable Transfer Complete Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+		} else {
+			/*
+			 * Clear Buffer Write Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+		}
+		/*
+		 * Clear Buffer Write Ready Interrupt in Interrupt Status
+		 * Register
+		 */
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
+		/*
+		 * Write Packet Data to Data Port Register
+		 */
+		for (Index = 0U; Index < (PktSize/4U); Index++) {
+			XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+						XNANDPSU_BUF_DATA_PORT_OFFSET,
+						BufPtr[Index]);
+		}
+		BufPtr += (PktSize/4U);
+
+		if (BufWrCnt < PktCount) {
+			/*
+			 * Enable Buffer Write Ready Interrupt in Interrupt
+			 * Status Enable Register
+			 */
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+		} else {
+			break;
+		}
+	}
+WriteDmaDone:
+	/*
+	 * Poll for Transfer Complete event
+	 */
+	Status = XNandPsu_PollRegTimeout(
+			InstancePtr,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
+	if (Status != XST_SUCCESS) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Poll for xfer complete timeout\r\n",
+							__func__);
+#endif
+		goto Out;
+	}
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
+	 * Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
+
+	/*
+	 * Clear Transfer Complete Interrupt in Interrupt Status Register
+	 */
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
+
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function initializes extended parameter page ECC information.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	ExtPrm is the Extended parameter page buffer.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if failed.
+*
+* @note		None
+*
+******************************************************************************/
+static s32 XNandPsu_InitExtEcc(XNandPsu *InstancePtr, OnfiExtPrmPage *ExtPrm)
+{
+	s32 Status = XST_FAILURE;
+	u32 Index;
+	u32 SectionType;
+	u32 SectionLen;
+	u32 Offset = 0U;
+	u32 Found = 0U;
+	OnfiExtEccBlock *EccBlock;
+
+	if (ExtPrm->Section0Type != 0x2U) {
+		Offset += (u32)ExtPrm->Section0Len;
+		if (ExtPrm->Section1Type != 0x2U) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Extended ECC section not found\r\n",__func__);
+#endif
+			Status = XST_FAILURE;
+		} else {
+			Found = 1U;
+		}
+	} else {
+		Found = 1U;
+	}
+
+	if (Found != 0U) {
+		EccBlock = (OnfiExtEccBlock *)&ExtPrm->SectionData[Offset];
+		Xil_AssertNonvoid(EccBlock != NULL);
+		if (EccBlock->CodeWordSize == 0U) {
+			Status = XST_FAILURE;
+		} else {
+			InstancePtr->Geometry.NumBitsECC =
+						EccBlock->NumBitsEcc;
+			InstancePtr->Geometry.EccCodeWordSize =
+						(u32)EccBlock->CodeWordSize;
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function prepares command to be written into command register.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Cmd1 is the first Onfi Command.
+* @param	Cmd1 is the second Onfi Command.
+* @param	EccState is the flag to set Ecc State.
+* @param	DmaMode is the flag to set DMA mode.
+*
+* @return
+*		None
+*
+* @note		None
+*
+******************************************************************************/
+void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
+			u8 DmaMode, u8 AddrCycles)
+{
+	u32 RegValue = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	RegValue = (u32)Cmd1 | (((u32)Cmd2 << (u32)XNANDPSU_CMD_CMD2_SHIFT) &
+			(u32)XNANDPSU_CMD_CMD2_MASK);
+
+	if ((EccState != 0U) && (InstancePtr->EccMode == XNANDPSU_HWECC)) {
+		RegValue |= 1U << XNANDPSU_CMD_ECC_ON_SHIFT;
+	}
+
+	if ((DmaMode != 0U) && (InstancePtr->DmaMode == XNANDPSU_MDMA)) {
+		RegValue |= XNANDPSU_MDMA << XNANDPSU_CMD_DMA_EN_SHIFT;
+	}
+
+	if (AddrCycles != 0U) {
+		RegValue |= (u32)AddrCycles <<
+				(u32)XNANDPSU_CMD_ADDR_CYCLES_SHIFT;
+	}
+
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_CMD_OFFSET, RegValue);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu.h
new file mode 100644
index 000000000..134116f2b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu.h
@@ -0,0 +1,584 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu.h
+*
+* This file implements a driver to support Arasan NAND controller
+* present in Zynq Ultrascale Mp.
+*
+* Driver Initialization
+*
+* The function call XNandPsu_CfgInitialize() should be called by the application
+* before any other function in the driver. The initialization function takes
+* device specific data (like device id, instance id, and base address) and
+* initializes the XNandPsu instance with the device specific data.
+*
+* Device Geometry
+*
+* NAND flash device is memory device and it is segmented into areas called
+* Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device
+* can have multiple LUN. LUN is sequential raw of multiple blocks of the same
+* size. A block is the smallest erasable unit of data within the Flash array of
+* a LUN. The size of each block is based on a power of 2. There is no
+* restriction on the number of blocks within the LUN. A block contains a number
+* of pages. A page is the smallest addressable unit for read and program
+* operations. The arrangement of LUN, blocks, and pages is referred to by this
+* module as the part's geometry.
+*
+* The cells within the part can be programmed from a logic 1 to a logic 0
+* and not the other way around. To change a cell back to a logic 1, the
+* entire block containing that cell must be erased. When a block is erased
+* all bytes contain the value 0xFF. The number of times a block can be
+* erased is finite. Eventually the block will wear out and will no longer
+* be capable of erasure. As of this writing, the typical flash block can
+* be erased 100,000 or more times.
+*
+* The jobs done by this driver typically are:
+*	- 8-bit operational mode
+*	- Read, Write, and Erase operation
+*
+* Write Operation
+*
+* The write call can be used to write a minimum of one byte and a maximum
+* entire flash. If the address offset specified to write is out of flash or if
+* the number of bytes specified from the offset exceed flash boundaries
+* an error is reported back to the user. The write is blocking in nature in that
+* the control is returned back to user only after the write operation is
+* completed successfully or an error is reported.
+*
+* Read Operation
+*
+* The read call can be used to read a minimum of one byte and maximum of
+* entire flash. If the address offset specified to read is out of flash or if
+* the number of bytes specified from the offset exceed flash boundaries
+* an error is reported back to the user. The read is blocking in nature in that
+* the control is returned back to user only after the read operation is
+* completed successfully or an error is reported.
+*
+* Erase Operation
+*
+* The erase operations are provided to erase a Block in the Flash memory. The
+* erase call is blocking in nature in that the control is returned back to user
+* only after the erase operation is completed successfully or an error is
+* reported.
+*
+* @note		Driver has been renamed to nandpsu after change in
+*		naming convention.
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads,
+* mutual exclusion, virtual memory, cache control, or HW write protection
+* management must be satisfied by the layer above this driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 2.0   sb     01/12/2015  Removed Null checks for Buffer passed
+*			   as parameter to Read API's
+*			   - XNandPsu_Read()
+*			   - XNandPsu_ReadPage
+*			   Modified
+*			   - XNandPsu_SetFeature()
+*			   - XNandPsu_GetFeature()
+*			   and made them public.
+*			   Removed Failure Return for BCF Error check in
+*			   XNandPsu_ReadPage() and added BCH_Error counter
+*			   in the instance pointer structure.
+* 			   Added XNandPsu_Prepare_Cmd API
+*			   Replaced
+*			   - XNandPsu_IntrStsEnable
+*			   - XNandPsu_IntrStsClear
+*			   - XNandPsu_IntrClear
+*			   - XNandPsu_SetProgramReg
+*			   with XNandPsu_WriteReg call
+*			   Modified xnandpsu.c file API's with above changes.
+* 			   Corrected the program command for Set Feature API.
+*			   Modified
+*			   - XNandPsu_OnfiReadStatus
+*			   - XNandPsu_GetFeature
+*			   - XNandPsu_SetFeature
+*			   to add support for DDR mode.
+*			   Changed Convention for SLC/MLC
+*			   SLC --> HAMMING
+*			   MLC --> BCH
+*			   SlcMlc --> IsBCH
+*			   Added support for writing BBT signature and version
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
+*			   Removed extra DMA mode initialization from
+*			   the XNandPsu_CfgInitialize API.
+*			   Modified
+*			   - XNandPsu_SetEccAddrSize
+*			   ECC address now is calculated based upon the
+*			   size of spare area
+*			   Modified Block Erase API, removed clearing of
+*			   packet register before erase.
+*			   Clearing Data Interface Register before
+*			   XNandPsu_OnfiReset call.
+*			   Modified XNandPsu_ChangeTimingMode API supporting
+*			   SDR and NVDDR interface for timing modes 0 to 5.
+*			   Modified Bbt Signature and Version Offset value for
+*			   Oob and No-Oob region.
+* 

+*
+******************************************************************************/
+
+#ifndef XNANDPSU_H		/* prevent circular inclusions */
+#define XNANDPSU_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include 
+#include "xstatus.h"
+#include "xil_assert.h"
+#include "xnandpsu_hw.h"
+#include "xnandpsu_onfi.h"
+#include "xil_cache.h"
+/************************** Constant Definitions *****************************/
+
+#define XNANDPSU_DEBUG
+
+#define XNANDPSU_MAX_TARGETS		1U	/**< ce_n0, ce_n1 */
+#define XNANDPSU_MAX_PKT_SIZE		0x7FFU	/**< Max packet size */
+#define XNANDPSU_MAX_PKT_COUNT		0xFFFU	/**< Max packet count */
+
+#define XNANDPSU_PAGE_SIZE_512		512U	/**< 512 bytes page */
+#define XNANDPSU_PAGE_SIZE_2K		2048U	/**< 2K bytes page */
+#define XNANDPSU_PAGE_SIZE_4K		4096U	/**< 4K bytes page */
+#define XNANDPSU_PAGE_SIZE_8K		8192U	/**< 8K bytes page */
+#define XNANDPSU_PAGE_SIZE_16K		16384U	/**< 16K bytes page */
+#define XNANDPSU_PAGE_SIZE_1K_16BIT	1024U	/**< 16-bit 2K bytes page */
+#define XNANDPSU_MAX_PAGE_SIZE		16384U	/**< Max page size supported */
+
+#define XNANDPSU_BUS_WIDTH_8		0U	/**< 8-bit bus width */
+#define XNANDPSU_BUS_WIDTH_16		1U	/**< 16-bit bus width */
+
+#define XNANDPSU_HAMMING		0x1U	/**< Hamming Flash */
+#define XNANDPSU_BCH			0x2U	/**< BCH Flash */
+
+#define XNANDPSU_MAX_BLOCKS		32768U	/**< Max number of Blocks */
+#define XNANDPSU_MAX_SPARE_SIZE		0x800U	/**< Max spare bytes of a NAND
+						  flash page of 16K */
+
+#define XNANDPSU_INTR_POLL_TIMEOUT	10000U
+
+#define XNANDPSU_SDR_CLK		((u16)100U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_0		((u16)20U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_1		((u16)33U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_2		((u16)50U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_3		((u16)66U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_4		((u16)83U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_5		((u16)100U * (u16)1000U * (u16)1000U)
+
+/**
+ * The XNandPsu_Config structure contains configuration information for NAND
+ * controller.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Instance ID of NAND flash controller */
+	u32 BaseAddress;	/**< Base address of NAND flash controller */
+} XNandPsu_Config;
+
+/**
+ * The XNandPsu_DataInterface enum contains flash operating mode.
+ */
+typedef enum {
+	XNANDPSU_SDR = 0U,		/**< Single Data Rate */
+	XNANDPSU_NVDDR			/**< Double Data Rate */
+} XNandPsu_DataInterface;
+
+/**
+ * XNandPsu_TimingMode enum contains timing modes.
+ */
+typedef enum {
+	XNANDPSU_SDR0 = 0U,
+	XNANDPSU_SDR1,
+	XNANDPSU_SDR2,
+	XNANDPSU_SDR3,
+	XNANDPSU_SDR4,
+	XNANDPSU_SDR5,
+	XNANDPSU_NVDDR0,
+	XNANDPSU_NVDDR1,
+	XNANDPSU_NVDDR2,
+	XNANDPSU_NVDDR3,
+	XNANDPSU_NVDDR4,
+	XNANDPSU_NVDDR5
+} XNandPsu_TimingMode;
+
+/**
+ * The XNandPsu_SWMode enum contains the driver operating mode.
+ */
+typedef enum {
+	XNANDPSU_POLLING = 0,		/**< Polling */
+	XNANDPSU_INTERRUPT		/**< Interrupt */
+} XNandPsu_SWMode;
+
+/**
+ * The XNandPsu_DmaMode enum contains the controller MDMA mode.
+ */
+typedef enum {
+	XNANDPSU_PIO = 0,		/**< PIO Mode */
+	XNANDPSU_SDMA,			/**< SDMA Mode */
+	XNANDPSU_MDMA			/**< MDMA Mode */
+} XNandPsu_DmaMode;
+
+/**
+ * The XNandPsu_EccMode enum contains ECC functionality.
+ */
+typedef enum {
+	XNANDPSU_NONE = 0,
+	XNANDPSU_HWECC,
+	XNANDPSU_EZNAND,
+	XNANDPSU_ONDIE
+} XNandPsu_EccMode;
+
+/**
+ * The XNandPsu_BbtOption enum contains the BBT storage option.
+ */
+typedef enum {
+	XNANDPSU_BBT_OOB = 0,		/**< OOB area */
+	XNANDPSU_BBT_NO_OOB,		/**< No OOB i.e page area */
+} XNandPsu_BbtOption;
+
+/**
+ * Bad block table descriptor
+ */
+typedef struct {
+	u32 PageOffset[XNANDPSU_MAX_TARGETS];
+				/**< Page offset where BBT resides */
+	u32 SigOffset;		/**< Signature offset in Spare area */
+	u32 VerOffset;		/**< Offset of BBT version */
+	u32 SigLength;		/**< Length of the signature */
+	u32 MaxBlocks;		/**< Max blocks to search for BBT */
+	char Signature[4];	/**< BBT signature */
+	u8 Version[XNANDPSU_MAX_TARGETS];
+				/**< BBT version */
+	u32 Valid;		/**< BBT descriptor is valid or not */
+	XNandPsu_BbtOption Option;	/**< BBT Oob option enabled/disabled */
+} XNandPsu_BbtDesc;
+
+/**
+ * Bad block pattern
+ */
+typedef struct {
+	u32 Options;		/**< Options to search the bad block pattern */
+	u32 Offset;		/**< Offset to search for specified pattern */
+	u32 Length;		/**< Number of bytes to check the pattern */
+	u8 Pattern[2];		/**< Pattern format to search for */
+} XNandPsu_BadBlockPattern;
+
+/**
+ * The XNandPsu_Geometry structure contains the ONFI geometry information.
+ */
+typedef struct {
+	/*
+	 * Parameter page information
+	 */
+	u32 BytesPerPage;	/**< Number of bytes per page */
+	u16 SpareBytesPerPage;	/**< Number of spare bytes per page */
+	u32 PagesPerBlock;	/**< Number of pages per block */
+	u32 BlocksPerLun;	/**< Number of blocks per LUN */
+	u8 NumLuns;		/**< Number of LUN's */
+	u8 RowAddrCycles;	/**< Row address cycles */
+	u8 ColAddrCycles;	/**< Column address cycles */
+	u8 NumBitsPerCell;	/**< Number of bits per cell (Hamming/BCH) */
+	u8 NumBitsECC;		/**< Number of bits ECC correctability */
+	u32 EccCodeWordSize;	/**< ECC codeword size */
+	/*
+	 * Driver specific information
+	 */
+	u32 BlockSize;		/**< Block size */
+	u32 NumTargetPages;	/**< Total number of pages in a Target */
+	u32 NumTargetBlocks;	/**< Total number of blocks in a Target */
+	u64 TargetSize;		/**< Target size in bytes */
+	u8 NumTargets;		/**< Number of targets present */
+	u32 NumPages;		/**< Total number of pages */
+	u32 NumBlocks;		/**< Total number of blocks */
+	u64 DeviceSize;		/**< Total flash size in bytes */
+} XNandPsu_Geometry;
+
+/**
+ * The XNandPsu_Features structure contains the ONFI features information.
+ */
+typedef struct {
+	u32 BusWidth;
+	u32 NvDdr;
+	u32 EzNand;
+	u32 OnDie;
+	u32 ExtPrmPage;
+} XNandPsu_Features;
+
+/**
+ * The XNandPsu_EccMatrix structure contains ECC features information.
+ */
+typedef struct {
+	u16 PageSize;
+	u16 CodeWordSize;
+	u8 NumEccBits;
+	u8 IsBCH;
+	u16 EccAddr;
+	u16 EccSize;
+} XNandPsu_EccMatrix;
+
+/**
+ * The XNandPsu_EccCfg structure contains ECC configuration.
+ */
+typedef struct {
+	u16 EccAddr;
+	u16 EccSize;
+	u16 CodeWordSize;
+	u8 NumEccBits;
+	u8 IsBCH;
+} XNandPsu_EccCfg;
+
+/**
+ * The XNandPsu structure contains the driver instance data. The user is
+ * required to allocate a variable of this type for the NAND controller.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	u32 IsReady;		/**< Device is initialized and ready */
+	XNandPsu_Config Config;
+	u16 Ecc_Stat_PerPage_flips;	/**< Ecc Correctable Error Counter for Current Page */
+	u32 Ecc_Stats_total_flips;     /**< Total Ecc Errors Corrected */
+	XNandPsu_DataInterface DataInterface;
+	XNandPsu_TimingMode TimingMode;
+	XNandPsu_SWMode Mode;		/**< Driver operating mode */
+	XNandPsu_DmaMode DmaMode;	/**< MDMA mode enabled/disabled */
+	XNandPsu_EccMode EccMode;	/**< ECC Mode */
+	XNandPsu_EccCfg EccCfg;		/**< ECC configuration */
+	XNandPsu_Geometry Geometry;	/**< Flash geometry */
+	XNandPsu_Features Features;	/**< ONFI features */
+	u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
+					/**< Partial read/write buffer */
+	/* Bad block table definitions */
+	XNandPsu_BbtDesc BbtDesc;	/**< Bad block table descriptor */
+	XNandPsu_BbtDesc BbtMirrorDesc;	/**< Mirror BBT descriptor */
+	XNandPsu_BadBlockPattern BbPattern;	/**< Bad block pattern to
+						  search */
+	u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2];	/**< Bad block table array */
+} XNandPsu;
+
+/******************* Macro Definitions (Inline Functions) *******************/
+
+/*****************************************************************************/
+/**
+ * This macro sets the bitmask in the register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	RegOffset is the register offset.
+ * @param	BitMask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset,
+ *							u32 BitMask)
+ *
+ *****************************************************************************/
+#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask)		\
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		(RegOffset),						\
+	((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		(RegOffset)) | (BitMask))))
+
+/*****************************************************************************/
+/**
+ * This macro clears the bitmask in the register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	RegOffset is the register offset.
+ * @param	BitMask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset,
+ *							u32 BitMask)
+ *
+ *****************************************************************************/
+#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask)		\
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		(RegOffset),						\
+	((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		(RegOffset)) & ~(BitMask))))
+
+/*****************************************************************************/
+/**
+ * This macro clears and updates the bitmask in the register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	RegOffset is the register offset.
+ * @param	Mask is the bitmask.
+ * @param	Value is the register value to write.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr,
+ *					u32 RegOffset, u32 Mask, u32 Val)
+ *
+ *****************************************************************************/
+#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value)	\
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		(RegOffset),						\
+	((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
+		(u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))
+
+/*****************************************************************************/
+/**
+ * This macro enables bitmask in Interrupt Signal Enable register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	Mask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask)
+ *
+ *****************************************************************************/
+#define XNandPsu_IntrSigEnable(InstancePtr, Mask)			\
+		XNandPsu_SetBits((InstancePtr),				\
+			XNANDPSU_INTR_SIG_EN_OFFSET,			\
+			(Mask))
+
+/*****************************************************************************/
+/**
+ * This macro clears bitmask in Interrupt Signal Enable register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	Mask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask)
+ *
+ *****************************************************************************/
+#define XNandPsu_IntrSigClear(InstancePtr, Mask)			\
+		XNandPsu_ClrBits((InstancePtr),				\
+			XNANDPSU_INTR_SIG_EN_OFFSET,			\
+			(Mask))
+
+/*****************************************************************************/
+/**
+ * This macro enables bitmask in Interrupt Status Enable register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	Mask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask)
+ *
+ *****************************************************************************/
+#define XNandPsu_IntrStsEnable(InstancePtr, Mask)			\
+		XNandPsu_SetBits((InstancePtr),				\
+			XNANDPSU_INTR_STS_EN_OFFSET,			\
+			(Mask))
+
+/*****************************************************************************/
+/**
+ * This macro checks for the ONFI ID.
+ *
+ * @param	Buff is the buffer holding ONFI ID
+ *
+ * @note	none.
+ *
+ *****************************************************************************/
+#define IS_ONFI(Buff)					\
+	(Buff[0] == (u8)'O') && (Buff[1] == (u8)'N') &&	\
+	(Buff[2] == (u8)'F') && (Buff[3] == (u8)'I')
+
+/************************** Function Prototypes *****************************/
+
+s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length);
+
+s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length,
+							u8 *SrcBuf);
+
+s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length,
+							u8 *DestBuf);
+
+s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block);
+
+s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
+
+s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
+
+s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
+				XNandPsu_DataInterface NewIntf,
+				XNandPsu_TimingMode NewMode);
+
+s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
+								u8 *Buf);
+
+s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
+								u8 *Buf);
+
+s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
+
+s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
+
+void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr);
+
+void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr);
+
+void XNandPsu_EnableEccMode(XNandPsu *InstancePtr);
+
+void XNandPsu_DisableEccMode(XNandPsu *InstancePtr);
+
+void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
+			u8 DmaMode, u8 AddrCycles);
+
+void XNandPsu_EnableBbtOobMode(XNandPsu *InstancePtr);
+
+void XNandPsu_DisableBbtOobMode(XNandPsu *InstancePtr);
+/*
+ * XNandPsu_LookupConfig in xnandpsu_sinit.c
+ */
+XNandPsu_Config *XNandPsu_LookupConfig(u16 DeviceID);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XNANDPSU_H end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_bbm.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_bbm.c
new file mode 100644
index 000000000..2410f7af6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_bbm.c
@@ -0,0 +1,1087 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_bbm.c
+*
+* This file implements the Bad Block Management (BBM) functionality.
+* See xnandpsu_bbm.h for more details.
+*
+* @note		None
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date        Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 2.0   sb     01/12/2015  Added support for writing BBT signature and version
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
+*			   Modified Bbt Signature and Version Offset value for
+*			   Oob and No-Oob region.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include 	/**< For memcpy and memset */
+#include "xil_types.h"
+#include "xnandpsu.h"
+#include "xnandpsu_bbm.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target);
+
+static s32 XNandPsu_SearchBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
+							u32 Target);
+
+static void XNandPsu_CreateBbt(XNandPsu *InstancePtr, u32 Target);
+
+static void XNandPsu_ConvertBbt(XNandPsu *InstancePtr, u8 *Buf, u32 Target);
+
+static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
+				XNandPsu_BbtDesc *MirrorDesc, u32 Target);
+
+static s32 XNandPsu_MarkBbt(XNandPsu* InstancePtr, XNandPsu_BbtDesc *Desc,
+							u32 Target);
+
+static s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function initializes the Bad Block Table(BBT) descriptors with a
+* predefined pattern for searching Bad Block Table(BBT) in flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		- NONE
+*
+******************************************************************************/
+void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr)
+{
+	u32 Index;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Initialize primary Bad Block Table(BBT)
+	 */
+	InstancePtr->BbtDesc.Option = XNANDPSU_BBT_OOB;
+	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
+		InstancePtr->BbtDesc.PageOffset[Index] =
+						XNANDPSU_BBT_DESC_PAGE_OFFSET;
+	}
+	if(InstancePtr->BbtDesc.Option == XNANDPSU_BBT_OOB) {
+		if (InstancePtr->EccMode == XNANDPSU_ONDIE) {
+			InstancePtr->BbtDesc.SigOffset =
+						XNANDPSU_ONDIE_SIG_OFFSET;
+			InstancePtr->BbtDesc.VerOffset =
+						XNANDPSU_ONDIE_VER_OFFSET;
+		} else {
+			InstancePtr->BbtDesc.SigOffset =
+						XNANDPSU_BBT_DESC_SIG_OFFSET;
+			InstancePtr->BbtDesc.VerOffset =
+						XNANDPSU_BBT_DESC_VER_OFFSET;
+		}
+	} else {
+		InstancePtr->BbtDesc.SigOffset =
+					XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET;
+		InstancePtr->BbtDesc.VerOffset =
+					XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET;
+	}
+	InstancePtr->BbtDesc.SigLength = XNANDPSU_BBT_DESC_SIG_LEN;
+	InstancePtr->BbtDesc.MaxBlocks = XNANDPSU_BBT_DESC_MAX_BLOCKS;
+	(void)strcpy(&InstancePtr->BbtDesc.Signature[0], "Bbt0");
+	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
+		InstancePtr->BbtDesc.Version[Index] = 0U;
+	}
+	InstancePtr->BbtDesc.Valid = 0U;
+
+	/*
+	 * Assuming that the flash device will have at least 4 blocks.
+	 */
+	if (InstancePtr->Geometry.NumTargetBlocks <= InstancePtr->
+							BbtDesc.MaxBlocks){
+		InstancePtr->BbtDesc.MaxBlocks = 4U;
+	}
+
+	/*
+	 * Initialize mirror Bad Block Table(BBT)
+	 */
+	InstancePtr->BbtMirrorDesc.Option = XNANDPSU_BBT_OOB;
+	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
+		InstancePtr->BbtMirrorDesc.PageOffset[Index] =
+						XNANDPSU_BBT_DESC_PAGE_OFFSET;
+	}
+	if(InstancePtr->BbtMirrorDesc.Option == XNANDPSU_BBT_OOB) {
+		if (InstancePtr->EccMode == XNANDPSU_ONDIE) {
+			InstancePtr->BbtMirrorDesc.SigOffset =
+						XNANDPSU_ONDIE_SIG_OFFSET;
+			InstancePtr->BbtMirrorDesc.VerOffset =
+						XNANDPSU_ONDIE_VER_OFFSET;
+		} else {
+			InstancePtr->BbtMirrorDesc.SigOffset =
+						XNANDPSU_BBT_DESC_SIG_OFFSET;
+			InstancePtr->BbtMirrorDesc.VerOffset =
+						XNANDPSU_BBT_DESC_VER_OFFSET;
+		}
+	} else {
+		InstancePtr->BbtMirrorDesc.SigOffset =
+					XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET;
+		InstancePtr->BbtMirrorDesc.VerOffset =
+					XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET;
+	}
+	InstancePtr->BbtMirrorDesc.SigLength = XNANDPSU_BBT_DESC_SIG_LEN;
+	InstancePtr->BbtMirrorDesc.MaxBlocks = XNANDPSU_BBT_DESC_MAX_BLOCKS;
+	(void)strcpy(&InstancePtr->BbtMirrorDesc.Signature[0], "1tbB");
+	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
+		InstancePtr->BbtMirrorDesc.Version[Index] = 0U;
+	}
+	InstancePtr->BbtMirrorDesc.Valid = 0U;
+
+	/*
+	 * Assuming that the flash device will have at least 4 blocks.
+	 */
+	if (InstancePtr->Geometry.NumTargetBlocks <= InstancePtr->
+						BbtMirrorDesc.MaxBlocks){
+		InstancePtr->BbtMirrorDesc.MaxBlocks = 4U;
+	}
+
+	/*
+	 * Initialize Bad block search pattern structure
+	 */
+	if (InstancePtr->Geometry.BytesPerPage > 512U) {
+		/* For flash page size > 512 bytes */
+		InstancePtr->BbPattern.Options = XNANDPSU_BBT_SCAN_2ND_PAGE;
+		InstancePtr->BbPattern.Offset =
+			XNANDPSU_BB_PTRN_OFF_LARGE_PAGE;
+		InstancePtr->BbPattern.Length =
+			XNANDPSU_BB_PTRN_LEN_LARGE_PAGE;
+	} else {
+		InstancePtr->BbPattern.Options = XNANDPSU_BBT_SCAN_2ND_PAGE;
+		InstancePtr->BbPattern.Offset =
+			XNANDPSU_BB_PTRN_OFF_SML_PAGE;
+		InstancePtr->BbPattern.Length =
+			XNANDPSU_BB_PTRN_LEN_SML_PAGE;
+	}
+	for(Index = 0U; Index < XNANDPSU_BB_PTRN_LEN_LARGE_PAGE; Index++) {
+		InstancePtr->BbPattern.Pattern[Index] = XNANDPSU_BB_PATTERN;
+	}
+}
+
+/*****************************************************************************/
+/**
+* This function scans the NAND flash for factory marked bad blocks and creates
+* a RAM based Bad Block Table(BBT).
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		- NONE
+*
+******************************************************************************/
+static void XNandPsu_CreateBbt(XNandPsu *InstancePtr, u32 Target)
+{
+	u32 BlockIndex;
+	u32 PageIndex;
+	u32 Length;
+	u32 BlockOffset;
+	u8 BlockShift;
+	u32 NumPages;
+	u32 Page;
+	u8 Buf[XNANDPSU_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
+	u32 StartBlock = Target * InstancePtr->Geometry.NumTargetBlocks;
+	u32 NumBlocks = InstancePtr->Geometry.NumTargetBlocks;
+	s32 Status;
+
+	/*
+	 * Number of pages to search for bad block pattern
+	 */
+	if ((InstancePtr->BbPattern.Options & XNANDPSU_BBT_SCAN_2ND_PAGE) != 0U)
+	{
+		NumPages = 2U;
+	} else {
+		NumPages = 1U;
+	}
+	/*
+	 * Scan all the blocks for factory marked bad blocks
+	 */
+	for(BlockIndex = StartBlock; BlockIndex < (StartBlock + NumBlocks);
+							BlockIndex++) {
+		/*
+		 * Block offset in Bad Block Table(BBT) entry
+		 */
+		BlockOffset = BlockIndex >> XNANDPSU_BBT_BLOCK_SHIFT;
+		/*
+		 * Block shift value in the byte
+		 */
+		BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
+		Page = BlockIndex * InstancePtr->Geometry.PagesPerBlock;
+		/*
+		 * Search for the bad block pattern
+		 */
+		for(PageIndex = 0U; PageIndex < NumPages; PageIndex++) {
+			Status = XNandPsu_ReadSpareBytes(InstancePtr,
+					(Page + PageIndex), &Buf[0]);
+
+			if (Status != XST_SUCCESS) {
+				/* Marking as bad block */
+				InstancePtr->Bbt[BlockOffset] |=
+					(u8)(XNANDPSU_BLOCK_FACTORY_BAD <<
+					 BlockShift);
+				break;
+			}
+			/*
+			 * Read the spare bytes to check for bad block
+			 * pattern
+			 */
+			for(Length = 0U; Length <
+				InstancePtr->BbPattern.Length; Length++) {
+				if (Buf[InstancePtr->BbPattern.Offset + Length]
+						!=
+					InstancePtr->BbPattern.Pattern[Length])
+				{
+					/* Bad block found */
+					InstancePtr->Bbt[BlockOffset] |=
+						(u8)
+						(XNANDPSU_BLOCK_FACTORY_BAD <<
+						 BlockShift);
+					break;
+				}
+			}
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+* This function reads the Bad Block Table(BBT) if present in flash. If not it
+* scans the flash for detecting factory marked bad blocks and creates a bad
+* block table and write the Bad Block Table(BBT) into the flash.
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+******************************************************************************/
+s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr)
+{
+	s32 Status;
+	u32 Index;
+	u32 BbtLen;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Zero the RAM based Bad Block Table(BBT) entries
+	 */
+	BbtLen = InstancePtr->Geometry.NumBlocks >>
+					XNANDPSU_BBT_BLOCK_SHIFT;
+	memset(&InstancePtr->Bbt[0], 0, BbtLen);
+
+	for (Index = 0U; Index < InstancePtr->Geometry.NumTargets; Index++) {
+
+		if (XNandPsu_ReadBbt(InstancePtr, Index) != XST_SUCCESS) {
+			/*
+			 * Create memory based Bad Block Table(BBT)
+			 */
+			XNandPsu_CreateBbt(InstancePtr, Index);
+			/*
+			 * Write the Bad Block Table(BBT) to the flash
+			 */
+			Status = XNandPsu_WriteBbt(InstancePtr,
+					&InstancePtr->BbtDesc,
+					&InstancePtr->BbtMirrorDesc, Index);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+			/*
+			 * Write the Mirror Bad Block Table(BBT) to the flash
+			 */
+			Status = XNandPsu_WriteBbt(InstancePtr,
+					&InstancePtr->BbtMirrorDesc,
+					&InstancePtr->BbtDesc, Index);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+			/*
+			 * Mark the blocks containing Bad Block Table
+			 * (BBT) as Reserved
+			 */
+			Status = XNandPsu_MarkBbt(InstancePtr,
+							&InstancePtr->BbtDesc,
+							Index);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+			Status = XNandPsu_MarkBbt(InstancePtr,
+						&InstancePtr->BbtMirrorDesc,
+							Index);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+		}
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function converts the Bad Block Table(BBT) read from the flash to the
+* RAM based Bad Block Table(BBT).
+*
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	Buf is the buffer which contains BBT read from flash.
+*
+* @return
+*		- NONE.
+*
+******************************************************************************/
+static void XNandPsu_ConvertBbt(XNandPsu *InstancePtr, u8 *Buf, u32 Target)
+{
+	u32 BlockOffset;
+	u8 BlockShift;
+	u32 Data;
+	u8 BlockType;
+	u32 BlockIndex;
+	u32 BbtLen = InstancePtr->Geometry.NumTargetBlocks >>
+					XNANDPSU_BBT_BLOCK_SHIFT;
+	u32 StartBlock = Target * InstancePtr->Geometry.NumTargetBlocks;
+
+	for(BlockOffset = StartBlock; BlockOffset < (StartBlock + BbtLen);
+						BlockOffset++) {
+		Data = *(Buf + BlockOffset);
+		/*
+		 * Clear the RAM based Bad Block Table(BBT) contents
+		 */
+		InstancePtr->Bbt[BlockOffset] = 0x0U;
+		/*
+		 * Loop through the every 4 blocks in the bitmap
+		 */
+		for(BlockIndex = 0U; BlockIndex < XNANDPSU_BBT_ENTRY_NUM_BLOCKS;
+				BlockIndex++) {
+			BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
+			BlockType = (u8) ((Data >> BlockShift) &
+				XNANDPSU_BLOCK_TYPE_MASK);
+			switch(BlockType) {
+				case XNANDPSU_FLASH_BLOCK_FAC_BAD:
+					/* Factory bad block */
+					InstancePtr->Bbt[BlockOffset] |=
+						(u8)
+						(XNANDPSU_BLOCK_FACTORY_BAD <<
+						BlockShift);
+					break;
+				case XNANDPSU_FLASH_BLOCK_RESERVED:
+					/* Reserved block */
+					InstancePtr->Bbt[BlockOffset] |=
+						(u8)
+						(XNANDPSU_BLOCK_RESERVED <<
+						BlockShift);
+					break;
+				case XNANDPSU_FLASH_BLOCK_BAD:
+					/* Bad block due to wear */
+					InstancePtr->Bbt[BlockOffset] |=
+						(u8)(XNANDPSU_BLOCK_BAD <<
+						BlockShift);
+					break;
+				default:
+					/* Good block */
+					/* The BBT entry already defaults to
+					 * zero */
+					break;
+			}
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+* This function searches the Bad Bloock Table(BBT) in flash and loads into the
+* memory based Bad Block Table(BBT).
+*
+* @param	InstancePtr is the pointer to the XNandPsu instance.
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+******************************************************************************/
+static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target)
+{
+	u64 Offset;
+	u8 Buf[XNANDPSU_BBT_BUF_LENGTH]
+					 __attribute__ ((aligned(64))) = {0U};
+	s32 Status1;
+	s32 Status2;
+	s32 Status;
+	u32 BufLen;
+	u8 * BufPtr = Buf;
+
+	XNandPsu_BbtDesc *Desc = &InstancePtr->BbtDesc;
+	XNandPsu_BbtDesc *MirrorDesc = &InstancePtr->BbtMirrorDesc;
+	BufLen = InstancePtr->Geometry.NumBlocks >>
+			XNANDPSU_BBT_BLOCK_SHIFT;
+	if (Desc->Option == XNANDPSU_BBT_NO_OOB) {
+		BufLen += Desc->VerOffset + XNANDPSU_BBT_VERSION_LENGTH;
+	}
+	/*
+	 * Search the Bad Block Table(BBT) in flash
+	 */
+	Status1 = XNandPsu_SearchBbt(InstancePtr, Desc, Target);
+	Status2 = XNandPsu_SearchBbt(InstancePtr, MirrorDesc, Target);
+	if ((Status1 != XST_SUCCESS) && (Status2 != XST_SUCCESS)) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Bad block table not found\r\n",__func__);
+#endif
+		Status = XST_FAILURE;
+		goto Out;
+	}
+#ifdef XNANDPSU_DEBUG
+	xil_printf("%s: Bad block table found\r\n",__func__);
+#endif
+	/*
+	 * Bad Block Table found
+	 */
+	if ((Desc->Valid != 0U) && (MirrorDesc->Valid != 0U)) {
+		/*
+		 * Valid BBT & Mirror BBT found
+		 */
+		if (Desc->Version[Target] > MirrorDesc->Version[Target]) {
+			Offset = (u64)Desc->PageOffset[Target] *
+				(u64)InstancePtr->Geometry.BytesPerPage;
+			Status = XNandPsu_Read(InstancePtr, Offset, BufLen,
+								&BufPtr[0]);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+
+			if (Desc->Option == XNANDPSU_BBT_NO_OOB){
+				BufPtr = BufPtr + Desc->VerOffset +
+						XNANDPSU_BBT_VERSION_LENGTH;
+			}
+			/*
+			 * Convert flash BBT to memory based BBT
+			 */
+			XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+			MirrorDesc->Version[Target] = Desc->Version[Target];
+
+			/*
+			 * Write the BBT to Mirror BBT location in flash
+			 */
+			Status = XNandPsu_WriteBbt(InstancePtr, MirrorDesc,
+							Desc, Target);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+		} else if (Desc->Version[Target] <
+						MirrorDesc->Version[Target]) {
+			Offset = (u64)MirrorDesc->PageOffset[Target] *
+				(u64)InstancePtr->Geometry.BytesPerPage;
+			Status = XNandPsu_Read(InstancePtr, Offset, BufLen,
+								&BufPtr[0]);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+			if(Desc->Option == XNANDPSU_BBT_NO_OOB){
+				BufPtr = BufPtr + Desc->VerOffset +
+						XNANDPSU_BBT_VERSION_LENGTH;
+			}
+			/*
+			 * Convert flash BBT to memory based BBT
+			 */
+			XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+			Desc->Version[Target] = MirrorDesc->Version[Target];
+
+			/*
+			 * Write the Mirror BBT to BBT location in flash
+			 */
+			Status = XNandPsu_WriteBbt(InstancePtr, Desc,
+							MirrorDesc, Target);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+		} else {
+			/* Both are up-to-date */
+			Offset = (u64)Desc->PageOffset[Target] *
+				(u64)InstancePtr->Geometry.BytesPerPage;
+			Status = XNandPsu_Read(InstancePtr, Offset, BufLen,
+								&BufPtr[0]);
+			if (Status != XST_SUCCESS) {
+				goto Out;
+			}
+
+			if(Desc->Option == XNANDPSU_BBT_NO_OOB){
+				BufPtr = BufPtr + Desc->VerOffset +
+						XNANDPSU_BBT_VERSION_LENGTH;
+			}
+
+			/*
+			 * Convert flash BBT to memory based BBT
+			 */
+			XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+		}
+	} else if (Desc->Valid != 0U) {
+		/*
+		 * Valid Primary BBT found
+		 */
+		Offset = (u64)Desc->PageOffset[Target] *
+			(u64)InstancePtr->Geometry.BytesPerPage;
+		Status = XNandPsu_Read(InstancePtr, Offset, BufLen, &BufPtr[0]);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+		if(Desc->Option == XNANDPSU_BBT_NO_OOB){
+			BufPtr = BufPtr + Desc->VerOffset +
+				XNANDPSU_BBT_VERSION_LENGTH;
+		}
+		/*
+		 * Convert flash BBT to memory based BBT
+		 */
+		XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+		MirrorDesc->Version[Target] = Desc->Version[Target];
+
+		/*
+		 * Write the BBT to Mirror BBT location in flash
+		 */
+		Status = XNandPsu_WriteBbt(InstancePtr, MirrorDesc, Desc,
+								Target);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+	} else {
+		/*
+		 * Valid Mirror BBT found
+		 */
+		Offset = (u64)MirrorDesc->PageOffset[Target] *
+			(u64)InstancePtr->Geometry.BytesPerPage;
+		Status = XNandPsu_Read(InstancePtr, Offset, BufLen, &BufPtr[0]);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+		if(Desc->Option == XNANDPSU_BBT_NO_OOB){
+			BufPtr = BufPtr + Desc->VerOffset +
+				XNANDPSU_BBT_VERSION_LENGTH;
+		}
+
+		/*
+		 * Convert flash BBT to memory based BBT
+		 */
+		XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+		Desc->Version[Target] = MirrorDesc->Version[Target];
+
+		/*
+		 * Write the Mirror BBT to BBT location in flash
+		 */
+		Status = XNandPsu_WriteBbt(InstancePtr, Desc, MirrorDesc,
+								Target);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function searches the BBT in flash.
+*
+* @param	InstancePtr is the pointer to the XNandPsu instance.
+* @param	Desc is the BBT descriptor pattern to search.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+******************************************************************************/
+static s32 XNandPsu_SearchBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
+								u32 Target)
+{
+	u32 StartBlock;
+	u32 SigOffset;
+	u32 VerOffset;
+	u32 MaxBlocks;
+	u32 PageOff;
+	u32 SigLength;
+	u8 Buf[XNANDPSU_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
+	u32 Block;
+	u32 Offset;
+	s32 Status;
+	u64 BlockOff;
+
+	StartBlock = ((Target + (u32)1) *
+				InstancePtr->Geometry.NumTargetBlocks) - (u32)1;
+	SigOffset = Desc->SigOffset;
+	VerOffset = Desc->VerOffset;
+	MaxBlocks = Desc->MaxBlocks;
+	SigLength = Desc->SigLength;
+
+	/*
+	 * Read the last 4 blocks for Bad Block Table(BBT) signature
+	 */
+	for(Block = 0U; Block < MaxBlocks; Block++) {
+		PageOff = (StartBlock - Block) *
+			InstancePtr->Geometry.PagesPerBlock;
+
+		if(Desc->Option == XNANDPSU_BBT_NO_OOB){
+			BlockOff = (u64)PageOff * (u64)InstancePtr->Geometry.BytesPerPage;
+			Status = XNandPsu_Read(InstancePtr, BlockOff,
+				Desc->VerOffset + XNANDPSU_BBT_VERSION_LENGTH, &Buf[0]);
+		}else{
+			Status = XNandPsu_ReadSpareBytes(InstancePtr, PageOff, &Buf[0]);
+		}
+		if (Status != XST_SUCCESS) {
+			continue;
+		}
+		/*
+		 * Check the Bad Block Table(BBT) signature
+		 */
+		for(Offset = 0U; Offset < SigLength; Offset++) {
+			if (Buf[Offset + SigOffset] !=
+				(u8)(Desc->Signature[Offset]))
+			{
+				break; /* Check the next blocks */
+			}
+		}
+		if (Offset >= SigLength) {
+			/*
+			 * Bad Block Table(BBT) found
+			 */
+			Desc->PageOffset[Target] = PageOff;
+			Desc->Version[Target] = Buf[VerOffset];
+			Desc->Valid = 1U;
+
+			Status = XST_SUCCESS;
+			goto Out;
+		}
+	}
+	/*
+	 * Bad Block Table(BBT) not found
+	 */
+	Status = XST_FAILURE;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function writes Bad Block Table(BBT) from RAM to flash.
+*
+* @param	InstancePtr is the pointer to the XNandPsu instance.
+* @param	Desc is the BBT descriptor to be written to flash.
+* @param	MirrorDesc is the mirror BBT descriptor.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+******************************************************************************/
+static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
+				XNandPsu_BbtDesc *MirrorDesc, u32 Target)
+{
+	u64 Offset;
+	u32 Block = {0U};
+	u32 EndBlock = ((Target + (u32)1) *
+			InstancePtr->Geometry.NumTargetBlocks) - (u32)1;
+	u8 Buf[XNANDPSU_BBT_BUF_LENGTH]
+					 __attribute__ ((aligned(64))) = {0U};
+	u8 SpareBuf[XNANDPSU_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
+	u8 Mask[4] = {0x00U, 0x01U, 0x02U, 0x03U};
+	u8 Data;
+	u32 BlockOffset;
+	u8 BlockShift;
+	s32 Status;
+	u32 BlockIndex;
+	u32 Index;
+	u8 BlockType;
+	u32 BbtLen = InstancePtr->Geometry.NumBlocks >>
+						XNANDPSU_BBT_BLOCK_SHIFT;
+	u32 BufLen = BbtLen;
+	if (Desc->Option == XNANDPSU_BBT_NO_OOB) {
+		BufLen += Desc->VerOffset + XNANDPSU_BBT_VERSION_LENGTH;
+	}
+	u8* BufPtr = Buf;
+	/*
+	 * Find a valid block to write the Bad Block Table(BBT)
+	 */
+	if ((!Desc->Valid) != 0U) {
+		for(Index = 0U; Index < Desc->MaxBlocks; Index++) {
+			Block  = (EndBlock - Index);
+			BlockOffset = Block >> XNANDPSU_BBT_BLOCK_SHIFT;
+			BlockShift = XNandPsu_BbtBlockShift(Block);
+			BlockType = (InstancePtr->Bbt[BlockOffset] >>
+					BlockShift) & XNANDPSU_BLOCK_TYPE_MASK;
+			switch(BlockType)
+			{
+				case XNANDPSU_BLOCK_BAD:
+				case XNANDPSU_BLOCK_FACTORY_BAD:
+					continue;
+				default:
+					/* Good Block */
+					break;
+			}
+			Desc->PageOffset[Target] = Block *
+				InstancePtr->Geometry.PagesPerBlock;
+			if (Desc->PageOffset[Target] !=
+					MirrorDesc->PageOffset[Target]) {
+				/* Free block found */
+				Desc->Valid = 1U;
+				break;
+			}
+		}
+
+		/*
+		 * Block not found for writing Bad Block Table(BBT)
+		 */
+		if (Index >= Desc->MaxBlocks) {
+#ifdef XNANDPSU_DEBUG
+		xil_printf("%s: Blocks unavailable for writing BBT\r\n",
+								__func__);
+#endif
+			Status = XST_FAILURE;
+			goto Out;
+		}
+	} else {
+		Block = Desc->PageOffset[Target] /
+					InstancePtr->Geometry.PagesPerBlock;
+	}
+	/*
+	 * Convert the memory based BBT to flash based table
+	 */
+	memset(Buf, 0xff, BufLen);
+
+	if(Desc->Option == XNANDPSU_BBT_NO_OOB){
+		BufPtr = BufPtr + Desc->VerOffset + XNANDPSU_BBT_VERSION_LENGTH;
+	}
+	/*
+	 * Loop through the number of blocks
+	 */
+	for(BlockOffset = 0U; BlockOffset < BufLen; BlockOffset++) {
+		Data = InstancePtr->Bbt[BlockOffset];
+		/*
+		 * Calculate the bit mask for 4 blocks at a time in loop
+		 */
+		for(BlockIndex = 0U; BlockIndex < XNANDPSU_BBT_ENTRY_NUM_BLOCKS;
+				BlockIndex++) {
+			BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
+			BufPtr[BlockOffset] &= ~(Mask[Data &
+					XNANDPSU_BLOCK_TYPE_MASK] <<
+					BlockShift);
+			Data >>= XNANDPSU_BBT_BLOCK_SHIFT;
+		}
+	}
+	/*
+	 * Write the Bad Block Table(BBT) to flash
+	 */
+	Status = XNandPsu_EraseBlock(InstancePtr, 0U, Block);
+	if (Status != XST_SUCCESS) {
+		goto Out;
+	}
+
+	if(Desc->Option == XNANDPSU_BBT_NO_OOB){
+		/*
+		 * Copy the signature and version to the Buffer
+		 */
+		memcpy(Buf + Desc->SigOffset, &Desc->Signature[0],
+							Desc->SigLength);
+		memcpy(Buf + Desc->VerOffset, &Desc->Version[Target], 1U);
+		/*
+		 * Write the Buffer to page offset
+		 */
+		Offset = (u64)Desc->PageOffset[Target] *
+				(u64)InstancePtr->Geometry.BytesPerPage;
+		Status = XNandPsu_Write(InstancePtr, Offset, BufLen, &Buf[0]);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+	}else{
+		/*
+		 * Write the BBT to page offset
+		 */
+		Offset = (u64)Desc->PageOffset[Target] *
+				(u64)InstancePtr->Geometry.BytesPerPage;
+		Status = XNandPsu_Write(InstancePtr, Offset, BbtLen, &Buf[0]);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+		/*
+		 * Write the signature and version in the spare data area
+		 */
+		memset(SpareBuf, 0xff, InstancePtr->Geometry.SpareBytesPerPage);
+		Status = XNandPsu_ReadSpareBytes(InstancePtr, Desc->PageOffset[Target],
+				&SpareBuf[0]);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+
+		memcpy(SpareBuf + Desc->SigOffset, &Desc->Signature[0],
+							Desc->SigLength);
+		memcpy(SpareBuf + Desc->VerOffset, &Desc->Version[Target], 1U);
+
+		Status = XNandPsu_WriteSpareBytes(InstancePtr,
+				Desc->PageOffset[Target], &SpareBuf[0]);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function updates the primary and mirror Bad Block Table(BBT) in the
+* flash.
+*
+* @param	InstancePtr is the pointer to the XNandPsu instance.
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+******************************************************************************/
+static s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target)
+{
+	s32 Status;
+	u8 Version;
+
+	/*
+	 * Update the version number
+	 */
+	Version = InstancePtr->BbtDesc.Version[Target];
+	InstancePtr->BbtDesc.Version[Target] = (u8)(((u16)Version +
+							(u16)1) % (u16)256U);
+
+	Version = InstancePtr->BbtMirrorDesc.Version[Target];
+	InstancePtr->BbtMirrorDesc.Version[Target] = (u8)(((u16)Version +
+							(u16)1) % (u16)256);
+	/*
+	 * Update the primary Bad Block Table(BBT) in flash
+	 */
+	Status = XNandPsu_WriteBbt(InstancePtr, &InstancePtr->BbtDesc,
+						&InstancePtr->BbtMirrorDesc,
+						Target);
+	if (Status != XST_SUCCESS) {
+		goto Out;
+	}
+
+	/*
+	 * Update the mirrored Bad Block Table(BBT) in flash
+	 */
+	Status = XNandPsu_WriteBbt(InstancePtr, &InstancePtr->BbtMirrorDesc,
+						&InstancePtr->BbtDesc,
+						Target);
+	if (Status != XST_SUCCESS) {
+		goto Out;
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function marks the block containing Bad Block Table as reserved
+* and updates the BBT.
+*
+* @param	InstancePtr is the pointer to the XNandPsu instance.
+* @param	Desc is the BBT descriptor pointer.
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+******************************************************************************/
+static s32 XNandPsu_MarkBbt(XNandPsu* InstancePtr, XNandPsu_BbtDesc *Desc,
+								u32 Target)
+{
+	u32 BlockIndex;
+	u32 BlockOffset;
+	u8 BlockShift;
+	u8 OldVal;
+	u8 NewVal;
+	s32 Status;
+	u32 UpdateBbt = 0U;
+	u32 Index;
+
+	/*
+	 * Mark the last four blocks as Reserved
+	 */
+	BlockIndex = ((Target + (u32)1) * InstancePtr->Geometry.NumTargetBlocks) -
+						Desc->MaxBlocks - (u32)1;
+
+	for(Index = 0U; Index < Desc->MaxBlocks; Index++) {
+
+		BlockOffset = BlockIndex >> XNANDPSU_BBT_BLOCK_SHIFT;
+		BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
+		OldVal = InstancePtr->Bbt[BlockOffset];
+		NewVal = (u8) (OldVal | (XNANDPSU_BLOCK_RESERVED <<
+							BlockShift));
+		InstancePtr->Bbt[BlockOffset] = NewVal;
+
+		if (OldVal != NewVal) {
+			UpdateBbt = 1U;
+		}
+		BlockIndex++;
+	}
+
+	/*
+	 * Update the BBT to flash
+	 */
+	if (UpdateBbt != 0U) {
+		Status = XNandPsu_UpdateBbt(InstancePtr, Target);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether a block is bad or not.
+*
+* @param	InstancePtr is the pointer to the XNandPsu instance.
+*
+* @param	Block is the block number.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+******************************************************************************/
+s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block)
+{
+	u8 Data;
+	u8 BlockShift;
+	u8 BlockType;
+	u32 BlockOffset;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Block < InstancePtr->Geometry.NumBlocks);
+
+	BlockOffset = Block >> XNANDPSU_BBT_BLOCK_SHIFT;
+	BlockShift = XNandPsu_BbtBlockShift(Block);
+	Data = InstancePtr->Bbt[BlockOffset];	/* Block information in BBT */
+	BlockType = (Data >> BlockShift) & XNANDPSU_BLOCK_TYPE_MASK;
+
+	if ((BlockType != XNANDPSU_BLOCK_GOOD) &&
+		(BlockType != XNANDPSU_BLOCK_RESERVED)) {
+		Status = XST_SUCCESS;
+	}
+	else {
+		Status = XST_FAILURE;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function marks a block as bad in the RAM based Bad Block Table(BBT). It
+* also updates the Bad Block Table(BBT) in the flash.
+*
+* @param	InstancePtr is the pointer to the XNandPsu instance.
+* @param	Block is the block number.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+******************************************************************************/
+s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block)
+{
+	u8 Data;
+	u8 BlockShift;
+	u32 BlockOffset;
+	u8 OldVal;
+	u8 NewVal;
+	s32 Status;
+	u32 Target;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Block < InstancePtr->Geometry.NumBlocks);
+
+	Target = Block / InstancePtr->Geometry.NumTargetBlocks;
+
+	BlockOffset = Block >> XNANDPSU_BBT_BLOCK_SHIFT;
+	BlockShift = XNandPsu_BbtBlockShift(Block);
+	Data = InstancePtr->Bbt[BlockOffset];	/* Block information in BBT */
+
+	/*
+	 * Mark the block as bad in the RAM based Bad Block Table
+	 */
+	OldVal = Data;
+	Data &= ~(XNANDPSU_BLOCK_TYPE_MASK << BlockShift);
+	Data |= (XNANDPSU_BLOCK_BAD << BlockShift);
+	NewVal = Data;
+	InstancePtr->Bbt[BlockOffset] = Data;
+
+	/*
+	 * Update the Bad Block Table(BBT) in flash
+	 */
+	if (OldVal != NewVal) {
+		Status = XNandPsu_UpdateBbt(InstancePtr, Target);
+		if (Status != XST_SUCCESS) {
+			goto Out;
+		}
+	}
+
+	Status = XST_SUCCESS;
+Out:
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_bbm.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_bbm.h
new file mode 100644
index 000000000..c128d9657
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_bbm.h
@@ -0,0 +1,211 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_bbm.h
+*
+* This file implements the Bad Block Management(BBM) functionality. This is
+* similar to the Bad Block Management which is a part of the MTD subsystem in
+* Linux.  The factory marked bad blocks are scanned initially and a Bad Block
+* Table(BBT) is created in the memory.  This table is also written to the flash
+* so that upon reboot, the BBT is read back from the flash and loaded into the
+* memory instead of scanning every time. The Bad Block Table(BBT) is written
+* into one of the the last four blocks in the flash memory. The last four
+* blocks are marked as Reserved so that user can't erase/program those blocks.
+*
+* There are two bad block tables, a primary table and a mirror table. The
+* tables are versioned and incrementing version number is used to detect and
+* recover from interrupted updates. Each table is stored in a separate block,
+* beginning in the first page of that block. Only two blocks would be necessary
+* in the absence of bad blocks within the last four; the range of four provides
+* a little slack in case one or two of those blocks is bad. These blocks are
+* marked as reserved and cannot be programmed by the user. A NAND Flash device
+* with 3 or more factory bad blocks in the last 4 cannot be used. The bad block
+* table signature is written into the spare data area of the pages containing
+* bad block table so that upon rebooting the bad block table signature is
+* searched and the bad block table is loaded into RAM. The signature is "Bbt0"
+* for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The
+* version offset follows the signature offset in the spare data area. The
+* version number increments on every update to the bad block table and the
+* version wraps at 0xff.
+*
+* Each block in the Bad Block Table(BBT) is represented by 2 bits.
+* The two bits are encoded as follows in RAM BBT.
+* 0'b00 -> Good Block
+* 0'b01 -> Block is bad due to wear
+* 0'b10 -> Reserved block
+* 0'b11 -> Factory marked bad block
+*
+* While writing to the flash the two bits are encoded as follows.
+* 0'b00 -> Factory marked bad block
+* 0'b01 -> Reserved block
+* 0'b10 -> Block is bad due to wear
+* 0'b11 -> Good Block
+*
+* The user can check for the validity of the block using the API
+* XNandPsu_IsBlockBad and take the action based on the return value. Also user
+* can update the bad block table using XNandPsu_MarkBlockBad API.
+*
+* @note		None
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date        Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 2.0   sb     01/12/2015  Added support for writing BBT signature and version
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
+*			   Modified Bbt Signature and Version Offset value for
+*			   Oob and No-Oob region.
+* 

+*
+******************************************************************************/
+#ifndef XNANDPSU_BBM_H		/* prevent circular inclusions */
+#define XNANDPSU_BBM_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xnandpsu.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Block definitions for RAM based Bad Block Table (BBT)
+ */
+#define XNANDPSU_BLOCK_GOOD			0x0U	/**< Block is good */
+#define XNANDPSU_BLOCK_BAD			0x1U	/**< Block is bad */
+#define XNANDPSU_BLOCK_RESERVED			0x2U	/**< Reserved block */
+#define XNANDPSU_BLOCK_FACTORY_BAD		0x3U	/**< Factory marked bad
+							  block */
+/*
+ * Block definitions for FLASH based Bad Block Table (BBT)
+ */
+#define XNANDPSU_FLASH_BLOCK_GOOD		0x3U	/**< Block is good */
+#define XNANDPSU_FLASH_BLOCK_BAD		0x2U	/**< Block is bad */
+#define XNANDPSU_FLASH_BLOCK_RESERVED		0x1U	/**< Reserved block */
+#define XNANDPSU_FLASH_BLOCK_FAC_BAD	0x0U	/**< Factory marked bad
+							  block */
+
+#define XNANDPSU_BBT_SCAN_2ND_PAGE		0x00000001U	/**< Scan the
+								  second page
+								  for bad block
+								  information
+								  */
+#define XNANDPSU_BBT_DESC_PAGE_OFFSET		0U	/**< Page offset of Bad
+							  Block Table Desc */
+#define XNANDPSU_BBT_DESC_SIG_OFFSET		8U	/**< Bad Block Table
+							  signature offset */
+#define XNANDPSU_BBT_DESC_VER_OFFSET		12U	/**< Bad block Table
+							  version offset */
+#define XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET	0U	/**< Bad Block Table
+							  signature offset in
+							  page memory */
+#define XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET	4U	/**< Bad block Table
+							  version offset in
+							  page memory */
+#define XNANDPSU_BBT_DESC_SIG_LEN		4U	/**< Bad block Table
+							  signature length */
+#define XNANDPSU_BBT_DESC_MAX_BLOCKS		64U	/**< Bad block Table
+							  max blocks */
+
+#define XNANDPSU_BBT_BLOCK_SHIFT		2U	/**< Block shift value
+							  for a block in BBT */
+#define XNANDPSU_BBT_ENTRY_NUM_BLOCKS		4U	/**< Num of blocks in
+							  one BBT entry */
+#define XNANDPSU_BB_PTRN_OFF_SML_PAGE	5U	/**< Bad block pattern
+							  offset in a page */
+#define XNANDPSU_BB_PTRN_LEN_SML_PAGE	1U	/**< Bad block pattern
+							  length */
+#define XNANDPSU_BB_PTRN_OFF_LARGE_PAGE	0U	/**< Bad block pattern
+							  offset in a large
+							  page */
+#define XNANDPSU_BB_PTRN_LEN_LARGE_PAGE	2U	/**< Bad block pattern
+							  length */
+#define XNANDPSU_BB_PATTERN			0xFFU	/**< Bad block pattern
+							  to search in a page
+							  */
+#define XNANDPSU_BLOCK_TYPE_MASK		0x03U	/**< Block type mask */
+#define XNANDPSU_BLOCK_SHIFT_MASK		0x06U	/**< Block shift mask
+							  for a Bad Block Table
+							  entry byte */
+
+#define XNANDPSU_ONDIE_SIG_OFFSET		0x4U
+#define XNANDPSU_ONDIE_VER_OFFSET		0x14U
+
+#define XNANDPSU_BBT_VERSION_LENGTH	1U
+#define XNANDPSU_BBT_SIG_LENGTH		4U
+
+#define XNANDPSU_BBT_BUF_LENGTH		((XNANDPSU_MAX_BLOCKS >> 		\
+					 XNANDPSU_BBT_BLOCK_SHIFT) +	\
+					(XNANDPSU_BBT_DESC_SIG_OFFSET +	\
+					 XNANDPSU_BBT_SIG_LENGTH +	\
+					 XNANDPSU_BBT_VERSION_LENGTH))
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro returns the Block shift value corresponding to a Block.
+*
+* @param        Block is the block number.
+*
+* @return       Block shift value
+*
+* @note         None.
+*
+*****************************************************************************/
+#define XNandPsu_BbtBlockShift(Block) \
+			((u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr);
+
+s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
+
+s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block);
+
+s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_g.c
new file mode 100644
index 000000000..8d75e6dbb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_g.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_g.c
+*
+* This file contains a configuration table where each entry is a configuration
+* structure for an XNandPsu device in the system.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 1.0   nm     06/02/2014  Changed the copyright to new copyright
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xparameters.h"
+#include "xnandpsu.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/**
+ * Each XNandPsu device in the system has an entry in this table.
+ */
+XNandPsu_Config XNandPsu_ConfigTable[] = {
+	{
+		0U,
+		XPAR_XNANDPSU_0_BASEADDR
+	}
+};
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_hw.h
new file mode 100644
index 000000000..f59b5b661
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_hw.h
@@ -0,0 +1,504 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_hw.h
+*
+* This file contains identifiers and low-level macros/functions for the Arasan
+* NAND flash controller driver.
+*
+* See xnandpsu.h for more information.
+*
+* @note		None
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date        Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First Release
+* 2.0   sb     11/04/2014  Changed XNANDPSU_ECC_SLC_MLC_MASK to
+*			   XNANDPSU_ECC_HAMMING_BCH_MASK.
+* 

+*
+******************************************************************************/
+
+#ifndef XNANDPSU_HW_H		/* prevent circular inclusions */
+#define XNANDPSU_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/************************** Register Offset Definitions **********************/
+
+#define XNANDPSU_PKT_OFFSET		0x00U	/**< Packet Register */
+#define XNANDPSU_MEM_ADDR1_OFFSET	0x04U	/**< Memory Address
+						  Register 1 */
+#define XNANDPSU_MEM_ADDR2_OFFSET	0x08U	/**< Memory Address
+						  Register 2 */
+#define XNANDPSU_CMD_OFFSET		0x0CU	/**< Command Register */
+#define XNANDPSU_PROG_OFFSET		0x10U	/**< Program Register */
+#define XNANDPSU_INTR_STS_EN_OFFSET	0x14U	/**< Interrupt Status
+						     Enable Register */
+#define XNANDPSU_INTR_SIG_EN_OFFSET	0x18U	/**< Interrupt Signal
+						     Enable Register */
+#define XNANDPSU_INTR_STS_OFFSET	0x1CU	/**< Interrupt Status
+						  Register */
+#define XNANDPSU_READY_BUSY_OFFSET	0x20U	/**< Ready/Busy status
+						  Register */
+#define XNANDPSU_FLASH_STS_OFFSET	0x28U	/**< Flash Status Register */
+#define XNANDPSU_TIMING_OFFSET		0x2CU	/**< Timing Register */
+#define XNANDPSU_BUF_DATA_PORT_OFFSET	0x30U	/**< Buffer Data Port
+						  Register */
+#define XNANDPSU_ECC_OFFSET		0x34U	/**< ECC Register */
+#define XNANDPSU_ECC_ERR_CNT_OFFSET	0x38U	/**< ECC Error Count
+						  Register */
+#define XNANDPSU_ECC_SPR_CMD_OFFSET	0x3CU	/**< ECC Spare Command
+						     Register */
+#define XNANDPSU_ECC_CNT_1BIT_OFFSET	0x40U	/**< Error Count 1bit
+						  Register */
+#define XNANDPSU_ECC_CNT_2BIT_OFFSET	0x44U	/**< Error Count 2bit
+						  Register */
+#define XNANDPSU_ECC_CNT_3BIT_OFFSET	0x48U	/**< Error Count 3bit
+						  Register */
+#define XNANDPSU_ECC_CNT_4BIT_OFFSET	0x4CU	/**< Error Count 4bit
+						  Register */
+#define XNANDPSU_CPU_REL_OFFSET		0x58U	/**< CPU Release Register */
+#define XNANDPSU_ECC_CNT_5BIT_OFFSET	0x5CU	/**< Error Count 5bit
+						  Register */
+#define XNANDPSU_ECC_CNT_6BIT_OFFSET	0x60U	/**< Error Count 6bit
+						  Register */
+#define XNANDPSU_ECC_CNT_7BIT_OFFSET	0x64U	/**< Error Count 7bit
+						  Register */
+#define XNANDPSU_ECC_CNT_8BIT_OFFSET	0x68U	/**< Error Count 8bit
+						  Register */
+#define XNANDPSU_DATA_INTF_OFFSET	0x6CU	/**< Data Interface Register */
+#define XNANDPSU_DMA_SYS_ADDR0_OFFSET	0x50U	/**< DMA System Address 0
+						  Register */
+#define XNANDPSU_DMA_SYS_ADDR1_OFFSET	0x24U	/**< DMA System Address 1
+						  Register */
+#define XNANDPSU_DMA_BUF_BND_OFFSET	0x54U	/**< DMA Buffer Boundary
+						  Register */
+#define XNANDPSU_SLV_DMA_CONF_OFFSET	0x80U	/**< Slave DMA Configuration
+						  Register */
+
+/** @name Packet Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_PKT_PKT_SIZE_MASK		0x000007FFU /**< Packet Size */
+#define XNANDPSU_PKT_PKT_CNT_MASK		0x00FFF000U /**< Packet Count*/
+#define XNANDPSU_PKT_PKT_CNT_SHIFT		12U /**< Packet Count Shift */
+/* @} */
+
+/** @name Memory Address Register 1 bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK	0x0000FFFFU /**< Column Address
+							     Mask */
+#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK		0xFFFF0000U /**< Page, Block
+							     Address Mask */
+#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT	16U /**< Page Shift */
+/* @} */
+
+/** @name Memory Address Register 2 bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK	0x000000FFU /**< Memory Address
+								*/
+#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK	0x01000000U /**< Bus Width */
+#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK	0x0E000000U /**< BCH Mode
+							     Value */
+#define XNANDPSU_MEM_ADDR2_MODE_MASK		0x30000000U /**< Flash
+							     Connection Mode */
+#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK	0xC0000000U /**< Chip Select */
+#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT	30U	/**< Chip select
+							shift */
+#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT	24U	/**< Bus width shift */
+#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT	25U
+/* @} */
+
+/** @name Command Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_CMD_CMD1_MASK			0x000000FFU /**< 1st Cycle
+							     Command */
+#define XNANDPSU_CMD_CMD2_MASK			0x0000FF00U /**< 2nd Cycle
+							     Command */
+#define XNANDPSU_CMD_PG_SIZE_MASK		0x03800000U /**< Page Size */
+#define XNANDPSU_CMD_DMA_EN_MASK		0x0C000000U /**< DMA Enable
+							     Mode */
+#define XNANDPSU_CMD_ADDR_CYCLES_MASK		0x70000000U /**< Number of
+							     Address Cycles */
+#define XNANDPSU_CMD_ECC_ON_MASK		0x80000000U /**< ECC ON/OFF */
+#define XNANDPSU_CMD_CMD2_SHIFT			8U /**< 2nd Cycle Command
+						    Shift */
+#define XNANDPSU_CMD_PG_SIZE_SHIFT		23U /**< Page Size Shift */
+#define XNANDPSU_CMD_DMA_EN_SHIFT		26U /**< DMA Enable Shift */
+#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT		28U /**< Number of Address
+						     Cycles Shift */
+#define XNANDPSU_CMD_ECC_ON_SHIFT		31U /**< ECC ON/OFF */
+/* @} */
+
+/** @name Program Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_PROG_RD_MASK			0x00000001U /**< Read */
+#define XNANDPSU_PROG_MUL_DIE_MASK		0x00000002U /**< Multi Die */
+#define XNANDPSU_PROG_BLK_ERASE_MASK		0x00000004U /**< Block Erase */
+#define XNANDPSU_PROG_RD_STS_MASK		0x00000008U /**< Read Status */
+#define XNANDPSU_PROG_PG_PROG_MASK		0x00000010U /**< Page Program */
+#define XNANDPSU_PROG_MUL_DIE_RD_MASK		0x00000020U /**< Multi Die Rd */
+#define XNANDPSU_PROG_RD_ID_MASK		0x00000040U /**< Read ID */
+#define XNANDPSU_PROG_RD_PRM_PG_MASK		0x00000080U /**< Read Param
+							     Page */
+#define XNANDPSU_PROG_RST_MASK			0x00000100U /**< Reset */
+#define XNANDPSU_PROG_GET_FEATURES_MASK		0x00000200U /**< Get Features */
+#define XNANDPSU_PROG_SET_FEATURES_MASK		0x00000400U /**< Set Features */
+#define XNANDPSU_PROG_RD_UNQ_ID_MASK		0x00000800U /**< Read Unique
+							     ID */
+#define XNANDPSU_PROG_RD_STS_ENH_MASK		0x00001000U /**< Read Status
+							     Enhanced */
+#define XNANDPSU_PROG_RD_INTRLVD_MASK		0x00002000U /**< Read
+							     Interleaved */
+#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK	0x00004000U /**< Change Read
+								Column
+								Enhanced */
+#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK	0x00008000U /**< Copy Back
+								Interleaved */
+#define XNANDPSU_PROG_RD_CACHE_START_MASK	0x00010000U /**< Read Cache
+							     Start */
+#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK		0x00020000U /**< Read Cache
+							     Sequential */
+#define XNANDPSU_PROG_RD_CACHE_RAND_MASK	0x00040000U /**< Read Cache
+								Random */
+#define XNANDPSU_PROG_RD_CACHE_END_MASK		0x00080000U /**< Read Cache
+							     End */
+#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK	0x00100000U /**< Small Data
+							     Move */
+#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK	0x00200000U /**< Change Row
+								Address */
+#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK	0x00400000U /**< Change Row
+								Address End */
+#define XNANDPSU_PROG_RST_LUN_MASK		0x00800000U /**< Reset LUN */
+#define XNANDPSU_PROG_PGM_PG_CLR_MASK		0x01000000U /**< Enhanced
+							     Program Page
+							     Register Clear */
+#define XNANDPSU_PROG_VOL_SEL_MASK		0x02000000U /**< Volume Select */
+#define XNANDPSU_PROG_ODT_CONF_MASK		0x04000000U /**< ODT Configure */
+/* @} */
+
+/** @name Interrupt Status Enable Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
+								     Write Ready
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
+								     Read Ready
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								     Complete
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
+								     Bit Error
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single
+								     Bit Error
+								     Status
+								     Enable,
+								     BCH Detect
+								     Error
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error
+								     AHB Status
+								     Enable */
+/* @} */
+
+/** @name Interrupt Signal Enable Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
+								     Write Ready
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
+								     Read Ready
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								     Complete
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
+								     Bit Error
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single
+								     Bit Error
+								     Signal
+								     Enable,
+								     BCH Detect
+								     Error
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error
+								     AHB Signal
+								     Enable */
+/* @} */
+
+/** @name Interrupt Status Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
+								     Write
+								     Ready */
+#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
+								     Read
+								     Ready */
+#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								     Complete */
+#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
+								    Bit Error */
+#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK		0x00000010U /**< Single
+								     Bit Error,
+								     BCH Detect
+								     Error */
+#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK		0x00000040U /**< DMA
+								     Interrupt
+								     */
+#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK		0x00000080U /**< Error
+								     AHB */
+/* @} */
+
+/** @name Interrupt bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer Write
+								Ready Status
+								Enable */
+#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer Read
+								Ready Status
+								Enable */
+#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								Complete Status
+								Enable */
+#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi Bit Error
+								Status Enable */
+#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single Bit Error
+								Status Enable,
+								BCH Detect Error
+								Status Enable */
+#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA Status
+								Enable */
+#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error AHB Status
+								Enable */
+/* @} */
+
+/** @name ID2 Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ID2_DEVICE_ID2_MASK		0x000000FFU /**< MSB Device ID */
+/* @} */
+
+/** @name Flash Status Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_FLASH_STS_FLASH_STS_MASK	0x0000FFFFU /**< Flash Status
+							     Value */
+/* @} */
+
+/** @name Timing Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_TIMING_TCCS_TIME_MASK		0x00000003U /**< Change column
+							     setup time */
+#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK	0x00000004U /**< Slow/Fast device
+							     */
+#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK	0x00000078U /**< Write/Read data
+							     transaction value
+							     */
+#define XNANDPSU_TIMING_TADL_TIME_MASK		0x00007F80U /**< Address latch
+							     enable to Data
+							     loading time */
+/* @} */
+
+/** @name ECC Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ECC_ADDR_MASK			0x0000FFFFU /**< ECC address */
+#define XNANDPSU_ECC_SIZE_MASK			0x01FF0000U /**< ECC size */
+#define XNANDPSU_ECC_HAMMING_BCH_MASK		0x02000000U /**< Hamming/BCH
+							     support */
+/* @} */
+
+/** @name ECC Error Count Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK	0x000000FFU /**< Packet
+								     bound error
+								     count */
+#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK	0x0000FF00U /**< Page
+								     bound error
+								     count */
+/* @} */
+
+/** @name ECC Spare Command Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK		0x000000FFU /**< ECC
+								     spare
+								     command */
+#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK	0x70000000U /**< Number
+								     of ECC/
+								     spare
+								     address
+								     cycles */
+/* @} */
+
+/** @name Data Interface Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_DATA_INTF_SDR_MASK		0x00000007U /**< SDR mode */
+#define XNANDPSU_DATA_INTF_NVDDR_MASK		0x00000038U /**< NVDDR mode */
+#define XNANDPSU_DATA_INTF_NVDDR2_MASK		0x000001C0U /**< NVDDR2 mode */
+#define XNANDPSU_DATA_INTF_DATA_INTF_MASK	0x00000600U /**< Data
+							     Interface */
+#define XNANDPSU_DATA_INTF_NVDDR_SHIFT		3U /**< NVDDR mode shift */
+#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT	9U /**< Data Interface Shift */
+/* @} */
+
+/** @name DMA Buffer Boundary Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_DMA_BUF_BND_BND_MASK		0x00000007U /**< DMA buffer
+							     boundary */
+#define XNANDPSU_DMA_BUF_BND_4K			0x0U
+#define XNANDPSU_DMA_BUF_BND_8K			0x1U
+#define XNANDPSU_DMA_BUF_BND_16K		0x2U
+#define XNANDPSU_DMA_BUF_BND_32K		0x3U
+#define XNANDPSU_DMA_BUF_BND_64K		0x4U
+#define XNANDPSU_DMA_BUF_BND_128K		0x5U
+#define XNANDPSU_DMA_BUF_BND_256K		0x6U
+#define XNANDPSU_DMA_BUF_BND_512K		0x7U
+/* @} */
+
+/** @name Slave DMA Configuration Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK		0x00000001U /**< Slave
+								     DMA
+								     Transfer
+								     Direction
+								     */
+#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK	0x001FFFFEU /**< Slave
+								     DMA
+								     Transfer
+								     Count */
+#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK	0x00E00000U /**< Slave
+								     DMA
+								     Burst
+								     Size */
+#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK	0x0F000000U /**< DMA
+								     Timeout
+								     Counter
+								     Value */
+#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK		0x10000000U /**< Slave
+								     DMA
+								     Enable */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the base address of controller registers.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XNandPsu_ReadReg(BaseAddress, RegOffset)			\
+			Xil_In32((BaseAddress) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	BaseAddress is the the base address of controller registers.
+* @param	RegOffset is the register offset to be written.
+* @param	Data is the the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XNandPsu_WriteReg(BaseAddress, RegOffset, Data)			\
+			Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XNANDPSU_HW_H end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_onfi.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_onfi.c
new file mode 100644
index 000000000..6dbf31030
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_onfi.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_onfi.c
+*
+* This file contains the implementation of ONFI specific functions.
+*
+* @note		None
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xnandpsu_onfi.h"
+#include "xnandpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* This function calculates ONFI paramater page CRC.
+*
+* @param	Parambuf is a pointer to the ONFI paramater page buffer.
+* @param	StartOff is the starting offset in buffer to calculate CRC.
+* @param	Length is the number of bytes for which CRC is calculated.
+*
+* @return
+*		CRC value.
+* @note
+*		None.
+*
+******************************************************************************/
+u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length)
+{
+	const u32 CrcInit = 0x4F4EU;
+	const u32 Order = 16U;
+	const u32 Polynom = 0x8005U;
+	u32 i, j, c, Bit;
+	u32 Crc = CrcInit;
+	u32 DataIn;
+	u32 DataByteCount = 0U;
+	u32 CrcMask, CrcHighBit;
+
+	CrcMask = ((u32)(((u32)1 << (Order - (u32)1)) -(u32)1) << (u32)1) | (u32)1;
+	CrcHighBit = (u32)((u32)1 << (Order - (u32)1));
+	/*
+	 * CRC covers the data bytes between byte 0 and byte 253
+	 * (ONFI 1.0, section 5.4.1.36)
+	 */
+	for(i = StartOff; i < Length; i++) {
+		DataIn = ParamBuf[i];
+		c = (u32)DataIn;
+		DataByteCount++;
+		for(j = 0x80U; j; j >>= 1U) {
+			Bit = Crc & CrcHighBit;
+			Crc <<= 1U;
+			if ((c & j) != 0U) {
+				Bit ^= CrcHighBit;
+			}
+			if (Bit != 0U) {
+				Crc ^= Polynom;
+			}
+		}
+		Crc &= CrcMask;
+	}
+	return Crc;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_onfi.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_onfi.h
new file mode 100644
index 000000000..41da5569c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_onfi.h
@@ -0,0 +1,340 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_onfi.h
+*
+* This file defines all the ONFI 3.1 specific commands and values.
+*
+* @note		None
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 

+*
+******************************************************************************/
+#ifndef XNANDPSU_ONFI_H		/* prevent circular inclusions */
+#define XNANDPSU_ONFI_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Standard ONFI 3.1 Commands
+ */
+/*
+ * ONFI 3.1 Mandatory Commands
+ */
+#define ONFI_CMD_RD1			0x00U	/**< Read (1st cycle) */
+#define ONFI_CMD_RD2			0x30U	/**< Read (2nd cycle) */
+#define ONFI_CMD_CHNG_RD_COL1		0x05U	/**< Change Read Column
+						  (1st cycle) */
+#define ONFI_CMD_CHNG_RD_COL2		0xE0U	/**< Change Read Column
+						  (2nd cycle) */
+#define ONFI_CMD_BLK_ERASE1		0x60U	/**< Block Erase (1st cycle) */
+#define ONFI_CMD_BLK_ERASE2		0xD0U	/**< Block Erase (2nd cycle) */
+#define ONFI_CMD_RD_STS			0x70U	/**< Read Status */
+#define ONFI_CMD_PG_PROG1		0x80U	/**< Page Program(1st cycle) */
+#define ONFI_CMD_PG_PROG2		0x10U	/**< Page Program(2nd cycle) */
+#define ONFI_CMD_CHNG_WR_COL		0x85U	/**< Change Write Column */
+#define ONFI_CMD_RD_ID			0x90U	/**< Read ID */
+#define ONFI_CMD_RD_PRM_PG		0xECU	/**< Read Parameter Page */
+#define ONFI_CMD_RST			0xFFU	/**< Reset */
+/*
+ * ONFI 3.1 Optional Commands
+ */
+#define ONFI_CMD_MUL_RD1		0x00U	/**< Multiplane Read
+						  (1st cycle) */
+#define ONFI_CMD_MUL_RD2		0x32U	/**< Multiplane Read
+						  (2nd cycle) */
+#define ONFI_CMD_CPBK_RD1		0x00U	/**< Copyback Read
+						  (1st cycle) */
+#define ONFI_CMD_CPBK_RD2		0x35U	/**< Copyback Read
+						  (2nd cycle) */
+#define ONFI_CMD_CHNG_RD_COL_ENHCD1	0x06U	/**< Change Read Column
+						  Enhanced (1st cycle) */
+#define ONFI_CMD_CHNG_RD_COL_ENHCD2	0xE0U	/**< Change Read Column
+						  Enhanced (2nd cycle) */
+#define ONFI_CMD_RD_CACHE_RND1		0x00U	/**< Read Cache Random
+						  (1st cycle) */
+#define ONFI_CMD_RD_CACHE_RND2		0x31U	/**< Read Cache Random
+						  (2nd cycle) */
+#define ONFI_CMD_RD_CACHE_SEQ		0x31U	/**< Read Cache Sequential */
+#define ONFI_CMD_RD_CACHE_END		0x3FU	/**< Read Cache End */
+#define ONFI_CMD_MUL_BLK_ERASE1		0x60U	/**< Multiplane Block Erase
+						  (1st cycle) */
+#define ONFI_CMD_MUL_BLK_ERASE2		0xD1U	/**< Multiplane Block Erase
+						  (2nd cycle) */
+#define ONFI_CMD_RD_STS_ENHCD		0x78U	/**< Read Status Enhanced */
+#define ONFI_CMD_BLK_ERASE_INTRLVD2	0xD1U	/**< Block Erase Interleaved
+						  (2nd cycle) */
+#define ONFI_CMD_MUL_PG_PROG1		0x80U	/**< Multiplane Page Program
+						  (1st cycle) */
+#define ONFI_CMD_MUL_PG_PROG2		0x11U	/**< Multiplane Page Program
+						  (2nd cycle) */
+#define ONFI_CMD_PG_CACHE_PROG1		0x80U	/**< Page Cache Program
+						  (1st cycle) */
+#define ONFI_CMD_PG_CACHE_PROG2		0x15U	/**< Page Cache Program
+						  (2nd cycle) */
+#define ONFI_CMD_CPBK_PROG1		0x85U	/**< Copyback Program
+						  (1st cycle) */
+#define ONFI_CMD_CPBK_PROG2		0x10U	/**< Copyback Program
+						  (2nd cycle) */
+#define ONFI_CMD_MUL_CPBK_PROG1		0x85U	/**< Multiplane Copyback
+						  Program (1st cycle) */
+#define ONFI_CMD_MUL_CPBK_PROG2		0x10U	/**< Multiplane Copyback
+						  Program (2nd cycle) */
+#define ONFI_CMD_SMALL_DATA_MV1		0x85U	/**< Small Data Move
+						  (1st cycle) */
+#define ONFI_CMD_SMALL_DATA_MV2		0x10U	/**< Small Data Move
+						  (2nd cycle) */
+#define ONFI_CMD_CHNG_ROW_ADDR		0x85U	/**< Change Row Address */
+#define ONFI_CMD_VOL_SEL		0xE1U	/**< Volume Select */
+#define ONFI_CMD_ODT_CONF		0xE2U	/**< ODT Configure */
+#define ONFI_CMD_RD_UNIQID		0xEDU	/**< Read Unique ID */
+#define ONFI_CMD_GET_FEATURES		0xEEU	/**< Get Features */
+#define ONFI_CMD_SET_FEATURES		0xEFU	/**< Set Features */
+#define ONFI_CMD_LUN_GET_FEATURES	0xD4U	/**< LUN Get Features */
+#define ONFI_CMD_LUN_SET_FEATURES	0xD5U	/**< LUN Set Features */
+#define ONFI_CMD_RST_LUN		0xFAU	/**< Reset LUN */
+#define ONFI_CMD_SYN_RST		0xFCU	/**< Synchronous Reset */
+
+/*
+ * ONFI Status Register bit offsets
+ */
+#define ONFI_STS_FAIL			0x01U	/**< FAIL */
+#define ONFI_STS_FAILC			0x02U	/**< FAILC */
+#define ONFI_STS_CSP			0x08U	/**< CSP */
+#define ONFI_STS_VSP			0x10U	/**< VSP */
+#define ONFI_STS_ARDY			0x20U	/**< ARDY */
+#define ONFI_STS_RDY			0x40U	/**< RDY */
+#define ONFI_STS_WP			0x80U	/**< WP_n */
+
+/*
+ * ONFI constants
+ */
+#define ONFI_CRC_LEN			254U	/**< ONFI CRC Buf Length */
+#define ONFI_PRM_PG_LEN			256U	/**< Parameter Page Length */
+#define ONFI_MND_PRM_PGS		3U	/**< Number of mandatory
+						  parameter pages */
+#define ONFI_SIG_LEN			4U	/**< Signature Length */
+#define ONFI_CMD_INVALID		0x00U	/**< Invalid Command */
+
+#define ONFI_READ_ID_LEN		4U	/**< ONFI ID length */
+#define ONFI_READ_ID_ADDR		0x20U	/**< ONFI Read ID Address */
+#define ONFI_READ_ID_ADDR_CYCLES	1U	/**< ONFI Read ID Address
+						  cycles */
+
+#define ONFI_PRM_PG_ADDR_CYCLES		1U	/**< ONFI Read Parameter page
+						  address cycles */
+
+/**
+ * This enum defines the ONFI 3.1 commands.
+ */
+enum OnfiCommandList {
+	READ=0,				/**< Read */
+	MULTIPLANE_READ,		/**< Multiplane Read */
+	COPYBACK_READ,			/**< Copyback Read */
+	CHANGE_READ_COLUMN,		/**< Change Read Column */
+	CHANGE_READ_COLUMN_ENHANCED,	/**< Change Read Column Enhanced */
+	READ_CACHE_RANDOM,		/**< Read Cache Random */
+	READ_CACHE_SEQUENTIAL,		/**< Read Cache Sequential */
+	READ_CACHE_END,			/**< Read Cache End */
+	BLOCK_ERASE,			/**< Block Erase */
+	MULTIPLANE_BLOCK_ERASE,		/**< Multiplane Block Erase */
+	READ_STATUS,			/**< Read Status */
+	READ_STATUS_ENHANCED,		/**< Read Status Enhanced */
+	PAGE_PROGRAM,			/**< Page Program */
+	MULTIPLANE_PAGE_PROGRAM,	/**< Multiplane Page Program */
+	PAGE_CACHE_PROGRAM,		/**< Page Cache Program */
+	COPYBACK_PROGRAM,		/**< Copyback Program */
+	MULTIPLANE_COPYBACK_PROGRAM,	/**< Multiplance Copyback Program */
+	SMALL_DATA_MOVE,		/**< Small Data Move */
+	CHANGE_WRITE_COLUMN,		/**< Change Write Column */
+	CHANGE_ROW_ADDR,		/**< Change Row Address */
+	READ_ID,			/**< Read ID */
+	VOLUME_SELECT,			/**< Volume Select */
+	ODT_CONFIGURE,			/**< ODT Configure */
+	READ_PARAM_PAGE,		/**< Read Parameter Page */
+	READ_UNIQUE_ID,			/**< Read Unique ID */
+	GET_FEATURES,			/**< Get Features */
+	SET_FEATURES,			/**< Set Features */
+	LUN_GET_FEATURES,		/**< LUN Get Features */
+	LUN_SET_FEATURES,		/**< LUN Set Features */
+	RESET_LUN,			/**< Reset LUN */
+	SYN_RESET,			/**< Synchronous Reset */
+	RESET,				/**< Reset */
+	MAX_CMDS			/**< Dummy Command */
+};
+
+/**************************** Type Definitions *******************************/
+/*
+ * Parameter page structure of ONFI 3.1 specification.
+ */
+typedef struct {
+	/*
+	 * Revision information and features block
+	 */
+	u8 Signature[4];		/**< Parameter page signature */
+	u16 Revision;			/**< Revision Number */
+	u16 Features;			/**< Features supported */
+	u16 OptionalCmds;		/**< Optional commands supported */
+	u8 JedecJtgPrmAdvCmd;		/**< ONFI JEDEC JTG primary advanced
+					  command support */
+	u8 Reserved0;			/**< Reserved (11) */
+	u16 ExtParamPageLen;		/**< Extended Parameter Page Length */
+	u8 NumOfParamPages;		/**< Number of Parameter Pages */
+	u8 Reserved1[17];		/**< Reserved (15-31) */
+	/*
+	 * Manufacturer information block
+	 */
+	u8 DeviceManufacturer[12];	/**< Device manufacturer */
+	u8 DeviceModel[20];		/**< Device model */
+	u8 JedecManufacturerId;		/**< JEDEC Manufacturer ID */
+	u8 DateCode[2];			/**< Date code */
+	u8 Reserved2[13];		/**< Reserved (67-79) */
+	/*
+	 * Memory organization block
+	*/
+	u32 BytesPerPage;		/**< Number of data bytes per page */
+	u16 SpareBytesPerPage;		/**< Number of spare bytes per page */
+	u32 BytesPerPartialPage;	/**< Number of data bytes per
+					  partial page */
+	u16 SpareBytesPerPartialPage;	/**< Number of spare bytes per
+					  partial page */
+	u32 PagesPerBlock;		/**< Number of pages per block */
+	u32 BlocksPerLun;		/**< Number of blocks per LUN */
+	u8 NumLuns;			/**< Number of LUN's */
+	u8 AddrCycles;			/**< Number of address cycles */
+	u8 BitsPerCell;			/**< Number of bits per cell */
+	u16 MaxBadBlocksPerLun;		/**< Bad blocks maximum per LUN */
+	u16 BlockEndurance;		/**< Block endurance */
+	u8 GuaranteedValidBlock;	/**< Guaranteed valid blocks at
+					  beginning of target */
+	u16 BlockEnduranceGVB;		/**< Block endurance for guaranteed
+					  valid block */
+	u8 ProgramsPerPage;		/**< Number of programs per page */
+	u8 PartialProgAttr;		/**< Partial programming attributes */
+	u8 EccBits;			/**< Number of bits ECC
+					  correctability */
+	u8 PlaneAddrBits;		/**< Number of plane address bits */
+	u8 PlaneOperationAttr;		/**< Multi-plane operation
+					  attributes */
+	u8 EzNandSupport;		/**< EZ NAND support */
+	u8 Reserved3[12];		/**< Reserved (116 - 127) */
+	/*
+	 * Electrical parameters block
+	*/
+	u8 IOPinCapacitance;		/**< I/O pin capacitance, maximum */
+	u16 SDRTimingMode;		/**< SDR Timing mode support */
+	u16 SDRPagecacheTimingMode;	/**< SDR Program cache timing mode */
+	u16 TProg;			/**< Maximum page program time */
+	u16 TBers;			/**< Maximum block erase time */
+	u16 TR;				/**< Maximum page read time */
+	u16 TCcs;			/**< Maximum change column setup
+					  time */
+	u8 NVDDRTimingMode;		/**< NVDDR timing mode support */
+	u8 NVDDR2TimingMode;		/**< NVDDR2 timing mode support */
+	u8 SynFeatures;			/**< NVDDR/NVDDR2 features */
+	u16 ClkInputPinCap;		/**< CLK input pin capacitance */
+	u16 IOPinCap;			/**< I/O pin capacitance */
+	u16 InputPinCap;		/**< Input pin capacitance typical */
+	u8 InputPinCapMax;		/**< Input pin capacitance maximum */
+	u8 DrvStrength;			/**< Driver strength support */
+	u16 TMr;			/**< Maximum multi-plane read time */
+	u16 TAdl;			/**< Program page register clear
+					  enhancement value */
+	u16 TEr;			/**< Typical page read time for
+					  EZ NAND */
+	u8 NVDDR2Features;		/**< NVDDR2 Features */
+	u8 NVDDR2WarmupCycles;		/**< NVDDR2 Warmup Cycles */
+	u8 Reserved4[4];		/**< Reserved (160 - 163) */
+	/*
+	 * Vendor block
+	 */
+	u16 VendorRevisionNum;		/**< Vendor specific revision number */
+	u8 VendorSpecific[88];		/**< Vendor specific */
+	u16 Crc;			/**< Integrity CRC */
+}__attribute__((packed))OnfiParamPage;
+
+/*
+ * ONFI extended parameter page structure.
+ */
+typedef struct {
+	u16 Crc;
+	u8 Sig[4];
+	u8 Reserved1[10];
+	u8 Section0Type;
+	u8 Section0Len;
+	u8 Section1Type;
+	u8 Section1Len;
+	u8 ResSection[12];
+	u8 SectionData[256];
+}__attribute__((packed))OnfiExtPrmPage;
+
+/*
+ * Driver extended parameter page information.
+ */
+typedef struct {
+	u8 NumBitsEcc;
+	u8 CodeWordSize;
+	u16 MaxBadBlocks;
+	u16 BlockEndurance;
+	u16 Reserved;
+}__attribute__((packed))OnfiExtEccBlock;
+
+typedef struct {
+	u8 Command1;			/**< Command Cycle 1 */
+	u8 Command2;			/**< Command Cycle 2 */
+} OnfiCmdFormat;
+
+extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
+
+/************************** Function Prototypes ******************************/
+
+u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XNANDPSU_ONFI_H end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_sinit.c
new file mode 100644
index 000000000..c3e56ff04
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/nandpsu_v1_0/src/xnandpsu_sinit.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_sinit.c
+*
+* The implementation of the XNandPsu driver's static initialzation
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xnandpsu.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+extern XNandPsu_Config XNandPsu_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the controller configuration based on the unique controller ID. A
+* table contains the configuration info for each controller in the system.
+*
+* @param	DeviceID is the ID of the controller to look up the
+*		configuration for.
+*
+* @return
+*		A pointer to the configuration found or NULL if the specified
+*		controller ID was not found.
+*
+******************************************************************************/
+XNandPsu_Config *XNandPsu_LookupConfig(u16 DeviceID)
+{
+	XNandPsu_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_XNANDPSU_NUM_INSTANCES; Index++) {
+		if (XNandPsu_ConfigTable[Index].DeviceId == DeviceID) {
+			CfgPtr = &XNandPsu_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XNandPsu_Config *)CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/Makefile
new file mode 100644
index 000000000..88a66dd93
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xqspipsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling qspipsu"
+
+xqspipsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xqspipsu_includes
+
+xqspipsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu.c
new file mode 100644
index 000000000..9be11b8f1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu.c
@@ -0,0 +1,1228 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu.c
+*
+* This file implements the functions required to use the QSPIPSU hardware to
+* perform a transfer. These are accessible to the user via xqspipsu.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+*                    Clear and disbale DMA interrupts/status in abort.
+*                    Use DMA DONE bit instead of BUSY as recommended.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspipsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+			unsigned ByteCount);
+static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode);
+static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+			u32 *GenFifoEntry);
+static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg, int Size);
+static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg);
+static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr);
+static inline int XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg, int Index);
+static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr);
+static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg, int Size);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPsu instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific QSPIPSU device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is busy, disallow the initialize and return a status
+	 * indicating it is already started. This allows the user to stop the
+	 * device and re-initialize, but prevents a user from inadvertently
+	 * initializing. This assumes the busy flag is cleared at startup.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/* Set some default values. */
+	InstancePtr->IsBusy = FALSE;
+
+	InstancePtr->Config.BaseAddress = EffectiveAddr + XQSPIPSU_OFFSET;
+	InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+	InstancePtr->StatusHandler = StubStatusHandler;
+
+	/* Other instance variable initializations */
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->GenFifoBufferPtr = NULL;
+	InstancePtr->TxBytes = 0;
+	InstancePtr->RxBytes = 0;
+	InstancePtr->GenFifoEntries = 0;
+	InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
+	InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
+	InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
+	InstancePtr->IsUnaligned = 0;
+
+	/* Select QSPIPSU */
+	XQspiPsu_Select(InstancePtr);
+
+	/*
+	 * Reset the QSPIPSU device to get it into its initial state. It is
+	 * expected that device configuration will take place after this
+	 * initialization is done, but before the device is started.
+	 */
+	XQspiPsu_Reset(InstancePtr);
+
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPIPSU device. Reset must only be called after the driver has
+* been initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPIPSU device after the reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPsu_Reset(XQspiPsu *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Abort any transfer that is in progress */
+	XQspiPsu_Abort(InstancePtr);
+
+	/* Default value to config register */
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_CFG_OFFSET);
+
+	/* DMA mode */
+	ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+	ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
+	/* Manual start */
+	ConfigReg |= XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK;
+	/* Little endain by default */
+	ConfigReg &= ~XQSPIPSU_CFG_ENDIAN_MASK;
+	/* Disable poll timeout */
+	ConfigReg &= ~XQSPIPSU_CFG_EN_POLL_TO_MASK;
+	/* Set hold bit */
+	ConfigReg |= XQSPIPSU_CFG_WP_HOLD_MASK;
+	/* Clear prescalar by default */
+	ConfigReg &= ~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK;
+	/* CPOL CPHA 00 */
+	ConfigReg &= ~XQSPIPSU_CFG_CLK_PHA_MASK;
+	ConfigReg &= ~XQSPIPSU_CFG_CLK_POL_MASK;
+
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_CFG_OFFSET, ConfigReg);
+
+	/* Set by default to allow for high frequencies */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_LPBK_DLY_ADJ_OFFSET,
+		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_LPBK_DLY_ADJ_OFFSET) |
+			XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK);
+
+	/* Reset thresholds */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_TX_THRESHOLD_OFFSET,
+		XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_RX_THRESHOLD_OFFSET,
+		XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GF_THRESHOLD_OFFSET,
+		XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL);
+
+	/* DMA init */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET,
+			XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None.
+*
+* @note
+*
+******************************************************************************/
+void XQspiPsu_Abort(XQspiPsu *InstancePtr)
+{
+
+	u32 IntrStatus, ConfigReg;
+
+	IntrStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_ISR_OFFSET);
+
+	/* Clear and disable interrupts */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_ISR_OFFSET, IntrStatus | XQSPIPSU_ISR_WR_TO_CLR_MASK);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
+		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET));
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_STS_OFFSET,
+			XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_STS_OFFSET) |
+				XQSPIPSU_QSPIDMA_DST_STS_WTC);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_IDR_OFFSET, XQSPIPSU_IDR_ALL_MASK);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
+			XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK);
+
+	/* Clear FIFO */
+	if((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_ISR_OFFSET) & XQSPIPSU_ISR_RXEMPTY_MASK)) {
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_FIFO_CTRL_OFFSET,
+			XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK |
+			XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK);
+	}
+
+	/*
+	 * Switch to IO mode to Clear RX FIFO. This is becuase of DMA behaviour
+	 * where it waits on RX empty and goes busy assuming there is data
+	 * to be transfered even if there is no request.
+	 */
+	if ((IntrStatus & XQSPIPSU_ISR_RXEMPTY_MASK) != 0) {
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_CFG_OFFSET);
+		ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_CFG_OFFSET, ConfigReg);
+
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_FIFO_CTRL_OFFSET,
+				XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK);
+
+		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+			ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
+			XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_CFG_OFFSET, ConfigReg);
+		}
+	}
+
+	/* Disable QSPIPSU */
+	XQspiPsu_Disable(InstancePtr);
+
+	InstancePtr->TxBytes = 0;
+	InstancePtr->RxBytes = 0;
+	InstancePtr->GenFifoEntries = 0;
+	InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function performs a transfer on the bus in polled mode. The messages
+* passed are all transferred on the bus between one CS assert and de-assert.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	NumMsg is the number of messages to be transferred.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*		- XST_DEVICE_BUSY if a transfer is already in progress.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				unsigned NumMsg)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	int Index;
+	u8 IsManualStart = FALSE;
+	u32 QspiPsuStatusReg, DmaStatusReg;
+	u32 BaseAddress;
+	int Status;
+	u32 RxThr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	for (Index = 0; Index < NumMsg; Index++) {
+		Xil_AssertNonvoid(Msg[Index].ByteCount > 0);
+	}
+
+	/* Check whether there is another transfer in progress. Not thread-safe */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+
+	/* Start if manual start */
+	IsManualStart = XQspiPsu_IsManualStart(InstancePtr);
+
+	/* Enable */
+	XQspiPsu_Enable(InstancePtr);
+
+	/* Select slave */
+	XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
+
+	/* list */
+	for (Index = 0; Index < NumMsg; Index++) {
+
+GENFIFO:
+		Status = XQspiPsu_GenFifoEntryData(InstancePtr, Msg, Index);
+		if (Status != XST_SUCCESS) {
+			return Status;
+		}
+
+		if (IsManualStart) {
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+				XQspiPsu_ReadReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET) |
+					XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+		}
+
+		/* Use thresholds here */
+		/* If there is more data to be transmitted */
+		do {
+			QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_ISR_OFFSET);
+
+			/* Transmit more data if left */
+			if ((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) &&
+				(Msg[Index].TxBfrPtr != NULL) &&
+				(InstancePtr->TxBytes > 0)) {
+				XQspiPsu_FillTxFifo(InstancePtr, &Msg[Index],
+						XQSPIPSU_TXD_DEPTH);
+			}
+
+			/* Check if DMA RX is complete and update RxBytes */
+			if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
+				(Msg[Index].RxBfrPtr != NULL)) {
+				u32 DmaIntrSts;
+				DmaIntrSts = XQspiPsu_ReadReg(BaseAddress,
+								XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
+				if (DmaIntrSts & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) {
+					XQspiPsu_WriteReg(BaseAddress,
+						XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
+						DmaIntrSts);
+					/* Read remaining bytes using IO mode */
+					if(InstancePtr->RxBytes % 4 != 0 ) {
+						XQspiPsu_WriteReg(BaseAddress,
+							XQSPIPSU_CFG_OFFSET,
+							(XQspiPsu_ReadReg(BaseAddress,
+							XQSPIPSU_CFG_OFFSET) &
+							~XQSPIPSU_CFG_MODE_EN_MASK));
+						InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
+						Msg[Index].ByteCount =
+							(InstancePtr->RxBytes % 4);
+						Msg[Index].RxBfrPtr += (InstancePtr->RxBytes -
+								(InstancePtr->RxBytes % 4));
+						InstancePtr->IsUnaligned = 1;
+						goto GENFIFO;
+					}
+					InstancePtr->RxBytes = 0;
+				}
+			} else if (Msg[Index].RxBfrPtr != NULL) {
+				/* Check if PIO RX is complete and update RxBytes */
+				RxThr = XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_RX_THRESHOLD_OFFSET);
+				if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
+								!= 0U) {
+					XQspiPsu_ReadRxFifo(InstancePtr,
+							&Msg[Index], RxThr);
+
+				} else if ((QspiPsuStatusReg &
+					XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != 0U) {
+					    XQspiPsu_ReadRxFifo(InstancePtr,
+						    &Msg[Index], InstancePtr->RxBytes);
+				}
+			}
+		} while (!(QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) ||
+			(InstancePtr->TxBytes != 0) ||
+			!(QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) ||
+			(InstancePtr->RxBytes != 0));
+
+		if(InstancePtr->IsUnaligned) {
+			InstancePtr->IsUnaligned = 0;
+			XQspiPsu_WriteReg(BaseAddress,
+				XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
+				BaseAddress,
+				XQSPIPSU_CFG_OFFSET) |
+				XQSPIPSU_CFG_MODE_EN_DMA_MASK));
+			InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
+		}
+	}
+
+	/* De-select slave */
+	XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
+
+	if (IsManualStart) {
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
+				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+	}
+
+	QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
+	while (!(QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK)) {
+		QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_ISR_OFFSET);
+	}
+
+	/* Clear the busy flag. */
+	InstancePtr->IsBusy = FALSE;
+
+	/* Disable the device. */
+	XQspiPsu_Disable(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function initiates a transfer on the bus and enables interrupts.
+* The transfer is completed by the interrupt handler. The messages passed are
+* all transferred on the bus between one CS assert and de-assert.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	NumMsg is the number of messages to be transferred.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*		- XST_DEVICE_BUSY if a transfer is already in progress.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				unsigned NumMsg)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	int Index;
+	u8 IsManualStart = FALSE;
+	u32 BaseAddress;
+	int Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	for (Index = 0; Index < NumMsg; Index++) {
+		Xil_AssertNonvoid(Msg[Index].ByteCount > 0);
+	}
+
+	/* Check whether there is another transfer in progress. Not thread-safe */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+
+	/* Start if manual start */
+	IsManualStart = XQspiPsu_IsManualStart(InstancePtr);
+
+	InstancePtr->Msg = Msg;
+	InstancePtr->NumMsg = NumMsg;
+	InstancePtr->MsgCnt = 0;
+
+	/* Enable */
+	XQspiPsu_Enable(InstancePtr);
+
+	/* Select slave */
+	XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
+
+	/* This might not work if not manual start */
+	/* Put first message in FIFO along with the above slave select */
+	Status = XQspiPsu_GenFifoEntryData(InstancePtr, Msg, 0);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	if (IsManualStart) {
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
+				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+	}
+
+	/* Enable interrupts */
+	XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IER_OFFSET,
+		XQSPIPSU_IER_TXNOT_FULL_MASK | XQSPIPSU_IER_TXEMPTY_MASK |
+		XQSPIPSU_IER_RXNEMPTY_MASK | XQSPIPSU_IER_GENFIFOEMPTY_MASK);
+
+	if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET,
+				XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
+{
+	u8 IsManualStart = FALSE;
+	u32 QspiPsuStatusReg, DmaIntrStatusReg;
+	u32 BaseAddress;
+	XQspiPsu_Msg *Msg;
+	int NumMsg;
+	int MsgCnt;
+	u8 DeltaMsgCnt = 0;
+	u32 RxThr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+	Msg = InstancePtr->Msg;
+	NumMsg = InstancePtr->NumMsg;
+	MsgCnt = InstancePtr->MsgCnt;
+
+	/* Start if manual start */
+	IsManualStart = XQspiPsu_IsManualStart(InstancePtr);
+
+	/* QSPIPSU Intr cleared on read */
+	QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
+	if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+		/* DMA Intr write to clear */
+		DmaIntrStatusReg = XQspiPsu_ReadReg(BaseAddress,
+					XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
+
+		XQspiPsu_WriteReg(BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET, DmaIntrStatusReg);
+	}
+	if ((QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK) ||
+		(DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK)) {
+		/* Call status handler to indicate error */
+		InstancePtr->StatusHandler(InstancePtr->StatusRef,
+					XST_SPI_COMMAND_ERROR, 0);
+	}
+
+	/* Fill more data to be txed if required */
+	if ((MsgCnt < NumMsg) && (Msg[MsgCnt].TxBfrPtr != NULL) &&
+		(QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) &&
+		(InstancePtr->TxBytes > 0)) {
+		XQspiPsu_FillTxFifo(InstancePtr, &Msg[MsgCnt],
+				XQSPIPSU_TXD_DEPTH);
+	}
+
+	/*
+	 * Check if the entry is ONLY TX and increase MsgCnt.
+	 * This is to allow TX and RX together in one entry - corner case.
+	 */
+	if ((MsgCnt < NumMsg) && (Msg[MsgCnt].TxBfrPtr != NULL) &&
+		(QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) &&
+		(QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) &&
+		(InstancePtr->TxBytes == 0) &&
+		(Msg[MsgCnt].RxBfrPtr == NULL)) {
+		MsgCnt += 1;
+		DeltaMsgCnt = 1;
+	}
+
+	if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA &&
+		(MsgCnt < NumMsg) && (Msg[MsgCnt].RxBfrPtr != NULL)) {
+		if ((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK)) {
+				/* Read remaining bytes using IO mode */
+			if(InstancePtr->RxBytes % 4 != 0 ) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
+					BaseAddress, XQSPIPSU_CFG_OFFSET) &
+					~XQSPIPSU_CFG_MODE_EN_MASK));
+				InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
+				Msg[MsgCnt].ByteCount = (InstancePtr->RxBytes % 4);
+				Msg[MsgCnt].RxBfrPtr += (InstancePtr->RxBytes -
+						(InstancePtr->RxBytes % 4));
+				InstancePtr->IsUnaligned = 1;
+				XQspiPsu_GenFifoEntryData(InstancePtr, Msg,
+						MsgCnt);
+				if(IsManualStart) {
+					XQspiPsu_WriteReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET,
+						XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET) |
+						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+				}
+			}
+			else {
+				InstancePtr->RxBytes = 0;
+				MsgCnt += 1;
+				DeltaMsgCnt = 1;
+			}
+		}
+	} else if ((MsgCnt < NumMsg) && (Msg[MsgCnt].RxBfrPtr != NULL)) {
+		RxThr = XQspiPsu_ReadReg(BaseAddress,
+					XQSPIPSU_RX_THRESHOLD_OFFSET);
+		if (InstancePtr->RxBytes != 0) {
+			if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
+							!= 0) {
+				XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
+					RxThr);
+			} else if ((QspiPsuStatusReg &
+				XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != 0) {
+				XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
+					InstancePtr->RxBytes);
+			}
+			if (InstancePtr->RxBytes == 0) {
+				MsgCnt += 1;
+				DeltaMsgCnt = 1;
+			}
+		}
+	}
+
+	/*
+	 * Dummy byte transfer
+	 * MsgCnt < NumMsg check is to ensure is it a valid dummy cycle message
+	 * If one of the above conditions increased MsgCnt, then
+	 * the new message is yet to be placed in the FIFO; hence !DeltaMsgCnt.
+	 */
+	if ((MsgCnt < NumMsg) && !DeltaMsgCnt &&
+		(Msg[MsgCnt].RxBfrPtr == NULL) &&
+		(Msg[MsgCnt].TxBfrPtr == NULL) &&
+		(QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK)) {
+		MsgCnt += 1;
+		DeltaMsgCnt = 1;
+	}
+	InstancePtr->MsgCnt = MsgCnt;
+
+	/*
+	 * DeltaMsgCnt is to handle conditions where genfifo empty can be set
+	 * while tx is still not empty or rx dma is not yet done.
+	 * MsgCnt > NumMsg indicates CS de-assert entry was also executed.
+	 */
+	if ((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) &&
+		(DeltaMsgCnt || (MsgCnt > NumMsg))) {
+		if (MsgCnt < NumMsg) {
+			if(InstancePtr->IsUnaligned) {
+				InstancePtr->IsUnaligned = 0;
+				XQspiPsu_WriteReg(InstancePtr->Config.
+					BaseAddress, XQSPIPSU_CFG_OFFSET,
+					(XQspiPsu_ReadReg(InstancePtr->Config.
+					BaseAddress, XQSPIPSU_CFG_OFFSET) |
+					XQSPIPSU_CFG_MODE_EN_DMA_MASK));
+				InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
+			}
+			/* This might not work if not manual start */
+			XQspiPsu_GenFifoEntryData(InstancePtr, Msg, MsgCnt);
+
+			if (IsManualStart) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET,
+					XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET) |
+						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+			}
+		} else if (MsgCnt == NumMsg) {
+			/* This is just to keep track of the de-assert entry */
+			MsgCnt += 1;
+			InstancePtr->MsgCnt = MsgCnt;
+
+			/* De-select slave */
+			XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
+
+			if (IsManualStart) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET,
+					XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET) |
+						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+			}
+		} else {
+			/* Disable interrupts */
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IDR_OFFSET,
+					XQSPIPSU_IER_TXNOT_FULL_MASK |
+					XQSPIPSU_IER_TXEMPTY_MASK |
+					XQSPIPSU_IER_RXNEMPTY_MASK |
+					XQSPIPSU_IER_GENFIFOEMPTY_MASK);
+			if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
+					XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
+			}
+
+			/* Clear the busy flag. */
+			InstancePtr->IsBusy = FALSE;
+
+			/* Disable the device. */
+			XQspiPsu_Disable(InstancePtr);
+
+			/* Call status handler to indicate completion */
+			InstancePtr->StatusHandler(InstancePtr->StatusRef,
+						XST_SPI_TRANSFER_DONE, 0);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+* 
+*
+* XST_SPI_TRANSFER_DONE		The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
+*				but there were none available in the transmit
+*				register/FIFO. This typically means the slave
+*				application did not issue a transfer request
+*				fast enough, or the processor/driver could not
+*				fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN	The QSPIPSU device lost data. Data was received
+*				but the receive data register/FIFO was full.
+*
+* 

+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
+				XQspiPsu_StatusHandler FuncPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FuncPtr;
+	InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				unsigned ByteCount)
+{
+	(void) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects SPI mode - x1 or x2 or x4.
+*
+* @param	SpiMode - spi or dual or quad.
+* @return	Mask to set desired SPI mode in GENFIFO entry.
+*
+* @note		None.
+*
+******************************************************************************/
+static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
+{
+	u32 Mask;
+	switch (SpiMode) {
+		case XQSPIPSU_SELECT_MODE_DUALSPI:
+			Mask = XQSPIPSU_GENFIFO_MODE_DUALSPI;
+			break;
+		case XQSPIPSU_SELECT_MODE_QUADSPI:
+			Mask = XQSPIPSU_GENFIFO_MODE_QUADSPI;
+			break;
+		case XQSPIPSU_SELECT_MODE_SPI:
+		default:
+			Mask = XQSPIPSU_GENFIFO_MODE_SPI;
+	}
+
+	return Mask;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks the TX/RX buffers in the message and setups up the
+* GENFIFO entries, TX FIFO or RX DMA as required.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	GenFifoEntry is pointer to the variable in which GENFIFO mask
+*		is returned to calling function
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+					u32 *GenFifoEntry)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Transmit */
+	if ((Msg->TxBfrPtr != NULL) && (Msg->RxBfrPtr == NULL)) {
+		/* Setup data to be TXed */
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_TX;
+		InstancePtr->TxBytes = Msg->ByteCount;
+		XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
+		/* Discard RX data */
+		*GenFifoEntry &= ~XQSPIPSU_GENFIFO_RX;
+		InstancePtr->RxBytes = 0;
+	}
+
+	/* Receive */
+	if ((Msg->TxBfrPtr == NULL) && (Msg->RxBfrPtr != NULL)) {
+		/* TX auto fill */
+		*GenFifoEntry &= ~XQSPIPSU_GENFIFO_TX;
+		InstancePtr->TxBytes = 0;
+		/* Setup RX */
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_RX;
+		InstancePtr->RxBytes = Msg->ByteCount;
+		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+			XQspiPsu_SetupRxDma(InstancePtr, Msg);
+		}
+	}
+
+	/* If only dummy is requested as a separate entry */
+	if ((Msg->TxBfrPtr == NULL) && (Msg->RxBfrPtr == NULL)) {
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
+		InstancePtr->TxBytes = 0;
+		InstancePtr->RxBytes = 0;
+	}
+
+	/* Dummy and cmd sent by upper layer to received data */
+	if ((Msg->TxBfrPtr != NULL) && (Msg->RxBfrPtr != NULL)) {
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry |= (XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
+		InstancePtr->TxBytes = Msg->ByteCount;
+		InstancePtr->RxBytes = Msg->ByteCount;
+		XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
+		/* Add check for DMA or PIO here */
+		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+			XQspiPsu_SetupRxDma(InstancePtr, Msg);
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Fills the TX FIFO as long as there is room in the FIFO or the bytes required
+* to be transmitted.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	Size is the number of bytes to be transmitted.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg, int Size)
+{
+	int Count = 0;
+	u32 Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Msg->TxBfrPtr != NULL);
+
+	while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
+		Data = *((u32*)Msg->TxBfrPtr);
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_TXD_OFFSET, Data);
+		Msg->TxBfrPtr += 4;
+		InstancePtr->TxBytes -= 4;
+		Count++;
+	}
+	if (InstancePtr->TxBytes < 0)
+		InstancePtr->TxBytes = 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets up the RX DMA operation.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg)
+{
+	int Remainder;
+	int DmaRxBytes;
+	u64 AddrTemp;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Msg->RxBfrPtr != NULL);
+
+	AddrTemp = (u64)(INTPTR)(Msg->RxBfrPtr) &
+				XQSPIPSU_QSPIDMA_DST_ADDR_MASK;
+	/* Check for RXBfrPtr to be word aligned */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET,
+			(u32)AddrTemp);
+
+	AddrTemp = AddrTemp >> 32;
+	if (AddrTemp & 0xFFF) {
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET,
+				(u32)AddrTemp &
+				XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
+	}
+
+	Remainder = InstancePtr->RxBytes % 4;
+	DmaRxBytes = InstancePtr->RxBytes;
+	if (Remainder != 0) {
+		/* This is done to make Dma bytes aligned */
+		DmaRxBytes = InstancePtr->RxBytes - Remainder;
+		Msg->ByteCount = DmaRxBytes;
+	}
+
+	/* Write no. of words to DMA DST SIZE */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, DmaRxBytes);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes the GENFIFO entry to assert CS.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
+{
+	u32 GenFifoEntry;
+
+	GenFifoEntry = 0x0;
+	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_DATA_XFER | XQSPIPSU_GENFIFO_EXP);
+	GenFifoEntry &= ~XQSPIPSU_GENFIFO_MODE_MASK;
+	GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
+	GenFifoEntry |= InstancePtr->GenFifoCS;
+	GenFifoEntry &= ~XQSPIPSU_GENFIFO_BUS_MASK;
+	GenFifoEntry |= InstancePtr->GenFifoBus;
+	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
+			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_SETUP;
+
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes the GENFIFO entries to transmit the messages requested.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	Index of the current message to be handled.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*		- XST_DEVICE_BUSY if a transfer is already in progress.
+*
+* @note		None.
+*
+******************************************************************************/
+static inline int XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
+						XQspiPsu_Msg *Msg, int Index)
+{
+	u32 GenFifoEntry;
+	u32 BaseAddress;
+	int TempCount;
+	int ImmData;
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+
+	GenFifoEntry = 0x0;
+	/* Bus width */
+	GenFifoEntry &= ~XQSPIPSU_GENFIFO_MODE_MASK;
+	GenFifoEntry |= XQspiPsu_SelectSpiMode(Msg[Index].BusWidth);
+
+	GenFifoEntry |= InstancePtr->GenFifoCS;
+	GenFifoEntry &= ~XQSPIPSU_GENFIFO_BUS_MASK;
+	GenFifoEntry |= InstancePtr->GenFifoBus;
+
+	/* Data */
+	if (Msg[Index].Flags & XQSPIPSU_MSG_FLAG_STRIPE)
+		GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
+	else
+		GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
+
+	XQspiPsu_TXRXSetup(InstancePtr, &Msg[Index], &GenFifoEntry);
+
+	if (Msg[Index].ByteCount < XQSPIPSU_GENFIFO_IMM_DATA_MASK) {
+		GenFifoEntry &= ~XQSPIPSU_GENFIFO_IMM_DATA_MASK;
+		GenFifoEntry |= Msg[Index].ByteCount;
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
+				GenFifoEntry);
+	} else {
+		TempCount = Msg[Index].ByteCount;
+		u32 Exponent = 8;	/* 2^8 = 256 */
+
+		/* Check for ByteCount upper limit - 2^28 for DMA */
+		if (TempCount > XQSPIPSU_DMA_BYTES_MAX) {
+			return XST_FAILURE;
+		}
+
+		ImmData = TempCount & 0xFF;
+		/* Exponent entries */
+		GenFifoEntry |= XQSPIPSU_GENFIFO_EXP;
+		while (TempCount != 0) {
+			if (TempCount & XQSPIPSU_GENFIFO_EXP_START) {
+				GenFifoEntry &= ~XQSPIPSU_GENFIFO_IMM_DATA_MASK;
+				GenFifoEntry |= Exponent;
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_GEN_FIFO_OFFSET,
+					GenFifoEntry);
+			}
+			TempCount = TempCount >> 1;
+			Exponent++;
+		}
+
+		/* Immediate entry */
+		GenFifoEntry &= ~XQSPIPSU_GENFIFO_EXP;
+		if (ImmData & 0xFF) {
+			GenFifoEntry &= ~XQSPIPSU_GENFIFO_IMM_DATA_MASK;
+			GenFifoEntry |= ImmData & 0xFF;
+			XQspiPsu_WriteReg(BaseAddress,
+				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes the GENFIFO entry to de-assert CS.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
+{
+	u32 GenFifoEntry;
+
+	GenFifoEntry = 0x0;
+	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_DATA_XFER | XQSPIPSU_GENFIFO_EXP);
+	GenFifoEntry &= ~XQSPIPSU_GENFIFO_MODE_MASK;
+	GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
+	GenFifoEntry &= ~XQSPIPSU_GENFIFO_BUS_MASK;
+	GenFifoEntry |= InstancePtr->GenFifoBus;
+	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
+			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_HOLD;
+
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the specified number of bytes from RX FIFO
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	Size is the number of bytes to be read.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg, int Size)
+{
+	int Count = 0;
+	u32 Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Msg != NULL);
+
+	while (InstancePtr->RxBytes != 0 && Count < Size) {
+		Data = XQspiPsu_ReadReg(InstancePtr->
+				Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
+		if (InstancePtr->RxBytes >= 4) {
+			*(u32 *)Msg->RxBfrPtr = Data;
+			InstancePtr->RxBytes -= 4;
+			Msg->RxBfrPtr += 4;
+			Count += 4;
+		} else {
+			/* Read unaligned bytes (< 4 bytes) */
+			while (InstancePtr->RxBytes != 0) {
+				*Msg->RxBfrPtr = Data;
+				InstancePtr->RxBytes--;
+				Msg->RxBfrPtr++;
+				Count++;
+				Data >>= 8;
+			}
+		}
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu.h
new file mode 100644
index 000000000..9395ea260
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu.h
@@ -0,0 +1,263 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu.h
+*
+* This is the header file for the implementation of QSPIPSU driver.
+* Generic QSPI interface allows for communication to any QSPI slave device.
+* GQSPI contains a GENFIFO into which the bus transfers required are to be
+* pushed with appropriate configuration. The controller provides TX and RX
+* FIFO's and a DMA to be used for RX transfers. The controller executes each
+* GENFIFO entry noting the configuration and places data on the bus as required
+*
+* The different options in GENFIFO are as follows:
+* IMM_DATA : Can be one byte of data to be transmitted, number of clocks or
+*            number of bytes in transfer.
+* DATA_XFER : Indicates that data/clocks need to be transmitted or received.
+* EXPONENT : e when 2^e bytes are involved in transfer.
+* SPI_MODE : SPI/Dual SPI/Quad SPI
+* CS : Lower or Upper CS or Both
+* Bus : Lower or Upper Bus or Both
+* TX : When selected, controller transmits data in IMM or fetches number of
+*      bytes mentioned form TX FIFO. If not selected, dummies are pumped.
+* RX : When selected, controller receives and fills the RX FIFO/allows RX DMA
+*      of requested number of bytes. If not selected, RX data is discarded.
+* Stripe : Byte stripe over lower and upper bus or not.
+* Poll : Polls response to match for to a set value (used along with POLL_CFG
+*        registers) and then proceeds to next GENFIFO entry.
+*        This feature is not currently used in the driver.
+*
+* GENFIFO has manual and auto start options.
+* All DMA requests need a 4-byte aligned destination address buffer and
+* size of transfer should also be a multiple of 4.
+* This driver supports DMA RX and IO RX.
+*
+* Initialization:
+* This driver uses the GQSPI controller with RX DMA. It supports both
+* interrupt and polled transfers. Manual start of GENFIFO is used.
+* XQspiPsu_CfgInitialize() initializes the instance variables.
+* Additional setting can be done using SetOptions/ClearOptions functions
+* and SelectSlave function.
+*
+* Transfer:
+* Polled or Interrupt transfers can be done. The transfer function needs the
+* message(s) to be transmitted in the form of an array of type XQspiPsu_Msg.
+* This is supposed to contain the byte count and any TX/RX buffers as required.
+* Flags can be used indicate further information such as whether the message
+* should be striped. The transfer functions form and write GENFIFO entries,
+* check the status of the transfer and report back to the application
+* when done.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+*                    Clear and disbale DMA interrupts/status in abort.
+*                    Use DMA DONE bit instead of BUSY as recommended.
+*
+* 

+*
+******************************************************************************/
+#ifndef _XQSPIPSU_H_		/* prevent circular inclusions */
+#define _XQSPIPSU_H_		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspipsu_hw.h"
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPIPSU device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param 	StatusEvent holds one or more status events that have occurred.
+ *		See the XQspiPsu_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for a flash message.
+ */
+typedef struct {
+	u8 *TxBfrPtr;
+	u8 *RxBfrPtr;
+	u32 ByteCount;
+	u32 BusWidth;
+	u32 Flags;
+} XQspiPsu_Msg;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
+	u8  BusWidth; 	/**< Bus width available on board */
+} XQspiPsu_Config;
+
+/**
+ * The XQspiPsu driver instance data. The user is required to allocate a
+ * variable of this type for every QSPIPSU device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XQspiPsu_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	u8 *GenFifoBufferPtr;	 /**< Gen FIFO entries */
+	int TxBytes;	 /**< Number of bytes to transfer (state) */
+	int RxBytes;	 /**< Number of bytes left to transfer(state) */
+	int GenFifoEntries;	 /**< Number of Gen FIFO entries remaining */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	u32 ReadMode;		 /**< DMA or IO mode */
+	u32 GenFifoCS;
+	u32 GenFifoBus;
+	int NumMsg;
+	int MsgCnt;
+	int IsUnaligned;
+	XQspiPsu_Msg *Msg;
+	XQspiPsu_StatusHandler StatusHandler;
+	void *StatusRef;  	 /**< Callback reference for status handler */
+} XQspiPsu;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQSPIPSU_READMODE_DMA	0x0
+#define XQSPIPSU_READMODE_IO	0x1
+
+#define XQSPIPSU_SELECT_FLASH_CS_LOWER	0x1
+#define XQSPIPSU_SELECT_FLASH_CS_UPPER	0x2
+#define XQSPIPSU_SELECT_FLASH_CS_BOTH	0x3
+
+#define XQSPIPSU_SELECT_FLASH_BUS_LOWER	0x1
+#define XQSPIPSU_SELECT_FLASH_BUS_UPPER	0x2
+#define XQSPIPSU_SELECT_FLASH_BUS_BOTH	0x3
+
+#define XQSPIPSU_SELECT_MODE_SPI	0x1
+#define XQSPIPSU_SELECT_MODE_DUALSPI	0x2
+#define XQSPIPSU_SELECT_MODE_QUADSPI	0x4
+
+#define XQSPIPSU_GENFIFO_CS_SETUP	0x04
+#define XQSPIPSU_GENFIFO_CS_HOLD	0x03
+
+#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION	0x2
+#define XQSPIPSU_CLK_PHASE_1_OPTION	0x4
+#define XQSPIPSU_MANUAL_START_OPTION	0x8
+
+#define XQSPIPSU_GENFIFO_EXP_START	0x100
+
+#define XQSPIPSU_DMA_BYTES_MAX		0x10000000
+
+#define XQSPIPSU_CLK_PRESCALE_2		0x00
+#define XQSPIPSU_CLK_PRESCALE_4		0x01
+#define XQSPIPSU_CLK_PRESCALE_8		0x02
+#define XQSPIPSU_CLK_PRESCALE_16		0x03
+#define XQSPIPSU_CLK_PRESCALE_32		0x04
+#define XQSPIPSU_CLK_PRESCALE_64		0x05
+#define XQSPIPSU_CLK_PRESCALE_128	0x06
+#define XQSPIPSU_CLK_PRESCALE_256	0x07
+#define XQSPIPSU_CR_PRESC_MAXIMUM	7
+
+#define XQSPIPSU_CONNECTION_MODE_SINGLE		0
+#define XQSPIPSU_CONNECTION_MODE_STACKED	1
+#define XQSPIPSU_CONNECTION_MODE_PARALLEL	2
+
+/* Add more flags as required */
+#define XQSPIPSU_MSG_FLAG_STRIPE	0x1
+
+#define XQspiPsu_Select(InstancePtr)	XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
+
+#define XQspiPsu_Enable(InstancePtr)	XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
+
+#define XQspiPsu_Disable(InstancePtr)	XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0)
+
+#define XQspiPsu_IsManualStart(InstancePtr) ((XQspiPsu_GetOptions(InstancePtr) & XQSPIPSU_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/************************** Function Prototypes ******************************/
+
+/* Initialization and reset */
+XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
+int XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
+				u32 EffectiveAddr);
+void XQspiPsu_Reset(XQspiPsu *InstancePtr);
+void XQspiPsu_Abort(XQspiPsu *InstancePtr);
+
+/* Transfer functions and handlers */
+int XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				unsigned NumMsg);
+int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				unsigned NumMsg);
+int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
+void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
+				XQspiPsu_StatusHandler FuncPtr);
+
+/* Configuration functions */
+int XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler);
+void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
+int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
+int XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
+u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr);
+int XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _XQSPIPSU_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
new file mode 100644
index 000000000..9096c5077
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspipsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPsu_Config XQspiPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_QSPI_0_DEVICE_ID,
+		XPAR_PSU_QSPI_0_BASEADDR,
+		XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ,
+		XPAR_PSU_QSPI_0_QSPI_MODE
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h
new file mode 100644
index 000000000..bd189ba7a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h
@@ -0,0 +1,837 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_hw.h
+*
+* This file contains low level access funcitons using the base address
+* directly without an instance.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   hk  08/21/14 First release
+*       hk  03/18/15 Add DMA status register masks required.
+*
+* 

+*
+******************************************************************************/
+#ifndef _XQSPIPSU_HW_H_		/* prevent circular inclusions */
+#define _XQSPIPSU_HW_H_		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * QSPI Base Address
+ */
+#define XQSPIPS_BASEADDR      0XFF0F0000
+
+/**
+ * GQSPI Base Address
+ */
+#define XQSPIPSU_BASEADDR     0xFF0F0100
+#define XQSPIPSU_OFFSET     0x100
+
+/**
+ * Register: XQSPIPS_EN_REG
+ */
+#define XQSPIPS_EN_REG    ( ( XQSPIPS_BASEADDR ) + 0X00000014 )
+
+#define XQSPIPS_EN_SHIFT   0
+#define XQSPIPS_EN_WIDTH   1
+#define XQSPIPS_EN_MASK    0X00000001
+
+/**
+ * Register: XQSPIPSU_CFG
+ */
+#define XQSPIPSU_CFG_OFFSET    0X00000000
+
+#define XQSPIPSU_CFG_MODE_EN_SHIFT   30
+#define XQSPIPSU_CFG_MODE_EN_WIDTH   2
+#define XQSPIPSU_CFG_MODE_EN_MASK    0XC0000000
+#define XQSPIPSU_CFG_MODE_EN_DMA_MASK	0X80000000
+
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT   29
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH   1
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK    0X20000000
+
+#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT   28
+#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH   1
+#define XQSPIPSU_CFG_START_GEN_FIFO_MASK    0X10000000
+
+#define XQSPIPSU_CFG_ENDIAN_SHIFT   26
+#define XQSPIPSU_CFG_ENDIAN_WIDTH   1
+#define XQSPIPSU_CFG_ENDIAN_MASK    0X04000000
+
+#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT   20
+#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH   1
+#define XQSPIPSU_CFG_EN_POLL_TO_MASK    0X00100000
+
+#define XQSPIPSU_CFG_WP_HOLD_SHIFT   19
+#define XQSPIPSU_CFG_WP_HOLD_WIDTH   1
+#define XQSPIPSU_CFG_WP_HOLD_MASK    0X00080000
+
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT   3
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH   3
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK    0X00000038
+
+#define XQSPIPSU_CFG_CLK_PHA_SHIFT   2
+#define XQSPIPSU_CFG_CLK_PHA_WIDTH   1
+#define XQSPIPSU_CFG_CLK_PHA_MASK    0X00000004
+
+#define XQSPIPSU_CFG_CLK_POL_SHIFT   1
+#define XQSPIPSU_CFG_CLK_POL_WIDTH   1
+#define XQSPIPSU_CFG_CLK_POL_MASK    0X00000002
+
+/**
+ * Register: XQSPIPSU_ISR
+ */
+#define XQSPIPSU_ISR_OFFSET	0X00000004
+
+#define XQSPIPSU_ISR_RXEMPTY_SHIFT   11
+#define XQSPIPSU_ISR_RXEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_RXEMPTY_MASK    0X00000800
+
+#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_ISR_GENFIFOFULL_MASK    0X00000400
+
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK    0X00000200
+
+#define XQSPIPSU_ISR_TXEMPTY_SHIFT   8
+#define XQSPIPSU_ISR_TXEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_TXEMPTY_MASK    0X00000100
+
+#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK    0X00000080
+
+#define XQSPIPSU_ISR_RXFULL_SHIFT   5
+#define XQSPIPSU_ISR_RXFULL_WIDTH   1
+#define XQSPIPSU_ISR_RXFULL_MASK    0X00000020
+
+#define XQSPIPSU_ISR_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_ISR_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_RXNEMPTY_MASK    0X00000010
+
+#define XQSPIPSU_ISR_TXFULL_SHIFT   3
+#define XQSPIPSU_ISR_TXFULL_WIDTH   1
+#define XQSPIPSU_ISR_TXFULL_MASK    0X00000008
+
+#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_ISR_TXNOT_FULL_MASK    0X00000004
+
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK    0X00000002
+
+#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002
+
+/**
+ * Register: XQSPIPSU_IER
+ */
+#define XQSPIPSU_IER_OFFSET    0X00000008
+
+#define XQSPIPSU_IER_RXEMPTY_SHIFT   11
+#define XQSPIPSU_IER_RXEMPTY_WIDTH   1
+#define XQSPIPSU_IER_RXEMPTY_MASK    0X00000800
+
+#define XQSPIPSU_IER_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_IER_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_IER_GENFIFOFULL_MASK    0X00000400
+
+#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK    0X00000200
+
+#define XQSPIPSU_IER_TXEMPTY_SHIFT   8
+#define XQSPIPSU_IER_TXEMPTY_WIDTH   1
+#define XQSPIPSU_IER_TXEMPTY_MASK    0X00000100
+
+#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_IER_GENFIFOEMPTY_MASK    0X00000080
+
+#define XQSPIPSU_IER_RXFULL_SHIFT   5
+#define XQSPIPSU_IER_RXFULL_WIDTH   1
+#define XQSPIPSU_IER_RXFULL_MASK    0X00000020
+
+#define XQSPIPSU_IER_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_IER_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_IER_RXNEMPTY_MASK    0X00000010
+
+#define XQSPIPSU_IER_TXFULL_SHIFT   3
+#define XQSPIPSU_IER_TXFULL_WIDTH   1
+#define XQSPIPSU_IER_TXFULL_MASK    0X00000008
+
+#define XQSPIPSU_IER_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_IER_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_IER_TXNOT_FULL_MASK    0X00000004
+
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK    0X00000002
+
+/**
+ * Register: XQSPIPSU_IDR
+ */
+#define XQSPIPSU_IDR_OFFSET    0X0000000C
+
+#define XQSPIPSU_IDR_RXEMPTY_SHIFT   11
+#define XQSPIPSU_IDR_RXEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_RXEMPTY_MASK    0X00000800
+
+#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_IDR_GENFIFOFULL_MASK    0X00000400
+
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK    0X00000200
+
+#define XQSPIPSU_IDR_TXEMPTY_SHIFT   8
+#define XQSPIPSU_IDR_TXEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_TXEMPTY_MASK    0X00000100
+
+#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK    0X00000080
+
+#define XQSPIPSU_IDR_RXFULL_SHIFT   5
+#define XQSPIPSU_IDR_RXFULL_WIDTH   1
+#define XQSPIPSU_IDR_RXFULL_MASK    0X00000020
+
+#define XQSPIPSU_IDR_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_IDR_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_RXNEMPTY_MASK    0X00000010
+
+#define XQSPIPSU_IDR_TXFULL_SHIFT   3
+#define XQSPIPSU_IDR_TXFULL_WIDTH   1
+#define XQSPIPSU_IDR_TXFULL_MASK    0X00000008
+
+#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_IDR_TXNOT_FULL_MASK    0X00000004
+
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK    0X00000002
+
+#define XQSPIPSU_IDR_ALL_MASK    0X0FBE
+
+/**
+ * Register: XQSPIPSU_IMR
+ */
+#define XQSPIPSU_IMR_OFFSET    0X00000010
+
+#define XQSPIPSU_IMR_RXEMPTY_SHIFT   11
+#define XQSPIPSU_IMR_RXEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_RXEMPTY_MASK    0X00000800
+
+#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_IMR_GENFIFOFULL_MASK    0X00000400
+
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK    0X00000200
+
+#define XQSPIPSU_IMR_TXEMPTY_SHIFT   8
+#define XQSPIPSU_IMR_TXEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_TXEMPTY_MASK    0X00000100
+
+#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK    0X00000080
+
+#define XQSPIPSU_IMR_RXFULL_SHIFT   5
+#define XQSPIPSU_IMR_RXFULL_WIDTH   1
+#define XQSPIPSU_IMR_RXFULL_MASK    0X00000020
+
+#define XQSPIPSU_IMR_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_IMR_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_RXNEMPTY_MASK    0X00000010
+
+#define XQSPIPSU_IMR_TXFULL_SHIFT   3
+#define XQSPIPSU_IMR_TXFULL_WIDTH   1
+#define XQSPIPSU_IMR_TXFULL_MASK    0X00000008
+
+#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_IMR_TXNOT_FULL_MASK    0X00000004
+
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK    0X00000002
+
+/**
+ * Register: XQSPIPSU_EN_REG
+ */
+#define XQSPIPSU_EN_OFFSET    0X00000014
+
+#define XQSPIPSU_EN_SHIFT   0
+#define XQSPIPSU_EN_WIDTH   1
+#define XQSPIPSU_EN_MASK    0X00000001
+
+/**
+ * Register: XQSPIPSU_TXD
+ */
+#define XQSPIPSU_TXD_OFFSET    0X0000001C
+
+#define XQSPIPSU_TXD_SHIFT   0
+#define XQSPIPSU_TXD_WIDTH   32
+#define XQSPIPSU_TXD_MASK    0XFFFFFFFF
+
+#define XQSPIPSU_TXD_DEPTH    32
+
+/**
+ * Register: XQSPIPSU_RXD
+ */
+#define XQSPIPSU_RXD_OFFSET    0X00000020
+
+#define XQSPIPSU_RXD_SHIFT   0
+#define XQSPIPSU_RXD_WIDTH   32
+#define XQSPIPSU_RXD_MASK    0XFFFFFFFF
+
+/**
+ * Register: XQSPIPSU_TX_THRESHOLD
+ */
+#define XQSPIPSU_TX_THRESHOLD_OFFSET    0X00000028
+
+#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT   0
+#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH   6
+#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK    0X0000003F
+#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL    0X01
+
+/**
+ * Register: XQSPIPSU_RX_THRESHOLD
+ */
+#define XQSPIPSU_RX_THRESHOLD_OFFSET    0X0000002C
+
+#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT   0
+#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH   6
+#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK    0X0000003F
+#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL    0X01
+
+#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32
+
+/**
+ * Register: XQSPIPSU_GPIO
+ */
+#define XQSPIPSU_GPIO_OFFSET    0X00000030
+
+#define XQSPIPSU_GPIO_WP_N_SHIFT   0
+#define XQSPIPSU_GPIO_WP_N_WIDTH   1
+#define XQSPIPSU_GPIO_WP_N_MASK    0X00000001
+
+/**
+ * Register: XQSPIPSU_LPBK_DLY_ADJ
+ */
+#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET    0X00000038
+
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT   5
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH   1
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK    0X00000020
+
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT   3
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH   2
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK    0X00000018
+
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT   0
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH   3
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK    0X00000007
+
+/**
+ * Register: XQSPIPSU_GEN_FIFO
+ */
+#define XQSPIPSU_GEN_FIFO_OFFSET    0X00000040
+
+#define XQSPIPSU_GEN_FIFO_DATA_SHIFT   0
+#define XQSPIPSU_GEN_FIFO_DATA_WIDTH   20
+#define XQSPIPSU_GEN_FIFO_DATA_MASK    0X000FFFFF
+
+/**
+ * Register: XQSPIPSU_SEL
+ */
+#define XQSPIPSU_SEL_OFFSET    0X00000044
+
+#define XQSPIPSU_SEL_SHIFT   0
+#define XQSPIPSU_SEL_WIDTH   1
+#define XQSPIPSU_SEL_MASK    0X00000001
+
+/**
+ * Register: XQSPIPSU_FIFO_CTRL
+ */
+#define XQSPIPSU_FIFO_CTRL_OFFSET    0X0000004C
+
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT   2
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH   1
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK    0X00000004
+
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT   1
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH   1
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK    0X00000002
+
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT   0
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH   1
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK    0X00000001
+
+/**
+ * Register: XQSPIPSU_GF_THRESHOLD
+ */
+#define XQSPIPSU_GF_THRESHOLD_OFFSET    0X00000050
+
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT   0
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH   5
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK    0X0000001F
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL    0X10
+
+/**
+ * Register: XQSPIPSU_POLL_CFG
+ */
+#define XQSPIPSU_POLL_CFG_OFFSET    0X00000054
+
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT   31
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH   1
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK    0X80000000
+
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT   30
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH   1
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK    0X40000000
+
+#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT   8
+#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH   8
+#define XQSPIPSU_POLL_CFG_MASK_EN_MASK    0X0000FF00
+
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT   0
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH   8
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK    0X000000FF
+
+/**
+ * Register: XQSPIPSU_P_TIMEOUT
+ */
+#define XQSPIPSU_P_TO_OFFSET    0X00000058
+
+#define XQSPIPSU_P_TO_VALUE_SHIFT   0
+#define XQSPIPSU_P_TO_VALUE_WIDTH   32
+#define XQSPIPSU_P_TO_VALUE_MASK    0XFFFFFFFF
+
+/**
+ * Register: XQSPIPSU_XFER_STS
+ */
+#define XQSPIPSU_XFER_STS_OFFSET	0X0000005C
+
+#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT   0
+#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH   32
+#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK    0XFFFFFFFF
+
+/**
+ * Register: XQSPIPSU_GF_SNAPSHOT
+ */
+#define XQSPIPSU_GF_SNAPSHOT_OFFSET    0X00000060
+
+#define XQSPIPSU_GF_SNAPSHOT_SHIFT   0
+#define XQSPIPSU_GF_SNAPSHOT_WIDTH   20
+#define XQSPIPSU_GF_SNAPSHOT_MASK    0X000FFFFF
+
+/**
+ * Register: XQSPIPSU_RX_COPY
+ */
+#define XQSPIPSU_RX_COPY_OFFSET    0X00000064
+
+#define XQSPIPSU_RX_COPY_UPPER_SHIFT   8
+#define XQSPIPSU_RX_COPY_UPPER_WIDTH   8
+#define XQSPIPSU_RX_COPY_UPPER_MASK    0X0000FF00
+
+#define XQSPIPSU_RX_COPY_LOWER_SHIFT   0
+#define XQSPIPSU_RX_COPY_LOWER_WIDTH   8
+#define XQSPIPSU_RX_COPY_LOWER_MASK    0X000000FF
+
+/**
+ * Register: XQSPIPSU_MOD_ID
+ */
+#define XQSPIPSU_MOD_ID_OFFSET    0X000000FC
+
+#define XQSPIPSU_MOD_ID_SHIFT   0
+#define XQSPIPSU_MOD_ID_WIDTH   32
+#define XQSPIPSU_MOD_ID_MASK    0XFFFFFFFF
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_ADDR
+ */
+#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET    0X00000700
+
+#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH   30
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK    0XFFFFFFFC
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_SIZE
+ */
+#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET    0X00000704
+
+#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH   27
+#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK    0X1FFFFFFC
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_STS
+ */
+#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET    0X00000708
+
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT   13
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK    0X0000E000
+
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH   8
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK    0X00001FE0
+
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH   4
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK    0X0000001E
+
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK    0X00000001
+
+#define XQSPIPSU_QSPIDMA_DST_STS_WTC	0xE000
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_CTRL
+ */
+#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET    0X0000070C
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT   25
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH   7
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK    0XFE000000
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT   24
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK    0X01000000
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT   23
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK    0X00800000
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT   22
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK    0X00400000
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT   10
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH   12
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK    0X003FFC00
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH   8
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK    0X000003FC
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK    0X00000002
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK    0X00000001
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL	0x803FFA00
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_I_STS
+ */
+#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET    0X00000714
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK    0X00000080
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK    0X00000040
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK    0X00000020
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK    0X00000010
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK    0X00000008
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK    0X00000004
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK    0X00000002
+
+#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK    0X000000FC
+#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK    0X000000FE
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_I_EN
+ */
+#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET    0X00000718
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK    0X00000080
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK    0X00000040
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK    0X00000020
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK    0X00000010
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK    0X00000008
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK    0X00000004
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK    0X00000002
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_I_DIS
+ */
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET    0X0000071C
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK    0X00000080
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK    0X00000040
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK    0X00000020
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK    0X00000010
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK    0X00000008
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK    0X00000004
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK    0X00000002
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_IMR
+ */
+#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET    0X00000720
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK    0X00000080
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK    0X00000040
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK    0X00000020
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK    0X00000010
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK    0X00000008
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK    0X00000004
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK    0X00000002
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_CTRL2
+ */
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET    0X00000724
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT   27
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK    0X08000000
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT   24
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK    0X07000000
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT   22
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK    0X00400000
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT   19
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK    0X00380000
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT   16
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK    0X00070000
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH   12
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK    0X0000FFF0
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH   4
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK    0X0000000F
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
+ */
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET    0X00000728
+
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH   12
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK    0X00000FFF
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
+ */
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET    0X00000EFC
+
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT   0
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH   32
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK    0XFFFFFFFF
+
+/*
+ * Generic FIFO masks
+ */
+#define XQSPIPSU_GENFIFO_IMM_DATA_MASK	0xFF
+#define XQSPIPSU_GENFIFO_DATA_XFER	0x100
+#define XQSPIPSU_GENFIFO_EXP		0x200
+#define XQSPIPSU_GENFIFO_MODE_SPI	0x400
+#define XQSPIPSU_GENFIFO_MODE_DUALSPI	0x800
+#define XQSPIPSU_GENFIFO_MODE_QUADSPI	0xC00
+#define XQSPIPSU_GENFIFO_MODE_MASK	0xC00	/* And with ~MASK first */
+#define XQSPIPSU_GENFIFO_CS_LOWER	0x1000
+#define XQSPIPSU_GENFIFO_CS_UPPER	0x2000
+#define XQSPIPSU_GENFIFO_BUS_LOWER	0x4000
+#define XQSPIPSU_GENFIFO_BUS_UPPER	0x8000
+#define XQSPIPSU_GENFIFO_BUS_BOTH	0xC000	/* inverse is no bus */
+#define XQSPIPSU_GENFIFO_BUS_MASK	0xC000	/* And with ~MASK first */
+#define XQSPIPSU_GENFIFO_TX		0x10000	/* inverse is zero pump */
+#define XQSPIPSU_GENFIFO_RX		0x20000	/* inverse is RX discard */
+#define XQSPIPSU_GENFIFO_STRIPE		0x40000
+#define XQSPIPSU_GENFIFO_POLL		0x80000
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPsu_In32 Xil_In32
+#define XQspiPsu_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPsu_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPsu_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _XQSPIPSU_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c
new file mode 100644
index 000000000..014159f18
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c
@@ -0,0 +1,416 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_options.c
+*
+* This file implements funcitons to configure the QSPIPSU component,
+* specifically some optional settings, clock and flash related information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspipsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+	{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},
+	{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},
+	{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},
+};
+
+#define XQSPIPSU_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPIPSU device driver.The options
+* control how the device behaves relative to the QSPIPSU bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 indicates the option should be turned ON and
+*		a 0 indicates no action. One or more bit values may be
+*		contained in the mask. See the bit definitions named
+*		XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	unsigned int Index;
+	u32 QspiPsuOptions;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPSU_CFG_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
+		if (Options & OptionsTable[Index].Option) {
+			/* Turn it on */
+			ConfigReg |= OptionsTable[Index].Mask;
+		}
+	}
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+			 ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the options for the QSPIPSU device driver.The options
+* control how the device behaves relative to the QSPIPSU bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 indicates the option should be turned OFF and
+*		a 0 indicates no action. One or more bit values may be
+*		contained in the mask. See the bit definitions named
+*		XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+int XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	unsigned int Index;
+	u32 QspiPsuOptions;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPSU_CFG_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
+		if (Options & OptionsTable[Index].Option) {
+			/* Turn it off */
+			ConfigReg &= ~OptionsTable[Index].Mask;
+		}
+	}
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+			 ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPIPSU device. The options control how
+* the device behaves relative to the QSPIPSU bus.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ConfigReg;
+	unsigned int Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the current options from QSPIPSU configuration register.
+	 */
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPSU_CFG_OFFSET);
+
+	/* Loop through the options table to grab options */
+	for (Index = 0; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
+		if (ConfigReg & OptionsTable[Index].Mask) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* Configures the clock according to the prescaler passed.
+*
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Prescaler - clock prescaler to be set.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Prescaler <= XQSPIPSU_CR_PRESC_MAXIMUM);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Read the configuration register, mask out the relevant bits, and set
+	 * them with the shifted value passed into the function. Write the
+	 * results back to the configuration register.
+	 */
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPSU_CFG_OFFSET);
+
+	ConfigReg &= ~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK;
+	ConfigReg |= (u32) (Prescaler & XQSPIPSU_CR_PRESC_MAXIMUM) <<
+			    XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT;
+
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPSU_CFG_OFFSET, ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This funciton should be used to tell the QSPIPSU driver the HW flash
+* configuration being used. This API should be called atleast once in the
+* application. If desired, it can be called multiple times when switching
+* between communicating to different flahs devices/using different configs.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	FlashCS - Flash Chip Select.
+* @param	FlashBus - Flash Bus (Upper, Lower or Both).
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		If this funciton is not called atleast once in the application,
+*		the driver assumes there is a single flash connected to the
+*		lower bus and CS line.
+*
+******************************************************************************/
+void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/*
+	 * Bus and CS lines selected here will be updated in the instance and
+	 * used for subsequent GENFIFO entries during transfer.
+	 */
+
+	/* Choose slave select line */
+	switch (FlashCS) {
+		case XQSPIPSU_SELECT_FLASH_CS_BOTH:
+			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER |
+						XQSPIPSU_GENFIFO_CS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_CS_UPPER:
+			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_CS_LOWER:
+		default:
+			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
+	}
+
+	/* Choose bus */
+	switch (FlashBus) {
+		case XQSPIPSU_SELECT_FLASH_BUS_BOTH:
+			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER |
+						XQSPIPSU_GENFIFO_BUS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_BUS_UPPER:
+			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_BUS_LOWER:
+		default:
+			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the Read mode for the QSPIPSU device driver.The device
+* must be idle rather than busy transferring data before setting Read mode
+* options.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Mode contains the specified Mode to be set. See the
+* 		bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting Mode.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+int XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	InstancePtr->ReadMode = Mode;
+
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPSU_CFG_OFFSET);
+
+	if (Mode == XQSPIPSU_READMODE_DMA) {
+		ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+		ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
+	} else {
+		ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+	}
+
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+			 ConfigReg);
+
+	return XST_SUCCESS;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c
new file mode 100644
index 000000000..5b598c8a7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_sinit.c
+*
+* The implementation of the XQspiPsu component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   hk  08/21/14 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspipsu.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPsu_Config XQspiPsu_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspipsu.h for the definition of XQspiPsu_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId)
+{
+	XQspiPsu_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XQSPIPSU_NUM_INSTANCES; Index++) {
+		if (XQspiPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XQspiPsu_ConfigTable[Index];
+			break;
+		}
+	}
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/Makefile
new file mode 100644
index 000000000..04867a484
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scugic_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scugic"
+
+scugic_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scugic_includes
+
+scugic_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic.c
new file mode 100644
index 000000000..64954b9a0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic.c
@@ -0,0 +1,712 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
+*		      "Config" entry is now made as pointer in the XScuGic
+*		      structure, necessary changes are made.
+*		      The HandlerTable can now be populated through the low
+*		      level routine XScuGic_RegisterHandler added in this
+*		      release. Hence necessary checks are added not to
+*		      overwrite the HandlerTable entriesin function
+*		      XScuGic_CfgInitialize.
+* 1.03a srt  02/27/13 Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+* 		      Removed Offset calculation macros, defined in _hw.h
+*		      (CR 702687)
+*			  Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.06a asa  16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+*			  in function XScuGic_CfgInitialize is removed as it was
+*		      a bug.
+* 3.00  kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DistributorInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+
+	/*
+	 * The distrubutor should not be initialized by FreeRTOS in the case of
+	 * AMP -- it is assumed that Linux is the master of this device in that
+	 * case.
+	 */
+	return;
+#endif
+	Xil_AssertVoid(InstancePtr != NULL);
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for
+	 * non-secure interrupts
+	 * All are secure, so leave at the default. Set to 1 for non-secure
+	 * interrupts.
+	 */
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) {
+		/*
+		 * Each INT_ID uses two bits, or 16 INT_ID per register
+		 * Set them all to be level sensitive, active HIGH.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+					0U);
+	}
+
+
+#define DEFAULT_PRIORITY    0xa0a0a0a0U
+	for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) {
+		/*
+		 * 2. The priority using int the priority_level register
+		 * The priority_level and spi_target registers use one byte per
+		 * INT_ID.
+		 * Write a default value that can be changed elsewhere.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_IdBaseAddress for this parameters, passing the physical
+*		address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr,
+				XScuGic_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	u32 Int_Id;
+	u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
+	(void) EffectiveAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+		InstancePtr->IsReady = 0;
+		InstancePtr->Config = ConfigPtr;
+
+
+		for (Int_Id = 0U; Int_IdConfig->HandlerTable[Int_Id].Handler == NULL)) {
+				InstancePtr->Config->HandlerTable[Int_Id].Handler =
+									StubHandler;
+			}
+			InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+								InstancePtr;
+		}
+
+		DistributorInit(InstancePtr, Cpu_Id);
+		CPUInitialize(InstancePtr);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return
+*
+*		- XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+                      Xil_InterruptHandler Handler, void *CallBackRef)
+{
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertNonvoid(Handler != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used as an index into the table to select the proper
+	 * handler
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param	Int_Id contains the ID of the interrupt source and should
+*		be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the interrupt such that it won't occur while disconnecting
+	 * the handler, only disable the specified interrupt id without modifying
+	 * the other interrupt ids
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+
+	/*
+	 * Disconnect the handler and connect a stub, the callback reference
+	 * must be set to this instance to allow unhandled interrupts to be
+	 * tracked
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Enable the selected interrupt source by setting the
+	 * corresponding bit in the Enable Set register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the selected interrupt source by setting the
+	 * corresponding bit in the IDR.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller.  This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode.  A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id is the software interrupt ID to simulate an interrupt.
+* @param	Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Int_Id <= 15U) ;
+	Xil_AssertNonvoid(Cpu_Id <= 255U) ;
+
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired interrupt. Int_Id currently limited to 0 - 15
+	 * Use the target list for the Cpu ID.
+	 */
+	Mask = ((Cpu_Id << 16U) | Int_Id) &
+		(XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+	/*
+	 * Write to the Software interrupt trigger register. Use the appropriate
+	 * CPU Int_Id.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+	/* Indicate the interrupt was successfully simulated */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef) {
+	/*
+	 * verify that the inputs are valid
+	 */
+	Xil_AssertVoid(CallBackRef != NULL);
+
+	/*
+	 * Indicate another unhandled interrupt for stats
+	 */
+	((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority;
+	LocalPriority = Priority;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				RegValue);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic.h
new file mode 100644
index 000000000..86adf7b18
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic.h
@@ -0,0 +1,315 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+*   - specific individual interrupt enabling/disabling
+*   - specific individual interrupt acknowledging
+*   - attaching specific callback function to handle interrupt source
+*   - assigning desired priority to interrupt source if default is not
+*     acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* Interrupt Vector Tables
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs.  The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+	Xil_InterruptHandler Handler;
+	void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
+	u32 DistBaseAddress;	/**< Distributor Register base address */
+	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+				 Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+	XScuGic_Config *Config;  /**< Configuration table entry */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+			Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+							u32 EffectiveAddr);
+
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger);
+
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32  XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_g.c
new file mode 100644
index 000000000..830f94ebf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_g.c
@@ -0,0 +1,56 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[] =
+{
+	{
+		XPAR_PSU_ACPU_GIC_DEVICE_ID,
+		XPAR_PSU_ACPU_GIC_BASEADDR,
+		XPAR_PSU_ACPU_GIC_DIST_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_hw.c
new file mode 100644
index 000000000..866aadf64
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_hw.c
@@ -0,0 +1,567 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm  07/18/11 First release
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+*					  Added support to direct interrupts to the appropriate CPU.
+*			  Earlier interrupts were directed to CPU1 (hard coded). Now
+*			  depending upon the CPU selected by the user (xparameters.h),
+*			  interrupts will be directed to the relevant CPU.
+*			  This fixes CR 699688.
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved functions
+*			  XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config, u32 CpuID);
+static void CPUInit(XScuGic_Config *Config);
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+
+	/*
+	 * The distrubutor should not be initialized by FreeRTOS in the case of
+	 * AMP -- it is assumed that Linux is the master of this device in that
+	 * case.
+	 */
+	return;
+#endif
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for non-secure
+	 * interrupts. All are secure, so leave at the default. Set to 1 for
+	 * non-secure interrupts.
+	 */
+
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_IdDistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+	}
+
+
+#define DEFAULT_PRIORITY	0xa0a0a0a0U
+	for (Int_Id = 0U; Int_IdDistBaseAddress,
+				XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_IdDistBaseAddress,
+				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
+	}
+
+	for (Int_Id = 0U; Int_IdDistBaseAddress,
+		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+		Int_Id),
+		0xFFFFFFFFU);
+
+	}
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+						XSCUGIC_EN_INT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param	ConfigPtr is a pointer to a config table for the particular
+*		device this driver is associated with.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+	/*
+	 * Program the priority mask of the CPU using the Priority mask
+	 * register
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+									0xF0U);
+
+	/*
+	 * If the CPU operates in both security domains, set parameters in the
+	 * control_s register.
+	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
+	 * 2. Program the AckCtl bit
+	 * 3. Program the SBPR bit to select the binary pointer behavior
+	 * 4. Set EnableS = 1 to enable secure interrupts
+	 * 5. Set EnbleNS = 1 to enable non secure interrupts
+	 */
+
+	/*
+	 * If the CPU operates only in the secure domain, setup the
+	 * control_s register.
+	 * 1. Set FIQen=1,
+	 * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+	 * interrupts Only enable the IRQ output unless secure interrupts
+	 * are needed.
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param ConfigPtr is a pointer to a config table for the particular device
+*        this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory address
+*        space. The caller is responsible for keeping the address mapping
+*        from EffectiveAddr to the device physical base address unchanged
+*        once this function is invoked. Unexpected errors may occur if the
+*        address mapping changes after this function is called. If address
+*        translation is not used, use Config->BaseAddress for this parameters,
+*        passing the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+	XScuGic_Config *Config;
+	u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
+
+	Config = &XScuGic_ConfigTable[(u32 )DeviceId];
+
+	DistInit(Config, Cpu_Id);
+
+	CPUInit(Config);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param	DeviceId is the unique identifier for the ScuGic device.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+	u32 InterruptID;
+	u32 IntIDFull;
+	XScuGic_VectorTableEntry *TablePtr;
+	XScuGic_Config *CfgPtr;
+
+	CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId];
+
+	/*
+	 * Read the int_ack register to identify the highest priority
+	 * interrupt ID and make sure it is valid. Reading Int_Ack will
+	 * clear the interrupt in the GIC.
+	 */
+	IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
+	InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+	if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	}
+
+	/*
+	 * If the interrupt is shared, do some locking here if there are
+	 * multiple processors.
+	 */
+	/*
+	 * If pre-eption is required:
+	 * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	 * interrupts or the F bit for secure interrupts
+	 */
+
+	/*
+	 * If we need to change security domains, issue a SMC instruction here.
+	 */
+
+	/*
+	 * Execute the ISR. Jump into the Interrupt service routine based on
+	 * the IRQSource. A software trigger is cleared by the ACK.
+	 */
+	TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+	if(TablePtr != NULL) {
+		TablePtr->Handler(TablePtr->CallBackRef);
+	}
+
+IntrExit:
+	/*
+	 * Write to the EOI register, we are all done here.
+	 * Let this function return, the boot code will restore the stack.
+	 */
+	XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	/*
+	 * Return from the interrupt. Change security domains could happen
+	 * here.
+	 */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID.  The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param	BaseAddress is the CPU Interface Register base address of the
+*		interrupt controller whose vector table will be modified.
+* @param	InterruptId is the interrupt ID to be associated with the input
+*		handler.
+* @param	Handler is the function pointer that will be added to
+*		the vector table for the given interrupt ID.
+* @param	CallBackRef is the argument that will be passed to the new
+*		handler function when it is called. This is user-specific.
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler IntrHandler, void *CallBackRef)
+{
+	XScuGic_Config *CfgPtr;
+	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+	if(CfgPtr != NULL) {
+		if( IntrHandler != NULL) {
+			CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
+		}
+		if( CallBackRef != NULL) {
+			CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param	CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return 	A pointer to the configuration structure for the specified
+*		device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+				CpuBaseAddress) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_SetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority = Priority;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					RegValue);
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_GetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_hw.h
new file mode 100644
index 000000000..580ce6ba9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_hw.h
@@ -0,0 +1,637 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL    	248U
+#define XSCUGIC_INTR_PRIO_MASK			0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET		0x00000000U /**< Distributor Enable
+							Register */
+#define XSCUGIC_IC_TYPE_OFFSET		0x00000004U /**< Interrupt Controller
+							Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008U /**< Implementor ID
+							Register */
+#define XSCUGIC_SECURITY_OFFSET		0x00000080U /**< Interrupt Security
+							Register */
+#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100U /**< Enable Set
+							Register */
+#define XSCUGIC_DISABLE_OFFSET		0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET	0x00000200U /**< Pending Set
+							Register */
+#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280U /**< Pending Clear
+							Register */
+#define XSCUGIC_ACTIVE_OFFSET		0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET		0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800U /**< SPI Target
+							Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET		0x00000C00U /**< Interrupt Configuration
+							Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04U /**< SPI Status Register
+							0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80U /**< AHB Configuration
+							Register */
+#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00U /**< Software Triggered
+							Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET		0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET		0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name  Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK		0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name  Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK	0x0000F800U /**< Number of Lockable
+						Shared Peripheral
+						Interrupts*/
+#define XSCUGIC_DOMAIN_MASK	0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK	0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK	0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name  Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK	0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK	0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name  Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080.  A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK	0x00000001U /**< Each bit corresponds to an
+					      INT_ID */
+/* @} */
+
+/** @name  Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK	0x000000FFU /**< Each Byte corresponds to an
+						INT_ID */
+#define XSCUGIC_PRIORITY_MAX	0x000000FFU /**< Highest value of a priority
+						actually the lowest priority*/
+/* @} */
+
+/** @name  SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK	0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK	0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK	0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK	0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK	0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK	0x00000003U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK	0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK	0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name  Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI    Read Only    b10 always
+ * PPI    Read Only    depending on how the PPIs are configured.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive
+ * SPI                LSB is read only.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK    0x00000003U    /**< */
+/* @} */
+
+/** @name  PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK	0x00008000U    /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK	0x00004000U    /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK	0x00002000U    /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK	0x00001000U    /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK	0x00000800U    /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK	0x00000400U    /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK	0x00000200U    /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK	0x00000100U    /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK	0x00000080U    /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK	0x00000040U    /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK	0x00000020U    /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK	0x00000010U    /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK	0x00000008U    /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK	0x00000004U    /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK	0x00000002U    /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK	0x00000001U    /**< PPI Status */
+/* @} */
+
+/** @name  SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK    0x00000001U    /**< Each bit corresponds to an SPI
+					     input */
+/* @} */
+
+/** @name  AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK       0x00000004U    /**< 0-GIC uses little Endian,
+                                                  1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002U    /**< 0-Uses CFGBIGEND control,
+                                                  1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001U    /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name  Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000U    /**< Target List filter
+                                                            b00-Use the target List
+                                                            b01-All CPUs except requester
+                                                            b10-To Requester
+                                                            b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000U    /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000U    /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000FU    /**< Set to the INTID
+                                                        signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET		0x00000000U /**< CPU Interface Control
+							Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET		0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET		0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET		0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET		0x00000018U /**< Highest Pending Interrupt
+							Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001CU /**< Aliased non-Secure
+						        Binary Point Register */
+
+/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK	0x00000010U    /**< Secure Binary Pointer,
+                                                 0=separate registers,
+                                                 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008U    /**< Use nFIQ_C for secure
+                                                  interrupts,
+                                                  0= use IRQ for both,
+                                                  1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004U    /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002U    /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK		0x00000001U    /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK		0x000000FFU*/   /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK	0x00000007U  /**< Binary point mask value
+						Value  Secure  Non-secure
+						b000    0xFE    0xFF
+						b001    0xFC    0xFE
+						b010    0xF8    0xFC
+						b011    0xF0    0xF8
+						b100    0xE0    0xF0
+						b101    0xC0    0xE0
+						b110    0x80    0xC0
+						b111    0x00    0x80
+						*/
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK		0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK		0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK		0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK	0x000000FFU    /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK		0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK		0x00000C00U */	 /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param	Register is the register offset for the clear/enable bank.
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+		((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32  XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+                                        u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_intr.c
new file mode 100644
index 000000000..3efd84022
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_intr.c
@@ -0,0 +1,170 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller.  The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing.  This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported.  This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system.  The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 XScuGic_InterruptHandler has changed correspondingly
+*		      since the HandlerTable has now moved to XScuGic_Config.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+	u32 InterruptID;
+	    u32 IntIDFull;
+	    XScuGic_VectorTableEntry *TablePtr;
+
+	    /* Assert that the pointer to the instance is valid
+	     */
+	    Xil_AssertVoid(InstancePtr != NULL);
+
+	    /*
+	     * Read the int_ack register to identify the highest priority interrupt ID
+	     * and make sure it is valid. Reading Int_Ack will clear the interrupt
+	     * in the GIC.
+	     */
+	    IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+	    InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+	    if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	    }
+
+	    /*
+	     * If the interrupt is shared, do some locking here if there are multiple
+	     * processors.
+	     */
+	    /*
+	     * If pre-eption is required:
+	     * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	     * interrupts or the F bit for secure interrupts
+	     */
+
+	    /*
+	     * If we need to change security domains, issue a SMC instruction here.
+	     */
+
+	    /*
+	     * Execute the ISR. Jump into the Interrupt service routine based on the
+	     * IRQSource. A software trigger is cleared by the ACK.
+	     */
+	    TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+		if(TablePtr != NULL) {
+	        TablePtr->Handler(TablePtr->CallBackRef);
+		}
+
+	IntrExit:
+	    /*
+	     * Write to the EOI register, we are all done here.
+	     * Let this function return, the boot code will restore the stack.
+	     */
+	    XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	    /*
+	     * Return from the interrupt. Change security domains could happen here.
+     */
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_selftest.c
new file mode 100644
index 000000000..c6df73752
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_selftest.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define	XSCUGIC_PCELL_ID	0xB105F00DU
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* 		- XST_SUCCESS if self-test is successful.
+* 		- XST_FAILURE if the self-test is not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+	u32 RegValue1 = 0U;
+	u32 Index;
+	s32 Status;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the ID registers.
+	 */
+	for(Index=0U; Index<=3U; Index++) {
+		RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+			((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U);
+	}
+
+	if(XSCUGIC_PCELL_ID != RegValue1){
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_sinit.c
new file mode 100644
index 000000000..c90dabdfb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_0/src/xscugic_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique identifier for a device.
+*
+* @return	A pointer to the XScuGic configuration structure for the
+*		specified device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/Makefile
new file mode 100644
index 000000000..f57081af6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsdps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling sdps"
+
+xsdps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsdps_includes
+
+xsdps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps.c
new file mode 100644
index 000000000..c4c66f6f1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps.c
@@ -0,0 +1,1118 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk     12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1   hk     04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#ifdef __arm__
+
+#include "sleep.h"
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+#include "microblaze_sleep.h"
+
+#endif
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN	0x1AA
+#define XSDPS_RESPOCR_READY	0x80000000
+#define XSDPS_ACMD41_HCS	0x40000000
+#define XSDPS_ACMD41_3V3	0x00300000
+#define XSDPS_CMD1_HIGH_VOL	0x00FF8000
+#define XSDPS_CMD1_DUAL_VOL	0x00FF8010
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XSDPS_INIT_DELAY	2000
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(u32 Cmd);
+int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific SD device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		This function initializes the host controller.
+*		Initial clock of 400KHz is set.
+*		Voltage of 3.3V is selected as that is supported by host.
+*		Interrupts status is enabled and signal disabled by default.
+*		Default data direction is card to host and
+*		32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
+*
+******************************************************************************/
+int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	u32 ClockReg;
+	u32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
+	InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
+
+	/*
+	 * "Software reset for all" is initiated
+	 */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_ALL_MASK);
+
+	/*
+	 * Proceed with initialization only after reset is complete
+	 */
+	while (XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_SW_RST_OFFSET) & XSDPS_SWRST_ALL_MASK);
+
+	/*
+	 * Read capabilities register and update it in Instance pointer.
+	 * It is sufficient to read this once on power on.
+	 */
+	InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_CAPS_OFFSET);
+
+	/*
+	 * Select voltage and enable bus power.
+	 */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_POWER_CTRL_OFFSET,
+			XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+	/*
+	 * Change the clock frequency to 400 KHz
+	 */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH ;
+	}
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			XSDPS_HC_DMA_ADMA2_32_MASK);
+
+	/*
+	 * Enable all interrupt status except card interrupt initially
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_EN_OFFSET,
+			XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_EN_OFFSET,
+			XSDPS_ERROR_INTR_ALL_MASK);
+
+	/*
+	 * Disable all interrupt signals by default.
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0);
+
+	/*
+	 * Transfer mode register - default value
+	 * DMA enabled, block count enabled, data direction card to host(read)
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_DAT_DIR_SEL_MASK);
+
+	/*
+	 * Set block size to 512 by default
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+			   initialization cycle failed
+*
+* @note		This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD8 and ACDM41 are sent to identify voltage and
+*		high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+int XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	u32 Status;
+	u32 RespOCR = 0x0;
+	u32 CSD[4];
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if(InstancePtr->Config.CardDetect) {
+		/*
+		 * Check the present state register to make sure
+		 * card is inserted and detected by host controller
+		 */
+		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+		if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0)	{
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/*
+	 * 74 CLK delay after card is powered up, before the first command.
+	 */
+
+#ifdef __arm__
+
+	usleep(XSDPS_INIT_DELAY);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	/*
+	 * CMD0 no response expected
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * CMD8; response expected
+	 * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+			XSDPS_CMD8_VOL_PATTERN, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_RESP0_OFFSET);
+	if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+		InstancePtr->CardType = CT_SD1;
+	}
+	else {
+		InstancePtr->CardType = CT_SD2;
+	}
+
+	RespOCR = 0;
+	/*
+	 * Send ACMD41 while card is still busy with power up
+	 */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0) {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0, 0);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * 0x40300000 - Host High Capacity support & 3.3V window
+		 */
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+				(XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3), 0);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Response with card capacity
+		 */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/*
+	 * Update HCS support flag based on card capacity response
+	 */
+	if (RespOCR & XSDPS_ACMD41_HCS)
+		InstancePtr->HCS = 1;
+
+	/*
+	 * CMD2 for Card ID
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+	do {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0, 0);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Relative card address is stored as the upper 16 bits
+		 * This is to avoid shifting when sending commands
+		 */
+		InstancePtr->RelCardAddr =
+				XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_RESP0_OFFSET) & 0xFFFF0000;
+	} while (InstancePtr->RelCardAddr == 0);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function does SD command generation.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cmd is the command to be sent.
+* @param	Arg is the argument to be sent along with the command.
+* 		This could be address or any other information
+* @param	BlkCnt - Block count passed by the user.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 			is in progress or command or data inhibit is set
+*
+******************************************************************************/
+int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+	u32 PresentStateReg;
+	u32 CommandReg;
+	u32 StatusReg;
+	u32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check the command inhibit to make sure no other
+	 * command transfer is in progress
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if (PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Write block count register
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_CNT_OFFSET, BlkCnt);
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_TIMEOUT_CTRL_OFFSET, 0xE);
+
+	/*
+	 * Write argument register
+	 */
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XSDPS_ARGMT_OFFSET, Arg);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+	/*
+	 * Command register is set to trigger transfer of command
+	 */
+	CommandReg = XSdPs_FrameCmd(Cmd);
+
+	/*
+	 * Mask to avoid writing to reserved bits 31-30
+	 * This is necessary because 0x80000000 is used  by this software to
+	 * distinguish between ACMD and CMD of same number
+	 */
+	CommandReg = CommandReg & 0x3FFF;
+
+	/*
+	 * Check for data inhibit in case of command using DAT lines
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_INHIBIT_DAT_MASK) &&
+			(CommandReg & XSDPS_DAT_PRESENT_SEL_MASK)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET,
+			CommandReg);
+
+	/*
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_CC_MASK) == 0);
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET,
+			XSDPS_INTR_CC_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param	Command to be sent.
+*
+* @return	Command register value complete with response type and
+* 		data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(u32 Cmd)
+{
+		u32 RetVal;
+
+		RetVal = Cmd;
+
+		switch(Cmd) {
+		case CMD0:
+			RetVal |= RESP_NONE;
+		break;
+		case CMD1:
+			RetVal |= RESP_R3;
+		break;
+		case CMD2:
+			RetVal |= RESP_R2;
+		break;
+		case CMD3:
+			RetVal |= RESP_R6;
+		break;
+		case CMD4:
+			RetVal |= RESP_NONE;
+			break;
+		case CMD5:
+			RetVal |= RESP_R1B;
+		break;
+
+#ifndef MMC_CARD
+		case CMD6:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+			break;
+#else
+		case CMD6:
+			RetVal |= RESP_R1B;
+			break;
+#endif
+
+		case ACMD6:
+			RetVal |= RESP_R1;
+		break;
+		case CMD7:
+			RetVal |= RESP_R1;
+		break;
+
+#ifndef MMC_CARD
+		case CMD8:
+			RetVal |= RESP_R1;
+			break;
+#else
+		case CMD8:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+			break;
+#endif
+
+		case CMD9:
+			RetVal |= RESP_R2;
+		break;
+		case CMD10:
+		case CMD12:
+		case ACMD13:
+		case CMD16:
+			RetVal |= RESP_R1;
+		break;
+		case CMD17:
+		case CMD18:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD23:
+		case ACMD23:
+		case CMD24:
+		case CMD25:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+		case ACMD41:
+			RetVal |= RESP_R3;
+		break;
+		case ACMD42:
+			RetVal |= RESP_R1;
+		break;
+		case ACMD51:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD52:
+		case CMD55:
+			RetVal |= RESP_R1;
+		break;
+		case CMD58:
+		break;
+		}
+
+		return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+	u32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if(InstancePtr->Config.CardDetect) {
+		/*
+		 * Check status to ensure card is initialized
+		 */
+		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+		if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/*
+	 * Set block size to 512 if not already set
+	 */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK);
+
+	Xil_DCacheInvalidateRange(Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+
+	/*
+	 * Send block read command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+	u32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if(InstancePtr->Config.CardDetect) {
+		/*
+		 * Check status to ensure card is initialized
+		 */
+		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+		if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/*
+	 * Set block size to 512 if not already set
+	 */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+	Xil_DCacheFlushRange(Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	/*
+	 * Send block write command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+	u32 Status = 0;
+
+	/*
+	 * Send CMD7 - Select card
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+			InstancePtr->RelCardAddr, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	/*
+	 * Set default block size
+	 */
+	Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	BlkCnt - block count.
+* @param	Buff pointer to data buffer.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+	u32 TotalDescLines = 0;
+	u32 DescNum = 0;
+	u32 BlkSize = 0;
+
+	/*
+	 * Setup ADMA2 - Write descriptor table and point ADMA SAR to it
+	 */
+	BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_BLK_SIZE_OFFSET);
+	BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
+
+	if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+		TotalDescLines = 1;
+
+	}else {
+
+		TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+		if ((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH)
+			TotalDescLines += 1;
+
+	}
+
+	for (DescNum = 0; DescNum < (TotalDescLines-1); DescNum++) {
+		InstancePtr->Adma2_DescrTbl[DescNum].Address =
+				(u32)(Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+		InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+				XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+		/*
+		 * This will write '0' to length field which indicates 65536
+		 */
+		InstancePtr->Adma2_DescrTbl[DescNum].Length =
+				(u16)XSDPS_DESC_MAX_LENGTH;
+	}
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+			(u32)(Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+			XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+			(BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH);
+
+
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+			(u32)&(InstancePtr->Adma2_DescrTbl[0]));
+
+	Xil_DCacheFlushRange(&(InstancePtr->Adma2_DescrTbl[0]),
+			sizeof(XSdPs_Adma2Descriptor) * 32);
+
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) MMC is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the initialization
+*			   cycle failed
+* @note 	This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD1 sent to identify voltage and high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+int XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	u32 Status;
+	u32 RespOCR = 0x0;
+	u32 CSD[4];
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if(InstancePtr->Config.CardDetect) {
+		/*
+		 * Check the present state register to make sure
+		 * card is inserted and detected by host controller
+		 */
+		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+		if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0)	{
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/*
+	 * 74 CLK delay after card is powered up, before the first command.
+	 */
+
+#ifdef __arm__
+
+	usleep(XSDPS_INIT_DELAY);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	/*
+	 * CMD0 no response expected
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardType = CT_MMC;
+	RespOCR = 0;
+	/*
+	 * Send CMD1 while card is still busy with power up
+	 */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0) {
+
+		/*
+		 * Host High Capacity support & High volage window
+		 */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+				XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Response with card capacity
+		 */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/*
+	 * Update HCS support flag based on card capacity response
+	 */
+	if (RespOCR & XSDPS_ACMD41_HCS)
+		InstancePtr->HCS = 1;
+
+	/*
+	 * CMD2 for Card ID
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Relative card address is stored as the upper 16 bits
+	 * This is to avoid shifting when sending commands
+	 */
+	InstancePtr->RelCardAddr =
+			XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET) & 0xFFFF0000;
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps.h
new file mode 100644
index 000000000..64532a0d3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps.h
@@ -0,0 +1,208 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+*
+* 

+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include 
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CLK_400_KHZ		400000		/**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ		50000000	/**< 50 MHZ */
+#define CT_MMC					0x1		/**< MMC Card */
+#define CT_SD1					0x2		/**< SD ver 1 */
+#define CT_SD2					0x3		/**< SD ver 2 */
+/**************************** Type Definitions *******************************/
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Unique ID  of device */
+	u32 BaseAddress;		/**< Base address of the device */
+	u32 InputClockHz;		/**< Input clock frequency */
+	u32 CardDetect;			/**< Card Detect */
+	u32 WriteProtect;			/**< Write Protect */
+} XSdPs_Config;
+
+/*
+ * ADMA2 descriptor table
+ */
+typedef struct {
+	u16 Attribute;		/**< Attributes of descriptor */
+	u16 Length;		/**< Length of current dma transfer */
+	u32 Address;		/**< Address of current dma transfer */
+} XSdPs_Adma2Descriptor;
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSdPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 Host_Caps;		/**< Capabilities of host controller */
+	u32 HCS;		/**< High capacity support in card */
+	u32 CardID[4];		/**< Card ID */
+	u32 RelCardAddr;	/**< Relative Card Address */
+	u32 CardType;		/**< Card Type(version) */
+	/**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+int XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+int XSdPs_Select_Card (XSdPs *InstancePtr);
+int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+int XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+int XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+int XSdPs_Pullup(XSdPs *InstancePtr);
+int XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_g.c
new file mode 100644
index 000000000..535a31c62
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_g.c
@@ -0,0 +1,65 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_SD_0_DEVICE_ID,
+		XPAR_PSU_SD_0_BASEADDR,
+		XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ,
+		XPAR_PSU_SD_0_HAS_CD,
+		XPAR_PSU_SD_0_HAS_WP
+	},
+	{
+		XPAR_PSU_SD_1_DEVICE_ID,
+		XPAR_PSU_SD_1_BASEADDR,
+		XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
+		XPAR_PSU_SD_1_HAS_CD,
+		XPAR_PSU_SD_1_HAS_WP
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_hw.h
new file mode 100644
index 000000000..a9670d0fc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_hw.h
@@ -0,0 +1,605 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*
+* 

+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET	0x00	/**< SDMA System Address
+							Register */
+#define XSDPS_BLK_SIZE_OFFSET		0x04	/**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET		0x06	/**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET		0x08	/**< Argument Register */
+#define XSDPS_XFER_MODE_OFFSET		0x0C	/**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET		0x0E	/**< Command Register */
+#define XSDPS_RESP0_OFFSET		0x10	/**< Response0 Register */
+#define XSDPS_RESP1_OFFSET		0x14	/**< Response1 Register */
+#define XSDPS_RESP2_OFFSET		0x18	/**< Response2 Register */
+#define XSDPS_RESP3_OFFSET		0x1C	/**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET	0x20	/**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET		0x24	/**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET		0x28	/**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET		0x29	/**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET	0x2A	/**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET	0x2B	/**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET		0x2C	/**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET	0x2E	/**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET		0x2F	/**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 	0x30	/**< Normal Interrupt
+							Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 	0x32	/**< Error Interrupt
+							Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET	0x34	/**< Normal Interrupt
+						Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET	0x36	/**< Error Interrupt
+						Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET	0x38	/**< Normal Interrupt
+						Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET	0x3A	/**< Error Interrupt
+						Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET	0x3C	/**< Auto CMD12 Error Status
+							Register */
+#define XSDPS_HOST_CTRL2_OFFSET		0x3E	/**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 		0x40	/**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 		0x44	/**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET	0x48	/**< Maximum Current
+						Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET	0x4C	/**< Maximum Current
+						Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET	0x52	/**< Force Event for
+						Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET	0x50	/**< Auto CM12 Error Interrupt
+							Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET	0x54	/**< ADMA Error Status
+							Register */
+#define XSDPS_ADMA_SAR_OFFSET		0x58	/**< ADMA System Address
+							Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET	0x5C	/**< ADMA System Address
+							Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET		0x60	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET		0x64	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET		0x68	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET		0x6C	/**< Preset Value Register */
+#define XSDPS_SHARED_BUS_CTRL_OFFSET	0xE0	/**< Shared Bus Control
+							Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET	0xFC	/**< Slot Interrupt Status
+							Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET	0xFE	/**< Host Controller Version
+							Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * 			Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK		0x00000001 /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK		0x00000002 /**< Bus width */
+#define XSDPS_HC_SPEED_MASK		0x00000004 /**< High Speed */
+#define XSDPS_HC_DMA_MASK		0x00000018 /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK		0x00000000 /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK		0x00000008 /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK	0x00000010 /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK	0x00000018 /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH		0x00000020 /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK	0x00000040 /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK	0x00000080 /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK		0x00000001 /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK		0x0000000E /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK	0x0000000E /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK	0x0000000C /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK	0x0000000A /**< Bus Voltage 1.8V */
+
+#define XSDPS_BGC_STP_REQ_MASK		0x00000001 /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK		0x00000002 /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK		0x00000004 /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK		0x00000008 /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK		0x00000010 /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK		0x00000020 /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK	0x00000040 /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK		0x00000080 /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK	0x00000001 /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK	0x00000002 /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK	0x00000004 /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK		0x00000001
+#define XSDPS_CC_INT_CLK_STABLE_MASK	0x00000002
+#define XSDPS_CC_SD_CLK_EN_MASK			0x00000004
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK		0x00000020
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK	0x000000C0
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK		0x0000FF00
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK		0x00008000
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK		0x00004000
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK		0x00002000
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK		0x00001000
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK		0x00000800
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK		0x00000400
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK		0x00000200
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK		0x00000100
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK	0x00000000
+
+#define XSDPS_TC_CNTR_VAL_MASK			0x0000000F
+
+#define XSDPS_SWRST_ALL_MASK			0x00000001
+#define XSDPS_SWRST_CMD_LINE_MASK		0x00000002
+#define XSDPS_SWRST_DAT_LINE_MASK		0x00000004
+
+#define XSDPS_CC_MAX_NUM_OF_DIV		9
+#define XSDPS_CC_DIV_SHIFT		8
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ *  Normal and Error Interrupt Status Register 
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ *  Normal and Error Interrupt Status Enable Register 
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ *  Normal and Error Interrupt Signal Enable Register 
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK		0x00000001 /**< Command Complete */
+#define XSDPS_INTR_TC_MASK		0x00000002 /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK		0x00000004 /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK		0x00000008 /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK		0x00000010 /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK		0x00000020 /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK	0x00000040 /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK	0x00000080 /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK		0x00000100 /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK		0x00000200 /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK		0x00000400 /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK		0x00000800 /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK	0x00001000 /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK	0x00002000 /**< Boot Terminate
+							Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK	0x00004000 /**< Boot Ack Recv
+							Interrupt */
+#define XSDPS_INTR_ERR_MASK		0x00008000 /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK	0x0000FFFF
+
+#define XSDPS_INTR_ERR_CT_MASK		0x00000001 /**< Command Timeout
+							Error */
+#define XSDPS_INTR_ERR_CCRC_MASK	0x00000002 /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK		0x00000004 /**< Command End Bit
+							Error */
+#define XSDPS_INTR_ERR_CI_MASK		0x00000008 /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK		0x00000010 /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK	0x00000020 /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK		0x00000040 /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_I_LMT_MASK	0x00000080 /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK	0x00000100 /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK	0x00000200 /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK		0x00001000 /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK	0x0000E000 /**< Vendor Specific
+							Error */
+#define XSDPS_ERROR_INTR_ALL_MASK	0x0000F3FF /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK		0x00000FFF /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK	0x00007000 /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_CNT_MASK		0x0000FFFF /**< Block Count for
+								Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK		0x00000001 /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK	0x00000002 /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK	0x00000004 /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK	0x00000010 /**< Data Transfer
+							Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK	0x00000020 /**< Multi/Single
+							Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK		0x00000003 /**< Response Type
+							Select */
+#define XSDPS_CMD_RESP_NONE_MASK	0x00000000 /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK	0x00000001 /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK		0x00000002 /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK	0x00000003 /**< Response length 48 &
+							check busy after
+							response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK	0x00000008 /**< Command CRC Check
+							Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK	0x00000010 /**< Command Index Check
+							Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK	0x00000020 /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK		0x000000C0 /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK	0x00000000 /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK	0x00000040 /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK	0x00000080 /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK	0x000000C0 /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK			0x00003F00 /**< Command Index Mask -
+							Set to CMD0-63,
+							AMCD0-63 */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK	0x0000003F /**< Timeout clock freq
+							select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK	0x00000080 /**< Timeout clock unit -
+							MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK	0x00030000 /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK	0x00000000 /**< Max block 512 bytes */
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK	0x00040000 /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK		0x00080000 /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK	0x00200000 /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK		0x00400000 /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK	0x00800000 /**< Suspend/Resume
+							support */
+#define XSDPS_CAP_VOLT_3V3_MASK		0x01000000 /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK		0x02000000 /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK		0x04000000 /**< 1.8V support */
+#define XSDPS_CAP_INTR_MODE_MASK	0x08000000 /**< Interrupt mode
+							support */
+#define XSDPS_CAP_SYS_BUS_64_MASK	0x10000000 /**< 64 bit system bus
+							support */
+#define XSDPS_CAP_SPI_MODE_MASK		0x20000000 /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK	0x20000000 /**< SPI block mode */
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK	0x00000001 /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK	0x00000002 /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK	0x00000004 /**< DAT line active */
+#define XSDPS_PSR_WR_ACTIVE_MASK	0x00000100 /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK	0x00000200 /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK	0x00000400 /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK	0x00000800 /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK	0x00010000 /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK	0x00020000 /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK		0x00040000 /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK		0x00080000 /**< Write protect switch
+								pin level */
+
+/* @} */
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK	0x200
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX	 0x8000
+#define CMD0	 0x0000
+#define CMD1	 0x0100
+#define CMD2	 0x0200
+#define CMD3	 0x0300
+#define CMD4	 0x0400
+#define CMD5	 0x0500
+#define CMD6     0x0600
+#define ACMD6    (XSDPS_APP_CMD_PREFIX + 0x0600)
+#define CMD7	 0x0700
+#define CMD8	 0x0800
+#define CMD9	 0x0900
+#define CMD10	 0x0A00
+#define CMD12	 0x0C00
+#define ACMD13	 (XSDPS_APP_CMD_PREFIX + 0x0D00)
+#define CMD16	 0x1000
+#define CMD17	 0x1100
+#define CMD18	 0x1200
+#define CMD23	 0x1700
+#define ACMD23	 (XSDPS_APP_CMD_PREFIX + 0x1700)
+#define CMD24	 0x1800
+#define CMD25	 0x1900
+#define CMD41	 0x2900
+#define ACMD41	 (XSDPS_APP_CMD_PREFIX + 0x2900)
+#define ACMD42	 (XSDPS_APP_CMD_PREFIX + 0x2A00)
+#define ACMD51	 (XSDPS_APP_CMD_PREFIX + 0x3300)
+#define CMD52	 0x3400
+#define CMD55	 0x3700
+#define CMD58	 0x3A00
+
+#define RESP_NONE	XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1		XSDPS_CMD_RESP_L48_MASK | XSDPS_CMD_CRC_CHK_EN_MASK | \
+			XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B	XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2		XSDPS_CMD_RESP_L136_MASK | XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3		XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6		XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536
+
+#define XSDPS_DESC_VALID     	(0x1 << 0)
+#define XSDPS_DESC_END       	(0x1 << 1)
+#define XSDPS_DESC_INT       	(0x1 << 2)
+#define XSDPS_DESC_TRAN  	(0x2 << 4)
+
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+	XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
+	XSdPs_In16((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u16 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
+	XSdPs_In8((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
+
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+		XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_options.c
new file mode 100644
index 000000000..b56f6d466
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_options.c
@@ -0,0 +1,792 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#ifdef __arm__
+
+#include "sleep.h"
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+#include "microblaze_sleep.h"
+
+#endif
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_SCR_BLKCNT	1
+#define XSDPS_SCR_BLKSIZE	8
+#define XSDPS_4_BIT_WIDTH	0x2
+#define XSDPS_SWITCH_CMD_BLKCNT		1
+#define XSDPS_SWITCH_CMD_BLKSIZE	64
+#define XSDPS_SWITCH_CMD_HS_GET	0x00FFFFF0
+#define XSDPS_SWITCH_CMD_HS_SET	0x80FFFFF1
+#define XSDPS_EXT_CSD_CMD_BLKCNT	1
+#define XSDPS_EXT_CSD_CMD_BLKSIZE	512
+#define XSDPS_CLK_52_MHZ		52000000
+#define XSDPS_MMC_HIGH_SPEED_ARG	0x03B90100
+#define XSDPS_MMC_4_BIT_BUS_ARG		0x03B70100
+#define XSDPS_MMC_DELAY_FOR_SWITCH	2000
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	BlkSize - Block size passed by the user.
+*
+* @return	None
+*
+******************************************************************************/
+int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+	u32 Status = 0;
+	u32 PresentStateReg = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+
+	if (PresentStateReg & (XSDPS_PSR_INHIBIT_CMD_MASK |
+			XSDPS_PSR_INHIBIT_DAT_MASK |
+			XSDPS_PSR_WR_ACTIVE_MASK | XSDPS_PSR_RD_ACTIVE_MASK)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+
+	/*
+	 * Send block write command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	/*
+	 * Set block size to the value passed
+	 */
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			 BlkSize);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SCR - buffer to store SCR register returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u16 BlkCnt;
+	u16 BlkSize;
+	int LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+		SCR[LoopCnt] = 0;
+	}
+
+	/*
+	 * Send block write command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	BlkCnt = XSDPS_SCR_BLKCNT;
+	BlkSize = XSDPS_SCR_BLKSIZE;
+
+	/*
+	 * Set block size to the value passed
+	 */
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Xil_DCacheInvalidateRange(SCR, 8);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u32 Arg = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef MMC_CARD
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Arg = XSDPS_4_BIT_WIDTH;
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_WIDTH_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,StatusReg);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+#else
+
+	Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+#ifdef __arm__
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_WIDTH_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,StatusReg);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+#endif
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store function group support data
+*		returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u32 Arg = 0;
+	u16 BlkCnt;
+	u16 BlkSize;
+	int LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0;
+	}
+
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+	Xil_DCacheInvalidateRange(ReadBuff, 64);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u32 Arg = 0;
+
+#ifndef MMC_CARD
+	u32 ClockReg;
+	u8 ReadBuff[64];
+	u16 BlkCnt;
+	u16 BlkSize;
+#endif
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef MMC_CARD
+
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	Xil_DCacheInvalidateRange(ReadBuff, 64);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Arg = XSDPS_SWITCH_CMD_HS_SET;
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	/*
+	 * Change the clock frequency to 50 MHz
+	 */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_50_MHZ);
+	if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+	}
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_SPEED_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,StatusReg);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+#else
+
+	Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+#ifdef __arm__
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_SPEED_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,StatusReg);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+#endif
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SelFreq - Clock frequency in Hz.
+*
+* @return	None
+*
+* @note		This API will change clock frequency to the value less than
+*		or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+	u16 ClockReg;
+	int DivCnt;
+	u16 Divisor;
+	u16 ClkLoopCnt;
+	int Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable clock
+	 */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~(XSDPS_CC_INT_CLK_EN_MASK | XSDPS_CC_SD_CLK_EN_MASK);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/*
+	 * Calculate divisor
+	 */
+	DivCnt = 0x1;
+	for(ClkLoopCnt = 0; ClkLoopCnt < XSDPS_CC_MAX_NUM_OF_DIV;
+		ClkLoopCnt++) {
+		if( ((InstancePtr->Config.InputClockHz)/DivCnt) <= SelFreq) {
+			Divisor = DivCnt/2;
+			Divisor = Divisor << XSDPS_CC_DIV_SHIFT;
+			break;
+		}
+		DivCnt = DivCnt << 1;
+	}
+
+	if(ClkLoopCnt == 9) {
+
+		/*
+		 * No valid divisor found for given frequency
+		 */
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Set clock divisor
+	 */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+	ClockReg |= Divisor | XSDPS_CC_INT_CLK_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/*
+	 * Wait for internal clock to stabilize
+	 */
+	while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+		XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0);
+
+	/*
+	 * Enable SD clock
+	 */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Pullup(XSdPs *InstancePtr)
+{
+	u32 Status = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store EXT_CSD
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u32 Arg = 0;
+	u16 BlkCnt;
+	u16 BlkSize;
+	int LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0;
+	}
+
+	BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+	BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	Xil_DCacheInvalidateRange(ReadBuff, 512);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Arg = 0;
+
+	/*
+	 * Send SEND_EXT_CSD command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_sinit.c
new file mode 100644
index 000000000..4be1ac7fd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_4/src/xsdps_sinit.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+	XSdPs_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XSDPS_NUM_INSTANCES; Index++) {
+		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSdPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/Makefile
new file mode 100644
index 000000000..10d24d73b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xspips_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling spips"
+
+xspips_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xspips_includes
+
+xspips_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips.c
new file mode 100644
index 000000000..a4fdddc3c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips.c
@@ -0,0 +1,1126 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xspips.c
+*
+* Contains implements the interface functions of the XSpiPs driver.
+* See xspips.h for a detailed description of the device and driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/25/10 First release
+* 1.01	sg     03/07/12 Updated the code to always clear the relevant bits
+*			before writing to config register.
+*			Always clear the slave select bits before write and
+*			clear the bits to no slave at the end of transfer
+*			Modified the Polled transfer transmit/receive logic.
+*			Tx should wait on TXOW Interrupt and Rx on RXNEMTY.
+* 1.03	sg     09/21/12 Added memory barrier dmb in polled transfer and
+*			interrupt handler to overcome the clock domain
+*			crossing issue in the controller. For CR #679252.
+* 1.04a	sg     01/30/13 Changed SPI transfer logic for polled and interrupt
+*			modes to be based on filled tx fifo count and receive
+*			based on it. RXNEMPTY interrupt is not used.
+*			SetSlaveSelect API logic is modified to drive the bit
+*			position low based on the slave select value
+*			requested. GetSlaveSelect API will return the value
+*			based on bit position that is low.
+* 1.06a hk     08/22/13 Changed GetSlaveSelect function. CR# 727866.
+*                       Added masking ConfigReg before writing in SetSlaveSel
+*                       Added extended slave select support - CR#722569.
+*                       Added check for MODF in polled transfer function.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Send one byte to the currently selected slave. A byte of data is written to
+* transmit FIFO/register.
+*
+* @param	BaseAddress is the  base address of the device
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSpiPs_SendByte(u32 BaseAddress, u8 Data);
+*
+*****************************************************************************/
+#define XSpiPs_SendByte(BaseAddress, Data) \
+        XSpiPs_Out32((BaseAddress) + (u32)XSPIPS_TXD_OFFSET, (u32)(Data))
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from the device's receive FIFO/register. It is assumed
+* that the byte is already available.
+*
+* @param	BaseAddress is the  base address of the device
+*
+* @return	The byte retrieved from the receive FIFO/register.
+*
+* @note		C-Style signature:
+*		u8 XSpiPs_RecvByte(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XSpiPs_RecvByte(BaseAddress) \
+		XSpiPs_In32((u32)((BaseAddress) + (u32)XSPIPS_RXD_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				u32 ByteCount);
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSpiPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Device is disabled
+*   - Slave mode
+*   - Active high clock polarity
+*   - Clock phase 0
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific SPI device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config. This function can initialize multiple
+*		instance objects with the use of multiple calls giving different
+*		Config information on each call.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSpiPs_CfgInitialize(XSpiPs *InstancePtr, XSpiPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is busy, disallow the initialize and return a status
+	 * indicating it is already started. This allows the user to stop the
+	 * device and re-initialize, but prevents a user from inadvertently
+	 * initializing. This assumes the busy flag is cleared at startup.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_IS_STARTED;
+	} else {
+
+		/*
+		 * Set some default values.
+		 */
+		InstancePtr->IsBusy = FALSE;
+
+		InstancePtr->Config.BaseAddress = EffectiveAddr;
+		InstancePtr->StatusHandler = StubStatusHandler;
+
+		InstancePtr->SendBufferPtr = NULL;
+		InstancePtr->RecvBufferPtr = NULL;
+		InstancePtr->RequestedBytes = 0U;
+		InstancePtr->RemainingBytes = 0U;
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		/*
+		 * Reset the SPI device to get it into its initial state. It is
+		 * expected that device configuration will take place after this
+		 * initialization is done, but before the device is started.
+		 */
+		XSpiPs_Reset(InstancePtr);
+		Status = (s32)XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Resets the SPI device. Reset must only be called after the driver has been
+* initialized. The configuration of the device after reset is the same as its
+* configuration after initialization.  Any data transfer that is in progress
+* is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the SPI device after the reset.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XSpiPs_Reset(XSpiPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress
+	 */
+	XSpiPs_Abort(InstancePtr);
+
+        /*
+         * Reset any values that are not reset by the hardware reset such that
+         * the software state matches the hardware device
+         */
+        XSpiPs_WriteReg(InstancePtr->Config.BaseAddress, XSPIPS_CR_OFFSET,
+                        XSPIPS_CR_RESET_STATE);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Transfers specified data on the SPI bus. If the SPI device is configured as
+* a master, this function initiates bus communication and sends/receives the
+* data to/from the selected SPI slave. If the SPI device is configured as a
+* slave, this function prepares the buffers to be sent/received when selected
+* by a master. For every byte sent, a byte is received. This function should
+* be used to perform interrupt based transfers.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* 
+*   XSpiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XSpiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XSpiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XSpiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+* 

+* Although this function takes entire buffers as arguments, the driver can only
+* transfer a limited number of bytes at a time, limited by the size of the
+* FIFO. A call to this function only starts the transfer, then subsequent
+* transfers of the data is performed by the interrupt service routine until
+* the entire buffer has been transferred. The status callback function is
+* called when the entire buffer has been sent/received.
+*
+* This function is non-blocking. As a master, the SetSlaveSelect function must
+* be called prior to this function.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	SendBufPtr is a pointer to a buffer of data for sending.
+*		This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+*
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the SPI bus at the same time.
+*
+******************************************************************************/
+s32 XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
+			u8 *RecvBufPtr, u32 ByteCount)
+{
+	u32 ConfigReg;
+	u8 TransCount = 0U;
+	s32 StatusTransfer;
+
+	/*
+	 * The RecvBufPtr argument can be null
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0U);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		StatusTransfer = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		/*
+		 * Set the busy flag, which will be cleared in the ISR when the
+		 * transfer is entirely done.
+		 */
+		InstancePtr->IsBusy = TRUE;
+
+		/*
+		 * Set up buffer pointers.
+		 */
+		InstancePtr->SendBufferPtr = SendBufPtr;
+		InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+		InstancePtr->RequestedBytes = ByteCount;
+		InstancePtr->RemainingBytes = ByteCount;
+
+	/*
+	 * If manual chip select mode, initialize the slave select value.
+	 */
+	if (XSpiPs_IsManualChipSelect(InstancePtr) != FALSE) {
+		ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET);
+		/*
+		 * Set the slave select value.
+		 */
+		ConfigReg &= (u32)(~XSPIPS_CR_SSCTRL_MASK);
+		ConfigReg |= InstancePtr->SlaveSelect;
+		XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				 XSPIPS_CR_OFFSET, ConfigReg);
+	}
+
+		/*
+		 * Enable the device.
+		 */
+		XSpiPs_Enable(InstancePtr);
+
+		/*
+		 * Clear all the interrrupts.
+		 */
+		XSpiPs_WriteReg(InstancePtr->Config.BaseAddress, XSPIPS_SR_OFFSET,
+				XSPIPS_IXR_WR_TO_CLR_MASK);
+
+		/*
+		 * Fill the TXFIFO with as many bytes as it will take (or as many as
+		 * we have to send).
+		 */
+		while ((InstancePtr->RemainingBytes > 0U) &&
+			(TransCount < XSPIPS_FIFO_DEPTH)) {
+			XSpiPs_SendByte(InstancePtr->Config.BaseAddress,
+				  *InstancePtr->SendBufferPtr);
+                  InstancePtr->SendBufferPtr += 1;
+			InstancePtr->RemainingBytes--;
+			TransCount++;
+		}
+
+		/*
+		 * Enable interrupts (connecting to the interrupt controller and
+		 * enabling interrupts should have been done by the caller).
+		 */
+		XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XSPIPS_IER_OFFSET, XSPIPS_IXR_DFLT_MASK);
+
+		/*
+		 * If master mode and manual start mode, issue manual start command
+		 * to start the transfer.
+		 */
+	     if ((XSpiPs_IsManualStart(InstancePtr) == TRUE)
+		&& (XSpiPs_IsMaster(InstancePtr) == TRUE)) {
+			ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XSPIPS_CR_OFFSET);
+				ConfigReg |= XSPIPS_CR_MANSTRT_MASK;
+			XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET, ConfigReg);
+		 }
+		StatusTransfer = (s32)XST_SUCCESS;
+	}
+	return StatusTransfer;
+}
+
+/*****************************************************************************/
+/**
+* Transfers specified data on the SPI bus in polled mode.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* 
+*   XSpiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XSpiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XSpiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XSpiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	SendBufPtr is a pointer to a buffer of data for sending.
+*		This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the SPI bus at the same time.
+*
+******************************************************************************/
+s32 XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
+				u8 *RecvBufPtr, u32 ByteCount)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	u32 TransCount;
+	u32 CheckTransfer;
+	s32 Status_Polled;
+	u8 TempData;
+
+	/*
+	 * The RecvBufPtr argument can be NULL.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0U);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status_Polled = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		/*
+		 * Set the busy flag, which will be cleared when the transfer is
+		 * entirely done.
+		 */
+		InstancePtr->IsBusy = TRUE;
+
+		/*
+		 * Set up buffer pointers.
+		 */
+		InstancePtr->SendBufferPtr = SendBufPtr;
+		InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+		InstancePtr->RequestedBytes = ByteCount;
+		InstancePtr->RemainingBytes = ByteCount;
+
+		/*
+		 * If manual chip select mode, initialize the slave select value.
+		 */
+	     if (XSpiPs_IsManualChipSelect(InstancePtr) == TRUE) {
+			ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 XSPIPS_CR_OFFSET);
+			/*
+			 * Set the slave select value.
+			 */
+			ConfigReg &= (u32)(~XSPIPS_CR_SSCTRL_MASK);
+			ConfigReg |= InstancePtr->SlaveSelect;
+			XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Enable the device.
+		 */
+		XSpiPs_Enable(InstancePtr);
+
+		while((InstancePtr->RemainingBytes > (u32)0U) ||
+			(InstancePtr->RequestedBytes > (u32)0U)) {
+			TransCount = 0U;
+			/*
+			 * Fill the TXFIFO with as many bytes as it will take (or as
+			 * many as we have to send).
+			 */
+			while ((InstancePtr->RemainingBytes > (u32)0U) &&
+				((u32)TransCount < (u32)XSPIPS_FIFO_DEPTH)) {
+				XSpiPs_SendByte(InstancePtr->Config.BaseAddress,
+						*InstancePtr->SendBufferPtr);
+				InstancePtr->SendBufferPtr += 1;
+				InstancePtr->RemainingBytes--;
+				++TransCount;
+			}
+
+			/*
+			 * If master mode and manual start mode, issue manual start
+			 * command to start the transfer.
+			 */
+			if ((XSpiPs_IsManualStart(InstancePtr) == TRUE)
+				&& (XSpiPs_IsMaster(InstancePtr) == TRUE)) {
+				ConfigReg = XSpiPs_ReadReg(
+						InstancePtr->Config.BaseAddress,
+						 XSPIPS_CR_OFFSET);
+				ConfigReg |= XSPIPS_CR_MANSTRT_MASK;
+				XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+						 XSPIPS_CR_OFFSET, ConfigReg);
+			}
+
+			/*
+			 * Wait for the transfer to finish by polling Tx fifo status.
+			 */
+	        CheckTransfer = (u32)0U;
+	        while (CheckTransfer == 0U){
+			StatusReg = XSpiPs_ReadReg(
+					        InstancePtr->Config.BaseAddress,
+						        XSPIPS_SR_OFFSET);
+				if ( (StatusReg & XSPIPS_IXR_MODF_MASK) != 0U) {
+					/*
+					 * Clear the mode fail bit
+					 */
+					XSpiPs_WriteReg(
+						InstancePtr->Config.BaseAddress,
+						XSPIPS_SR_OFFSET,
+						XSPIPS_IXR_MODF_MASK);
+					return (s32)XST_SEND_ERROR;
+				}
+		        CheckTransfer = (StatusReg &
+							XSPIPS_IXR_TXOW_MASK);
+		    }
+
+			/*
+			 * A transmit has just completed. Process received data and
+			 * check for more data to transmit.
+			 * First get the data received as a result of the transmit
+			 * that just completed. Receive data based on the
+			 * count obtained while filling tx fifo. Always get the
+			 * received data, but only fill the receive buffer if it
+			 * points to something (the upper layer software may not
+			 * care to receive data).
+			 */
+			while (TransCount != (u32)0U) {
+				TempData = (u8)XSpiPs_RecvByte(
+					InstancePtr->Config.BaseAddress);
+				if (InstancePtr->RecvBufferPtr != NULL) {
+					*(InstancePtr->RecvBufferPtr) = TempData;
+					InstancePtr->RecvBufferPtr += 1;
+				}
+				InstancePtr->RequestedBytes--;
+				--TransCount;
+			}
+		}
+
+		/*
+		 * Clear the slave selects now, before terminating the transfer.
+		 */
+		if (XSpiPs_IsManualChipSelect(InstancePtr) == TRUE) {
+			ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSPIPS_CR_OFFSET);
+			ConfigReg |= XSPIPS_CR_SSCTRL_MASK;
+			XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Clear the busy flag.
+		 */
+		InstancePtr->IsBusy = FALSE;
+
+		/*
+		 * Disable the device.
+		 */
+		XSpiPs_Disable(InstancePtr);
+		Status_Polled = (s32)XST_SUCCESS;
+	}
+	return Status_Polled;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects or deselect the slave with which the master communicates. This setting
+* affects the SPI_ss_outN signals. The behavior depends on the setting of the
+* CR_SSDECEN bit. If CR_SSDECEN is 0, the SPI_ss_outN bits will be output with a
+* single signal low. If CR_SSDECEN is 1, the SPI_ss_outN bits will reflect the
+* value set.
+*
+* The user is not allowed to deselect the slave while a transfer is in progress.
+* If no transfer is in progress, the user can select a new slave, which
+* implicitly deselects the current slave. In order to explicitly deselect the
+* current slave, a value of all 1's, 0x0F can be passed in as the argument to
+* the function.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	SlaveSel is the slave number to be selected.
+* 		Normally, 3 slaves can be selected with values 0-2.
+* 		In case, 3-8 decode option is set, then upto 8 slaves
+* 		can be selected. Only one slave can be selected at a time.
+*
+* @return
+*		- XST_SUCCESS if the slave is selected or deselected
+*		successfully.
+*		- XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
+*		changed.
+*
+* @note
+*
+* This function only sets the slave which will be selected when a transfer
+* occurs. The slave is not selected when the SPI is idle. The slave select
+* has no affect when the device is configured as a slave.
+*
+******************************************************************************/
+s32 XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel)
+{
+	u32 ConfigReg;
+	s32 Status_Slave;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(SlaveSel <= XSPIPS_CR_SSCTRL_MAXIMUM);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status_Slave = (s32)XST_DEVICE_BUSY;
+	} else {
+		/*
+		 * If decode slave select option is set,
+		 * then set slave select value directly.
+		 * Update the Instance structure member.
+		 */
+		if ( XSpiPs_IsDecodeSSelect( InstancePtr ) == TRUE) {
+			InstancePtr->SlaveSelect = ((u32)SlaveSel) << XSPIPS_CR_SSCTRL_SHIFT;
+		}
+		else {
+		/*
+		 * Set the bit position to low using SlaveSel. Update the Instance
+		 * structure member.
+		 */
+			InstancePtr->SlaveSelect = ((~(1U << SlaveSel)) & \
+				XSPIPS_CR_SSCTRL_MAXIMUM) << XSPIPS_CR_SSCTRL_SHIFT;
+		}
+
+		/*
+		 * Read the config register, update the slave select value and write
+		 * back to config register.
+		 */
+		ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XSPIPS_CR_OFFSET);
+		ConfigReg &= (u32)(~XSPIPS_CR_SSCTRL_MASK);
+		ConfigReg |= InstancePtr->SlaveSelect;
+		XSpiPs_WriteReg(InstancePtr->Config.BaseAddress, XSPIPS_CR_OFFSET,
+				 ConfigReg);
+	    Status_Slave = (s32)XST_SUCCESS;
+	}
+	return Status_Slave;
+}
+
+/*****************************************************************************/
+/**
+*
+* Gets the current slave select setting for the SPI device.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	The slave number selected (starting from 0).
+*
+* @note		None.
+*
+******************************************************************************/
+u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr)
+{
+	u32 ConfigReg;
+	u32 SlaveSel;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ConfigReg = InstancePtr->SlaveSelect;
+	ConfigReg &= XSPIPS_CR_SSCTRL_MASK;
+	ConfigReg >>= XSPIPS_CR_SSCTRL_SHIFT;
+	ConfigReg &= XSPIPS_CR_SSCTRL_MAXIMUM;
+
+	/*
+	 * If decode slave select option is set, then read value directly.
+	 */
+	if ( XSpiPs_IsDecodeSSelect( InstancePtr ) == TRUE) {
+		SlaveSel = ConfigReg;
+	}
+	else {
+
+		/*
+		 * Get the slave select value
+		 */
+		if(ConfigReg == 0x0FU) {
+			/*
+			 * No slave selected
+			 */
+			SlaveSel = 0xFU;
+		}else {
+			/*
+			 * Get selected slave number (0,1 or 2)
+			 */
+			SlaveSel = ((~ConfigReg) & XSPIPS_CR_SSCTRL_MAXIMUM)/2;
+		}
+	}
+	return (u8)SlaveSel;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+* 
+* XST_SPI_MODE_FAULT		A mode fault error occurred, meaning the device
+*				is selected as slave while being a master.
+*
+* XST_SPI_TRANSFER_DONE		The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
+*				but there were none available in the transmit
+*				register/FIFO. This typically means the slave
+*				application did not issue a transfer request
+*				fast enough, or the processor/driver could not
+*				fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN	The SPI device lost data. Data was received
+*				but the receive data register/FIFO was full.
+*
+* XST_SPI_SLAVE_MODE_FAULT	A slave SPI device was selected as a slave
+*				while it was disabled. This indicates the
+*				master is already transferring data (which is
+*				being dropped until the slave application
+*				issues a transfer).
+* 

+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FunctionPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XSpiPs_SetStatusHandler(XSpiPs *InstancePtr, void *CallBackRef,
+				XSpiPs_StatusHandler FunctionPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FunctionPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FunctionPtr;
+	InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				u32 ByteCount)
+{
+	(void) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for SPI interrupts. This function must be connected
+* by the user to an interrupt controller.
+*
+* The interrupts that are handled are:
+*
+* - Mode Fault Error. This interrupt is generated if this device is selected
+*   as a slave when it is configured as a master. The driver aborts any data
+*   transfer that is in progress by resetting FIFOs (if present) and resetting
+*   its buffer pointers. The upper layer software is informed of the error.
+*
+* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
+*   transmit register or FIFO is empty. The driver uses this interrupt during a
+*   transmission to continually send/receive data until the transfer is done.
+*
+* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
+*   the SPI device, when configured as a slave, attempts to read an empty
+*   DTR/FIFO.  An empty DTR/FIFO usually means that software is not giving the
+*   device data in a timely manner. No action is taken by the driver other than
+*   to inform the upper layer software of the error.
+*
+* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
+*   SPI device attempts to write a received byte to an already full DRR/FIFO.
+*   A full DRR/FIFO usually means software is not emptying the data in a timely
+*   manner.  No action is taken by the driver other than to inform the upper
+*   layer software of the error.
+*
+* - Slave Mode Fault Error. This interrupt is generated if a slave device is
+*   selected as a slave while it is disabled. No action is taken by the driver
+*   other than to inform the upper layer software of the error.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* The slave select register is being set to deselect the slave when a transfer
+* is complete.  This is being done regardless of whether it is a slave or a
+* master since the hardware does not drive the slave select as a slave.
+*
+******************************************************************************/
+void XSpiPs_InterruptHandler(XSpiPs *InstancePtr)
+{
+	XSpiPs *SpiPtr = InstancePtr;
+	u32 IntrStatus;
+	u32 ConfigReg;
+	u32 BytesDone; /* Number of bytes done so far. */
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(SpiPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Immediately clear the interrupts in case the ISR causes another
+	 * interrupt to be generated. If we clear at the end of the ISR,
+	 * we may miss newly generated interrupts.
+	 * Disable the TXOW interrupt because we transmit from within the ISR,
+	 * which could potentially cause another TX_OW interrupt.
+	 */
+	IntrStatus =
+		XSpiPs_ReadReg(SpiPtr->Config.BaseAddress, XSPIPS_SR_OFFSET);
+	XSpiPs_WriteReg(SpiPtr->Config.BaseAddress, XSPIPS_SR_OFFSET,
+			(IntrStatus & XSPIPS_IXR_WR_TO_CLR_MASK));
+	XSpiPs_WriteReg(SpiPtr->Config.BaseAddress, XSPIPS_IDR_OFFSET,
+			XSPIPS_IXR_TXOW_MASK);
+
+	/*
+	 * Check for mode fault error. We want to check for this error first,
+	 * before checking for progress of a transfer, since this error needs
+	 * to abort any operation in progress.
+	 */
+	if ((u32)XSPIPS_IXR_MODF_MASK == (u32)(IntrStatus & XSPIPS_IXR_MODF_MASK)) {
+		BytesDone = SpiPtr->RequestedBytes - SpiPtr->RemainingBytes;
+
+		/*
+		 * Abort any operation currently in progress. This includes
+		 * clearing the mode fault condition by reading the status
+		 * register. Note that the status register should be read after
+		 * the abort, since reading the status register clears the mode
+		 * fault condition and would cause the device to restart any
+		 * transfer that may be in progress.
+		 */
+		XSpiPs_Abort(SpiPtr);
+
+		SpiPtr->StatusHandler(SpiPtr->StatusRef, XST_SPI_MODE_FAULT,
+					BytesDone);
+
+		return; /* Do not continue servicing other interrupts. */
+	}
+
+
+	if ((IntrStatus & XSPIPS_IXR_TXOW_MASK) != 0U) {
+		u8 TempData;
+		u32 TransCount;
+		/*
+		 * A transmit has just completed. Process received data and
+		 * check for more data to transmit.
+		 * First get the data received as a result of the transmit that
+		 * just completed.  Always get the received data, but only fill
+		 * the receive buffer if it is not null (it can be null when
+		 * the device does not care to receive data).
+		 * Initialize the TransCount based on the requested bytes.
+		 * Loop on receive FIFO based on TransCount.
+		 */
+		TransCount = SpiPtr->RequestedBytes - SpiPtr->RemainingBytes;
+
+		while (TransCount != 0U) {
+			TempData = (u8)XSpiPs_RecvByte(SpiPtr->Config.BaseAddress);
+			if (SpiPtr->RecvBufferPtr != NULL) {
+				*SpiPtr->RecvBufferPtr = TempData;
+				SpiPtr->RecvBufferPtr += 1;
+			}
+			SpiPtr->RequestedBytes--;
+			--TransCount;
+		}
+
+		/*
+		 * Fill the TXFIFO until data exists, otherwise fill upto
+		 * FIFO depth.
+		 */
+		while ((SpiPtr->RemainingBytes > 0U) &&
+			(TransCount < XSPIPS_FIFO_DEPTH)) {
+			XSpiPs_SendByte(SpiPtr->Config.BaseAddress,
+					 *SpiPtr->SendBufferPtr);
+			SpiPtr->SendBufferPtr += 1;
+			SpiPtr->RemainingBytes--;
+			++TransCount;
+		}
+
+		if ((SpiPtr->RemainingBytes == 0U) &&
+			(SpiPtr->RequestedBytes == 0U)) {
+			/*
+			 * No more data to send. Disable the interrupt and
+			 * inform the upper layer software that the transfer
+			 * is done. The interrupt will be re-enabled when
+			 * another transfer is initiated.
+			 */
+			XSpiPs_WriteReg(SpiPtr->Config.BaseAddress,
+				 XSPIPS_IDR_OFFSET, XSPIPS_IXR_DFLT_MASK);
+
+			/*
+			 * Disable slave select lines as the transfer
+			 * is complete.
+			 */
+			if (XSpiPs_IsManualChipSelect(InstancePtr) == TRUE) {
+				ConfigReg = XSpiPs_ReadReg(
+					SpiPtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET);
+				ConfigReg |= XSPIPS_CR_SSCTRL_MASK;
+				XSpiPs_WriteReg(
+					SpiPtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET, ConfigReg);
+			}
+
+			/*
+			 * Clear the busy flag.
+			 */
+			SpiPtr->IsBusy = FALSE;
+
+			/*
+			 * Disable the device.
+			 */
+			XSpiPs_Disable(SpiPtr);
+
+			/*
+			 * Inform the Transfer done to upper layers.
+			 */
+			SpiPtr->StatusHandler(SpiPtr->StatusRef,
+						XST_SPI_TRANSFER_DONE,
+						SpiPtr->RequestedBytes);
+		} else {
+			/*
+			 * Enable the TXOW interrupt.
+			 */
+			XSpiPs_WriteReg(SpiPtr->Config.BaseAddress,
+				 XSPIPS_IER_OFFSET, XSPIPS_IXR_TXOW_MASK);
+			/*
+			 * Start the transfer by not inhibiting the transmitter
+			 * any longer.
+			 */
+			if ((XSpiPs_IsManualStart(SpiPtr) == TRUE)
+				&& (XSpiPs_IsMaster(SpiPtr) == TRUE)) {
+				ConfigReg = XSpiPs_ReadReg(
+					SpiPtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET);
+				ConfigReg |= XSPIPS_CR_MANSTRT_MASK;
+				XSpiPs_WriteReg(
+					SpiPtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET, ConfigReg);
+			}
+		}
+	}
+
+	/*
+	 * Check for overflow and underflow errors.
+	 */
+	if ((IntrStatus & XSPIPS_IXR_RXOVR_MASK) != 0U) {
+		BytesDone = SpiPtr->RequestedBytes - SpiPtr->RemainingBytes;
+		SpiPtr->IsBusy = FALSE;
+
+		/*
+		 * The Slave select lines are being manually controlled.
+		 * Disable them because the transfer is complete.
+		 */
+		if (XSpiPs_IsManualChipSelect(SpiPtr) == TRUE) {
+			ConfigReg = XSpiPs_ReadReg(
+				SpiPtr->Config.BaseAddress,
+				 XSPIPS_CR_OFFSET);
+			ConfigReg |= XSPIPS_CR_SSCTRL_MASK;
+			XSpiPs_WriteReg(
+				SpiPtr->Config.BaseAddress,
+				 XSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		SpiPtr->StatusHandler(SpiPtr->StatusRef,
+			XST_SPI_RECEIVE_OVERRUN, BytesDone);
+	}
+
+	if ((IntrStatus & XSPIPS_IXR_TXUF_MASK) != 0U) {
+		BytesDone = SpiPtr->RequestedBytes - SpiPtr->RemainingBytes;
+
+		SpiPtr->IsBusy = FALSE;
+		/*
+		 * The Slave select lines are being manually controlled.
+		 * Disable them because the transfer is complete.
+		 */
+		if (XSpiPs_IsManualChipSelect(SpiPtr) == TRUE) {
+			ConfigReg = XSpiPs_ReadReg(
+				SpiPtr->Config.BaseAddress,
+				 XSPIPS_CR_OFFSET);
+			ConfigReg |= XSPIPS_CR_SSCTRL_MASK;
+			XSpiPs_WriteReg(
+				SpiPtr->Config.BaseAddress,
+				 XSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		SpiPtr->StatusHandler(SpiPtr->StatusRef,
+			XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
+	}
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by disabling the device and resetting the FIFOs
+* if present. The byte counts are cleared, the busy flag is cleared, and mode
+* fault is cleared.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* This function does a read/modify/write of the Config register. The user of
+* this function needs to take care of critical sections.
+*
+******************************************************************************/
+void XSpiPs_Abort(XSpiPs *InstancePtr)
+{
+
+	u8 Temp;
+	u32 Check;
+	XSpiPs_Disable(InstancePtr);
+
+	/*
+	 * Clear the RX FIFO and drop any data.
+	 */
+	Check = (XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+		XSPIPS_SR_OFFSET) & XSPIPS_IXR_RXNEMPTY_MASK);
+	while (Check != (u32)0U) {
+		Temp = (u8)XSpiPs_RecvByte(InstancePtr->Config.BaseAddress);
+		if(Temp != (u8)0U){
+		}
+		Check = (XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+		XSPIPS_SR_OFFSET) & XSPIPS_IXR_RXNEMPTY_MASK);
+	}
+
+	/*
+	 * Clear mode fault condition.
+	 */
+	XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XSPIPS_SR_OFFSET,
+			XSPIPS_IXR_MODF_MASK);
+
+	InstancePtr->RemainingBytes = 0U;
+	InstancePtr->RequestedBytes = 0U;
+	InstancePtr->IsBusy = FALSE;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips.h
new file mode 100644
index 000000000..3d699105e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips.h
@@ -0,0 +1,691 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xspips.h
+*
+* This file contains the implementation of the XSpiPs driver. It works for
+* both the master and slave mode. User documentation for the driver functions
+* is contained in this file in the form of comment blocks at the front of each
+* function.
+*
+* An SPI device connects to an SPI bus through a 4-wire serial interface.
+* The SPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* Initialization & Configuration
+*
+* The XSpiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*	- XSpiPs_LookupConfig(DeviceId) - Use the devide identifier to find the
+*	static configuration structure defined in xspips_g.c. This is setup by
+*	the tools. For some operating systems the config structure will be
+*	initialized by the software and this call is not needed.
+*	- XSpiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	configuration structure provided by the caller. If running in a system
+*	with address translation, the provided virtual memory base address
+*	replaces the physical address present in the configuration structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* Multiple Slaves
+*
+* Contention between multiple masters is detected by the hardware, in which
+* case a mode fault occurs on the device. The device is disabled immediately
+* by hardware, and the current word transfer is stopped. The Aborted word
+* transfer due to the mode fault is resumed once the devie is enabled again.
+*
+* Modes of Operation
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+*	     is written into the TXFIFO and deasserted when the TXFIFO becomes
+*	     empty
+* - Manual CS: Software must assert and deassert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+*		TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+*		  the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+*   TXFIFO write otherwise there could be a race condition where the TXFIFO
+*   becomes empty before the new word is written. In that case the
+*   transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+*   keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is deasserted.
+*   This results in a single transaction to be split into multiple pieces each
+*   with its own chip select. This will result in garbage data to be sent.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XSpiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Full
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Full
+* - Data Transmit Register/FIFO Overwater
+* - Mode Fault Error
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* SPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data.  The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the SPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the SPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The interrupt applies to both master
+* and slave operation. The driver reports this condition to the upper layer
+* software through the status handler. This likely indicates a problem with
+* the higher layer protocol, or a problem with the slave performance.
+*
+* The Mode Fault Error interrupt -- indicates that while configured as a
+* master, the device was selected as a slave by another master. This can be
+* used by the application for arbitration in a multimaster environment or to
+* indicate a problem with arbitration. When this interrupt occurs, the
+* driver invokes the status callback with a status value of
+* XST_SPI_MODE_FAULT. It is up to the application to resolve the conflict.
+* When configured as a slave, Mode Fault Error interrupt indicates that a slave
+* device was selected as a slave by a master, but the slave device was
+* disabled. When configured as a master, Mode Fault Error interrupt indicates
+* that another SPI device is acting as a master on the bus.
+*
+*
+* Polled Operation
+*
+* Transfer in polled mode is supported through a separate interface function
+* XSpiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* Device Busy
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error). This applies to both
+* master and slave devices.
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xspips_g.c file or
+* passed in via XSpiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an SPI device, including the base
+* address for the device.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	drg/jz 01/25/10 First release
+* 1.00	sdm    10/25/11 Removed the Divide by 2 in the SPI Clock Prescaler
+*			options as this is not supported in the device.
+* 1.01	sg     03/07/12 Updated the code to always clear the relevant bits
+*			before writing to config register.
+*			Always clear the slave select bits before write and
+*			clear the bits to no slave at the end of transfer
+*			Modified the Polled transfer transmit/receive logic.
+*			Tx should wait on TXOW Interrupt and Rx on RXNEMTY.
+* 1.02	sg     05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
+*			for CR 658289
+* 1.03	sg     09/21/12 Added memory barrier dmb in polled transfer and
+*			interrupt handler to overcome the clock domain
+*			crossing issue in the controller. For CR #679252.
+* 1.04a	sg     01/30/13 Created XSPIPS_MANUAL_START_OPTION. Created macros
+*			XSpiPs_IsMaster, XSpiPs_IsManualStart and
+*			XSpiPs_IsManualChipSelect. Changed SPI
+*			Enable/Disable macro argument from BaseAddress to
+*			Instance Pointer. Added DelayNss argument to SetDelays
+*			and GetDelays API's. Added macros to set/get the
+*			RX Watermark value.Created macros XSpiPs_IsMaster,
+*			XSpiPs_IsManualStart and XSpiPs_IsManualChipSelect.
+*			Changed SPI transfer logic for polled and interrupt
+*			modes to be based on filled tx fifo count and receive
+*			based on it. RXNEMPTY interrupt is not used.
+*			SetSlaveSelect API logic is modified to drive the bit
+*			position low based on the slave select value
+*			requested. GetSlaveSelect API will return the value
+*			based on bit position that is low.
+*			Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
+*			to XSPIPS_CR_RESET_STATE. Created
+* 			XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
+*			write-to-clear. Added shift and mask macros for d_nss
+*			parameter. Added Rx Watermark mask.
+* 1.05a hk 	   26/04/13 Added disable and enable in XSpiPs_SetOptions when
+*				CPOL/CPHA bits are set/reset. Fix for CR#707669.
+* 1.06a hk     08/22/13 Changed GetSlaveSelect function. CR# 727866.
+*                       Added masking ConfigReg before writing in SetSlaveSel
+*                       Added extended slave select support - CR#722569.
+*                       Added prototypes of reset API and related constant
+*                       definitions.
+*                       Added check for MODF in polled transfer function.
+* 3.0   vm    12/09/14	Modified driver source code for MISRA-C:2012 compliance.
+*			Support for Zynq Ultrascale Mp added.
+*
+* 

+*
+******************************************************************************/
+#ifndef XSPIPS_H		/* prevent circular inclusions */
+#define XSPIPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xspips_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an SPI device.  Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ * The Master option configures the SPI device as a master.
+ * By default, the device is a slave.
+ *
+ * The Active Low Clock option configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The Clock Phase option configures the SPI device for one of two
+ * transfer formats.  A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ * The Slave Select Decode Enable option selects how the SPI_SS_outN are
+ * controlled by the SPI Slave Select Decode bits.
+ * 0: Use this setting for the standard configuration of up to three slave
+ * select outputs. Only one of the three slave select outputs will be low.
+ * (Default)
+ * 1: Use this setting for the optional configuration of an additional decoder
+ * to support 8 slave select outputs. SPI_SS_outN reflects the value in the
+ * register.
+ *
+ * The SPI Force Slave Select option is used to enable manual control of
+ * the signals SPI_SS_outN.
+ * 0: The SPI_SS_outN signals are controlled by the SPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS_outN signal indicated by the Slave Select Control bit is
+ * forced active (driven low) regardless of any transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * SPI clock to be set to a faster speed. If the SPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the SPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The Manual Start option is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the SPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XSPIPS_MASTER_OPTION				0x00000001U  /**< Master mode option */
+#define XSPIPS_CLK_ACTIVE_LOW_OPTION		0x00000002U  /**< Active Low Clock option */
+#define XSPIPS_CLK_PHASE_1_OPTION			0x00000004U  /**< Clock Phase one option */
+#define XSPIPS_DECODE_SSELECT_OPTION		0x00000008U  /**< Select 16 slaves Option */
+#define XSPIPS_FORCE_SSELECT_OPTION			0x00000010U /**< Force Slave Select */
+#define XSPIPS_MANUAL_START_OPTION			0x00000020U /**< Manual Start mode option */
+/*@}*/
+
+
+/** @name SPI Clock Prescaler options
+ * The SPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/4 to pclk/256.
+ *
+ * @{
+ */
+
+#define XSPIPS_CLK_PRESCALE_4		0x01U  /**< PCLK/4 Prescaler */
+#define XSPIPS_CLK_PRESCALE_8		0x02U  /**< PCLK/8 Prescaler */
+#define XSPIPS_CLK_PRESCALE_16		0x03U  /**< PCLK/16 Prescaler */
+#define XSPIPS_CLK_PRESCALE_32		0x04U  /**< PCLK/32 Prescaler */
+#define XSPIPS_CLK_PRESCALE_64		0x05U  /**< PCLK/64 Prescaler */
+#define XSPIPS_CLK_PRESCALE_128		0x06U  /**< PCLK/128 Prescaler */
+#define XSPIPS_CLK_PRESCALE_256		0x07U  /**< PCLK/256 Prescaler */
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver.  These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XSPIPS_EVENT_MODE_FAULT		1U  /**< Mode fault error */
+#define XSPIPS_EVENT_TRANSFER_DONE	2U  /**< Transfer done */
+#define XSPIPS_EVENT_TRANSMIT_UNDERRUN	3U  /**< TX FIFO empty */
+#define XSPIPS_EVENT_RECEIVE_OVERRUN	4U /**< Receive data loss because
+						RX FIFO full */
+/*@}*/
+
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the SPI device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param 	StatusEvent holds one or more status events that have occurred.
+ *		See the XSpiPs_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XSpiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					u32 ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+} XSpiPs_Config;
+
+/**
+ * The XSpiPs driver instance data. The user is required to allocate a
+ * variable of this type for every SPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSpiPs_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	u32 RequestedBytes; /**< Number of bytes to transfer (state) */
+	u32 RemainingBytes; /**< Number of bytes left to transfer(state) */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	u32 SlaveSelect;     /**< The slave select value when
+					 XSPIPS_FORCE_SSELECT_OPTION is set */
+
+	XSpiPs_StatusHandler StatusHandler;
+	void *StatusRef;  	 /**< Callback reference for status handler */
+
+} XSpiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XSpiPs_IsManualStart(XSpiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XSpiPs_IsManualStart(InstancePtr) \
+		(((XSpiPs_GetOptions(InstancePtr) & \
+		  XSPIPS_MANUAL_START_OPTION) != (u32)0U) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XSpiPs_IsManualChipSelect(XSpiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XSpiPs_IsManualChipSelect(InstancePtr) \
+		(((XSpiPs_GetOptions(InstancePtr) & \
+		  XSPIPS_FORCE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Decode Slave Select option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XSpiPs_IsDecodeSSelect(XSpiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XSpiPs_IsDecodeSSelect(InstancePtr) \
+		(((XSpiPs_GetOptions(InstancePtr) & \
+		  XSPIPS_DECODE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Master Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XSpiPs_IsMaster(XSpiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XSpiPs_IsMaster(InstancePtr) \
+		(((XSpiPs_GetOptions(InstancePtr) & \
+		  XSPIPS_MASTER_OPTION) != (u32)0U) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	RegisterValue is the value to be writen, valid values are
+*		0-255.
+*
+* @return	None
+*
+* @note
+* C-Style signature:
+*	void XSpiPs_SetSlaveIdle(XSpiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XSpiPs_SetSlaveIdle(InstancePtr, RegisterValue)	\
+	XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + 	\
+		XSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XSPIPS_SICR_*
+* constants defined in xspips_hw.h to interpret the bit-mask returned.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	8-bit value representing the contents of the SIC register.
+*
+* @note		C-Style signature:
+*		u32 XSpiPs_GetSlaveIdle(XSpiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XSpiPs_GetSlaveIdle(InstancePtr)				\
+	XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + 		\
+	XSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	RegisterValue is the value to be written, valid values
+*		are 1-128.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XSpiPs_SetTXWatermark(XSpiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XSpiPs_SetTXWatermark(InstancePtr, RegisterValue)		\
+	XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+		XSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Use the XSPIPS_TXWR_* constants defined xspips_hw.h to interpret
+* the bit-mask returned.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	8-bit value representing the contents of the TXWR register.
+*
+* @note		C-Style signature:
+*		u32 XSpiPs_GetTXWatermark(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XSpiPs_GetTXWatermark(InstancePtr)				\
+	XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	RegisterValue is the value to be written, valid values
+*		are 1-128.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XSpiPs_SetRXWatermark(XSpiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XSpiPs_SetRXWatermark(InstancePtr, RegisterValue)		\
+	XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+		XSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Use the XSPIPS_RXWR_* constants defined xspips_hw.h to interpret
+* the bit-mask returned.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	A 8-bit value representing the contents of the RXWR register.
+*
+* @note		C-Style signature:
+*		u32 XSpiPs_GetRXWatermark(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XSpiPs_GetRXWatermark(InstancePtr)				\
+	XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSpiPs_Enable(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XSpiPs_Enable(InstancePtr)					\
+	XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, \
+		XSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSpiPs_Disable(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XSpiPs_Disable(InstancePtr)					\
+	XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, 0U)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xspips_sinit.c
+ */
+XSpiPs_Config *XSpiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xspips.c
+ */
+s32 XSpiPs_CfgInitialize(XSpiPs *InstancePtr, XSpiPs_Config * ConfigPtr,
+				u32 EffectiveAddr);
+
+void XSpiPs_Reset(XSpiPs *InstancePtr);
+
+s32 XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+			u32 ByteCount);
+
+s32 XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
+				u8 *RecvBufPtr, u32 ByteCount);
+
+void XSpiPs_SetStatusHandler(XSpiPs *InstancePtr, void *CallBackRef,
+				XSpiPs_StatusHandler FunctionPtr);
+void XSpiPs_InterruptHandler(XSpiPs *InstancePtr);
+
+void XSpiPs_Abort(XSpiPs *InstancePtr);
+
+s32 XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel);
+u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xspips_selftest.c
+ */
+s32 XSpiPs_SelfTest(XSpiPs *InstancePtr);
+
+/*
+ * Functions for options, in xspips_options.c
+ */
+s32 XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options);
+u32 XSpiPs_GetOptions(XSpiPs *InstancePtr);
+
+s32 XSpiPs_SetClkPrescaler(XSpiPs *InstancePtr, u8 Prescaler);
+u8 XSpiPs_GetClkPrescaler(XSpiPs *InstancePtr);
+
+s32 XSpiPs_SetDelays(XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			u8 DelayAfter, u8 DelayInit);
+void XSpiPs_GetDelays(XSpiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_g.c
new file mode 100644
index 000000000..749beceb3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_g.c
@@ -0,0 +1,61 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xspips.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSpiPs_Config XSpiPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_SPI_0_DEVICE_ID,
+		XPAR_PSU_SPI_0_BASEADDR,
+		XPAR_PSU_SPI_0_SPI_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_SPI_1_DEVICE_ID,
+		XPAR_PSU_SPI_1_BASEADDR,
+		XPAR_PSU_SPI_1_SPI_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_hw.c
new file mode 100644
index 000000000..3c4f510b2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_hw.c
@@ -0,0 +1,129 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xspips_hw.c
+*
+* Contains the reset and post boot rom state initialization.
+* Function prototypes in xspips_hw.h
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.06a hk     08/22/13 First release.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xspips_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Resets the spi module
+*
+* @param    BaseAddress is the base address of the device.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSpiPs_ResetHw(u32 BaseAddress)
+{
+	u32 Check;
+	/*
+	 * Disable Interrupts
+	 */
+	XSpiPs_WriteReg(BaseAddress, XSPIPS_IDR_OFFSET,
+			XSPIPS_IXR_DISABLE_ALL_MASK);
+
+	/*
+	 * Disable device
+	 */
+	XSpiPs_WriteReg(BaseAddress, XSPIPS_ER_OFFSET,
+				0U);
+	/*
+	 * Write default value to RX and TX threshold registers
+	 * RX threshold should be set to 1 here as the corresponding
+	 * status bit is used to clear the FIFO next
+	 */
+	XSpiPs_WriteReg(BaseAddress, XSPIPS_TXWR_OFFSET,
+			(XSPIPS_TXWR_RESET_VALUE & XSPIPS_TXWR_MASK));
+	XSpiPs_WriteReg(BaseAddress, XSPIPS_RXWR_OFFSET,
+			(XSPIPS_RXWR_RESET_VALUE & XSPIPS_RXWR_MASK));
+
+	/*
+	 * Clear RXFIFO
+	 */
+	Check = (XSpiPs_ReadReg(BaseAddress,XSPIPS_SR_OFFSET) &
+		XSPIPS_IXR_RXNEMPTY_MASK);
+	while (Check != 0U) {
+		(void)XSpiPs_ReadReg(BaseAddress, XSPIPS_RXD_OFFSET);
+		Check = (XSpiPs_ReadReg(BaseAddress,XSPIPS_SR_OFFSET) &
+			XSPIPS_IXR_RXNEMPTY_MASK);
+	}
+
+	/*
+	 * Clear status register by writing 1 to the write to clear bits
+	 */
+	XSpiPs_WriteReg(BaseAddress, XSPIPS_SR_OFFSET,
+				XSPIPS_IXR_WR_TO_CLR_MASK);
+
+	/*
+	 * Write default value to configuration register
+	 * De-select all slaves
+	 */
+	XSpiPs_WriteReg(BaseAddress, XSPIPS_CR_OFFSET,
+				XSPIPS_CR_RESET_STATE |
+				XSPIPS_CR_SSCTRL_MASK);
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_hw.h
new file mode 100644
index 000000000..897340369
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_hw.h
@@ -0,0 +1,310 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xspips_hw.h
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xspips.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00   drg/jz 01/25/10 First release
+* 1.02a  sg     05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
+*			 for CR 658289
+* 1.04a	 sg     01/30/13 Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
+*			 to XSPIPS_CR_RESET_STATE. Created
+* 			 XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
+*			 write-to-clear. Added shift and mask macros for d_nss
+*			 parameter. Added Rx Watermark mask.
+* 1.06a hk      08/22/13 Added prototypes of reset API and related constant
+*                        definitions.
+* 3.00  kvn     02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XSPIPS_HW_H		/* prevent circular inclusions */
+#define XSPIPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SPI device.
+ * @{
+ */
+#define XSPIPS_CR_OFFSET	0x00U  /**< Configuration */
+#define XSPIPS_SR_OFFSET	0x04U  /**< Interrupt Status */
+#define XSPIPS_IER_OFFSET	0x08U  /**< Interrupt Enable */
+#define XSPIPS_IDR_OFFSET	0x0CU  /**< Interrupt Disable */
+#define XSPIPS_IMR_OFFSET	0x10U  /**< Interrupt Enabled Mask */
+#define XSPIPS_ER_OFFSET	0x14U  /**< Enable/Disable Register */
+#define XSPIPS_DR_OFFSET	0x18U  /**< Delay Register */
+#define XSPIPS_TXD_OFFSET	0x1CU  /**< Data Transmit Register */
+#define XSPIPS_RXD_OFFSET	0x20U  /**< Data Receive Register */
+#define XSPIPS_SICR_OFFSET	0x24U  /**< Slave Idle Count */
+#define XSPIPS_TXWR_OFFSET	0x28U  /**< Transmit FIFO Watermark */
+#define XSPIPS_RXWR_OFFSET	0x2CU  /**< Receive FIFO Watermark */
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affects the operation of an SPI device. Read/Write.
+ * @{
+ */
+#define XSPIPS_CR_MODF_GEN_EN_MASK 0x00020000U /**< Modefail Generation
+						 Enable */
+#define XSPIPS_CR_MANSTRT_MASK   0x00010000U /**< Manual Transmission Start */
+#define XSPIPS_CR_MANSTRTEN_MASK 0x00008000U /**< Manual Transmission Start
+						 Enable */
+#define XSPIPS_CR_SSFORCE_MASK   0x00004000U /**< Force Slave Select */
+#define XSPIPS_CR_SSCTRL_MASK    0x00003C00U /**< Slave Select Decode */
+#define XSPIPS_CR_SSCTRL_SHIFT   10U	    /**< Slave Select Decode shift */
+#define XSPIPS_CR_SSCTRL_MAXIMUM 0xFU	    /**< Slave Select maximum value */
+#define XSPIPS_CR_SSDECEN_MASK   0x00000200U /**< Slave Select Decode Enable */
+
+#define XSPIPS_CR_PRESC_MASK     0x00000038U /**< Prescaler Setting */
+#define XSPIPS_CR_PRESC_SHIFT    3U	    /**< Prescaler shift */
+#define XSPIPS_CR_PRESC_MAXIMUM  0x07U	    /**< Prescaler maximum value */
+
+#define XSPIPS_CR_CPHA_MASK      0x00000004U /**< Phase Configuration */
+#define XSPIPS_CR_CPOL_MASK      0x00000002U /**< Polarity Configuration */
+
+#define XSPIPS_CR_MSTREN_MASK    0x00000001U /**< Master Mode Enable */
+#define XSPIPS_CR_RESET_STATE    0x00020000U /**< Mode Fail Generation Enable */
+/* @} */
+
+
+/** @name SPI Interrupt Registers
+ *
+ * SPI Status Register
+ *
+ * This register holds the interrupt status flags for an SPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * SPI Interrupt Enable Register
+ *
+ * This register is used to enable chosen interrupts for an SPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * SPI Interrupt Mask register.  Write only.
+ *
+ * SPI Interrupt Disable Register 
+ *
+ * This register is used to disable chosen interrupts for an SPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * SPI Interrupt Mask register. Write only.
+ *
+ * SPI Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled interrupts of an SPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XSPIPS_IXR_TXUF_MASK		0x00000040U  /**< Tx FIFO Underflow */
+#define XSPIPS_IXR_RXFULL_MASK		0x00000020U  /**< Rx FIFO Full */
+#define XSPIPS_IXR_RXNEMPTY_MASK	0x00000010U  /**< Rx FIFO Not Empty */
+#define XSPIPS_IXR_TXFULL_MASK		0x00000008U  /**< Tx FIFO Full */
+#define XSPIPS_IXR_TXOW_MASK		0x00000004U  /**< Tx FIFO Overwater */
+#define XSPIPS_IXR_MODF_MASK		0x00000002U  /**< Mode Fault */
+#define XSPIPS_IXR_RXOVR_MASK		0x00000001U  /**< Rx FIFO Overrun */
+#define XSPIPS_IXR_DFLT_MASK		0x00000027U  /**< Default interrupts
+							 mask */
+#define XSPIPS_IXR_WR_TO_CLR_MASK	0x00000043U  /**< Interrupts which
+							 need write to clear */
+#define XSPIPS_ISR_RESET_STATE		0x04U	    /**< Default to tx/rx
+						       * reg empty */
+#define XSPIPS_IXR_DISABLE_ALL_MASK	0x00000043U  /**< Disable all
+						       * interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an SPI device.
+ * Read/Write
+ * @{
+ */
+#define XSPIPS_ER_ENABLE_MASK	0x00000001U /**< SPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XSPIPS_DR_NSS_MASK	0xFF000000U /**< Delay for slave select
+					      * de-assertion between
+					      * word transfers mask */
+#define XSPIPS_DR_NSS_SHIFT	24U	   /**< Delay for slave select
+					      * de-assertion between
+					      * word transfers shift */
+#define XSPIPS_DR_BTWN_MASK	0x00FF0000U /**< Delay Between Transfers	mask */
+#define XSPIPS_DR_BTWN_SHIFT	16U	   /**< Delay Between Transfers shift */
+#define XSPIPS_DR_AFTER_MASK	0x0000FF00U /**< Delay After Transfers mask */
+#define XSPIPS_DR_AFTER_SHIFT	8U 	   /**< Delay After Transfers shift */
+#define XSPIPS_DR_INIT_MASK	0x000000FFU /**< Delay Initially mask */
+/* @} */
+
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * SPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XSPIPS_SICR_MASK	0x000000FFU /**< Slave Idle Count Mask */
+/* @} */
+
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO. The
+ * transmit FIFO is 128 bytes deep, so the register is 7 bits. Valid values
+ * are 1 to 128.
+ *
+ * @{
+ */
+#define XSPIPS_TXWR_MASK	0x0000007FU /**< Transmit Watermark Mask */
+#define XSPIPS_TXWR_RESET_VALUE	0x00000001U /**< Transmit Watermark
+					      * register reset value */
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO. The
+ * receive FIFO is 128 bytes deep, so the register is 7 bits. Valid values
+ * are 1 to 128.
+ *
+ * @{
+ */
+#define XSPIPS_RXWR_MASK	0x0000007FU /**< Receive Watermark Mask */
+#define XSPIPS_RXWR_RESET_VALUE	0x00000001U /**< Receive Watermark
+					      * register reset value */
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XSPIPS_FIFO_DEPTH	128U /**< FIFO depth of Tx and Rx */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XSpiPs_In32 Xil_In32
+#define XSpiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSpiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSpiPs_ReadReg(BaseAddress, RegOffset) \
+	XSpiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSpiPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XSpiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+    XSpiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+void XSpiPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_options.c
new file mode 100644
index 000000000..71cbca395
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_options.c
@@ -0,0 +1,430 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xspips_options.c
+*
+* Contains functions for the configuration of the XSpiPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/25/10 First release
+* 1.00	sdm    10/25/11 Removed the Divide by 2 in the SPI Clock Prescaler
+*			options as this is not supported in the device
+* 1.04a	sg     01/30/13 Added XSPIPS_MANUAL_START_OPTION. SetDelays and
+*			GetDelays API's include DelayNss parameter.
+* 1.05a hk 	   26/04/13 Added disable and enable in XSpiPs_SetOptions when
+*				CPOL/CPHA bits are set/reset. Fix for CR#707669.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+	{XSPIPS_MASTER_OPTION, XSPIPS_CR_MSTREN_MASK},
+	{XSPIPS_CLK_ACTIVE_LOW_OPTION, XSPIPS_CR_CPOL_MASK},
+	{XSPIPS_CLK_PHASE_1_OPTION, XSPIPS_CR_CPHA_MASK},
+	{XSPIPS_DECODE_SSELECT_OPTION, XSPIPS_CR_SSDECEN_MASK},
+	{XSPIPS_FORCE_SSELECT_OPTION, XSPIPS_CR_SSFORCE_MASK},
+	{XSPIPS_MANUAL_START_OPTION, XSPIPS_CR_MANSTRTEN_MASK}
+};
+
+#define XSPIPS_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the SPI device driver. The options control
+* how the device behaves relative to the SPI bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained in
+*		the mask. See the bit definitions named XSPIPS_*_OPTIONS in the
+*		file xspips.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	u32 Index;
+	u32 CurrentConfigReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET);
+
+		CurrentConfigReg = ConfigReg;
+
+		/*
+		 * Loop through the options table, turning the option on or off
+		 * depending on whether the bit is set in the incoming options flag.
+		 */
+		for (Index = 0U; Index < XSPIPS_NUM_OPTIONS; Index++) {
+			if ((Options & OptionsTable[Index].Option) != (u32)0U) {
+				/* Turn it on */
+				ConfigReg |= OptionsTable[Index].Mask;
+			}
+			else {
+				/* Turn it off */
+				ConfigReg &= ~(OptionsTable[Index].Mask);
+			}
+		}
+
+
+		/*
+		 * If CPOL-CPHA bits are toggled from previous state,
+		 * disable before writing the configuration register and then enable.
+		 */
+		if( ((CurrentConfigReg & XSPIPS_CR_CPOL_MASK) !=
+			(ConfigReg & XSPIPS_CR_CPOL_MASK)) ||
+			((CurrentConfigReg & XSPIPS_CR_CPHA_MASK) !=
+			(ConfigReg & XSPIPS_CR_CPHA_MASK)) ) {
+				XSpiPs_Disable(InstancePtr);
+			}
+
+		/*
+		 * Now write the Config register. Leave it to the upper layers
+		 * to restart the device.
+		 */
+		XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XSPIPS_CR_OFFSET, ConfigReg);
+
+		/*
+		 * Enable
+		 */
+		if( ((CurrentConfigReg & XSPIPS_CR_CPOL_MASK) !=
+			(ConfigReg & XSPIPS_CR_CPOL_MASK)) ||
+			((CurrentConfigReg & XSPIPS_CR_CPHA_MASK) !=
+			(ConfigReg & XSPIPS_CR_CPHA_MASK)) ) {
+				XSpiPs_Enable(InstancePtr);
+			}
+
+		Status = (s32)XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the SPI device. The options control how
+* the device behaves relative to the SPI bus.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XSPIPS_*_OPTIONS in file xspips.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XSpiPs_GetOptions(XSpiPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 ConfigReg;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the current options
+	 */
+	ConfigReg =
+		XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XSPIPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to grab options
+	 */
+	for (Index = 0; Index < XSPIPS_NUM_OPTIONS; Index++) {
+		if (ConfigReg & OptionsTable[Index].Mask) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the clock prescaler for an SPI device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	Prescaler is the value that determine how much the clock should
+*		be divided by. Use the XSPIPS_CLK_PRESCALE_* constants defined
+*		in xspips.h for this setting.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XSpiPs_SetClkPrescaler(XSpiPs *InstancePtr, u8 Prescaler)
+{
+	u32 ConfigReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Prescaler > 0U) && (Prescaler <= XSPIPS_CR_PRESC_MAXIMUM));
+
+	/*
+	 * Do not allow the prescaler to be changed while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		/*
+		 * Read the Config register, mask out the interesting bits, and set
+		 * them with the shifted value passed into the function. Write the
+		 * results back to the Config register.
+		 */
+		ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XSPIPS_CR_OFFSET);
+
+		ConfigReg &= (u32)(~XSPIPS_CR_PRESC_MASK);
+		ConfigReg |= (u32) ((u32)Prescaler & (u32)XSPIPS_CR_PRESC_MAXIMUM) <<
+			XSPIPS_CR_PRESC_SHIFT;
+
+		XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XSPIPS_CR_OFFSET,
+				ConfigReg);
+
+		Status = (s32)XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the clock prescaler of an SPI device.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return	The prescaler value.
+*
+* @note		None.
+*
+*
+******************************************************************************/
+u8 XSpiPs_GetClkPrescaler(XSpiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSPIPS_CR_OFFSET);
+
+	ConfigReg &= XSPIPS_CR_PRESC_MASK;
+
+	return (u8)(ConfigReg >> XSPIPS_CR_PRESC_SHIFT);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the delay register for the SPI device driver.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0. The range of
+* each delay value is 0-255.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	DelayNss is the delay for which the chip select outputs will
+*		be de-asserted between words when CPHA=0.
+* @param	DelayBtwn is the delay between one Slave Select being
+*		de-activated and the activation of another slave. The delay is
+*		the number of master clock periods given by DelayBtwn + 2.
+* @param	DelayAfter define the delay between the last bit of the current
+*		byte transfer and the first bit of the next byte transfer.
+*		The delay in number of master clock periods is given as:
+*		CPHA=0:DelayInit+DelayAfter+3
+*		CPHA=1:DelayAfter+1
+* @param	DelayInit is the delay between asserting the slave select signal
+*		and the first bit transfer. The delay int number of master clock
+*		periods is DelayInit+1.
+*
+* @return
+*		- XST_SUCCESS if delays are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSpiPs_SetDelays(XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit)
+{
+	u32 DelayRegister;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the delays to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		/* Shift, Mask and OR the values to build the register settings */
+		DelayRegister = (u32) DelayNss << XSPIPS_DR_NSS_SHIFT;
+		DelayRegister |= (u32) DelayBtwn << XSPIPS_DR_BTWN_SHIFT;
+		DelayRegister |= (u32) DelayAfter << XSPIPS_DR_AFTER_SHIFT;
+		DelayRegister |= (u32) DelayInit;
+
+		XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XSPIPS_DR_OFFSET, DelayRegister);
+
+		Status = (s32)XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the delay settings for an SPI device.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+* @param	DelayNss is a pointer to the delay for which the chip select
+*		outputs will be de-asserted between words when CPHA=0.
+* @param	DelayBtwn is a pointer to the Delay Between transfers value.
+*		This is a return parameter.
+* @param	DelayAfter is a pointer to the Delay After transfer value.
+*		This is a return parameter.
+* @param	DelayInit is a pointer to the Delay Initially value. This is
+*		a return parameter.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XSpiPs_GetDelays(XSpiPs *InstancePtr,u8 *DelayNss, u8 *DelayBtwn,
+			u8 *DelayAfter, u8 *DelayInit)
+{
+	u32 DelayRegister;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	DelayRegister = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSPIPS_DR_OFFSET);
+
+	*DelayInit = (u8)(DelayRegister & XSPIPS_DR_INIT_MASK);
+
+	*DelayAfter = (u8)((DelayRegister & XSPIPS_DR_AFTER_MASK) >>
+				 XSPIPS_DR_AFTER_SHIFT);
+
+	*DelayBtwn = (u8)((DelayRegister & XSPIPS_DR_BTWN_MASK) >>
+				XSPIPS_DR_BTWN_SHIFT);
+
+	*DelayNss = (u8)((DelayRegister & XSPIPS_DR_NSS_MASK) >>
+				XSPIPS_DR_NSS_SHIFT);
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_selftest.c
new file mode 100644
index 000000000..780975a2e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_selftest.c
@@ -0,0 +1,156 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xspips_selftest.c
+*
+* This component contains the implementation of selftest functions for an SPI
+* device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00  drg/jz 01/25/10 First release
+* 1.04a	sg     01/30/13 SetDelays test includes DelayTestNss parameter.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+* 		- XST_SUCCESS if successful
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSpiPs_SelfTest(XSpiPs *InstancePtr)
+{
+	s32 Status;
+	u32 Register;
+	u8 DelayTestNss;
+	u8 DelayTestBtwn;
+	u8 DelayTestAfter;
+	u8 DelayTestInit;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Reset the SPI device to leave it in a known good state
+	 */
+	XSpiPs_Reset(InstancePtr);
+
+	/*
+	 * All the SPI registers should be in their default state right now.
+	 */
+	Register = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XSPIPS_CR_OFFSET);
+	if (Register != XSPIPS_CR_RESET_STATE) {
+		return (s32)XST_REGISTER_ERROR;
+	}
+
+	Register = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XSPIPS_SR_OFFSET);
+	if (Register != XSPIPS_ISR_RESET_STATE) {
+		return (s32)XST_REGISTER_ERROR;
+	}
+
+	DelayTestNss = 0x5AU;
+	DelayTestBtwn = 0xA5U;
+	DelayTestAfter = 0xAAU;
+	DelayTestInit = 0x55U;
+
+	/*
+	 * Write and read the delay register, just to be sure there is some
+	 * hardware out there.
+	 */
+	Status = XSpiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
+				   DelayTestAfter, DelayTestInit);
+	if (Status != (s32)XST_SUCCESS) {
+		return Status;
+	}
+
+	XSpiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
+			&DelayTestAfter, &DelayTestInit);
+	if ((0x5AU != DelayTestNss) || (0xA5U != DelayTestBtwn) ||
+		(0xAAU != DelayTestAfter) || (0x55U != DelayTestInit)) {
+		return (s32)XST_REGISTER_ERROR;
+	}
+
+	Status = XSpiPs_SetDelays(InstancePtr, 0U, 0U, 0U, 0U);
+	if (Status != (s32)XST_SUCCESS) {
+		return Status;
+	}
+
+	/*
+	 * Reset the SPI device to leave it in a known good state
+	 */
+	XSpiPs_Reset(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_sinit.c
new file mode 100644
index 000000000..47fcee58b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/spips_v3_0/src/xspips_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xspips_sinit.c
+*
+* The implementation of the XSpiPs driver's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/25/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xspips.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSpiPs_Config XSpiPs_ConfigTable[XPAR_XSPIPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xspips.h for the definition of XSpiPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XSpiPs_Config *XSpiPs_LookupConfig(u16 DeviceId)
+{
+	XSpiPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XSPIPS_NUM_INSTANCES; Index++) {
+		if (XSpiPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSpiPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XSpiPs_Config *)CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/Makefile
new file mode 100644
index 000000000..7f051ce50
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/Makefile
@@ -0,0 +1,75 @@
+###############################################################################
+#
+# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+include config.make
+
+AS=aarch64-none-elf-as
+CC=aarch64-none-elf-gcc
+AR=aarch64-none-elf-ar
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
+
+
+#The following flags are required for PEEP. We can remove them later
+ECC_FLAGS	+= -march=armv8-a
+
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+INCLUDEFILES=*.h
+
+libs: $(LIBS)
+
+standalone_libs: $(LIBSOURCES)
+	echo "Compiling standalone A53"
+	$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+
+.PHONY: include
+include: standalone_includes
+
+standalone_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OUTS}
+	$(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/_exit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/_exit.c
new file mode 100644
index 000000000..77806d1ba
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/_exit.c
@@ -0,0 +1,45 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (sint32 status)
+{
+  (void)status;
+  while (1)
+  {
+	__asm__("wfi");
+  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/_open.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/_open.c
new file mode 100644
index 000000000..a4b7f8241
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/_open.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
+{
+  (void *)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/_sbrk.c
new file mode 100644
index 000000000..5911b0585
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/_sbrk.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) caddr_t _sbrk ( s32 incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( s32 incr )
+{
+  static u8 *heap = NULL;
+  u8 *prev_heap;
+  static u8 *HeapEndPtr = (u8 *)&_heap_end;
+  caddr_t Status;
+
+  if (heap == NULL) {
+    heap = (u8 *)&_heap_start;
+  }
+  prev_heap = heap;
+
+  heap += incr;
+
+  if (heap > HeapEndPtr){
+	  Status = (caddr_t) -1;
+  }
+  else if (prev_heap != NULL) {
+	  Status = (caddr_t) ((void *)prev_heap);
+  }
+  else {
+	  Status = (caddr_t) -1;
+  }
+
+  return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/abort.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/abort.c
new file mode 100644
index 000000000..f64509404
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/abort.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include 
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+  _exit(1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/asm_vectors.S
new file mode 100644
index 000000000..2d779f5ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/asm_vectors.S
@@ -0,0 +1,208 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file asm_vectors.s
+*
+* This file contains the initial vector table for the Cortex A53 processor
+* Currently NEON registers are not saved on stack if interrupt is taken.
+* It will be implemented.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00	pkp	5/21/14 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+
+
+.org 0
+.text
+
+.globl _boot
+.globl _vector_table
+
+.globl FIQInterrupt
+.globl IRQInterrupt
+.globl SErrorInterrupt
+.globl SynchronousInterrupt
+
+
+.org 0
+
+.section .vectors, "a"
+
+_vector_table:
+
+.set	VBAR, _vector_table
+.org VBAR
+	b	_boot
+.org (VBAR + 0x200)
+	b	SynchronousInterruptHandler
+
+.org (VBAR + 0x280)
+	b	IRQInterruptHandler
+
+.org (VBAR + 0x300)
+	b	FIQInterruptHandler
+
+.org (VBAR + 0x380)
+	b	SErrorInterruptHandler
+
+
+SynchronousInterruptHandler:
+	stp	X0,X1, [sp,#-0x10]!
+	stp	X2,X3, [sp,#-0x10]!
+	stp	X4,X5, [sp,#-0x10]!
+	stp	X6,X7, [sp,#-0x10]!
+	stp	X8,X9, [sp,#-0x10]!
+	stp	X10,X11, [sp,#-0x10]!
+	stp	X12,X13, [sp,#-0x10]!
+	stp	X14,X15, [sp,#-0x10]!
+	stp	X16,X17, [sp,#-0x10]!
+	stp     X18,X19, [sp,#-0x10]!
+	stp     X29,X30, [sp,#-0x10]!
+
+        bl      SynchronousInterrupt
+
+	ldp     X29,X30, [sp], #0x10
+        ldp     X18,X19, [sp], #0x10
+	ldp	X16,X17, [sp], #0x10
+	ldp	X14,X15, [sp], #0x10
+	ldp	X12,X13, [sp], #0x10
+	ldp	X10,X11, [sp], #0x10
+	ldp	X8,X9, [sp], #0x10
+	ldp	X6,X7, [sp], #0x10
+	ldp	X4,X5, [sp], #0x10
+	ldp	X2,X3, [sp], #0x10
+	ldp	X0,X1, [sp], #0x10
+
+	eret
+
+IRQInterruptHandler:
+	stp	X0,X1, [sp,#-0x10]!
+	stp	X2,X3, [sp,#-0x10]!
+	stp	X4,X5, [sp,#-0x10]!
+	stp	X6,X7, [sp,#-0x10]!
+	stp	X8,X9, [sp,#-0x10]!
+	stp	X10,X11, [sp,#-0x10]!
+	stp	X12,X13, [sp,#-0x10]!
+	stp	X14,X15, [sp,#-0x10]!
+	stp	X16,X17, [sp,#-0x10]!
+	stp     X18,X19, [sp,#-0x10]!
+	stp     X29,X30, [sp,#-0x10]!
+
+	bl      IRQInterrupt
+
+	ldp     X29,X30, [sp], #0x10
+	ldp     X18,X19, [sp], #0x10
+	ldp	X16,X17, [sp], #0x10
+	ldp	X14,X15, [sp], #0x10
+	ldp	X12,X13, [sp], #0x10
+	ldp	X10,X11, [sp], #0x10
+	ldp	X8,X9, [sp], #0x10
+	ldp	X6,X7, [sp], #0x10
+	ldp	X4,X5, [sp], #0x10
+	ldp	X2,X3, [sp], #0x10
+	ldp	X0,X1, [sp], #0x10
+
+	eret
+
+FIQInterruptHandler:
+
+	stp	X0,X1, [sp,#-0x10]!
+	stp	X2,X3, [sp,#-0x10]!
+	stp	X4,X5, [sp,#-0x10]!
+	stp	X6,X7, [sp,#-0x10]!
+	stp	X8,X9, [sp,#-0x10]!
+	stp	X10,X11, [sp,#-0x10]!
+	stp	X12,X13, [sp,#-0x10]!
+	stp	X14,X15, [sp,#-0x10]!
+	stp	X16,X17, [sp,#-0x10]!
+	stp     X18,X19, [sp,#-0x10]!
+	stp     X29,X30, [sp,#-0x10]!
+
+        bl      FIQInterrupt
+
+	ldp     X29,X30, [sp], #0x10
+        ldp     X18,X19, [sp], #0x10
+	ldp	X16,X17, [sp], #0x10
+	ldp	X14,X15, [sp], #0x10
+	ldp	X12,X13, [sp], #0x10
+	ldp	X10,X11, [sp], #0x10
+	ldp	X8,X9, [sp], #0x10
+	ldp	X6,X7, [sp], #0x10
+	ldp	X4,X5, [sp], #0x10
+	ldp	X2,X3, [sp], #0x10
+	ldp	X0,X1, [sp], #0x10
+
+	eret
+
+SErrorInterruptHandler:
+
+	stp	X0,X1, [sp,#-0x10]!
+	stp	X2,X3, [sp,#-0x10]!
+	stp	X4,X5, [sp,#-0x10]!
+	stp	X6,X7, [sp,#-0x10]!
+	stp	X8,X9, [sp,#-0x10]!
+	stp	X10,X11, [sp,#-0x10]!
+	stp	X12,X13, [sp,#-0x10]!
+	stp	X14,X15, [sp,#-0x10]!
+	stp	X16,X17, [sp,#-0x10]!
+	stp     X18,X19, [sp,#-0x10]!
+	stp     X29,X30, [sp,#-0x10]!
+
+        bl      SErrorInterrupt
+
+	ldp     X29,X30, [sp], #0x10
+        ldp     X18,X19, [sp], #0x10
+	ldp	X16,X17, [sp], #0x10
+	ldp	X14,X15, [sp], #0x10
+	ldp	X12,X13, [sp], #0x10
+	ldp	X10,X11, [sp], #0x10
+	ldp	X8,X9, [sp], #0x10
+	ldp	X6,X7, [sp], #0x10
+	ldp	X4,X5, [sp], #0x10
+	ldp	X2,X3, [sp], #0x10
+	ldp	X0,X1, [sp], #0x10
+
+	eret
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/boot.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/boot.S
new file mode 100644
index 000000000..3d5f5d0a3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/boot.S
@@ -0,0 +1,266 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file boot.S
+*
+* This file contains the initial startup code for the Cortex A53 processor
+* Currently the processor starts at EL3 and boot code, startup and main
+* code will run on secure EL3.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	5/21/14 Initial version
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+.globl MMUTableL0
+.globl MMUTableL1
+.globl MMUTableL2
+.global _prestart
+.global _boot
+
+.global __el3_stack
+.global __el2_stack
+.global __el1_stack
+.global __el0_stack
+.global _vector_table
+
+
+.set EL3_stack,		__el3_stack
+.set EL2_stack,		__el2_stack
+.set EL1_stack,		__el1_stack
+.set EL0_stack,		__el0_stack
+
+.set TT_S1_FAULT,	0x0
+.set TT_S1_TABLE,	0x3
+
+.set L0Table,	MMUTableL0
+.set L1Table,	MMUTableL1
+.set L2Table,	MMUTableL2
+.set vector_base,	_vector_table
+
+.section .boot,"ax"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+	mov      x0, #0
+	mov      x1, #0
+	mov      x2, #0
+	mov      x3, #0
+	mov      x4, #0
+	mov      x5, #0
+	mov      x6, #0
+	mov      x7, #0
+	mov      x8, #0
+	mov      x9, #0
+	mov      x10, #0
+	mov      x11, #0
+	mov      x12, #0
+	mov      x13, #0
+	mov      x14, #0
+	mov      x15, #0
+	mov      x16, #0
+	mov      x17, #0
+	mov      x18, #0
+	mov      x19, #0
+	mov      x20, #0
+	mov      x21, #0
+	mov      x22, #0
+	mov      x23, #0
+	mov      x24, #0
+	mov      x25, #0
+	mov      x26, #0
+	mov      x27, #0
+	mov      x28, #0
+	mov      x29, #0
+	mov      x30, #0
+#if 0 //dont put other a53 cpus in wfi
+   //Which core am I
+   // ----------------
+	mrs      x0, MPIDR_EL1
+	and      x0, x0, #0xFF                     //Mask off to leave Aff0
+	cbz      x0, OKToRun                          //If core 0, run the primary init code
+EndlessLoop0:
+	wfi
+	b        EndlessLoop0
+#endif
+OKToRun:
+
+	/*Set vector table base addresses. */
+	ldr	x1, =vector_base
+	msr	VBAR_EL3,x1
+	msr	VBAR_EL2,x1
+	msr	VBAR_EL1,x1
+
+	/*Define stack pointer for current exception level*/
+	ldr	 x2,=EL3_stack
+	mov	 sp,x2
+
+	/* Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU*/
+	mov      x0, #0                 // Clear all trap bits
+	msr      CPTR_EL3, x0
+
+
+	/* Configure SCR_EL3 */
+	mov      w1, #0              	//; Initial value of register is unknown
+	orr      w1, w1, #(1 << 11)  	//; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
+	orr      w1, w1, #(1 << 10)  	//; Set RW bit (EL1 is AArch64, as this is the Secure world)
+	orr      w1, w1, #(1 << 3)   	//; Set EA bit (SError routed to EL3)
+	orr      w1, w1, #(1 << 2)   	//; Set FIQ bit (FIQs routed to EL3)
+	orr      w1, w1, #(1 << 1)   	//; Set IRQ bit (IRQs routed to EL3)
+	msr      SCR_EL3, x1
+
+	/*Enable ECC protection*/
+	mrs	x0, S3_1_C11_C0_2  	// register L2CTLR_EL1
+	orr	x0, x0, #(1<<22)
+	msr	S3_1_C11_C0_2, x0
+
+	/*configure cpu auxiliary control register EL1 */
+	ldr	x0,=0x80CA000 		// L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
+	msr	S3_1_C15_C2_0, x0 	//CPUACTLR_EL1
+
+
+	/*Enable hardware coherency between cores*/
+	mrs      x0, S3_1_c15_c2_1  	//Read EL1 CPU Extended Control Register
+	orr      x0, x0, #(1 << 6)  	//Set the SMPEN bit
+	msr      S3_1_c15_c2_1, x0  	//Write EL1 CPU Extended Control Register
+	isb
+
+	tlbi 	ALLE3
+	ic      IALLU                  	//; Invalidate I cache to PoU
+	bl 	invalidate_dcaches
+	dsb	 sy
+	isb
+
+	ldr      x1, =L0Table 		//; Get address of level 0 for TTBR0_EL1
+	msr      TTBR0_EL3, x1		//; Set TTBR0_EL3 (NOTE: There is no TTBR1 at EL1)
+
+
+	/**********************************************
+	* Set up memory attributes
+	* This equates to:
+	* 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
+	* 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
+	* 2 = b00000000 = Device-nGnRnE
+	**********************************************/
+	ldr      x1, =0x000000000000FF44
+	msr      MAIR_EL3, x1
+
+        /**********************************************
+        * Set up TCR_EL3
+	* Physical Address Size PS =  010 -> 40bits 1TB
+	* Granual Size TG0 = 00 -> 4KB
+        * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
+        ***************************************************/
+        ldr     x1,=0x80823518
+        msr     TCR_EL3, x1
+        isb
+
+	/* Configure SCTLR_EL3 */
+	mov      x1, #0                //Most of the SCTLR_EL3 bits are unknown at reset
+	orr      x1, x1, #(1 << 12)	//Enable I cache
+	orr      x1, x1, #(1 << 3)	//Enable SP alignment check
+	orr      x1, x1, #(1 << 2)	//Enable caches
+	orr      x1, x1, #(1 << 0)	//Enable MMU
+	msr      SCTLR_EL3, x1
+	dsb	 sy
+	isb
+
+	bl 	 _startup		//jump to start
+
+loop:	b	loop
+
+
+invalidate_dcaches:
+
+	dmb     ISH
+	mrs     x0, CLIDR_EL1          //; x0 = CLIDR
+	ubfx    w2, w0, #24, #3        //; w2 = CLIDR.LoC
+	cmp     w2, #0                 //; LoC is 0?
+	b.eq    invalidateCaches_end   //; No cleaning required and enable MMU
+	mov     w1, #0                 //; w1 = level iterator
+
+invalidateCaches_flush_level:
+	add     w3, w1, w1, lsl #1     //; w3 = w1 * 3 (right-shift for cache type)
+	lsr     w3, w0, w3             //; w3 = w0 >> w3
+	ubfx    w3, w3, #0, #3         //; w3 = cache type of this level
+	cmp     w3, #2                 //; No cache at this level?
+	b.lt    invalidateCaches_next_level
+
+	lsl     w4, w1, #1
+	msr     CSSELR_EL1, x4         //; Select current cache level in CSSELR
+	isb                            //; ISB required to reflect new CSIDR
+	mrs     x4, CCSIDR_EL1         //; w4 = CSIDR
+
+	ubfx    w3, w4, #0, #3
+	add    	w3, w3, #2             //; w3 = log2(line size)
+	ubfx    w5, w4, #13, #15
+	ubfx    w4, w4, #3, #10        //; w4 = Way number
+	clz     w6, w4                 //; w6 = 32 - log2(number of ways)
+
+invalidateCaches_flush_set:
+	mov     w8, w4                 //; w8 = Way number
+invalidateCaches_flush_way:
+	lsl     w7, w1, #1             //; Fill level field
+	lsl     w9, w5, w3
+	orr     w7, w7, w9             //; Fill index field
+	lsl     w9, w8, w6
+	orr     w7, w7, w9             //; Fill way field
+	dc      CISW, x7               //; Invalidate by set/way to point of coherency
+	subs    w8, w8, #1             //; Decrement way
+	b.ge    invalidateCaches_flush_way
+	subs    w5, w5, #1             //; Descrement set
+	b.ge    invalidateCaches_flush_set
+
+invalidateCaches_next_level:
+	add     w1, w1, #1             //; Next level
+	cmp     w2, w1
+	b.gt    invalidateCaches_flush_level
+
+invalidateCaches_end:
+	ret
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/bspconfig.h
new file mode 100644
index 000000000..68b572d09
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/bspconfig.h
@@ -0,0 +1,40 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#define MICROBLAZE_PVR_NONE
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/changelog.txt b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/changelog.txt
new file mode 100644
index 000000000..dc1873cde
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/changelog.txt
@@ -0,0 +1,222 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ---------------------------------------------------
+  * 3.02a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm  06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm  07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ *                     cacheable regions
+ *                     Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ *                     generated by the cpu driver, for enabling caches
+ * 3.02a sdm  07/08/11 Updated microblaze cache flush APIs based on write-back/
+ *                     write-thru caches
+ * 3.03a sdm  08/20/11 Updated the tag/data RAM latency values for L2CC
+ *		       Updated the MMU table to mark OCM in high address space
+ *		       as inner cacheable and reserved space as Invalid
+ * 3.03a sdm  08/20/11 Changes to support FreeRTOS
+ *		       Updated the MMU table to mark upper half of the DDR as
+ *		       non-cacheable
+ *		       Setup supervisor and abort mode stacks
+ *		       Do not initialize/enable L2CC in case of AMP
+ *		       Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm  08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ *		       in case of AMP
+ * 3.03a sdm  09/14/11 Added code for performance monitor and L2CC event
+ *		       counters
+ * 3.03a sdm  11/08/11 Updated microblaze xil_cache.h file to include
+ *		       xparameters.h file for CR630532 -  Xil_DCacheFlush()/
+ *		       Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ *		       for MicroBlaze will invalidate data in the cache instead
+ *		       of flushing it for writeback caches
+ * 3.04a sdm  11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm  01/02/12 Updated to clear cp15 regs with unknown reset values
+ *		       Remove redundant dsb/dmb instructions in cache maintenance
+ *		       APIs
+ *		       Remove redundant dsb in mcr instruction
+ * 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm  02/02/12 Removed some of the defines as they are being generated through
+ *                     driver tcl in xparameters.h. Update the gcc/translationtable.s
+ *                     for the QSPI complete address range - DT644567
+ *                     Removed profile directory for armcc compiler and changed
+ *                     profiling setting to false in standalone_v2_1_0.tcl file
+ *                     Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa  03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ *		       invalidate the caches before enabling back the MMU and
+ *		       D cache.
+ * 3.05a asa  04/15/12 Updated the function Xil_SetTlbAttributes in file
+ *		       xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ *		       array, flush the D-cache before changing the attributes
+ *		       in translation table. The user need not call Xil_DisableMMU
+ *		       before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ *	 sgd	       initialization is present. Changes for this were done in
+ *		       uart.c and xil-crt0.s.
+ *		       Made changes in xil_io.c to use volatile pointers.
+ *		       Made changes in xil_mmu.c to correct the function
+ *		       Xil_SetTlbAttributes.
+ *		       Changes are made xil-crt0.s to initialize the static
+ *		       C++ constructors.
+ *		       Changes are made in boot.s, to fix the TTBR settings,
+ *		       correct the L2 Cache Auxiliary register settings, L2 cache
+ *		       latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ *	 sgd	       usleep.c to use global timer intstead of CP15.
+ *		       Made changes in cortexa9/gcc/translation_table.s to map
+ *		       the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/boot.S to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/translation_table.s to
+ *		       map the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/boot.S to optimize the
+ *		       L2 cache settings. Changes the section properties for
+ *		       ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ *			and cortexa9/gcc/translation_table.S.
+ *		       Made changes in cortexa9/xil_cache.c to change the
+ *		       cache invalidation order.
+ * 3.07a asa  08/17/12 Made changes across files for Cortexa9 to remove
+ *		       compilation/linking issues for C++ compiler.
+ *		       Made changes in mb_interface.h to remove compilation/
+ *		       linking issues for C++ compiler.
+ *		       Added macros for swapb and swaph microblaze instructions
+ *		       mb_interface.h
+ *		       Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ *		       for CortexA9.
+ * 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa  08/31/12 Added xil_printf.h include
+ * 3.07a sgd  09/18/12 Corrected the L2 cache enable settings
+ *				Corrected L2 cache sequence disable sequence
+ * 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa  01/25/13 Updated to push and pop neon registers into stack for
+ *		       irq/fiq handling.
+ *		       Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ *		       fixes the CR #692094.
+ * 3.09a sgd  02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt  04/18/13 Implemented ARM Erratas.
+ *		       Cortex A9 Errata - 742230, 743622, 775420, 794073
+ *		       L2Cache PL310 Errata - 588369, 727915, 759370
+ *		       Please refer to file 'xil_errata.h' for errata
+ *		       description.
+ * 3.10a asa  05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ *		       cache APIs were corresponding to only Layer 1 cache
+ *		       memories. New APIs were now added and the existing cache
+ *		       related APIs were changed to provide a uniform interface
+ *		       to flush/invalidate/enable/disable the complete cache
+ *		       system which includes both L1 and L2 caches. The changes
+ *		       for these were done in:
+ *		       src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ *		       files.
+ *		       Four new files were added for supporting L2 cache. They are:
+ *		       microblaze_flush_cache_ext.S-> Flushes L2 cache
+ *		       microblaze_flush_cache_ext_range.S -> Flushes a range of
+ *		       memory in L2 cache.
+ *		       microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ *		       microblaze_invalidate_cache_ext_range -> Invalidates a
+ *		       range of memory in L2 cache.
+ *		       These changes are done to implement PR #697214.
+ * 3.10a  asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ *		       fix the CR #706464. L2 cache disabling happens independent
+ *		       of L1 data cache disable operation. Changes are done in the
+ *		       same file in cache handling APIs to do a L2 cache sync
+ *		       (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa  05/20/13 Added API/Macros for enabling and disabling nested
+ *		       interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt  05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ *		       sync operation. This fixes the CR# 716781.
+ * 3.11a asa  09/07/13 Updated armcc specific BSP files to have proper support
+ *		       for armcc toolchain.
+ *		       Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ *		       fix issues related to NEON context saving. The assembly
+ *		       routines for IRQ and FIQ handling are modified.
+ *		       Deprecated the older BSP (3.10a).
+ * 3.11a asa  09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ *		       various potential issues. Made changes in the function
+ *		       Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa  09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ *		       in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa  09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ *		       L2 cache sync operation and to fix issues around complete
+ *		       L2 cache flush/invalidation by ways.
+ * 3.12a asa  10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ *		       to fix linking issues with armcc/DS-5. Modified the armcc
+ *		       makefile to fix issues.
+ * 3.12a asa  11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0   hk   12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 	 pkp  22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ *		       and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ *		       src\cortexa9\armcc\) to fix CR#767251
+ * 4.0	 pkp  24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ *		       Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ *		       Few cache lines were missed to invalidate when unaligned address
+ *		       invalidation was accommodated in Xil_DCacheInvalidateRange.
+ *		       In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ *		       stack memory (which contains return address) was invalidated. So
+ *		       stack memory is flushed first and then L1D cache is invalidated.
+ *		       This is done to fix CR #763829
+ * 4.0 adk   22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ *			mblaze_nt_types.h file and replace uint32_t with u32 in the
+ *			profile_hist.c to fix the above CR.
+ * 4.1 bss   04/14/14  Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * 		       instead of libxil.a and added prototypes for
+ *		       microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ *		       mb_interface.h
+ * 4.1 hk    04/18/14  Add sleep function.
+ * 4.1 asa   04/21/14  Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ *		       some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa   04/28/14  Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss   04/29/14  Modified driver tcl to use libxil.a if libgloss.a does not exist
+ *			CR#794205
+ * 4.1 asa   05/09/14  Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ *		       common/xil_testcache.c
+ *	               Fix for CR#764881.
+ * 4.1 srt   06/27/14  Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ *                     output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp   06/27/14  Added support for IAR compiler in src/cortexa9/iccarm.
+ *		       Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp   06/19/14  Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ *		       cortexa9/armcc/boot.s. Added default exception handlers for data
+ *		       abort and prefetch abort using handlers called
+ *		       DataAbortHandler and PrefetchAbortHandler respectively in
+ *		       cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp   06/30/14  MakeFile for cortexa9/armcc has been changed to fixes the
+ *		       issue of improper linking of translation_table.s
+ * 4.2 pkp   07/04/14  added weak attribute for the function in BSP which are also present
+ *		       in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp   07/21/14  Corrected reset value of event counter in function
+ *		       Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp   07/21/14  Included xil_types.h file in xil_mmu.h which had contained a function
+ * 		       containing type def u32 defined in xil_types.g to resolve issue of
+ *		       CR#805869
+ * 4.2 pkp   08/04/14  Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ *		       it is not possible to generate timer in nanosecond due to limited
+ *		       cpu frequency
+ * 4.2 pkp   08/04/14  Removed PEEP board related code which contained initialization of
+ *		       uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ *		       and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ *		       removed function definition of XSmc_NorInit and XSmc_NorInit from
+ *		       cortexa9/smc.h
+ * 4.2 bss   08/11/14  Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ *		       cache_ext_range declarations in mb_interface.h CR#783821.
+ *		       Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp   08/21/14  modified makefile of iccarm for proper linking of objectfiles in
+ *		       cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp   09/02/14  modified translation table entries in cortexa9/gcc/translation_table.s,
+ *		       armcc/translation_table.s and iccarm/translation_table.s
+ *		       to properly defined reserved entries according to address map for
+ *		       fixing CR#820146
+ * 4.2 pkp   09/11/14  modified translation table entries in cortexa9/iccarm/translation_table.s
+ *		       and  cortexa9/armcc/translation_table.s to resolve compilation
+ *		       error for solving CR#822897
+ * 5.0 kvn   12/9/14   Support for Zync Ultrascale Mp.Also modified code for
+ *                     MISRA-C:2012 compliance.
+ * 5.0 pkp   12/15/14  Added APIs to get information about the platforms running the code by
+ *		       adding src/common/xplatform_info.*s
+ * 5.0 pkp   16/12/14  Modified boot code to enable scu after MMU is enabled and
+ *		       removed incorrect initialization of TLB lockdown register to fix
+ *		       CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ *		       and iccarm/boot.s
+ * 5.0 pkp   25/02/15  Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ *		       for iccarm and armcc compiler of cortexA9
+ *****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/close.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/close.c
new file mode 100644
index 000000000..38bc6dca2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/close.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+  (void)fd;
+  return (0);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/config.make b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/config.make
new file mode 100644
index 000000000..ead407023
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/config.make
@@ -0,0 +1,2 @@
+LIBSOURCES = *.c *.s *.S
+LIBS = standalone_libs
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/errno.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/errno.c
new file mode 100644
index 000000000..c0b1d14fa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/errno.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure.  This
+   function returns its address for use by the macro errno defined in
+   errno.h.  */
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+  return &_REENT->_errno;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/fcntl.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/fcntl.c
new file mode 100644
index 000000000..63d390af4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/fcntl.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ *          We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg)
+{
+  (void)fd;
+  (void)cmd;
+  (void)arg;
+  return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/fstat.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/fstat.c
new file mode 100644
index 000000000..a1d394c94
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/fstat.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+  (void)fd;
+  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+  return (0);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/getpid.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/getpid.c
new file mode 100644
index 000000000..73c7902ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/getpid.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+  return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+  return 1;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/inbyte.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/inbyte.c
new file mode 100644
index 000000000..0036459e4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif 
+
+char inbyte(void) {
+	 return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/initialise_monitor_handles.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/initialise_monitor_handles.c
new file mode 100644
index 000000000..4571f492e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/initialise_monitor_handles.c
@@ -0,0 +1,52 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file initialise_monitor_handles.c
+*
+* Contains blank function to avoid compilation error
+*
+* @note
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+******************************************************************************/
+__attribute__((weak)) void initialise_monitor_handles(){
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/isatty.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/isatty.c
new file mode 100644
index 000000000..d0a8a8251
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/isatty.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ *           returns 0 if not. Since we're hooked up to a
+ *           serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/kill.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/kill.c
new file mode 100644
index 000000000..fdbcb600a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/kill.c
@@ -0,0 +1,60 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _kill(s32 pid, s32 sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) s32 kill(s32 pid, s32 sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
+
+__attribute__((weak)) s32 _kill(s32 pid, s32 sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/lseek.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/lseek.c
new file mode 100644
index 000000000..0a3a1fa8f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/lseek.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek --  Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/open.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/open.c
new file mode 100644
index 000000000..04a136c68
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/open.c
@@ -0,0 +1,52 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode)
+{
+  (void *)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/outbyte.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/outbyte.c
new file mode 100644
index 000000000..8b56036b7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c); 
+
+#ifdef __cplusplus
+}
+#endif 
+
+void outbyte(char c) {
+	 XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/print.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/print.c
new file mode 100644
index 000000000..31d7b1989
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/print.c
@@ -0,0 +1,32 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#ifdef STDOUT_BASEADDRESS
+  while (*ptr != (char8)0) {
+    outbyte (*ptr);
+	*ptr++;
+  }
+#else
+(void)ptr;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/putnum.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/putnum.c
new file mode 100644
index 000000000..ec0dc37ee
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+  char8  buf[9];
+  u32  cnt;
+  s32 i;
+  char8  *ptr;
+  u32  digit;
+  for(i = 0; i<9; i++) {
+	buf[i] = '0';
+  }
+
+  ptr = buf;
+  for (cnt = 7U ; cnt >= 0U ; cnt--) {
+    digit = ((num >> (cnt * 4U)) & 0x0000000FU);
+
+    if ((digit <= 9U) && (ptr != NULL)) {
+		digit += (u32)'0';
+		*ptr = ((char8) digit);
+		ptr += 1;
+	} else if (ptr != NULL) {
+		digit += ((u32)'a' - (u32)10);
+		*ptr = ((char8)digit);
+		ptr += 1;
+	} else {
+		/*Made for MisraC Compliance*/;
+	}
+  }
+
+  if(ptr != NULL) {
+	  *ptr = (char8) 0;
+  }
+  print (buf);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/read.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/read.c
new file mode 100644
index 000000000..d0fe15eb2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/read.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+
+#include "xparameters.h"
+#include "xil_printf.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read  -- read bytes from the serial port. Ignore fd, since
+ *          we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    *LocalBuf = inbyte();
+	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
+	        break;
+		}
+	}
+	if(LocalBuf != NULL) {
+	LocalBuf -= i;
+	}
+  }
+
+  return (i + 1);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    *LocalBuf = inbyte();
+	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
+	        break;
+		}
+	}
+	if(LocalBuf != NULL) {
+	LocalBuf -= i;
+	}
+  }
+
+  return (i + 1);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/sbrk.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/sbrk.c
new file mode 100644
index 000000000..78b580912
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/sbrk.c
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+  char8 *base;
+  static char8 *heap_ptr = HeapBase;
+
+  base = heap_ptr;
+  if(heap_ptr != NULL) {
+	heap_ptr += nbytes;
+  }
+
+/*  if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
+  if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
+    return base;
+  }	else {
+    errno = ENOMEM;
+    return ((char8 *)-1);
+  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/sleep.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/sleep.c
new file mode 100644
index 000000000..e8aedafba
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/sleep.c
@@ -0,0 +1,86 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex A53 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds
+*
+* @param	seconds requested
+*
+* @return	0 always
+*
+* @note		None.
+*
+****************************************************************************/
+s32 sleep(u32 seconds)
+{
+	XTime tEnd, tCur;
+
+	/*write 50MHz frequency to System Time Stamp Generator Register*/
+	Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),XIOU_SCNTRS_FREQ);
+
+	/*Enable the counter*/
+	Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),XIOU_SCNTRS_CNT_CNTRL_REG_EN);
+
+	XTime_GetTime(&tCur);
+	tEnd  = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
+	do
+	{
+		XTime_GetTime(&tCur);
+	} while (tCur < tEnd);
+
+	/*Disable the counter*/
+	Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),(~(XIOU_SCNTRS_CNT_CNTRL_REG_EN)));
+	return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/sleep.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/sleep.h
new file mode 100644
index 000000000..8497d2fe6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/sleep.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+s32 usleep(u32 useconds);
+s32 sleep(u32 seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/translation_table.s b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/translation_table.s
new file mode 100644
index 000000000..ad5686a24
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/translation_table.s
@@ -0,0 +1,170 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file translation_table.s
+*
+* This file contains the initialization for the MMU table in RAM
+* needed by the Cortex A53 processor
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  05/21/14 Initial version
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+	.globl  MMUTableL0
+	.globl  MMUTableL1
+	.globl  MMUTableL2
+
+	.set reserved,	0x0 					/* Fault*/
+	.set Memory,	0x405 | (3 << 8) | (0x0)		/* normal writeback write allocate inner shared read write */
+	.set Device,	0x409 | (1 << 53)| (1 << 54) |(0x0)	/* strongly ordered read write non executable*/
+	.section .mmu_tbl0,"a"
+
+MMUTableL0:
+
+.set SECT, MMUTableL1
+.8byte	SECT + 0x3
+.set SECT, MMUTableL1+0x1000
+.8byte	SECT + 0x3
+
+	.section .mmu_tbl1,"a"
+
+MMUTableL1:
+
+.set SECT, MMUTableL2			/*1GB DDR*/
+.8byte	SECT + 0x3
+
+.rept	0x3				/*1GB DDR, 1GB PL, 2GB other devices n memory*/
+.set SECT, SECT + 0x1000
+.8byte	SECT + 0x3
+.endr
+
+.set SECT,0x100000000
+.rept	0xC
+.8byte	SECT + reserved
+.set SECT, SECT + 0x40000000	/*12GB Reserved*/
+.endr
+
+.rept	0x10
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*8GB PL, 8GB PCIe*/
+
+.endr
+
+.rept	0x20
+.8byte	SECT + Memory
+
+.set SECT, SECT + 0x40000000	/*32GB DDR*/
+.endr
+
+
+.rept	0xC0
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*192GB PL*/
+.endr
+
+
+.rept	0x100
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*256GB PL/PCIe*/
+.endr
+
+
+.rept	0x200
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*512GB PL/DDR*/
+.endr
+
+
+.section .mmu_tbl2,"a"
+
+MMUTableL2:
+
+.set SECT, 0
+
+.rept	0x0400			/*2GB DDR */
+.8byte	SECT + Memory
+.set	SECT, SECT+0x200000
+.endr
+
+.rept	0x0200			/*1GB lower PL*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x0100			/*512MB QSPI*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x080			/*256MB lower PCIe*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x040			/*128MB Reserved*/
+.8byte	SECT + reserved
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x8			/*16MB coresight*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x8			/*16MB RPU low latency port*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+
+.rept	0x022			/*68MB Device*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x8			/*8MB FPS*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+
+.rept	0x4			/*16MB LPS*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+
+.8byte	SECT + Device 		/*2MB PMU/CSU */
+.set	SECT, SECT+0x200000
+.8byte  SECT + Memory		/*2MB OCM/TCM*/
+.end
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/uart.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/uart.c
new file mode 100644
index 000000000..894db7fc3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/uart.c
@@ -0,0 +1,162 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file uart.c
+*
+* This file contains APIs for configuring the UART.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/* Register offsets */
+#define UART_CR_OFFSET		0x00000000U
+#define UART_MR_OFFSET		0x00000004U
+#define UART_BAUDGEN_OFFSET	0x00000018U
+#define UART_BAUDDIV_OFFSET	0x00000034U
+
+#define MAX_BAUD_ERROR_RATE	3U	/* max % error allowed */
+#define UART_BAUDRATE	115200U
+#define CSU_VERSION_REG     0xFFCA0044U
+
+void Init_Uart(void);
+
+void Init_Uart(void)
+{
+#ifdef STDOUT_BASEADDRESS
+	u8 IterBAUDDIV;		/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud
+				 * rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 InputClk;
+	u32 BaudRate = UART_BAUDRATE;
+
+	/* set CD and BDIV */
+
+#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
+	InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
+#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
+	InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
+#else
+	/* STDIO is not set or axi_uart is being used for STDIO */
+	return;
+#endif
+InputClk = 25000000U;
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) {
+
+		/*
+		 * Calculate the value for BRGR register
+		 */
+		BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 1U));
+
+		/*
+		 * Calculate the baud rate from the BRGR value
+		 */
+		CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 1U));
+
+		/*
+		 * Avoid unsigned integer underflow
+		 */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		} else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/*
+		 * Find the calculated baud rate closest to requested baud rate.
+		 */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/*
+	 * Make sure the best error is not too large.
+	 */
+	PercentError = (Best_Error * 100U) / BaudRate;
+	if (((u32)MAX_BAUD_ERROR_RATE) < PercentError) {
+		return;
+	}
+
+	/* set CD and BDIV */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV);
+
+    /*
+     * Veloce specific code
+     */
+    if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) {
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 2U);
+	    Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 4U);
+    }
+
+	/*
+	 * 8 data, 1 stop, 0 parity bits
+	 * sel_clk=uart_clk=APB clock
+	 */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U);
+
+	/* enable Tx/Rx and reset Tx/Rx data path */
+	Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U);
+
+	return;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/unlink.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/unlink.c
new file mode 100644
index 000000000..1fef96831
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/unlink.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ *           we just return an error.
+ */
+__attribute__((weak)) s32 unlink(char8 *path)
+{
+  (void *)path;
+  errno = EIO;
+  return (-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/usleep.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/usleep.c
new file mode 100644
index 000000000..7d0ff09f4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/usleep.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex A53 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa53.h"
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND  (COUNTS_PER_SECOND/1000000 )
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param	useconds requested
+*
+* @return	0 if the delay can be achieved, -1 if the requested delay
+*		is out of range
+*
+* @note		None.
+*
+****************************************************************************/
+s32 usleep(u32 useconds)
+{
+	XTime tEnd, tCur;
+
+	/*write 50MHz frequency to System Time Stamp Generator Register*/
+	Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),XIOU_SCNTRS_FREQ);
+
+	/*Enable the counter*/
+	Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),XIOU_SCNTRS_CNT_CNTRL_REG_EN);
+
+	XTime_GetTime(&tCur);
+	tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
+	do
+	{
+		XTime_GetTime(&tCur);
+	} while (tCur < tEnd);
+
+	/*Disable the counter*/
+	Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),(~(XIOU_SCNTRS_CNT_CNTRL_REG_EN)));
+	return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/vectors.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/vectors.c
new file mode 100644
index 000000000..61d9f741b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/vectors.c
@@ -0,0 +1,149 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A53 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/vectors.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/vectors.h
new file mode 100644
index 000000000..8c508c3a2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/vectors.h
@@ -0,0 +1,81 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A53 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/write.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/write.c
new file mode 100644
index 000000000..57c53eb27
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/write.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+
+#include "xparameters.h"
+#include "xil_printf.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ *          stdout and stderr are the same. Since we have no filesystem,
+ *          open will only return an error.
+ */
+__attribute__((weak)) s32
+write (s32 fd, char8* buf, s32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_write (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xbasic_types.h
new file mode 100644
index 000000000..07e3db39a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xbasic_types.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* 

+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef unsigned short	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef unsigned long	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include 
+#endif
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu0_cfg.h
new file mode 100644
index 000000000..9029bead8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu0_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU0_CFG_H__
+#define __XDDR_XMPU0_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu0Cfg Base Address
+ */
+#define XDDR_XMPU0_CFG_BASEADDR      0xFD000000UL
+
+/**
+ * Register: XddrXmpu0CfgCtrl
+ */
+#define XDDR_XMPU0_CFG_CTRL    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU0_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu0CfgErrSts1
+ */
+#define XDDR_XMPU0_CFG_ERR_STS1    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU0_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgErrSts2
+ */
+#define XDDR_XMPU0_CFG_ERR_STS2    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU0_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgPoison
+ */
+#define XDDR_XMPU0_CFG_POISON    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU0_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU0_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU0_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU0_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgIsr
+ */
+#define XDDR_XMPU0_CFG_ISR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU0_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgImr
+ */
+#define XDDR_XMPU0_CFG_IMR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU0_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu0CfgIen
+ */
+#define XDDR_XMPU0_CFG_IEN    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU0_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgIds
+ */
+#define XDDR_XMPU0_CFG_IDS    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU0_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgLock
+ */
+#define XDDR_XMPU0_CFG_LOCK    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU0_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00Strt
+ */
+#define XDDR_XMPU0_CFG_R00_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU0_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00End
+ */
+#define XDDR_XMPU0_CFG_R00_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU0_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00Mstr
+ */
+#define XDDR_XMPU0_CFG_R00_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU0_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00
+ */
+#define XDDR_XMPU0_CFG_R00    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU0_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01Strt
+ */
+#define XDDR_XMPU0_CFG_R01_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU0_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01End
+ */
+#define XDDR_XMPU0_CFG_R01_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU0_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01Mstr
+ */
+#define XDDR_XMPU0_CFG_R01_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU0_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01
+ */
+#define XDDR_XMPU0_CFG_R01    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU0_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02Strt
+ */
+#define XDDR_XMPU0_CFG_R02_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU0_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02End
+ */
+#define XDDR_XMPU0_CFG_R02_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU0_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02Mstr
+ */
+#define XDDR_XMPU0_CFG_R02_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU0_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02
+ */
+#define XDDR_XMPU0_CFG_R02    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU0_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03Strt
+ */
+#define XDDR_XMPU0_CFG_R03_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU0_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03End
+ */
+#define XDDR_XMPU0_CFG_R03_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU0_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03Mstr
+ */
+#define XDDR_XMPU0_CFG_R03_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU0_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03
+ */
+#define XDDR_XMPU0_CFG_R03    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU0_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04Strt
+ */
+#define XDDR_XMPU0_CFG_R04_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU0_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04End
+ */
+#define XDDR_XMPU0_CFG_R04_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU0_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04Mstr
+ */
+#define XDDR_XMPU0_CFG_R04_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU0_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04
+ */
+#define XDDR_XMPU0_CFG_R04    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU0_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05Strt
+ */
+#define XDDR_XMPU0_CFG_R05_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU0_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05End
+ */
+#define XDDR_XMPU0_CFG_R05_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU0_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05Mstr
+ */
+#define XDDR_XMPU0_CFG_R05_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU0_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05
+ */
+#define XDDR_XMPU0_CFG_R05    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU0_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06Strt
+ */
+#define XDDR_XMPU0_CFG_R06_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU0_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06End
+ */
+#define XDDR_XMPU0_CFG_R06_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU0_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06Mstr
+ */
+#define XDDR_XMPU0_CFG_R06_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU0_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06
+ */
+#define XDDR_XMPU0_CFG_R06    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU0_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07Strt
+ */
+#define XDDR_XMPU0_CFG_R07_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU0_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07End
+ */
+#define XDDR_XMPU0_CFG_R07_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU0_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07Mstr
+ */
+#define XDDR_XMPU0_CFG_R07_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU0_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07
+ */
+#define XDDR_XMPU0_CFG_R07    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU0_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08Strt
+ */
+#define XDDR_XMPU0_CFG_R08_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU0_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08End
+ */
+#define XDDR_XMPU0_CFG_R08_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU0_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08Mstr
+ */
+#define XDDR_XMPU0_CFG_R08_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU0_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08
+ */
+#define XDDR_XMPU0_CFG_R08    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU0_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09Strt
+ */
+#define XDDR_XMPU0_CFG_R09_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU0_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09End
+ */
+#define XDDR_XMPU0_CFG_R09_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU0_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09Mstr
+ */
+#define XDDR_XMPU0_CFG_R09_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU0_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09
+ */
+#define XDDR_XMPU0_CFG_R09    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU0_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10Strt
+ */
+#define XDDR_XMPU0_CFG_R10_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU0_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10End
+ */
+#define XDDR_XMPU0_CFG_R10_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU0_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10Mstr
+ */
+#define XDDR_XMPU0_CFG_R10_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU0_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10
+ */
+#define XDDR_XMPU0_CFG_R10    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU0_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11Strt
+ */
+#define XDDR_XMPU0_CFG_R11_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU0_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11End
+ */
+#define XDDR_XMPU0_CFG_R11_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU0_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11Mstr
+ */
+#define XDDR_XMPU0_CFG_R11_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU0_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11
+ */
+#define XDDR_XMPU0_CFG_R11    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU0_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12Strt
+ */
+#define XDDR_XMPU0_CFG_R12_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU0_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12End
+ */
+#define XDDR_XMPU0_CFG_R12_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU0_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12Mstr
+ */
+#define XDDR_XMPU0_CFG_R12_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU0_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12
+ */
+#define XDDR_XMPU0_CFG_R12    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU0_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13Strt
+ */
+#define XDDR_XMPU0_CFG_R13_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU0_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13End
+ */
+#define XDDR_XMPU0_CFG_R13_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU0_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13Mstr
+ */
+#define XDDR_XMPU0_CFG_R13_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU0_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13
+ */
+#define XDDR_XMPU0_CFG_R13    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU0_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14Strt
+ */
+#define XDDR_XMPU0_CFG_R14_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU0_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14End
+ */
+#define XDDR_XMPU0_CFG_R14_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU0_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14Mstr
+ */
+#define XDDR_XMPU0_CFG_R14_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU0_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14
+ */
+#define XDDR_XMPU0_CFG_R14    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU0_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15Strt
+ */
+#define XDDR_XMPU0_CFG_R15_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU0_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15End
+ */
+#define XDDR_XMPU0_CFG_R15_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU0_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15Mstr
+ */
+#define XDDR_XMPU0_CFG_R15_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU0_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15
+ */
+#define XDDR_XMPU0_CFG_R15    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU0_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU0_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu1_cfg.h
new file mode 100644
index 000000000..e2fa6d4aa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu1_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU1_CFG_H__
+#define __XDDR_XMPU1_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu1Cfg Base Address
+ */
+#define XDDR_XMPU1_CFG_BASEADDR      0xFD010000UL
+
+/**
+ * Register: XddrXmpu1CfgCtrl
+ */
+#define XDDR_XMPU1_CFG_CTRL    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU1_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu1CfgErrSts1
+ */
+#define XDDR_XMPU1_CFG_ERR_STS1    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU1_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgErrSts2
+ */
+#define XDDR_XMPU1_CFG_ERR_STS2    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU1_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgPoison
+ */
+#define XDDR_XMPU1_CFG_POISON    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU1_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU1_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU1_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU1_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgIsr
+ */
+#define XDDR_XMPU1_CFG_ISR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU1_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgImr
+ */
+#define XDDR_XMPU1_CFG_IMR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU1_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu1CfgIen
+ */
+#define XDDR_XMPU1_CFG_IEN    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU1_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgIds
+ */
+#define XDDR_XMPU1_CFG_IDS    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU1_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgLock
+ */
+#define XDDR_XMPU1_CFG_LOCK    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU1_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00Strt
+ */
+#define XDDR_XMPU1_CFG_R00_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU1_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00End
+ */
+#define XDDR_XMPU1_CFG_R00_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU1_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00Mstr
+ */
+#define XDDR_XMPU1_CFG_R00_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU1_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00
+ */
+#define XDDR_XMPU1_CFG_R00    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU1_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01Strt
+ */
+#define XDDR_XMPU1_CFG_R01_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU1_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01End
+ */
+#define XDDR_XMPU1_CFG_R01_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU1_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01Mstr
+ */
+#define XDDR_XMPU1_CFG_R01_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU1_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01
+ */
+#define XDDR_XMPU1_CFG_R01    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU1_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02Strt
+ */
+#define XDDR_XMPU1_CFG_R02_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU1_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02End
+ */
+#define XDDR_XMPU1_CFG_R02_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU1_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02Mstr
+ */
+#define XDDR_XMPU1_CFG_R02_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU1_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02
+ */
+#define XDDR_XMPU1_CFG_R02    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU1_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03Strt
+ */
+#define XDDR_XMPU1_CFG_R03_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU1_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03End
+ */
+#define XDDR_XMPU1_CFG_R03_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU1_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03Mstr
+ */
+#define XDDR_XMPU1_CFG_R03_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU1_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03
+ */
+#define XDDR_XMPU1_CFG_R03    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU1_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04Strt
+ */
+#define XDDR_XMPU1_CFG_R04_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU1_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04End
+ */
+#define XDDR_XMPU1_CFG_R04_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU1_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04Mstr
+ */
+#define XDDR_XMPU1_CFG_R04_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU1_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04
+ */
+#define XDDR_XMPU1_CFG_R04    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU1_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05Strt
+ */
+#define XDDR_XMPU1_CFG_R05_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU1_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05End
+ */
+#define XDDR_XMPU1_CFG_R05_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU1_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05Mstr
+ */
+#define XDDR_XMPU1_CFG_R05_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU1_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05
+ */
+#define XDDR_XMPU1_CFG_R05    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU1_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06Strt
+ */
+#define XDDR_XMPU1_CFG_R06_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU1_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06End
+ */
+#define XDDR_XMPU1_CFG_R06_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU1_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06Mstr
+ */
+#define XDDR_XMPU1_CFG_R06_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU1_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06
+ */
+#define XDDR_XMPU1_CFG_R06    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU1_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07Strt
+ */
+#define XDDR_XMPU1_CFG_R07_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU1_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07End
+ */
+#define XDDR_XMPU1_CFG_R07_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU1_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07Mstr
+ */
+#define XDDR_XMPU1_CFG_R07_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU1_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07
+ */
+#define XDDR_XMPU1_CFG_R07    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU1_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08Strt
+ */
+#define XDDR_XMPU1_CFG_R08_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU1_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08End
+ */
+#define XDDR_XMPU1_CFG_R08_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU1_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08Mstr
+ */
+#define XDDR_XMPU1_CFG_R08_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU1_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08
+ */
+#define XDDR_XMPU1_CFG_R08    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU1_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09Strt
+ */
+#define XDDR_XMPU1_CFG_R09_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU1_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09End
+ */
+#define XDDR_XMPU1_CFG_R09_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU1_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09Mstr
+ */
+#define XDDR_XMPU1_CFG_R09_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU1_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09
+ */
+#define XDDR_XMPU1_CFG_R09    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU1_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10Strt
+ */
+#define XDDR_XMPU1_CFG_R10_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU1_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10End
+ */
+#define XDDR_XMPU1_CFG_R10_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU1_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10Mstr
+ */
+#define XDDR_XMPU1_CFG_R10_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU1_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10
+ */
+#define XDDR_XMPU1_CFG_R10    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU1_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11Strt
+ */
+#define XDDR_XMPU1_CFG_R11_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU1_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11End
+ */
+#define XDDR_XMPU1_CFG_R11_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU1_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11Mstr
+ */
+#define XDDR_XMPU1_CFG_R11_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU1_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11
+ */
+#define XDDR_XMPU1_CFG_R11    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU1_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12Strt
+ */
+#define XDDR_XMPU1_CFG_R12_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU1_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12End
+ */
+#define XDDR_XMPU1_CFG_R12_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU1_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12Mstr
+ */
+#define XDDR_XMPU1_CFG_R12_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU1_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12
+ */
+#define XDDR_XMPU1_CFG_R12    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU1_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13Strt
+ */
+#define XDDR_XMPU1_CFG_R13_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU1_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13End
+ */
+#define XDDR_XMPU1_CFG_R13_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU1_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13Mstr
+ */
+#define XDDR_XMPU1_CFG_R13_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU1_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13
+ */
+#define XDDR_XMPU1_CFG_R13    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU1_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14Strt
+ */
+#define XDDR_XMPU1_CFG_R14_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU1_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14End
+ */
+#define XDDR_XMPU1_CFG_R14_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU1_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14Mstr
+ */
+#define XDDR_XMPU1_CFG_R14_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU1_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14
+ */
+#define XDDR_XMPU1_CFG_R14    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU1_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15Strt
+ */
+#define XDDR_XMPU1_CFG_R15_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU1_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15End
+ */
+#define XDDR_XMPU1_CFG_R15_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU1_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15Mstr
+ */
+#define XDDR_XMPU1_CFG_R15_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU1_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15
+ */
+#define XDDR_XMPU1_CFG_R15    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU1_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU1_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu2_cfg.h
new file mode 100644
index 000000000..55ea2a7d3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu2_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU2_CFG_H__
+#define __XDDR_XMPU2_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu2Cfg Base Address
+ */
+#define XDDR_XMPU2_CFG_BASEADDR      0xFD020000UL
+
+/**
+ * Register: XddrXmpu2CfgCtrl
+ */
+#define XDDR_XMPU2_CFG_CTRL    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU2_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu2CfgErrSts1
+ */
+#define XDDR_XMPU2_CFG_ERR_STS1    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU2_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgErrSts2
+ */
+#define XDDR_XMPU2_CFG_ERR_STS2    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU2_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgPoison
+ */
+#define XDDR_XMPU2_CFG_POISON    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU2_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU2_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU2_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU2_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgIsr
+ */
+#define XDDR_XMPU2_CFG_ISR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU2_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgImr
+ */
+#define XDDR_XMPU2_CFG_IMR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU2_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu2CfgIen
+ */
+#define XDDR_XMPU2_CFG_IEN    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU2_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgIds
+ */
+#define XDDR_XMPU2_CFG_IDS    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU2_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgLock
+ */
+#define XDDR_XMPU2_CFG_LOCK    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU2_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00Strt
+ */
+#define XDDR_XMPU2_CFG_R00_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU2_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00End
+ */
+#define XDDR_XMPU2_CFG_R00_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU2_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00Mstr
+ */
+#define XDDR_XMPU2_CFG_R00_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU2_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00
+ */
+#define XDDR_XMPU2_CFG_R00    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU2_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01Strt
+ */
+#define XDDR_XMPU2_CFG_R01_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU2_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01End
+ */
+#define XDDR_XMPU2_CFG_R01_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU2_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01Mstr
+ */
+#define XDDR_XMPU2_CFG_R01_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU2_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01
+ */
+#define XDDR_XMPU2_CFG_R01    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU2_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02Strt
+ */
+#define XDDR_XMPU2_CFG_R02_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU2_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02End
+ */
+#define XDDR_XMPU2_CFG_R02_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU2_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02Mstr
+ */
+#define XDDR_XMPU2_CFG_R02_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU2_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02
+ */
+#define XDDR_XMPU2_CFG_R02    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU2_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03Strt
+ */
+#define XDDR_XMPU2_CFG_R03_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU2_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03End
+ */
+#define XDDR_XMPU2_CFG_R03_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU2_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03Mstr
+ */
+#define XDDR_XMPU2_CFG_R03_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU2_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03
+ */
+#define XDDR_XMPU2_CFG_R03    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU2_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04Strt
+ */
+#define XDDR_XMPU2_CFG_R04_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU2_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04End
+ */
+#define XDDR_XMPU2_CFG_R04_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU2_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04Mstr
+ */
+#define XDDR_XMPU2_CFG_R04_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU2_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04
+ */
+#define XDDR_XMPU2_CFG_R04    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU2_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05Strt
+ */
+#define XDDR_XMPU2_CFG_R05_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU2_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05End
+ */
+#define XDDR_XMPU2_CFG_R05_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU2_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05Mstr
+ */
+#define XDDR_XMPU2_CFG_R05_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU2_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05
+ */
+#define XDDR_XMPU2_CFG_R05    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU2_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06Strt
+ */
+#define XDDR_XMPU2_CFG_R06_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU2_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06End
+ */
+#define XDDR_XMPU2_CFG_R06_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU2_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06Mstr
+ */
+#define XDDR_XMPU2_CFG_R06_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU2_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06
+ */
+#define XDDR_XMPU2_CFG_R06    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU2_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07Strt
+ */
+#define XDDR_XMPU2_CFG_R07_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU2_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07End
+ */
+#define XDDR_XMPU2_CFG_R07_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU2_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07Mstr
+ */
+#define XDDR_XMPU2_CFG_R07_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU2_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07
+ */
+#define XDDR_XMPU2_CFG_R07    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU2_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08Strt
+ */
+#define XDDR_XMPU2_CFG_R08_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU2_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08End
+ */
+#define XDDR_XMPU2_CFG_R08_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU2_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08Mstr
+ */
+#define XDDR_XMPU2_CFG_R08_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU2_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08
+ */
+#define XDDR_XMPU2_CFG_R08    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU2_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09Strt
+ */
+#define XDDR_XMPU2_CFG_R09_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU2_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09End
+ */
+#define XDDR_XMPU2_CFG_R09_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU2_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09Mstr
+ */
+#define XDDR_XMPU2_CFG_R09_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU2_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09
+ */
+#define XDDR_XMPU2_CFG_R09    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU2_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10Strt
+ */
+#define XDDR_XMPU2_CFG_R10_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU2_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10End
+ */
+#define XDDR_XMPU2_CFG_R10_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU2_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10Mstr
+ */
+#define XDDR_XMPU2_CFG_R10_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU2_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10
+ */
+#define XDDR_XMPU2_CFG_R10    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU2_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11Strt
+ */
+#define XDDR_XMPU2_CFG_R11_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU2_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11End
+ */
+#define XDDR_XMPU2_CFG_R11_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU2_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11Mstr
+ */
+#define XDDR_XMPU2_CFG_R11_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU2_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11
+ */
+#define XDDR_XMPU2_CFG_R11    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU2_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12Strt
+ */
+#define XDDR_XMPU2_CFG_R12_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU2_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12End
+ */
+#define XDDR_XMPU2_CFG_R12_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU2_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12Mstr
+ */
+#define XDDR_XMPU2_CFG_R12_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU2_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12
+ */
+#define XDDR_XMPU2_CFG_R12    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU2_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13Strt
+ */
+#define XDDR_XMPU2_CFG_R13_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU2_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13End
+ */
+#define XDDR_XMPU2_CFG_R13_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU2_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13Mstr
+ */
+#define XDDR_XMPU2_CFG_R13_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU2_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13
+ */
+#define XDDR_XMPU2_CFG_R13    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU2_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14Strt
+ */
+#define XDDR_XMPU2_CFG_R14_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU2_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14End
+ */
+#define XDDR_XMPU2_CFG_R14_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU2_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14Mstr
+ */
+#define XDDR_XMPU2_CFG_R14_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU2_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14
+ */
+#define XDDR_XMPU2_CFG_R14    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU2_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15Strt
+ */
+#define XDDR_XMPU2_CFG_R15_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU2_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15End
+ */
+#define XDDR_XMPU2_CFG_R15_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU2_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15Mstr
+ */
+#define XDDR_XMPU2_CFG_R15_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU2_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15
+ */
+#define XDDR_XMPU2_CFG_R15    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU2_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU2_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu3_cfg.h
new file mode 100644
index 000000000..416314967
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu3_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU3_CFG_H__
+#define __XDDR_XMPU3_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu3Cfg Base Address
+ */
+#define XDDR_XMPU3_CFG_BASEADDR      0xFD030000UL
+
+/**
+ * Register: XddrXmpu3CfgCtrl
+ */
+#define XDDR_XMPU3_CFG_CTRL    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU3_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu3CfgErrSts1
+ */
+#define XDDR_XMPU3_CFG_ERR_STS1    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU3_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgErrSts2
+ */
+#define XDDR_XMPU3_CFG_ERR_STS2    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU3_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgPoison
+ */
+#define XDDR_XMPU3_CFG_POISON    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU3_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU3_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU3_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU3_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgIsr
+ */
+#define XDDR_XMPU3_CFG_ISR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU3_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgImr
+ */
+#define XDDR_XMPU3_CFG_IMR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU3_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu3CfgIen
+ */
+#define XDDR_XMPU3_CFG_IEN    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU3_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgIds
+ */
+#define XDDR_XMPU3_CFG_IDS    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU3_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgLock
+ */
+#define XDDR_XMPU3_CFG_LOCK    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU3_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00Strt
+ */
+#define XDDR_XMPU3_CFG_R00_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU3_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00End
+ */
+#define XDDR_XMPU3_CFG_R00_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU3_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00Mstr
+ */
+#define XDDR_XMPU3_CFG_R00_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU3_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00
+ */
+#define XDDR_XMPU3_CFG_R00    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU3_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01Strt
+ */
+#define XDDR_XMPU3_CFG_R01_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU3_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01End
+ */
+#define XDDR_XMPU3_CFG_R01_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU3_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01Mstr
+ */
+#define XDDR_XMPU3_CFG_R01_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU3_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01
+ */
+#define XDDR_XMPU3_CFG_R01    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU3_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02Strt
+ */
+#define XDDR_XMPU3_CFG_R02_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU3_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02End
+ */
+#define XDDR_XMPU3_CFG_R02_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU3_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02Mstr
+ */
+#define XDDR_XMPU3_CFG_R02_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU3_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02
+ */
+#define XDDR_XMPU3_CFG_R02    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU3_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03Strt
+ */
+#define XDDR_XMPU3_CFG_R03_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU3_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03End
+ */
+#define XDDR_XMPU3_CFG_R03_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU3_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03Mstr
+ */
+#define XDDR_XMPU3_CFG_R03_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU3_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03
+ */
+#define XDDR_XMPU3_CFG_R03    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU3_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04Strt
+ */
+#define XDDR_XMPU3_CFG_R04_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU3_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04End
+ */
+#define XDDR_XMPU3_CFG_R04_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU3_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04Mstr
+ */
+#define XDDR_XMPU3_CFG_R04_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU3_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04
+ */
+#define XDDR_XMPU3_CFG_R04    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU3_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05Strt
+ */
+#define XDDR_XMPU3_CFG_R05_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU3_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05End
+ */
+#define XDDR_XMPU3_CFG_R05_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU3_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05Mstr
+ */
+#define XDDR_XMPU3_CFG_R05_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU3_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05
+ */
+#define XDDR_XMPU3_CFG_R05    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU3_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06Strt
+ */
+#define XDDR_XMPU3_CFG_R06_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU3_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06End
+ */
+#define XDDR_XMPU3_CFG_R06_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU3_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06Mstr
+ */
+#define XDDR_XMPU3_CFG_R06_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU3_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06
+ */
+#define XDDR_XMPU3_CFG_R06    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU3_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07Strt
+ */
+#define XDDR_XMPU3_CFG_R07_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU3_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07End
+ */
+#define XDDR_XMPU3_CFG_R07_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU3_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07Mstr
+ */
+#define XDDR_XMPU3_CFG_R07_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU3_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07
+ */
+#define XDDR_XMPU3_CFG_R07    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU3_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08Strt
+ */
+#define XDDR_XMPU3_CFG_R08_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU3_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08End
+ */
+#define XDDR_XMPU3_CFG_R08_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU3_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08Mstr
+ */
+#define XDDR_XMPU3_CFG_R08_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU3_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08
+ */
+#define XDDR_XMPU3_CFG_R08    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU3_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09Strt
+ */
+#define XDDR_XMPU3_CFG_R09_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU3_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09End
+ */
+#define XDDR_XMPU3_CFG_R09_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU3_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09Mstr
+ */
+#define XDDR_XMPU3_CFG_R09_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU3_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09
+ */
+#define XDDR_XMPU3_CFG_R09    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU3_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10Strt
+ */
+#define XDDR_XMPU3_CFG_R10_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU3_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10End
+ */
+#define XDDR_XMPU3_CFG_R10_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU3_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10Mstr
+ */
+#define XDDR_XMPU3_CFG_R10_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU3_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10
+ */
+#define XDDR_XMPU3_CFG_R10    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU3_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11Strt
+ */
+#define XDDR_XMPU3_CFG_R11_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU3_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11End
+ */
+#define XDDR_XMPU3_CFG_R11_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU3_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11Mstr
+ */
+#define XDDR_XMPU3_CFG_R11_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU3_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11
+ */
+#define XDDR_XMPU3_CFG_R11    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU3_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12Strt
+ */
+#define XDDR_XMPU3_CFG_R12_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU3_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12End
+ */
+#define XDDR_XMPU3_CFG_R12_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU3_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12Mstr
+ */
+#define XDDR_XMPU3_CFG_R12_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU3_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12
+ */
+#define XDDR_XMPU3_CFG_R12    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU3_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13Strt
+ */
+#define XDDR_XMPU3_CFG_R13_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU3_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13End
+ */
+#define XDDR_XMPU3_CFG_R13_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU3_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13Mstr
+ */
+#define XDDR_XMPU3_CFG_R13_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU3_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13
+ */
+#define XDDR_XMPU3_CFG_R13    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU3_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14Strt
+ */
+#define XDDR_XMPU3_CFG_R14_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU3_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14End
+ */
+#define XDDR_XMPU3_CFG_R14_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU3_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14Mstr
+ */
+#define XDDR_XMPU3_CFG_R14_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU3_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14
+ */
+#define XDDR_XMPU3_CFG_R14    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU3_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15Strt
+ */
+#define XDDR_XMPU3_CFG_R15_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU3_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15End
+ */
+#define XDDR_XMPU3_CFG_R15_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU3_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15Mstr
+ */
+#define XDDR_XMPU3_CFG_R15_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU3_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15
+ */
+#define XDDR_XMPU3_CFG_R15    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU3_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU3_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu4_cfg.h
new file mode 100644
index 000000000..2df814419
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu4_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU4_CFG_H__
+#define __XDDR_XMPU4_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu4Cfg Base Address
+ */
+#define XDDR_XMPU4_CFG_BASEADDR      0xFD040000UL
+
+/**
+ * Register: XddrXmpu4CfgCtrl
+ */
+#define XDDR_XMPU4_CFG_CTRL    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU4_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu4CfgErrSts1
+ */
+#define XDDR_XMPU4_CFG_ERR_STS1    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU4_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgErrSts2
+ */
+#define XDDR_XMPU4_CFG_ERR_STS2    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU4_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgPoison
+ */
+#define XDDR_XMPU4_CFG_POISON    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU4_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU4_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU4_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU4_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgIsr
+ */
+#define XDDR_XMPU4_CFG_ISR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU4_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgImr
+ */
+#define XDDR_XMPU4_CFG_IMR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU4_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu4CfgIen
+ */
+#define XDDR_XMPU4_CFG_IEN    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU4_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgIds
+ */
+#define XDDR_XMPU4_CFG_IDS    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU4_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgLock
+ */
+#define XDDR_XMPU4_CFG_LOCK    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU4_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00Strt
+ */
+#define XDDR_XMPU4_CFG_R00_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU4_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00End
+ */
+#define XDDR_XMPU4_CFG_R00_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU4_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00Mstr
+ */
+#define XDDR_XMPU4_CFG_R00_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU4_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00
+ */
+#define XDDR_XMPU4_CFG_R00    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU4_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01Strt
+ */
+#define XDDR_XMPU4_CFG_R01_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU4_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01End
+ */
+#define XDDR_XMPU4_CFG_R01_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU4_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01Mstr
+ */
+#define XDDR_XMPU4_CFG_R01_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU4_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01
+ */
+#define XDDR_XMPU4_CFG_R01    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU4_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02Strt
+ */
+#define XDDR_XMPU4_CFG_R02_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU4_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02End
+ */
+#define XDDR_XMPU4_CFG_R02_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU4_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02Mstr
+ */
+#define XDDR_XMPU4_CFG_R02_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU4_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02
+ */
+#define XDDR_XMPU4_CFG_R02    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU4_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03Strt
+ */
+#define XDDR_XMPU4_CFG_R03_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU4_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03End
+ */
+#define XDDR_XMPU4_CFG_R03_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU4_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03Mstr
+ */
+#define XDDR_XMPU4_CFG_R03_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU4_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03
+ */
+#define XDDR_XMPU4_CFG_R03    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU4_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04Strt
+ */
+#define XDDR_XMPU4_CFG_R04_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU4_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04End
+ */
+#define XDDR_XMPU4_CFG_R04_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU4_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04Mstr
+ */
+#define XDDR_XMPU4_CFG_R04_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU4_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04
+ */
+#define XDDR_XMPU4_CFG_R04    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU4_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05Strt
+ */
+#define XDDR_XMPU4_CFG_R05_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU4_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05End
+ */
+#define XDDR_XMPU4_CFG_R05_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU4_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05Mstr
+ */
+#define XDDR_XMPU4_CFG_R05_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU4_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05
+ */
+#define XDDR_XMPU4_CFG_R05    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU4_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06Strt
+ */
+#define XDDR_XMPU4_CFG_R06_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU4_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06End
+ */
+#define XDDR_XMPU4_CFG_R06_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU4_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06Mstr
+ */
+#define XDDR_XMPU4_CFG_R06_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU4_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06
+ */
+#define XDDR_XMPU4_CFG_R06    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU4_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07Strt
+ */
+#define XDDR_XMPU4_CFG_R07_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU4_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07End
+ */
+#define XDDR_XMPU4_CFG_R07_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU4_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07Mstr
+ */
+#define XDDR_XMPU4_CFG_R07_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU4_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07
+ */
+#define XDDR_XMPU4_CFG_R07    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU4_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08Strt
+ */
+#define XDDR_XMPU4_CFG_R08_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU4_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08End
+ */
+#define XDDR_XMPU4_CFG_R08_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU4_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08Mstr
+ */
+#define XDDR_XMPU4_CFG_R08_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU4_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08
+ */
+#define XDDR_XMPU4_CFG_R08    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU4_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09Strt
+ */
+#define XDDR_XMPU4_CFG_R09_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU4_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09End
+ */
+#define XDDR_XMPU4_CFG_R09_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU4_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09Mstr
+ */
+#define XDDR_XMPU4_CFG_R09_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU4_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09
+ */
+#define XDDR_XMPU4_CFG_R09    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU4_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10Strt
+ */
+#define XDDR_XMPU4_CFG_R10_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU4_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10End
+ */
+#define XDDR_XMPU4_CFG_R10_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU4_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10Mstr
+ */
+#define XDDR_XMPU4_CFG_R10_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU4_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10
+ */
+#define XDDR_XMPU4_CFG_R10    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU4_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11Strt
+ */
+#define XDDR_XMPU4_CFG_R11_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU4_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11End
+ */
+#define XDDR_XMPU4_CFG_R11_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU4_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11Mstr
+ */
+#define XDDR_XMPU4_CFG_R11_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU4_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11
+ */
+#define XDDR_XMPU4_CFG_R11    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU4_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12Strt
+ */
+#define XDDR_XMPU4_CFG_R12_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU4_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12End
+ */
+#define XDDR_XMPU4_CFG_R12_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU4_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12Mstr
+ */
+#define XDDR_XMPU4_CFG_R12_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU4_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12
+ */
+#define XDDR_XMPU4_CFG_R12    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU4_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13Strt
+ */
+#define XDDR_XMPU4_CFG_R13_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU4_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13End
+ */
+#define XDDR_XMPU4_CFG_R13_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU4_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13Mstr
+ */
+#define XDDR_XMPU4_CFG_R13_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU4_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13
+ */
+#define XDDR_XMPU4_CFG_R13    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU4_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14Strt
+ */
+#define XDDR_XMPU4_CFG_R14_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU4_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14End
+ */
+#define XDDR_XMPU4_CFG_R14_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU4_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14Mstr
+ */
+#define XDDR_XMPU4_CFG_R14_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU4_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14
+ */
+#define XDDR_XMPU4_CFG_R14    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU4_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15Strt
+ */
+#define XDDR_XMPU4_CFG_R15_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU4_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15End
+ */
+#define XDDR_XMPU4_CFG_R15_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU4_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15Mstr
+ */
+#define XDDR_XMPU4_CFG_R15_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU4_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15
+ */
+#define XDDR_XMPU4_CFG_R15    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU4_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU4_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu5_cfg.h
new file mode 100644
index 000000000..60811718d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xddr_xmpu5_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU5_CFG_H__
+#define __XDDR_XMPU5_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu5Cfg Base Address
+ */
+#define XDDR_XMPU5_CFG_BASEADDR      0xFD050000UL
+
+/**
+ * Register: XddrXmpu5CfgCtrl
+ */
+#define XDDR_XMPU5_CFG_CTRL    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU5_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu5CfgErrSts1
+ */
+#define XDDR_XMPU5_CFG_ERR_STS1    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU5_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgErrSts2
+ */
+#define XDDR_XMPU5_CFG_ERR_STS2    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU5_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgPoison
+ */
+#define XDDR_XMPU5_CFG_POISON    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU5_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU5_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU5_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU5_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgIsr
+ */
+#define XDDR_XMPU5_CFG_ISR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU5_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgImr
+ */
+#define XDDR_XMPU5_CFG_IMR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU5_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu5CfgIen
+ */
+#define XDDR_XMPU5_CFG_IEN    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU5_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgIds
+ */
+#define XDDR_XMPU5_CFG_IDS    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU5_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgLock
+ */
+#define XDDR_XMPU5_CFG_LOCK    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU5_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00Strt
+ */
+#define XDDR_XMPU5_CFG_R00_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU5_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00End
+ */
+#define XDDR_XMPU5_CFG_R00_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU5_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00Mstr
+ */
+#define XDDR_XMPU5_CFG_R00_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU5_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00
+ */
+#define XDDR_XMPU5_CFG_R00    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU5_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01Strt
+ */
+#define XDDR_XMPU5_CFG_R01_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU5_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01End
+ */
+#define XDDR_XMPU5_CFG_R01_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU5_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01Mstr
+ */
+#define XDDR_XMPU5_CFG_R01_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU5_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01
+ */
+#define XDDR_XMPU5_CFG_R01    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU5_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02Strt
+ */
+#define XDDR_XMPU5_CFG_R02_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU5_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02End
+ */
+#define XDDR_XMPU5_CFG_R02_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU5_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02Mstr
+ */
+#define XDDR_XMPU5_CFG_R02_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU5_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02
+ */
+#define XDDR_XMPU5_CFG_R02    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU5_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03Strt
+ */
+#define XDDR_XMPU5_CFG_R03_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU5_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03End
+ */
+#define XDDR_XMPU5_CFG_R03_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU5_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03Mstr
+ */
+#define XDDR_XMPU5_CFG_R03_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU5_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03
+ */
+#define XDDR_XMPU5_CFG_R03    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU5_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04Strt
+ */
+#define XDDR_XMPU5_CFG_R04_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU5_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04End
+ */
+#define XDDR_XMPU5_CFG_R04_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU5_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04Mstr
+ */
+#define XDDR_XMPU5_CFG_R04_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU5_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04
+ */
+#define XDDR_XMPU5_CFG_R04    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU5_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05Strt
+ */
+#define XDDR_XMPU5_CFG_R05_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU5_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05End
+ */
+#define XDDR_XMPU5_CFG_R05_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU5_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05Mstr
+ */
+#define XDDR_XMPU5_CFG_R05_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU5_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05
+ */
+#define XDDR_XMPU5_CFG_R05    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU5_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06Strt
+ */
+#define XDDR_XMPU5_CFG_R06_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU5_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06End
+ */
+#define XDDR_XMPU5_CFG_R06_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU5_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06Mstr
+ */
+#define XDDR_XMPU5_CFG_R06_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU5_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06
+ */
+#define XDDR_XMPU5_CFG_R06    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU5_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07Strt
+ */
+#define XDDR_XMPU5_CFG_R07_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU5_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07End
+ */
+#define XDDR_XMPU5_CFG_R07_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU5_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07Mstr
+ */
+#define XDDR_XMPU5_CFG_R07_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU5_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07
+ */
+#define XDDR_XMPU5_CFG_R07    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU5_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08Strt
+ */
+#define XDDR_XMPU5_CFG_R08_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU5_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08End
+ */
+#define XDDR_XMPU5_CFG_R08_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU5_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08Mstr
+ */
+#define XDDR_XMPU5_CFG_R08_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU5_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08
+ */
+#define XDDR_XMPU5_CFG_R08    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU5_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09Strt
+ */
+#define XDDR_XMPU5_CFG_R09_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU5_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09End
+ */
+#define XDDR_XMPU5_CFG_R09_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU5_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09Mstr
+ */
+#define XDDR_XMPU5_CFG_R09_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU5_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09
+ */
+#define XDDR_XMPU5_CFG_R09    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU5_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10Strt
+ */
+#define XDDR_XMPU5_CFG_R10_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU5_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10End
+ */
+#define XDDR_XMPU5_CFG_R10_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU5_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10Mstr
+ */
+#define XDDR_XMPU5_CFG_R10_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU5_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10
+ */
+#define XDDR_XMPU5_CFG_R10    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU5_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11Strt
+ */
+#define XDDR_XMPU5_CFG_R11_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU5_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11End
+ */
+#define XDDR_XMPU5_CFG_R11_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU5_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11Mstr
+ */
+#define XDDR_XMPU5_CFG_R11_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU5_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11
+ */
+#define XDDR_XMPU5_CFG_R11    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU5_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12Strt
+ */
+#define XDDR_XMPU5_CFG_R12_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU5_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12End
+ */
+#define XDDR_XMPU5_CFG_R12_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU5_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12Mstr
+ */
+#define XDDR_XMPU5_CFG_R12_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU5_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12
+ */
+#define XDDR_XMPU5_CFG_R12    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU5_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13Strt
+ */
+#define XDDR_XMPU5_CFG_R13_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU5_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13End
+ */
+#define XDDR_XMPU5_CFG_R13_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU5_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13Mstr
+ */
+#define XDDR_XMPU5_CFG_R13_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU5_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13
+ */
+#define XDDR_XMPU5_CFG_R13    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU5_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14Strt
+ */
+#define XDDR_XMPU5_CFG_R14_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU5_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14End
+ */
+#define XDDR_XMPU5_CFG_R14_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU5_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14Mstr
+ */
+#define XDDR_XMPU5_CFG_R14_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU5_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14
+ */
+#define XDDR_XMPU5_CFG_R14    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU5_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15Strt
+ */
+#define XDDR_XMPU5_CFG_R15_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU5_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15End
+ */
+#define XDDR_XMPU5_CFG_R15_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU5_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15Mstr
+ */
+#define XDDR_XMPU5_CFG_R15_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU5_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15
+ */
+#define XDDR_XMPU5_CFG_R15    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU5_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU5_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xdebug.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xdebug.h
new file mode 100644
index 000000000..650946bd0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG  /* prevent circular inclusions */
+#define XDEBUG  /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x)  x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xenv.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xenv.h
new file mode 100644
index 000000000..c2f76ee26
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xenv.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xenv_standalone.h
new file mode 100644
index 000000000..edab9db71
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xenv_standalone.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* 

+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include 
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * 


+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_slcr.h
new file mode 100644
index 000000000..b565b958a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_slcr.h
@@ -0,0 +1,382 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_H__
+#define __XFPD_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcr Base Address
+ */
+#define XFPD_SLCR_BASEADDR      0xFD610000UL
+
+/**
+ * Register: XfpdSlcrWprot0
+ */
+#define XFPD_SLCR_WPROT0    ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
+#define XFPD_SLCR_WPROT0_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_WPROT0_ACT_SHIFT   0UL
+#define XFPD_SLCR_WPROT0_ACT_WIDTH   1UL
+#define XFPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
+#define XFPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrCtrl
+ */
+#define XFPD_SLCR_CTRL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIsr
+ */
+#define XFPD_SLCR_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrImr
+ */
+#define XFPD_SLCR_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrIer
+ */
+#define XFPD_SLCR_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIdr
+ */
+#define XFPD_SLCR_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrItr
+ */
+#define XFPD_SLCR_ITR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrWdtClkSel
+ */
+#define XFPD_SLCR_WDT_CLK_SEL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
+#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_WDT_CLK_SEL_SHIFT   0UL
+#define XFPD_SLCR_WDT_CLK_SEL_WIDTH   1UL
+#define XFPD_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIntFpd
+ */
+#define XFPD_SLCR_INT_FPD    ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
+#define XFPD_SLCR_INT_FPD_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT   0UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH   1UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrGpu
+ */
+#define XFPD_SLCR_GPU    ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
+#define XFPD_SLCR_GPU_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_GPU_ARCACHE_SHIFT   7UL
+#define XFPD_SLCR_GPU_ARCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_ARCACHE_MASK    0x00000780UL
+#define XFPD_SLCR_GPU_ARCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_AWCACHE_SHIFT   3UL
+#define XFPD_SLCR_GPU_AWCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_AWCACHE_MASK    0x00000078UL
+#define XFPD_SLCR_GPU_AWCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT   2UL
+#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP1_IDLE_MASK    0x00000004UL
+#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_MASK    0x00000002UL
+#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_IDLE_SHIFT   0UL
+#define XFPD_SLCR_GPU_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_IDLE_MASK    0x00000001UL
+#define XFPD_SLCR_GPU_IDLE_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrGdmaCfg
+ */
+#define XFPD_SLCR_GDMA_CFG    ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
+#define XFPD_SLCR_GDMA_CFG_RSTVAL   0x00000048UL
+
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT   5UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH   2UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK    0x00000060UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL  0x2UL
+
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT   0UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH   5UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK    0x0000001fUL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL  0x8UL
+
+/**
+ * Register: XfpdSlcrGdma
+ */
+#define XFPD_SLCR_GDMA    ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
+#define XFPD_SLCR_GDMA_RSTVAL   0x00003b3bUL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT   12UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK    0x00007000UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT   11UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK    0x00000800UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT   8UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK    0x00000700UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT   4UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK    0x00000070UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK    0x00000008UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT   0UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK    0x00000007UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL  0x3UL
+
+/**
+ * Register: XfpdSlcrAfiFs
+ */
+#define XFPD_SLCR_AFI_FS    ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
+#define XFPD_SLCR_AFI_FS_RSTVAL   0x00000a00UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT   10UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK    0x00000c00UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL  0x2UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT   8UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK    0x00000300UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL  0x2UL
+
+/**
+ * Register: XfpdSlcrErrAtbIsr
+ */
+#define XFPD_SLCR_ERR_ATB_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
+#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbImr
+ */
+#define XFPD_SLCR_ERR_ATB_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
+#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrErrAtbIer
+ */
+#define XFPD_SLCR_ERR_ATB_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
+#define XFPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbIdr
+ */
+#define XFPD_SLCR_ERR_ATB_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
+#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbCmdstore
+ */
+#define XFPD_SLCR_ATB_CMDSTORE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
+#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbRespEn
+ */
+#define XFPD_SLCR_ATB_RESP_EN    ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
+#define XFPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbResptype
+ */
+#define XFPD_SLCR_ATB_RESPTYPE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
+#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbPrescale
+ */
+#define XFPD_SLCR_ATB_PRESCALE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
+#define XFPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
+
+#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_slcr_secure.h
new file mode 100644
index 000000000..6541a4f1d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_slcr_secure.h
@@ -0,0 +1,277 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_SECURE_H__
+#define __XFPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcrSecure Base Address
+ */
+#define XFPD_SLCR_SECURE_BASEADDR      0xFD690000UL
+
+/**
+ * Register: XfpdSlcrSecCtrl
+ */
+#define XFPD_SLCR_SEC_CTRL    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIsr
+ */
+#define XFPD_SLCR_SEC_ISR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecImr
+ */
+#define XFPD_SLCR_SEC_IMR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecIer
+ */
+#define XFPD_SLCR_SEC_IER    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIdr
+ */
+#define XFPD_SLCR_SEC_IDR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecItr
+ */
+#define XFPD_SLCR_SEC_ITR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecSata
+ */
+#define XFPD_SLCR_SEC_SATA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XFPD_SLCR_SEC_SATA_RSTVAL   0x0000000eUL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT   3UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT   2UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecPcie
+ */
+#define XFPD_SLCR_SEC_PCIE    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XFPD_SLCR_SEC_PCIE_RSTVAL   0x01ffffffUL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT   24UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK    0x01000000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT   23UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK    0x00800000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT   22UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK    0x00400000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT   21UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK    0x00200000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT   20UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK    0x00100000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT   19UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK    0x00080000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT   18UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK    0x00040000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT   17UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK    0x00020000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT   16UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK    0x00010000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT   15UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK    0x00008000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT   14UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK    0x00004000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT   13UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK    0x00002000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT   12UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK    0x00001000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT   11UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK    0x00000800UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT   10UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK    0x00000400UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT   9UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK    0x00000200UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT   8UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK    0x00000100UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT   7UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK    0x00000080UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT   6UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK    0x00000040UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT   5UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK    0x00000020UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT   4UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK    0x00000010UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT   3UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT   2UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT   0UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecDpdma
+ */
+#define XFPD_SLCR_SEC_DPDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
+#define XFPD_SLCR_SEC_DPDMA_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH   1UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecGdma
+ */
+#define XFPD_SLCR_SEC_GDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
+#define XFPD_SLCR_SEC_GDMA_RSTVAL   0x000000ffUL
+
+#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH   8UL
+#define XFPD_SLCR_SEC_GDMA_TZ_MASK    0x000000ffUL
+#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL  0xffUL
+
+/**
+ * Register: XfpdSlcrSecGic
+ */
+#define XFPD_SLCR_SEC_GIC    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
+#define XFPD_SLCR_SEC_GIC_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT   0UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_xmpu_cfg.h
new file mode 100644
index 000000000..75aef19f9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_xmpu_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_XMPU_CFG_H__
+#define __XFPD_XMPU_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdXmpuCfg Base Address
+ */
+#define XFPD_XMPU_CFG_BASEADDR      0xFD5D0000UL
+
+/**
+ * Register: XfpdXmpuCfgCtrl
+ */
+#define XFPD_XMPU_CFG_CTRL    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000000UL )
+#define XFPD_XMPU_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuCfgErrSts1
+ */
+#define XFPD_XMPU_CFG_ERR_STS1    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000004UL )
+#define XFPD_XMPU_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgErrSts2
+ */
+#define XFPD_XMPU_CFG_ERR_STS2    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000008UL )
+#define XFPD_XMPU_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgPoison
+ */
+#define XFPD_XMPU_CFG_POISON    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000000CUL )
+#define XFPD_XMPU_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XFPD_XMPU_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XFPD_XMPU_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XFPD_XMPU_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_POISON_BASE_SHIFT   0UL
+#define XFPD_XMPU_CFG_POISON_BASE_WIDTH   20UL
+#define XFPD_XMPU_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XFPD_XMPU_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgIsr
+ */
+#define XFPD_XMPU_CFG_ISR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000010UL )
+#define XFPD_XMPU_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_ISR_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_ISR_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgImr
+ */
+#define XFPD_XMPU_CFG_IMR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000014UL )
+#define XFPD_XMPU_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_IMR_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_IMR_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuCfgIen
+ */
+#define XFPD_XMPU_CFG_IEN    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000018UL )
+#define XFPD_XMPU_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IEN_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_IEN_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgIds
+ */
+#define XFPD_XMPU_CFG_IDS    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000001CUL )
+#define XFPD_XMPU_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IDS_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_IDS_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgLock
+ */
+#define XFPD_XMPU_CFG_LOCK    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000020UL )
+#define XFPD_XMPU_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00Strt
+ */
+#define XFPD_XMPU_CFG_R00_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000100UL )
+#define XFPD_XMPU_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00End
+ */
+#define XFPD_XMPU_CFG_R00_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000104UL )
+#define XFPD_XMPU_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R00_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00Mstr
+ */
+#define XFPD_XMPU_CFG_R00_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000108UL )
+#define XFPD_XMPU_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00
+ */
+#define XFPD_XMPU_CFG_R00    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000010CUL )
+#define XFPD_XMPU_CFG_R00_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R00_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R00_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R00_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R00_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01Strt
+ */
+#define XFPD_XMPU_CFG_R01_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000110UL )
+#define XFPD_XMPU_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01End
+ */
+#define XFPD_XMPU_CFG_R01_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000114UL )
+#define XFPD_XMPU_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R01_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01Mstr
+ */
+#define XFPD_XMPU_CFG_R01_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000118UL )
+#define XFPD_XMPU_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01
+ */
+#define XFPD_XMPU_CFG_R01    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000011CUL )
+#define XFPD_XMPU_CFG_R01_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R01_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R01_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R01_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R01_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02Strt
+ */
+#define XFPD_XMPU_CFG_R02_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000120UL )
+#define XFPD_XMPU_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02End
+ */
+#define XFPD_XMPU_CFG_R02_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000124UL )
+#define XFPD_XMPU_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R02_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02Mstr
+ */
+#define XFPD_XMPU_CFG_R02_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000128UL )
+#define XFPD_XMPU_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02
+ */
+#define XFPD_XMPU_CFG_R02    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000012CUL )
+#define XFPD_XMPU_CFG_R02_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R02_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R02_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R02_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R02_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03Strt
+ */
+#define XFPD_XMPU_CFG_R03_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000130UL )
+#define XFPD_XMPU_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03End
+ */
+#define XFPD_XMPU_CFG_R03_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000134UL )
+#define XFPD_XMPU_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R03_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03Mstr
+ */
+#define XFPD_XMPU_CFG_R03_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000138UL )
+#define XFPD_XMPU_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03
+ */
+#define XFPD_XMPU_CFG_R03    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000013CUL )
+#define XFPD_XMPU_CFG_R03_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R03_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R03_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R03_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R03_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04Strt
+ */
+#define XFPD_XMPU_CFG_R04_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000140UL )
+#define XFPD_XMPU_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04End
+ */
+#define XFPD_XMPU_CFG_R04_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000144UL )
+#define XFPD_XMPU_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R04_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04Mstr
+ */
+#define XFPD_XMPU_CFG_R04_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000148UL )
+#define XFPD_XMPU_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04
+ */
+#define XFPD_XMPU_CFG_R04    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000014CUL )
+#define XFPD_XMPU_CFG_R04_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R04_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R04_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R04_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R04_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05Strt
+ */
+#define XFPD_XMPU_CFG_R05_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000150UL )
+#define XFPD_XMPU_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05End
+ */
+#define XFPD_XMPU_CFG_R05_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000154UL )
+#define XFPD_XMPU_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R05_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05Mstr
+ */
+#define XFPD_XMPU_CFG_R05_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000158UL )
+#define XFPD_XMPU_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05
+ */
+#define XFPD_XMPU_CFG_R05    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000015CUL )
+#define XFPD_XMPU_CFG_R05_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R05_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R05_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R05_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R05_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06Strt
+ */
+#define XFPD_XMPU_CFG_R06_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000160UL )
+#define XFPD_XMPU_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06End
+ */
+#define XFPD_XMPU_CFG_R06_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000164UL )
+#define XFPD_XMPU_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R06_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06Mstr
+ */
+#define XFPD_XMPU_CFG_R06_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000168UL )
+#define XFPD_XMPU_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06
+ */
+#define XFPD_XMPU_CFG_R06    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000016CUL )
+#define XFPD_XMPU_CFG_R06_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R06_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R06_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R06_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R06_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07Strt
+ */
+#define XFPD_XMPU_CFG_R07_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000170UL )
+#define XFPD_XMPU_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07End
+ */
+#define XFPD_XMPU_CFG_R07_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000174UL )
+#define XFPD_XMPU_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R07_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07Mstr
+ */
+#define XFPD_XMPU_CFG_R07_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000178UL )
+#define XFPD_XMPU_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07
+ */
+#define XFPD_XMPU_CFG_R07    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000017CUL )
+#define XFPD_XMPU_CFG_R07_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R07_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R07_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R07_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R07_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08Strt
+ */
+#define XFPD_XMPU_CFG_R08_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000180UL )
+#define XFPD_XMPU_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08End
+ */
+#define XFPD_XMPU_CFG_R08_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000184UL )
+#define XFPD_XMPU_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R08_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08Mstr
+ */
+#define XFPD_XMPU_CFG_R08_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000188UL )
+#define XFPD_XMPU_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08
+ */
+#define XFPD_XMPU_CFG_R08    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000018CUL )
+#define XFPD_XMPU_CFG_R08_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R08_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R08_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R08_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R08_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09Strt
+ */
+#define XFPD_XMPU_CFG_R09_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000190UL )
+#define XFPD_XMPU_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09End
+ */
+#define XFPD_XMPU_CFG_R09_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000194UL )
+#define XFPD_XMPU_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R09_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09Mstr
+ */
+#define XFPD_XMPU_CFG_R09_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000198UL )
+#define XFPD_XMPU_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09
+ */
+#define XFPD_XMPU_CFG_R09    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000019CUL )
+#define XFPD_XMPU_CFG_R09_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R09_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R09_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R09_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R09_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10Strt
+ */
+#define XFPD_XMPU_CFG_R10_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A0UL )
+#define XFPD_XMPU_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10End
+ */
+#define XFPD_XMPU_CFG_R10_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A4UL )
+#define XFPD_XMPU_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R10_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10Mstr
+ */
+#define XFPD_XMPU_CFG_R10_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A8UL )
+#define XFPD_XMPU_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10
+ */
+#define XFPD_XMPU_CFG_R10    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ACUL )
+#define XFPD_XMPU_CFG_R10_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R10_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R10_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R10_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R10_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11Strt
+ */
+#define XFPD_XMPU_CFG_R11_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B0UL )
+#define XFPD_XMPU_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11End
+ */
+#define XFPD_XMPU_CFG_R11_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B4UL )
+#define XFPD_XMPU_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R11_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11Mstr
+ */
+#define XFPD_XMPU_CFG_R11_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B8UL )
+#define XFPD_XMPU_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11
+ */
+#define XFPD_XMPU_CFG_R11    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001BCUL )
+#define XFPD_XMPU_CFG_R11_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R11_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R11_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R11_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R11_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12Strt
+ */
+#define XFPD_XMPU_CFG_R12_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C0UL )
+#define XFPD_XMPU_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12End
+ */
+#define XFPD_XMPU_CFG_R12_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C4UL )
+#define XFPD_XMPU_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R12_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12Mstr
+ */
+#define XFPD_XMPU_CFG_R12_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C8UL )
+#define XFPD_XMPU_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12
+ */
+#define XFPD_XMPU_CFG_R12    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001CCUL )
+#define XFPD_XMPU_CFG_R12_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R12_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R12_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R12_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R12_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13Strt
+ */
+#define XFPD_XMPU_CFG_R13_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D0UL )
+#define XFPD_XMPU_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13End
+ */
+#define XFPD_XMPU_CFG_R13_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D4UL )
+#define XFPD_XMPU_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R13_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13Mstr
+ */
+#define XFPD_XMPU_CFG_R13_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D8UL )
+#define XFPD_XMPU_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13
+ */
+#define XFPD_XMPU_CFG_R13    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001DCUL )
+#define XFPD_XMPU_CFG_R13_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R13_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R13_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R13_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R13_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14Strt
+ */
+#define XFPD_XMPU_CFG_R14_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E0UL )
+#define XFPD_XMPU_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14End
+ */
+#define XFPD_XMPU_CFG_R14_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E4UL )
+#define XFPD_XMPU_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R14_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14Mstr
+ */
+#define XFPD_XMPU_CFG_R14_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E8UL )
+#define XFPD_XMPU_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14
+ */
+#define XFPD_XMPU_CFG_R14    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ECUL )
+#define XFPD_XMPU_CFG_R14_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R14_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R14_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R14_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R14_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15Strt
+ */
+#define XFPD_XMPU_CFG_R15_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F0UL )
+#define XFPD_XMPU_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15End
+ */
+#define XFPD_XMPU_CFG_R15_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F4UL )
+#define XFPD_XMPU_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R15_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15Mstr
+ */
+#define XFPD_XMPU_CFG_R15_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F8UL )
+#define XFPD_XMPU_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15
+ */
+#define XFPD_XMPU_CFG_R15    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001FCUL )
+#define XFPD_XMPU_CFG_R15_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R15_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R15_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R15_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R15_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_xmpu_sink.h
new file mode 100644
index 000000000..39172f1f4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xfpd_xmpu_sink.h
@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_XMPU_SINK_H__
+#define __XFPD_XMPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdXmpuSink Base Address
+ */
+#define XFPD_XMPU_SINK_BASEADDR      0xFD4F0000UL
+
+/**
+ * Register: XfpdXmpuSinkErrSts
+ */
+#define XFPD_XMPU_SINK_ERR_STS    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XFPD_XMPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIsr
+ */
+#define XFPD_XMPU_SINK_ISR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XFPD_XMPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkImr
+ */
+#define XFPD_XMPU_SINK_IMR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XFPD_XMPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuSinkIer
+ */
+#define XFPD_XMPU_SINK_IER    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XFPD_XMPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIdr
+ */
+#define XFPD_XMPU_SINK_IDR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XFPD_XMPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_XMPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil-crt0.S
new file mode 100644
index 000000000..eab93d183
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil-crt0.S
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00	pkp  05/21/14 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+	.file	"xil-crt0.S"
+	.section ".got2","aw"
+	.align	2
+
+	.text
+.Lsbss_start:
+	.long	__sbss_start
+
+.Lsbss_end:
+	.long	__sbss_end
+
+.Lbss_start:
+	.long	__bss_start__
+
+.Lbss_end:
+	.long	__bss_end__
+
+
+
+	.globl	_startup
+_startup:
+
+	mov	x0, #0
+
+	/* clear sbss */
+	ldr 	w1,.Lsbss_start		/* calculate beginning of the SBSS */
+	ldr	w2,.Lsbss_end		/* calculate end of the SBSS */
+	uxtw	x1, w1			/*zero extension to w1 register*/
+	uxtw	x2, w2			/*zero extension to w2 register*/
+
+.Lloop_sbss:
+	cmp	x1,x2
+	bge	.Lenclsbss		/* If no SBSS, no clearing required */
+	str	x0, [x1], #8
+	b	.Lloop_sbss
+
+.Lenclsbss:
+	/* clear bss */
+	ldr	w1,.Lbss_start		/* calculate beginning of the BSS */
+	ldr	w2,.Lbss_end		/* calculate end of the BSS */
+	uxtw	x1, w1			/*zero extension to w1 register*/
+	uxtw	x2, w2			/*zero extension to w2 register*/
+
+.Lloop_bss:
+	cmp	x1,x2
+	bge	.Lenclbss		/* If no BSS, no clearing required */
+	str	x0, [x1], #8
+	b	.Lloop_bss
+
+.Lenclbss:
+
+	bl 	Init_Uart		/* Initialize UART */
+
+
+	/* make sure argc and argv are valid */
+	mov	x0, #0
+	mov	x1, #0
+
+	bl	main			/* Jump to main C code */
+
+
+
+	bl	_exit
+
+.Lexit:	/* should never get here */
+	b .Lexit
+
+.Lstart:
+	.size	_startup,.Lstart-_startup
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_assert.c
new file mode 100644
index 000000000..e89292b87
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_assert.c
@@ -0,0 +1,147 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 Initial release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+/*s32 Xil_AssertWait = 1*/
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Implement assert. Currently, it calls a user-defined callback function
+* if one has been set.  Then, it potentially enters an infinite loop depending
+* on the value of the Xil_AssertWait variable.
+*
+* @param    file is the name of the filename of the source
+* @param    line is the linenumber within File
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+	s32 Xil_AssertWait = 1;
+	/* if the callback has been set then invoke it */
+	if (Xil_AssertCallbackRoutine != 0) {
+		(*Xil_AssertCallbackRoutine)(File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (Xil_AssertWait != 0) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Set up a callback function to be invoked when an assert occurs. If there
+* was already a callback installed, then it is replaced.
+*
+* @param    routine is the callback to be invoked when an assert is taken
+*
+* @return   None.
+*
+* @note     This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+	Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* Null handler function. This follows the XInterruptHandler signature for
+* interrupt handlers. It can be used to assign a null handler (a stub) to an
+* interrupt controller vector table.
+*
+* @param    NullParameter is an arbitrary void pointer and not used.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void *) NullParameter;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_assert.h
new file mode 100644
index 000000000..6d3f96a83
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_assert.h
@@ -0,0 +1,189 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* This file contains assert related functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE     0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param    Expression is the expression to evaluate. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the Xil_AssertWait variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression)                \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
+* so that asserts which fail allow execution to continue.
+*
+* @param    Expression is the expression to evaluate. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
+* 	    case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression)             \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	  case no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways()                   \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	  case no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways()                \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return 0;                                       \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_cache.c
new file mode 100644
index 000000000..d5450c2be
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_cache.c
@@ -0,0 +1,648 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality. Cache APIs are
+* yet to be implemented. They are left blank to avoid any compilation error
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa53.h"
+#include "xil_exception.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#define IRQ_FIQ_MASK 0xC0U	/* Mask IRQ and FIQ interrupts in cpsr */
+
+/****************************************************************************
+*
+* Enable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+
+void Xil_DCacheEnable(void)
+{
+	u32 CtrlReg;
+	CtrlReg = mfcp(SCTLR_EL3);
+	/* enable caches only if they are disabled */
+	if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){
+
+		/* invalidate the Data cache */
+		Xil_DCacheInvalidate();
+
+		CtrlReg |= XREG_CONTROL_DCACHE_BIT;
+
+		/* enable the Data cache */
+		mtcp(SCTLR_EL3,CtrlReg);
+	}
+}
+
+/****************************************************************************
+*
+* Disable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+	u32 CtrlReg;
+	/* clean and invalidate the Data cache */
+	Xil_DCacheFlush();
+	CtrlReg = mfcp(SCTLR_EL3);
+
+	CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+	/* disable the Data cache */
+	mtcp(SCTLR_EL3,CtrlReg);
+}
+
+/****************************************************************************
+*
+* invalidate the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 LineSize, NumWays;
+	u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+
+	/* Number of level of cache*/
+	NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
+
+	CacheLevel=0U;
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
+
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0X00000001U;
+
+	/*Number of Set*/
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0X00000001U;
+
+	WayAdjust = clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(ISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += (0x00000001U << WayAdjust);
+	}
+
+	/* Wait for invalidate to complete */
+	dsb();
+
+	/* Select cache level 1 and D cache in CSSR */
+	CacheLevel += (0x00000001U<<1U) ;
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
+
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+		LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/* Number of Sets */
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0x00000001U;
+
+	WayAdjust = clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(ISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += (0x00000001U << WayAdjust);
+	}
+	/* Wait for invalidate to complete */
+	dsb();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the modified contents
+* are written to system memory before the line is invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 6 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(INTPTR adr)
+{
+
+	u32 currmask;
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(CSSELR_EL1,0x0);
+	mtcpdc(IVAC,(adr & (~0x3F)));
+	/* Wait for invalidate to complete */
+	dsb();
+	/* Select cache level 1 and D cache in CSSR */
+	mtcp(CSSELR_EL1,0x2);
+	mtcpdc(IVAC,(adr & (~0x3F)));
+	/* Wait for invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are written to system memory
+* before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR  adr, u32 len)
+{
+	const u32 cacheline = 64U;
+	u32 end;
+	u32 tempadr = adr;
+	u32 tempend;
+	u32 currmask;
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0U) {
+		end = tempadr + len;
+		tempend = end;
+
+		if ((tempadr & (cacheline-1U)) != 0U) {
+			tempadr &= (~(cacheline - 1U));
+			Xil_DCacheFlushLine(tempadr);
+			tempadr += cacheline;
+		}
+		if ((tempend & (cacheline-1U)) != 0U) {
+			tempend &= (~(cacheline - 1U));
+			Xil_DCacheFlushLine(tempend);
+		}
+
+		while (tempadr < tempend) {
+			/* Select cache level 0 and D cache in CSSR */
+			mtcp(CSSELR_EL1,0x0);
+			/* Invalidate Data cache line */
+			mtcpdc(IVAC,(tempadr & (~0x3F)));
+			/* Wait for invalidate to complete */
+			dsb();
+			/* Select cache level 0 and D cache in CSSR */
+			mtcp(CSSELR_EL1,0x2);
+			/* Invalidate Data cache line */
+			mtcpdc(IVAC,(tempadr & (~0x3F)));
+			/* Wait for invalidate to complete */
+			dsb();
+			tempadr += cacheline;
+		}
+	}
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 LineSize, NumWays;
+	u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+
+	/* Number of level of cache*/
+	NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
+
+	CacheLevel = 0U;
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
+
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/*Number of Set*/
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0x00000001U;
+
+	WayAdjust = clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Flush all the cachelines */
+	for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(CISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += (0x00000001U << WayAdjust);
+	}
+
+	/* Wait for Flush to complete */
+	dsb();
+
+	/* Select cache level 1 and D cache in CSSR */
+	CacheLevel += (0x00000001U << 1U);
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
+
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+		LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/* Number of Sets */
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0x00000001U;
+
+	WayAdjust=clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Flush all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(CISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set=0U;
+		Way += (0x00000001U<
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheInvalidateLine(INTPTR adr);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+void Xil_DCacheFlushLine(INTPTR adr);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_ICacheInvalidateLine(INTPTR adr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_cache_vxworks.h
new file mode 100644
index 000000000..64ae0fd90
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_cache_vxworks.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* 

+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_exception.c
new file mode 100644
index 000000000..e3fa6175e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_exception.c
@@ -0,0 +1,214 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A53 exception
+* Handler.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void Xil_ExceptionNullHandler(void *Data);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SyncAbortHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SErrorAbortHandler, NULL},
+
+};
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific  exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param	Data is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+	(void *)Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+*
+* The function is a common API used to initialize exception handlers across all
+* processors supported. For ARM CortexA53, the exception handlers are being
+* initialized statically and hence this function does not do anything.
+*
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+	return;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Id of the exception source and the
+* associated Handler that is to run when the exception is recognized. The
+* argument provided in this call as the Data is used as the argument
+* for the Handler when it is called.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+		See xil_exception_l.h for further information.
+* @param	Handler to the Handler for that exception.
+* @param	Data is a reference to Data that will be passed to the
+*		Handler when it gets called.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+				    Xil_ExceptionHandler Handler,
+				    void *Data)
+{
+	XExc_VectorTable[Exception_id].Handler = Handler;
+	XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* Removes the Handler for a specific exception Id. The stub Handler is then
+* registered for this exception Id.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*		See xil_exception_l.h for further information.
+
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+	Xil_ExceptionRegisterHandler(Exception_id,
+				       Xil_ExceptionNullHandler,
+				       NULL);
+}
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_exception.h
new file mode 100644
index 000000000..818d44300
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_exception.h
@@ -0,0 +1,168 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST			0U
+#define XIL_EXCEPTION_ID_SYNC_INT		1U
+#define XIL_EXCEPTION_ID_IRQ_INT		2U
+#define XIL_EXCEPTION_ID_FIQ_INT		3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_LAST			5U
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Enable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 0, exception is enabled.
+*		C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+
+#define Xil_ExceptionEnableMask(Mask)	\
+		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+
+/****************************************************************************/
+/**
+* Enable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Disable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 1, exception is disabled.
+*		C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+
+#define Xil_ExceptionDisableMask(Mask)	\
+		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+					 Xil_ExceptionHandler Handler,
+					 void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+
+extern void Xil_ExceptionInit(void);
+
+void Xil_SyncAbortHandler(void *CallBackRef);
+
+void Xil_SErrorAbortHandler(void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_hal.h
new file mode 100644
index 000000000..e29d2a79d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_hal.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* 

+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_io.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_io.c
new file mode 100644
index 000000000..e9dcdce37
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_io.c
@@ -0,0 +1,381 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.  These functions encapsulate Cortex A53 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa53.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for an 8-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u8 Xil_In8(INTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16(INTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32(INTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for an 8-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out8(INTPTR Addr, u8 Value)
+{
+	u8 *LocalAddr = (u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16(INTPTR Addr, u16 Value)
+{
+	u16 *LocalAddr = (u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32(INTPTR Addr, u32 Value)
+{
+	u32 *LocalAddr = (u32 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 64-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out64(INTPTR Addr, u64 Value)
+{
+	u64 *LocalAddr = (u64 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 64-bit memory location by reading the
+* specified Value to the the specified address.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+u64 Xil_In64(INTPTR Addr)
+{
+	return *(volatile u64 *) Addr;
+}
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16BE(INTPTR Addr)
+{
+	u16 temp;
+	u16 result;
+
+	temp = Xil_In16(Addr);
+
+	result = Xil_EndianSwap16(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32BE(INTPTR Addr)
+{
+	u32 temp;
+	u32 result;
+
+	temp = Xil_In32(Addr);
+
+	result = Xil_EndianSwap32(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16BE(INTPTR Addr, u16 Value)
+{
+	u16 temp;
+
+	temp = Xil_EndianSwap16(Value);
+
+    Xil_Out16(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32BE(INTPTR Addr, u32 Value)
+{
+	u32 temp;
+
+	temp = Xil_EndianSwap32(Value);
+
+    Xil_Out32(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_io.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_io.h
new file mode 100644
index 000000000..1c89574bb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_io.h
@@ -0,0 +1,240 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xil_printf.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+
+
+/*****************************************************************************/
+/**
+*
+* Perform an big-endian input operation for a 16-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In16LE(Addr) Xil_In16((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian input operation for a 32-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In32LE(Addr) Xil_In32((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 16-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 32-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from host byte order to network byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from host byte order to network byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htons(Data) Xil_EndianSwap16((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from network byte order to host byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from network byte order to host byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
+
+/************************** Function Prototypes ******************************/
+
+/* The following functions allow the software to be transportable across
+ * processors which may use memory mapped I/O or I/O which is mapped into a
+ * seperate address space.
+ */
+u8 Xil_In8(INTPTR Addr);
+u16 Xil_In16(INTPTR Addr);
+u32 Xil_In32(INTPTR Addr);
+u64 Xil_In64(INTPTR Addr);
+
+void Xil_Out8(INTPTR Addr, u8 Value);
+void Xil_Out16(INTPTR Addr, u16 Value);
+void Xil_Out32(INTPTR Addr, u32 Value);
+void Xil_Out64(INTPTR Addr, u64 Value);
+
+
+u16 Xil_In16BE(INTPTR Addr);
+u32 Xil_In32BE(INTPTR Addr);
+void Xil_Out16BE(INTPTR Addr, u16 Value);
+void Xil_Out32BE(INTPTR Addr, u32 Value);
+
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_macroback.h
new file mode 100644
index 000000000..f5316efbf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_macroback.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ *   XGpio_mSetDataDirection
+ *   XGpio_mGetDataReg
+ *   XGpio_mSetDataReg
+ *   XIIC_RESET
+ *   XIIC_CLEAR_STATS
+ *   XSpi_mReset
+ *   XSysAce_mSetCfgAddr
+ *   XSysAce_mIsCfgDone
+ *   XTft_mSetPixel
+ *   XTft_mGetPixel
+ *   XWdtTb_mEnableWdt
+ *   XWdtTb_mDisbleWdt
+ *   XWdtTb_mRestartWdt
+ *   XWdtTb_mGetTimebaseReg
+ *   XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_mmu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_mmu.c
new file mode 100644
index 000000000..ceae6edfa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_mmu.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+* MMU APIs are yet to be implemented. They are left blank to avoid any
+* compilation error
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+extern INTPTR MMUTableL1;
+extern INTPTR MMUTableL2;
+/************************** Function Prototypes ******************************/
+/*****************************************************************************
+*
+* Set the memory attributes for a section, in the translation table.
+*
+* @param	addr is the address for which attributes are to be set.
+* @param	attrib specifies the attributes for that memory region.
+*
+* @return	None.
+*
+* @note		The MMU and D-cache need not be disabled before changing an
+*			translation table attribute.
+*
+******************************************************************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib)
+{
+	INTPTR *ptr;
+	INTPTR section;
+	/* if region is less than 4GB MMUTable level 2 need to be modified */
+	if(Addr<0x100000000){
+	section = Addr / 0x00200000U;
+	ptr = &MMUTableL2 + section;
+	*ptr = (Addr & (~0x001FFFFFU)) | attrib;
+	}
+	/* if region is greater than 4GB MMUTable level 1 need to be modified */
+	else{
+	section = Addr / 0x40000000U;
+	ptr = &MMUTableL1 + section;
+	*ptr = (Addr & (~0x3FFFFFFFU)) | attrib;
+	}
+
+	Xil_DCacheFlush();
+	mtcptlbi(ALLE3);
+
+	dsb(); /* ensure completion of the BP and TLB invalidation */
+    isb(); /* synchronize context on this processor */
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_mmu.h
new file mode 100644
index 000000000..d74b3d930
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_mmu.h
@@ -0,0 +1,79 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_printf.c
new file mode 100644
index 000000000..39e13e82b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_printf.c
@@ -0,0 +1,329 @@
+/*---------------------------------------------------*/
+/* Modified from :                                   */
+/* Public Domain version of printf                   */
+/* Rud Merriam, Compsult, Inc. Houston, Tx.          */
+/* For Embedded Systems Programming, 1991            */
+/*                                                   */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include 
+#include 
+#include 
+
+typedef struct params_s {
+    s32 len;
+    s32 num1;
+    s32 num2;
+    char8 pad_character;
+    s32 do_padding;
+    s32 left_flag;
+} params_t;
+
+static void padding( const s32 l_flag,const params_t *par);
+static void outs(const charptr lp, params_t *par);
+static void outnum( const s32 n, const s32 base, params_t *par);
+static s32 getnum( charptr* linep);
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine puts pad characters into the output  */
+/* buffer.                                           */
+/*                                                   */
+static void padding( const s32 l_flag, const params_t *par)
+{
+    s32 i;
+
+    if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+		i=(par->len);
+        for (; i<(par->num1); i++) {
+            outbyte( par->pad_character);
+		}
+    }
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a string to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+static void outs(const charptr lp, params_t *par)
+{
+    charptr LocalPtr;
+	LocalPtr = lp;
+    /* pad on left if needed                         */
+	if(LocalPtr != NULL) {
+		par->len = (s32)strlen( LocalPtr);
+	}
+    padding( !(par->left_flag), par);
+
+    /* Move string to the buffer                     */
+    while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+		(par->num2)--;
+        outbyte(*LocalPtr);
+		LocalPtr += 1;
+}
+
+    /* Pad on right if needed                        */
+    /* CR 439175 - elided next stmt. Seemed bogus.   */
+    /* par->len = strlen( lp)                      */
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a number to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+
+static void outnum( const s32 n, const s32 base, params_t *par)
+{
+    charptr cp;
+    s32 negative;
+	s32 i;
+    char8 outbuf[32];
+    const char8 digits[] = "0123456789ABCDEF";
+    u32 num;
+    for(i = 0; i<32; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = (n);
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+	outbyte( outbuf[i] );
+		i--;
+}
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine gets a number from the format        */
+/* string.                                           */
+/*                                                   */
+static s32 getnum( charptr* linep)
+{
+    s32 n;
+    s32 ResultIsDigit = 0;
+    charptr cptr;
+    n = 0;
+    cptr = *linep;
+	if(cptr != NULL){
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    while (ResultIsDigit != 0) {
+		if(cptr != NULL){
+			n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+			cptr += 1;
+			if(cptr != NULL){
+				ResultIsDigit = isdigit(((s32)*cptr));
+			}
+		}
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    *linep = ((charptr )(cptr));
+    return(n);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine operates just like a printf/sprintf  */
+/* routine. It outputs a set of data under the       */
+/* control of a formatting string. Not all of the    */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded  */
+/* systems work. Primarily the floating point        */
+/* routines are omitted. Other formats could be      */
+/* added easily by following the examples shown for  */
+/* the supported formats.                            */
+/*                                                   */
+
+/* void esp_printf( const func_ptr f_ptr,
+   const charptr ctrl1, ...) */
+void xil_printf( const char8 *ctrl1, ...)
+{
+	s32 Check;
+    s32 long_flag;
+    s32 dot_flag;
+
+    params_t par;
+
+    char8 ch;
+    va_list argp;
+    char8 *ctrl = (char8 *)ctrl1;
+
+    va_start( argp, ctrl1);
+
+    while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+        /* move format string chars to buffer until a  */
+        /* format control is found.                    */
+        if (*ctrl != '%') {
+            outbyte(*ctrl);
+			ctrl += 1;
+            continue;
+        }
+
+        /* initialize all the flags for this format.   */
+        dot_flag = 0;
+		long_flag = 0;
+		par.left_flag = 0;
+		par.do_padding = 0;
+        par.pad_character = ' ';
+        par.num2=32767;
+		par.num1=0;
+		par.len=0;
+
+ try_next:
+		if(ctrl != NULL) {
+			ctrl += 1;
+		}
+		if(ctrl != NULL) {
+			ch = *ctrl;
+		}
+		else {
+			ch = *ctrl;
+		}
+
+        if (isdigit((s32)ch) != 0) {
+            if (dot_flag != 0) {
+                par.num2 = getnum(&ctrl);
+			}
+            else {
+                if (ch == '0') {
+                    par.pad_character = '0';
+				}
+				if(ctrl != NULL) {
+			par.num1 = getnum(&ctrl);
+				}
+                par.do_padding = 1;
+            }
+            if(ctrl != NULL) {
+			ctrl -= 1;
+			}
+            goto try_next;
+        }
+
+        switch (tolower((s32)ch)) {
+            case '%':
+                outbyte( '%');
+                Check = 1;
+                break;
+
+            case '-':
+                par.left_flag = 1;
+                Check = 0;
+                break;
+
+            case '.':
+                dot_flag = 1;
+                Check = 0;
+                break;
+
+            case 'l':
+                long_flag = 1;
+                Check = 0;
+                break;
+
+            case 'd':
+                if ((long_flag != 0) || (ch == 'D')) {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+                else {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+				Check = 1;
+                break;
+            case 'x':
+                outnum((s32)va_arg(argp, s32), 16L, &par);
+                Check = 1;
+                break;
+
+            case 's':
+                outs( va_arg( argp, char *), &par);
+                Check = 1;
+                break;
+
+            case 'c':
+                outbyte( va_arg( argp, s32));
+                Check = 1;
+                break;
+
+            case '\\':
+                switch (*ctrl) {
+                    case 'a':
+                        outbyte( ((char8)0x07));
+                        break;
+                    case 'h':
+                        outbyte( ((char8)0x08));
+                        break;
+                    case 'r':
+                        outbyte( ((char8)0x0D));
+                        break;
+                    case 'n':
+                        outbyte( ((char8)0x0D));
+                        outbyte( ((char8)0x0A));
+                        break;
+                    default:
+                        outbyte( *ctrl);
+                        break;
+                }
+                ctrl += 1;
+                Check = 0;
+                break;
+
+            default:
+		Check = 1;
+		break;
+        }
+        if(Check == 1) {
+			if(ctrl != NULL) {
+				ctrl += 1;
+			}
+                continue;
+        }
+        goto try_next;
+    }
+    va_end( argp);
+}
+
+/*---------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_printf.h
new file mode 100644
index 000000000..2be5c5734
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_printf.h
@@ -0,0 +1,44 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 
+#include "xil_types.h"
+#include "xparameters.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/*                                                   */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testcache.c
new file mode 100644
index 000000000..43732a4d1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testcache.c
@@ -0,0 +1,366 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+* 

+*
+* @note
+*
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+/**
+* Perform DCache range related API test such as Xil_DCacheFlushRange and
+* Xil_DCacheInvalidateRange. This test function writes a constant value
+* to the Data array, flushes the range, writes a new value, then invalidates
+* the corresponding range.
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     - -1 is returned for a failure
+*/
+s32 Xil_TestDCacheRange(void)
+{
+	s32 Index;
+	s32 Status = 0;
+	u32 CtrlReg;
+	INTPTR Value;
+
+	xil_printf("-- Cache Range Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A00505;
+
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    flush range done\r\n");
+
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A00505) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("	Flush worked\r\n");
+	}
+	else {
+		xil_printf("Error: flush dcache range not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+		#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+		#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0C505;
+
+
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    invalidate dcache range done\r\n");
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0A05;
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A0A05) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+
+	if (!Status) {
+		xil_printf("    Invalidate worked\r\n");
+	}
+	else {
+		xil_printf("Error: Invalidate dcache range not working\r\n");
+	}
+	xil_printf("-- Cache Range Test Complete --\r\n");
+	return Status;
+
+}
+
+/**
+* Perform DCache all related API test such as Xil_DCacheFlush and
+* Xil_DCacheInvalidate. This test function writes a constant value
+* to the Data array, flushes the DCache, writes a new value, then invalidates
+* the DCache.
+*
+* @return
+*     - 0 is returned for a pass
+*     - -1 is returned for a failure
+*/
+s32 Xil_TestDCacheAll(void)
+{
+	s32 Index;
+	s32 Status;
+	INTPTR Value;
+	u32 CtrlReg;
+
+	xil_printf("-- Cache All Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50500A0A;
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlush();
+	xil_printf("    flush all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+
+		if (Value != 0x50500A0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Flush all worked\r\n");
+	}
+	else {
+		xil_printf("Error: Flush dcache all not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x505FFA0A;
+
+	Xil_DCacheFlush();
+
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidate();
+
+	xil_printf("    invalidate all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50CFA0A;
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0x50CFA0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Invalidate all worked\r\n");
+	}
+	else {
+			xil_printf("Error: Invalidate dcache all not working\r\n");
+	}
+
+	xil_printf("-- DCache all Test Complete --\n\r");
+
+	return Status;
+}
+
+
+/**
+* Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     The function will hang if it fails.
+*/
+s32 Xil_TestICacheRange(void)
+{
+
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+	xil_printf("-- Invalidate icache range done --\r\n");
+
+	return 0;
+}
+
+/**
+* Perform Xil_ICacheInvalidate().
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     The function will hang if it fails.
+*/
+s32 Xil_TestICacheAll(void)
+{
+	Xil_ICacheInvalidate();
+	xil_printf("-- Invalidate icache all done --\r\n");
+	return 0;
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testcache.h
new file mode 100644
index 000000000..0ec0ea87e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testcache.h
@@ -0,0 +1,63 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* This file contains utility functions to test cache.
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
+#define XIL_TESTCACHE_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testio.c
new file mode 100644
index 000000000..4eaea4e55
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testio.c
@@ -0,0 +1,301 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.c
+*
+* Contains the memory test utility functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param	Data is the 16-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+	return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param	Data is the 32-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+	u16 Lo16;
+	u16 Hi16;
+
+	u16 Swap16Lo;
+	u16 Swap16Hi;
+
+	Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+	Lo16 = (u16)(Data & 0x0000FFFFU);
+
+	Swap16Lo = Swap16(Lo16);
+	Swap16Hi = Swap16(Hi16);
+
+	return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide register IO test where the register is
+* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
+* values.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Length is the Length of the block.
+* @param	Value is the constant used for writting the memory.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+	u8 ValueIn;
+	s32 Index;
+	s32 Status = 0;
+
+	for (Index = 0; Index < Length; Index++) {
+		Xil_Out8((INTPTR)Addr, Value);
+
+		ValueIn = Xil_In8((INTPTR)Addr);
+
+		if ((Value != ValueIn) && (Status == 0)) {
+			Status = -1;
+			break;
+		}
+	}
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide register IO test. Each location is tested
+* by sequentially writing a 16-bit wide register, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function performs the following
+* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
+* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
+* read-in value before comparing is controlled by the 5th argument.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Length is the Length of the block.
+* @param	Value is the constant used for writting the memory.
+* @param	Kind is the test kind. Acceptable values are:
+*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+	u16 *TempAddr16;
+	u16 ValueIn = 0U;
+	s32 Index;
+	TempAddr16 = Addr;
+	Xil_AssertNonvoid(TempAddr16 != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out16LE((INTPTR)TempAddr16, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out16BE((INTPTR)TempAddr16, Value);
+			break;
+		default:
+			Xil_Out16((INTPTR)TempAddr16, Value);
+			break;
+		}
+
+		ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out16((INTPTR)TempAddr16, Value);
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+			break;
+		default:
+			ValueIn = Xil_In16((INTPTR)TempAddr16);
+			break;
+		}
+
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr16 += sizeof(u16);
+	}
+	return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide register IO test. Each location is tested
+* by sequentially writing a 32-bit wide regsiter, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function perform the following
+* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
+* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
+* before comparing is controlled by the 5th argument.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Length is the Length of the block.
+* @param	Value is the constant used for writting the memory.
+* @param	Kind is the test kind. Acceptable values are:
+*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+	u32 *TempAddr;
+	u32 ValueIn = 0U;
+	s32 Index;
+	TempAddr = Addr;
+	Xil_AssertNonvoid(TempAddr != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out32LE((INTPTR)TempAddr, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out32BE((INTPTR)TempAddr, Value);
+			break;
+		default:
+			Xil_Out32((INTPTR)TempAddr, Value);
+			break;
+		}
+
+		ValueIn = Xil_In32((INTPTR)TempAddr);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out32((INTPTR)TempAddr, Value);
+
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In32LE((INTPTR)TempAddr);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In32BE((INTPTR)TempAddr);
+			break;
+		default:
+			ValueIn = Xil_In32((INTPTR)TempAddr);
+			break;
+		}
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr += sizeof(u32);
+	}
+	return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testio.h
new file mode 100644
index 000000000..2fd4d5790
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testio.h
@@ -0,0 +1,91 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.h
+*
+* This file contains utility functions to teach endian related memory
+* IO functions.
+*
+* Memory test description
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
+#define XIL_TESTIO_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 	0
+#define XIL_TESTIO_LE		1
+#define XIL_TESTIO_BE		2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testmem.c
new file mode 100644
index 000000000..ef38d6d24
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testmem.c
@@ -0,0 +1,882 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u32 Val;
+	u32 FirtVal;
+	u32 WordMem32;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			*(Addr+I) = Val;
+			Val++;
+		}
+
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			WordMem32 = *(Addr+I);
+
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (1U << j);
+
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u32) RotateLeft(Val, 32U);
+			}
+
+			/*
+			 * Restore the reference 'val' to the
+			 * initial value
+			 */
+			Val = 1U << j;
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+
+				WordMem32 = *(Addr+I);
+
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = (u32)RotateLeft(Val, 32U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible
+		 * initial test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = ~(1U << j);
+
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = ~(1U << j);
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+				WordMem32 = *(Addr+I);
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* Read the location */
+			WordMem32 = *(Addr+I);
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+
+			if ((WordMem32 ^ Val) != 0x00000000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u32)0) {
+			Val = 0xDEADBEEFU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+
+			/* read memory location */
+
+			WordMem32 = *(Addr+I);
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant Pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u16 Val;
+	u16 FirtVal;
+	u16 WordMem16;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * selectthe proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (u16)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u16)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones
+			 * test to test for bad
+			 * data bits
+			 */
+
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u16) (~((INTPTR)(&Addr[I])));
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			Val = (u16) (~((INTPTR) (&Addr[I])));
+			if ((WordMem16 ^ Val) != 0x0000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+		if (Pattern == (u16)0) {
+			Val = 0xDEADU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u8 Val;
+	u8 FirtVal;
+	u8 WordMem8;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * select the proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+			Val = (u8)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u8)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test to test
+			 * for bad data bits
+			 */
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			if ((WordMem8 ^ Val) != 0x00U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u8)0) {
+			Val = 0xA5U;
+		}
+		else {
+			Val = Pattern;
+		}
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the left one bit position
+*
+* @param    Input is value to be rotated to the left
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting unsigned long value of the rotate left
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+	u32 Msb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+	/*
+	 * set the Width of the Input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	Msb = LocalInput & MsbMask;
+
+	ReturnVal = LocalInput << 1U;
+
+	if (Msb != 0x00000000U) {
+		ReturnVal = ReturnVal | (u32)0x00000001;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the right one bit position
+*
+* @param    Input is value to be rotated to the right
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting u32 value of the rotate right
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+	u32 Lsb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << 1U) - 1U;
+
+	/*
+	 * set the width of the input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	ReturnVal = LocalInput >> 1U;
+
+	Lsb = LocalInput & 0x00000001U;
+
+	if (Lsb != 0x00000000U) {
+		ReturnVal = ReturnVal | MsbMask;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testmem.h
new file mode 100644
index 000000000..1b67a5214
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_testmem.h
@@ -0,0 +1,162 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+*
+* This file contains utility functions to test memory.
+*
+* Memory test description
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* Subtest descriptions:
+* 
+* XIL_TESTMEM_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XIL_TESTMEM_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
+*	incrementing value as the test value for memory.
+*
+* XIL_TESTMEM_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XIL_TESTMEM_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XIL_TESTMEM_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XIL_TESTMEM_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+* 

+*
+* WARNING
+*
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+*
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
+#define XIL_TESTMEM_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE	1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS     0x00U
+#define XIL_TESTMEM_INCREMENT       0x01U
+#define XIL_TESTMEM_WALKONES        0x02U
+#define XIL_TESTMEM_WALKZEROS       0x03U
+#define XIL_TESTMEM_INVERSEADDR     0x04U
+#define XIL_TESTMEM_FIXEDPATTERN    0x05U
+#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_types.h
new file mode 100644
index 000000000..b9ef3c185
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xil_types.h
@@ -0,0 +1,184 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* This file contains basic types for Xilinx software IP.
+
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include 
+#include 
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< component has been initialized */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< component has been started */
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/**
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/**
+ * xbasic_types.h does not typedef s* or u64
+ */
+
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include 
+#endif
+
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/*@}*/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xiou_secure_slcr.h
new file mode 100644
index 000000000..cb4ad4903
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xiou_secure_slcr.h
@@ -0,0 +1,174 @@
+/* ### HEADER ### */
+
+#ifndef __XIOU_SECURE_SLCR_H__
+#define __XIOU_SECURE_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XiouSecureSlcr Base Address
+ */
+#define XIOU_SECURE_SLCR_BASEADDR      0xFF240000UL
+
+/**
+ * Register: XiouSecSlcrAxiWprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_WPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
+#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT   25UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK    0x0e000000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrAxiRprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_RPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
+#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrCtrl
+ */
+#define XIOU_SEC_SLCR_CTRL    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
+#define XIOU_SEC_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIsr
+ */
+#define XIOU_SEC_SLCR_ISR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
+#define XIOU_SEC_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrImr
+ */
+#define XIOU_SEC_SLCR_IMR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
+#define XIOU_SEC_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSecSlcrIer
+ */
+#define XIOU_SEC_SLCR_IER    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XIOU_SEC_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIdr
+ */
+#define XIOU_SEC_SLCR_IDR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
+#define XIOU_SEC_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrItr
+ */
+#define XIOU_SEC_SLCR_ITR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
+#define XIOU_SEC_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XIOU_SECURE_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xiou_slcr.h
new file mode 100644
index 000000000..d81d178d3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xiou_slcr.h
@@ -0,0 +1,4029 @@
+/* ### HEADER ### */
+
+#ifndef __XIOU_SLCR_H__
+#define __XIOU_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XiouSlcr Base Address
+ */
+#define XIOU_SLCR_BASEADDR      0xFF180000UL
+
+/**
+ * Register: XiouSlcrMioPin0
+ */
+#define XIOU_SLCR_MIO_PIN_0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000000UL )
+#define XIOU_SLCR_MIO_PIN_0_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin1
+ */
+#define XIOU_SLCR_MIO_PIN_1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000004UL )
+#define XIOU_SLCR_MIO_PIN_1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin2
+ */
+#define XIOU_SLCR_MIO_PIN_2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000008UL )
+#define XIOU_SLCR_MIO_PIN_2_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin3
+ */
+#define XIOU_SLCR_MIO_PIN_3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XIOU_SLCR_MIO_PIN_3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin4
+ */
+#define XIOU_SLCR_MIO_PIN_4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000010UL )
+#define XIOU_SLCR_MIO_PIN_4_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin5
+ */
+#define XIOU_SLCR_MIO_PIN_5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000014UL )
+#define XIOU_SLCR_MIO_PIN_5_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin6
+ */
+#define XIOU_SLCR_MIO_PIN_6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000018UL )
+#define XIOU_SLCR_MIO_PIN_6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin7
+ */
+#define XIOU_SLCR_MIO_PIN_7    ( ( XIOU_SLCR_BASEADDR ) + 0x0000001CUL )
+#define XIOU_SLCR_MIO_PIN_7_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin8
+ */
+#define XIOU_SLCR_MIO_PIN_8    ( ( XIOU_SLCR_BASEADDR ) + 0x00000020UL )
+#define XIOU_SLCR_MIO_PIN_8_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin9
+ */
+#define XIOU_SLCR_MIO_PIN_9    ( ( XIOU_SLCR_BASEADDR ) + 0x00000024UL )
+#define XIOU_SLCR_MIO_PIN_9_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin10
+ */
+#define XIOU_SLCR_MIO_PIN_10    ( ( XIOU_SLCR_BASEADDR ) + 0x00000028UL )
+#define XIOU_SLCR_MIO_PIN_10_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin11
+ */
+#define XIOU_SLCR_MIO_PIN_11    ( ( XIOU_SLCR_BASEADDR ) + 0x0000002CUL )
+#define XIOU_SLCR_MIO_PIN_11_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin12
+ */
+#define XIOU_SLCR_MIO_PIN_12    ( ( XIOU_SLCR_BASEADDR ) + 0x00000030UL )
+#define XIOU_SLCR_MIO_PIN_12_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin13
+ */
+#define XIOU_SLCR_MIO_PIN_13    ( ( XIOU_SLCR_BASEADDR ) + 0x00000034UL )
+#define XIOU_SLCR_MIO_PIN_13_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin14
+ */
+#define XIOU_SLCR_MIO_PIN_14    ( ( XIOU_SLCR_BASEADDR ) + 0x00000038UL )
+#define XIOU_SLCR_MIO_PIN_14_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin15
+ */
+#define XIOU_SLCR_MIO_PIN_15    ( ( XIOU_SLCR_BASEADDR ) + 0x0000003CUL )
+#define XIOU_SLCR_MIO_PIN_15_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin16
+ */
+#define XIOU_SLCR_MIO_PIN_16    ( ( XIOU_SLCR_BASEADDR ) + 0x00000040UL )
+#define XIOU_SLCR_MIO_PIN_16_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin17
+ */
+#define XIOU_SLCR_MIO_PIN_17    ( ( XIOU_SLCR_BASEADDR ) + 0x00000044UL )
+#define XIOU_SLCR_MIO_PIN_17_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin18
+ */
+#define XIOU_SLCR_MIO_PIN_18    ( ( XIOU_SLCR_BASEADDR ) + 0x00000048UL )
+#define XIOU_SLCR_MIO_PIN_18_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin19
+ */
+#define XIOU_SLCR_MIO_PIN_19    ( ( XIOU_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XIOU_SLCR_MIO_PIN_19_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin20
+ */
+#define XIOU_SLCR_MIO_PIN_20    ( ( XIOU_SLCR_BASEADDR ) + 0x00000050UL )
+#define XIOU_SLCR_MIO_PIN_20_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin21
+ */
+#define XIOU_SLCR_MIO_PIN_21    ( ( XIOU_SLCR_BASEADDR ) + 0x00000054UL )
+#define XIOU_SLCR_MIO_PIN_21_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin22
+ */
+#define XIOU_SLCR_MIO_PIN_22    ( ( XIOU_SLCR_BASEADDR ) + 0x00000058UL )
+#define XIOU_SLCR_MIO_PIN_22_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin23
+ */
+#define XIOU_SLCR_MIO_PIN_23    ( ( XIOU_SLCR_BASEADDR ) + 0x0000005CUL )
+#define XIOU_SLCR_MIO_PIN_23_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin24
+ */
+#define XIOU_SLCR_MIO_PIN_24    ( ( XIOU_SLCR_BASEADDR ) + 0x00000060UL )
+#define XIOU_SLCR_MIO_PIN_24_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin25
+ */
+#define XIOU_SLCR_MIO_PIN_25    ( ( XIOU_SLCR_BASEADDR ) + 0x00000064UL )
+#define XIOU_SLCR_MIO_PIN_25_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin26
+ */
+#define XIOU_SLCR_MIO_PIN_26    ( ( XIOU_SLCR_BASEADDR ) + 0x00000068UL )
+#define XIOU_SLCR_MIO_PIN_26_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin27
+ */
+#define XIOU_SLCR_MIO_PIN_27    ( ( XIOU_SLCR_BASEADDR ) + 0x0000006CUL )
+#define XIOU_SLCR_MIO_PIN_27_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin28
+ */
+#define XIOU_SLCR_MIO_PIN_28    ( ( XIOU_SLCR_BASEADDR ) + 0x00000070UL )
+#define XIOU_SLCR_MIO_PIN_28_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin29
+ */
+#define XIOU_SLCR_MIO_PIN_29    ( ( XIOU_SLCR_BASEADDR ) + 0x00000074UL )
+#define XIOU_SLCR_MIO_PIN_29_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin30
+ */
+#define XIOU_SLCR_MIO_PIN_30    ( ( XIOU_SLCR_BASEADDR ) + 0x00000078UL )
+#define XIOU_SLCR_MIO_PIN_30_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin31
+ */
+#define XIOU_SLCR_MIO_PIN_31    ( ( XIOU_SLCR_BASEADDR ) + 0x0000007CUL )
+#define XIOU_SLCR_MIO_PIN_31_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin32
+ */
+#define XIOU_SLCR_MIO_PIN_32    ( ( XIOU_SLCR_BASEADDR ) + 0x00000080UL )
+#define XIOU_SLCR_MIO_PIN_32_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin33
+ */
+#define XIOU_SLCR_MIO_PIN_33    ( ( XIOU_SLCR_BASEADDR ) + 0x00000084UL )
+#define XIOU_SLCR_MIO_PIN_33_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin34
+ */
+#define XIOU_SLCR_MIO_PIN_34    ( ( XIOU_SLCR_BASEADDR ) + 0x00000088UL )
+#define XIOU_SLCR_MIO_PIN_34_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin35
+ */
+#define XIOU_SLCR_MIO_PIN_35    ( ( XIOU_SLCR_BASEADDR ) + 0x0000008CUL )
+#define XIOU_SLCR_MIO_PIN_35_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin36
+ */
+#define XIOU_SLCR_MIO_PIN_36    ( ( XIOU_SLCR_BASEADDR ) + 0x00000090UL )
+#define XIOU_SLCR_MIO_PIN_36_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin37
+ */
+#define XIOU_SLCR_MIO_PIN_37    ( ( XIOU_SLCR_BASEADDR ) + 0x00000094UL )
+#define XIOU_SLCR_MIO_PIN_37_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin38
+ */
+#define XIOU_SLCR_MIO_PIN_38    ( ( XIOU_SLCR_BASEADDR ) + 0x00000098UL )
+#define XIOU_SLCR_MIO_PIN_38_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin39
+ */
+#define XIOU_SLCR_MIO_PIN_39    ( ( XIOU_SLCR_BASEADDR ) + 0x0000009CUL )
+#define XIOU_SLCR_MIO_PIN_39_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin40
+ */
+#define XIOU_SLCR_MIO_PIN_40    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A0UL )
+#define XIOU_SLCR_MIO_PIN_40_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin41
+ */
+#define XIOU_SLCR_MIO_PIN_41    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A4UL )
+#define XIOU_SLCR_MIO_PIN_41_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin42
+ */
+#define XIOU_SLCR_MIO_PIN_42    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A8UL )
+#define XIOU_SLCR_MIO_PIN_42_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin43
+ */
+#define XIOU_SLCR_MIO_PIN_43    ( ( XIOU_SLCR_BASEADDR ) + 0x000000ACUL )
+#define XIOU_SLCR_MIO_PIN_43_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin44
+ */
+#define XIOU_SLCR_MIO_PIN_44    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B0UL )
+#define XIOU_SLCR_MIO_PIN_44_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin45
+ */
+#define XIOU_SLCR_MIO_PIN_45    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B4UL )
+#define XIOU_SLCR_MIO_PIN_45_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin46
+ */
+#define XIOU_SLCR_MIO_PIN_46    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B8UL )
+#define XIOU_SLCR_MIO_PIN_46_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin47
+ */
+#define XIOU_SLCR_MIO_PIN_47    ( ( XIOU_SLCR_BASEADDR ) + 0x000000BCUL )
+#define XIOU_SLCR_MIO_PIN_47_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin48
+ */
+#define XIOU_SLCR_MIO_PIN_48    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C0UL )
+#define XIOU_SLCR_MIO_PIN_48_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin49
+ */
+#define XIOU_SLCR_MIO_PIN_49    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C4UL )
+#define XIOU_SLCR_MIO_PIN_49_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin50
+ */
+#define XIOU_SLCR_MIO_PIN_50    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C8UL )
+#define XIOU_SLCR_MIO_PIN_50_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin51
+ */
+#define XIOU_SLCR_MIO_PIN_51    ( ( XIOU_SLCR_BASEADDR ) + 0x000000CCUL )
+#define XIOU_SLCR_MIO_PIN_51_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin52
+ */
+#define XIOU_SLCR_MIO_PIN_52    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D0UL )
+#define XIOU_SLCR_MIO_PIN_52_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin53
+ */
+#define XIOU_SLCR_MIO_PIN_53    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D4UL )
+#define XIOU_SLCR_MIO_PIN_53_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin54
+ */
+#define XIOU_SLCR_MIO_PIN_54    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D8UL )
+#define XIOU_SLCR_MIO_PIN_54_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin55
+ */
+#define XIOU_SLCR_MIO_PIN_55    ( ( XIOU_SLCR_BASEADDR ) + 0x000000DCUL )
+#define XIOU_SLCR_MIO_PIN_55_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin56
+ */
+#define XIOU_SLCR_MIO_PIN_56    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E0UL )
+#define XIOU_SLCR_MIO_PIN_56_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin57
+ */
+#define XIOU_SLCR_MIO_PIN_57    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E4UL )
+#define XIOU_SLCR_MIO_PIN_57_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin58
+ */
+#define XIOU_SLCR_MIO_PIN_58    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E8UL )
+#define XIOU_SLCR_MIO_PIN_58_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin59
+ */
+#define XIOU_SLCR_MIO_PIN_59    ( ( XIOU_SLCR_BASEADDR ) + 0x000000ECUL )
+#define XIOU_SLCR_MIO_PIN_59_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin60
+ */
+#define XIOU_SLCR_MIO_PIN_60    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F0UL )
+#define XIOU_SLCR_MIO_PIN_60_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin61
+ */
+#define XIOU_SLCR_MIO_PIN_61    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F4UL )
+#define XIOU_SLCR_MIO_PIN_61_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin62
+ */
+#define XIOU_SLCR_MIO_PIN_62    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F8UL )
+#define XIOU_SLCR_MIO_PIN_62_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin63
+ */
+#define XIOU_SLCR_MIO_PIN_63    ( ( XIOU_SLCR_BASEADDR ) + 0x000000FCUL )
+#define XIOU_SLCR_MIO_PIN_63_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin64
+ */
+#define XIOU_SLCR_MIO_PIN_64    ( ( XIOU_SLCR_BASEADDR ) + 0x00000100UL )
+#define XIOU_SLCR_MIO_PIN_64_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin65
+ */
+#define XIOU_SLCR_MIO_PIN_65    ( ( XIOU_SLCR_BASEADDR ) + 0x00000104UL )
+#define XIOU_SLCR_MIO_PIN_65_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin66
+ */
+#define XIOU_SLCR_MIO_PIN_66    ( ( XIOU_SLCR_BASEADDR ) + 0x00000108UL )
+#define XIOU_SLCR_MIO_PIN_66_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin67
+ */
+#define XIOU_SLCR_MIO_PIN_67    ( ( XIOU_SLCR_BASEADDR ) + 0x0000010CUL )
+#define XIOU_SLCR_MIO_PIN_67_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin68
+ */
+#define XIOU_SLCR_MIO_PIN_68    ( ( XIOU_SLCR_BASEADDR ) + 0x00000110UL )
+#define XIOU_SLCR_MIO_PIN_68_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin69
+ */
+#define XIOU_SLCR_MIO_PIN_69    ( ( XIOU_SLCR_BASEADDR ) + 0x00000114UL )
+#define XIOU_SLCR_MIO_PIN_69_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin70
+ */
+#define XIOU_SLCR_MIO_PIN_70    ( ( XIOU_SLCR_BASEADDR ) + 0x00000118UL )
+#define XIOU_SLCR_MIO_PIN_70_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin71
+ */
+#define XIOU_SLCR_MIO_PIN_71    ( ( XIOU_SLCR_BASEADDR ) + 0x0000011CUL )
+#define XIOU_SLCR_MIO_PIN_71_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin72
+ */
+#define XIOU_SLCR_MIO_PIN_72    ( ( XIOU_SLCR_BASEADDR ) + 0x00000120UL )
+#define XIOU_SLCR_MIO_PIN_72_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin73
+ */
+#define XIOU_SLCR_MIO_PIN_73    ( ( XIOU_SLCR_BASEADDR ) + 0x00000124UL )
+#define XIOU_SLCR_MIO_PIN_73_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin74
+ */
+#define XIOU_SLCR_MIO_PIN_74    ( ( XIOU_SLCR_BASEADDR ) + 0x00000128UL )
+#define XIOU_SLCR_MIO_PIN_74_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin75
+ */
+#define XIOU_SLCR_MIO_PIN_75    ( ( XIOU_SLCR_BASEADDR ) + 0x0000012CUL )
+#define XIOU_SLCR_MIO_PIN_75_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin76
+ */
+#define XIOU_SLCR_MIO_PIN_76    ( ( XIOU_SLCR_BASEADDR ) + 0x00000130UL )
+#define XIOU_SLCR_MIO_PIN_76_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin77
+ */
+#define XIOU_SLCR_MIO_PIN_77    ( ( XIOU_SLCR_BASEADDR ) + 0x00000134UL )
+#define XIOU_SLCR_MIO_PIN_77_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Ctrl0
+ */
+#define XIOU_SLCR_BANK0_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000138UL )
+#define XIOU_SLCR_BANK0_CTRL0_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank0Ctrl1
+ */
+#define XIOU_SLCR_BANK0_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000013CUL )
+#define XIOU_SLCR_BANK0_CTRL1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Ctrl3
+ */
+#define XIOU_SLCR_BANK0_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000140UL )
+#define XIOU_SLCR_BANK0_CTRL3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Ctrl4
+ */
+#define XIOU_SLCR_BANK0_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000144UL )
+#define XIOU_SLCR_BANK0_CTRL4_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank0Ctrl5
+ */
+#define XIOU_SLCR_BANK0_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000148UL )
+#define XIOU_SLCR_BANK0_CTRL5_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank0Ctrl6
+ */
+#define XIOU_SLCR_BANK0_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x0000014CUL )
+#define XIOU_SLCR_BANK0_CTRL6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Sts
+ */
+#define XIOU_SLCR_BANK0_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000150UL )
+#define XIOU_SLCR_BANK0_STS_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_SHIFT   0UL
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_WIDTH   1UL
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_MASK    0x00000001UL
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Ctrl0
+ */
+#define XIOU_SLCR_BANK1_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000154UL )
+#define XIOU_SLCR_BANK1_CTRL0_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank1Ctrl1
+ */
+#define XIOU_SLCR_BANK1_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000158UL )
+#define XIOU_SLCR_BANK1_CTRL1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Ctrl3
+ */
+#define XIOU_SLCR_BANK1_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000015CUL )
+#define XIOU_SLCR_BANK1_CTRL3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Ctrl4
+ */
+#define XIOU_SLCR_BANK1_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000160UL )
+#define XIOU_SLCR_BANK1_CTRL4_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank1Ctrl5
+ */
+#define XIOU_SLCR_BANK1_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000164UL )
+#define XIOU_SLCR_BANK1_CTRL5_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank1Ctrl6
+ */
+#define XIOU_SLCR_BANK1_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000168UL )
+#define XIOU_SLCR_BANK1_CTRL6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Sts
+ */
+#define XIOU_SLCR_BANK1_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x0000016CUL )
+#define XIOU_SLCR_BANK1_STS_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_SHIFT   0UL
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_WIDTH   1UL
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_MASK    0x00000001UL
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Ctrl0
+ */
+#define XIOU_SLCR_BANK2_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000170UL )
+#define XIOU_SLCR_BANK2_CTRL0_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank2Ctrl1
+ */
+#define XIOU_SLCR_BANK2_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000174UL )
+#define XIOU_SLCR_BANK2_CTRL1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Ctrl3
+ */
+#define XIOU_SLCR_BANK2_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000178UL )
+#define XIOU_SLCR_BANK2_CTRL3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Ctrl4
+ */
+#define XIOU_SLCR_BANK2_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x0000017CUL )
+#define XIOU_SLCR_BANK2_CTRL4_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank2Ctrl5
+ */
+#define XIOU_SLCR_BANK2_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000180UL )
+#define XIOU_SLCR_BANK2_CTRL5_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank2Ctrl6
+ */
+#define XIOU_SLCR_BANK2_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000184UL )
+#define XIOU_SLCR_BANK2_CTRL6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Sts
+ */
+#define XIOU_SLCR_BANK2_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000188UL )
+#define XIOU_SLCR_BANK2_STS_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_SHIFT   0UL
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_WIDTH   1UL
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_MASK    0x00000001UL
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioLpbck
+ */
+#define XIOU_SLCR_MIO_LPBCK    ( ( XIOU_SLCR_BASEADDR ) + 0x00000200UL )
+#define XIOU_SLCR_MIO_LPBCK_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_SHIFT   3UL
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT   2UL
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT   1UL
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_SHIFT   0UL
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioMstTri0
+ */
+#define XIOU_SLCR_MIO_MST_TRI0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000204UL )
+#define XIOU_SLCR_MIO_MST_TRI0_RSTVAL   0xffffffffUL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT   31UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK    0x80000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT   30UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK    0x40000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT   29UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK    0x20000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT   28UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK    0x10000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT   27UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK    0x08000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT   26UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK    0x04000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT   25UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK    0x02000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT   24UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK    0x01000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT   23UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK    0x00800000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT   22UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK    0x00400000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT   21UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK    0x00200000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT   20UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK    0x00100000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT   19UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK    0x00080000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT   18UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK    0x00040000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT   17UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK    0x00020000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT   16UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK    0x00010000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT   15UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK    0x00008000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT   14UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK    0x00004000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT   13UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK    0x00002000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT   12UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK    0x00001000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT   11UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK    0x00000800UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT   10UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK    0x00000400UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT   9UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK    0x00000200UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT   8UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK    0x00000100UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT   7UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK    0x00000080UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT   6UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK    0x00000040UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT   5UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK    0x00000020UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT   4UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK    0x00000010UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT   3UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT   2UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT   0UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrMioMstTri1
+ */
+#define XIOU_SLCR_MIO_MST_TRI1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000208UL )
+#define XIOU_SLCR_MIO_MST_TRI1_RSTVAL   0xffffffffUL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT   31UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK    0x80000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT   30UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK    0x40000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT   29UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK    0x20000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT   28UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK    0x10000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT   27UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK    0x08000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT   26UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK    0x04000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT   25UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK    0x02000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT   24UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK    0x01000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT   23UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK    0x00800000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT   22UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK    0x00400000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT   21UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK    0x00200000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT   20UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK    0x00100000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT   19UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK    0x00080000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT   18UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK    0x00040000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT   17UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK    0x00020000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT   16UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK    0x00010000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT   15UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK    0x00008000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT   14UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK    0x00004000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT   13UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK    0x00002000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT   12UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK    0x00001000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT   11UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK    0x00000800UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT   10UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK    0x00000400UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT   9UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK    0x00000200UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT   8UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK    0x00000100UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT   7UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK    0x00000080UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT   6UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK    0x00000040UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT   5UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK    0x00000020UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT   4UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK    0x00000010UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT   3UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT   2UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT   0UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrMioMstTri2
+ */
+#define XIOU_SLCR_MIO_MST_TRI2    ( ( XIOU_SLCR_BASEADDR ) + 0x0000020CUL )
+#define XIOU_SLCR_MIO_MST_TRI2_RSTVAL   0x00003fffUL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT   13UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK    0x00002000UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT   12UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK    0x00001000UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT   11UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK    0x00000800UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT   10UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK    0x00000400UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT   9UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK    0x00000200UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT   8UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK    0x00000100UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT   7UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK    0x00000080UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT   6UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK    0x00000040UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT   5UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK    0x00000020UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT   4UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK    0x00000010UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT   3UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT   2UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT   0UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrWdtClkSel
+ */
+#define XIOU_SLCR_WDT_CLK_SEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000300UL )
+#define XIOU_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_WDT_CLK_SEL_SHIFT   0UL
+#define XIOU_SLCR_WDT_CLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrCanMioCtrl
+ */
+#define XIOU_SLCR_CAN_MIO_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000304UL )
+#define XIOU_SLCR_CAN_MIO_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT   23UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK    0x00800000UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT   22UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK    0x00400000UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT   15UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH   7UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK    0x003f8000UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT   8UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK    0x00000100UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT   7UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK    0x00000080UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT   0UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH   7UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK    0x0000007fUL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrGemClkCtrl
+ */
+#define XIOU_SLCR_GEM_CLK_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000308UL )
+#define XIOU_SLCR_GEM_CLK_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT   22UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK    0x00400000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT   20UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH   2UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK    0x00300000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   18UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00040000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   17UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00020000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   16UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00010000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   15UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00008000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   13UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00002000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   12UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00001000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   11UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000800UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   10UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000400UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   8UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000100UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   7UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000080UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   6UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000040UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   5UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000020UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   3UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000008UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   2UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000004UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   0UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdioClkCtrl
+ */
+#define XIOU_SLCR_SDIO_CLK_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x0000030CUL )
+#define XIOU_SLCR_SDIO_CLK_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT   18UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_MASK    0x00040000UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT   17UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK    0x00020000UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT   2UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT   0UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH   2UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK    0x00000003UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrCtrlRegSd
+ */
+#define XIOU_SLCR_CTRL_REG_SD    ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL )
+#define XIOU_SLCR_CTRL_REG_SD_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT   15UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH   1UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK    0x00008000UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT   0UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH   1UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdItapdly
+ */
+#define XIOU_SLCR_SD_ITAPDLY    ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL )
+#define XIOU_SLCR_SD_ITAPDLY_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   25UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x02000000UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   24UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x01000000UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   16UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   9UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x00000200UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   8UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x00000100UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   0UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x000000ffUL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdOtapdlysel
+ */
+#define XIOU_SLCR_SD_OTAPDLYSEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL )
+#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   22UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00400000UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH   6UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK    0x003f0000UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   6UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00000040UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH   6UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK    0x0000003fUL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCfgReg1
+ */
+#define XIOU_SLCR_SD_CFG_REG1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL )
+#define XIOU_SLCR_SD_CFG_REG1_RSTVAL   0x32403240UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT   23UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK    0x7f800000UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   17UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x007e0000UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   16UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00010000UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT   7UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK    0x00007f80UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   1UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x0000007eUL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   0UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00000001UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCfgReg2
+ */
+#define XIOU_SLCR_SD_CFG_REG2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL )
+#define XIOU_SLCR_SD_CFG_REG2_RSTVAL   0x0ffc0ffcUL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   28UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x30000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT   27UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK    0x08000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT   26UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK    0x04000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT   25UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK    0x02000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT   24UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK    0x01000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT   23UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK    0x00800000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT   22UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK    0x00400000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT   21UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK    0x00200000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   20UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00100000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT   19UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK    0x00080000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT   18UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK    0x00040000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT   16UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK    0x00030000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   12UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x00003000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT   11UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK    0x00000800UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT   10UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK    0x00000400UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT   9UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK    0x00000200UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT   8UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK    0x00000100UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT   7UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK    0x00000080UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT   6UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK    0x00000040UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT   5UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK    0x00000020UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   4UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00000010UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT   3UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK    0x00000008UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK    0x00000004UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT   0UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK    0x00000003UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCfgReg3
+ */
+#define XIOU_SLCR_SD_CFG_REG3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL )
+#define XIOU_SLCR_SD_CFG_REG3_RSTVAL   0x06070607UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   26UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x04000000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT   22UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK    0x03c00000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT   21UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK    0x00200000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT   20UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK    0x00100000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT   19UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK    0x00080000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT   18UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK    0x00040000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT   17UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK    0x00020000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT   16UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK    0x00010000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   10UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x00000400UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT   6UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK    0x000003c0UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT   5UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK    0x00000020UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT   4UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK    0x00000010UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT   3UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK    0x00000008UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT   2UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK    0x00000004UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK    0x00000002UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT   0UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK    0x00000001UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrSdInitpreset
+ */
+#define XIOU_SLCR_SD_INITPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL )
+#define XIOU_SLCR_SD_INITPRESET_RSTVAL   0x01000100UL
+
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL  0x100UL
+
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL  0x100UL
+
+/**
+ * Register: XiouSlcrSdDsppreset
+ */
+#define XIOU_SLCR_SD_DSPPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL )
+#define XIOU_SLCR_SD_DSPPRESET_RSTVAL   0x00040004UL
+
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL  0x4UL
+
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL  0x4UL
+
+/**
+ * Register: XiouSlcrSdHspdpreset
+ */
+#define XIOU_SLCR_SD_HSPDPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL )
+#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL   0x00020002UL
+
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL  0x2UL
+
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL  0x2UL
+
+/**
+ * Register: XiouSlcrSdSdr12preset
+ */
+#define XIOU_SLCR_SD_SDR12PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL )
+#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL   0x00040004UL
+
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL  0x4UL
+
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL  0x4UL
+
+/**
+ * Register: XiouSlcrSdSdr25preset
+ */
+#define XIOU_SLCR_SD_SDR25PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL )
+#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL   0x00020002UL
+
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL  0x2UL
+
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL  0x2UL
+
+/**
+ * Register: XiouSlcrSdSdr50prset
+ */
+#define XIOU_SLCR_SD_SDR50PRSET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL )
+#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL   0x00010001UL
+
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   16UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   0UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrSdSdr104prst
+ */
+#define XIOU_SLCR_SD_SDR104PRST    ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL )
+#define XIOU_SLCR_SD_SDR104PRST_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   16UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   0UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdDdr50preset
+ */
+#define XIOU_SLCR_SD_DDR50PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL )
+#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL   0x00020002UL
+
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL  0x2UL
+
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL  0x2UL
+
+/**
+ * Register: XiouSlcrSdMaxcur1p8
+ */
+#define XIOU_SLCR_SD_MAXCUR1P8    ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL )
+#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdMaxcur3p0
+ */
+#define XIOU_SLCR_SD_MAXCUR3P0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL )
+#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdMaxcur3p3
+ */
+#define XIOU_SLCR_SD_MAXCUR3P3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL )
+#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdDllCtrl
+ */
+#define XIOU_SLCR_SD_DLL_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL )
+#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT   18UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK    0x00040000UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT   17UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00020000UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT   16UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK    0x00010000UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT   2UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK    0x00000004UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00000002UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT   0UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK    0x00000001UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCdnCtrl
+ */
+#define XIOU_SLCR_SD_CDN_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL )
+#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK    0x00010000UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK    0x00000001UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrGemCtrl
+ */
+#define XIOU_SLCR_GEM_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL )
+#define XIOU_SLCR_GEM_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   6UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x000000c0UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   4UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x00000030UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x0000000cUL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   0UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x00000003UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrTtcApbClk
+ */
+#define XIOU_SLCR_TTC_APB_CLK    ( ( XIOU_SLCR_BASEADDR ) + 0x00000380UL )
+#define XIOU_SLCR_TTC_APB_CLK_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT   6UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK    0x000000c0UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT   4UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK    0x00000030UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK    0x0000000cUL
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT   0UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK    0x00000003UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrTapdlyBypass
+ */
+#define XIOU_SLCR_TAPDLY_BYPASS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000390UL )
+#define XIOU_SLCR_TAPDLY_BYPASS_RSTVAL   0x00000007UL
+
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_SHIFT   2UL
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_WIDTH   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_MASK    0x00000004UL
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_DEFVAL  0x1UL
+
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_SHIFT   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_WIDTH   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_MASK    0x00000002UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_SHIFT   0UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_WIDTH   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_MASK    0x00000001UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrCoherentCtrl
+ */
+#define XIOU_SLCR_COHERENT_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000400UL )
+#define XIOU_SLCR_COHERENT_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT   28UL
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_MASK    0xf0000000UL
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_SHIFT   24UL
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK    0x0f000000UL
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT   20UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK    0x00f00000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT   16UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK    0x000f0000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   12UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x0000f000UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   8UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x00000f00UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x000000f0UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   0UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x0000000fUL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrVideoPssClkSel
+ */
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000404UL )
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_SHIFT   1UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_WIDTH   1UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_MASK    0x00000002UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_DEFVAL  0x0UL
+
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_SHIFT   0UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrInterconnectRoute
+ */
+#define XIOU_SLCR_INTERCONNECT_ROUTE    ( ( XIOU_SLCR_BASEADDR ) + 0x00000408UL )
+#define XIOU_SLCR_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_SHIFT   7UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_MASK    0x00000080UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_SHIFT   6UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK    0x00000040UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT   5UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK    0x00000020UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT   4UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK    0x00000010UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   3UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000008UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   2UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000004UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000002UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000001UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrRamXemacps
+ */
+#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL )
+#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXemacps
+ */
+#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL )
+#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXemacps
+ */
+#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL )
+#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXemacps
+ */
+#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL )
+#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXsdps
+ */
+#define XIOU_SLCR_RAM_XSDPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL )
+#define XIOU_SLCR_RAM_XSDPS_RSTVAL   0x0000005bUL
+
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXsdps
+ */
+#define XIOU_SLCR_RAM_XSDPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL )
+#define XIOU_SLCR_RAM_XSDPS_RSTVAL   0x0000005bUL
+
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamCan0
+ */
+#define XIOU_SLCR_RAM_CAN0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000518UL )
+#define XIOU_SLCR_RAM_CAN0_RSTVAL   0x005b5b5bUL
+
+#define XIOU_SLCR_RAM_CAN0_EMASA2_SHIFT   22UL
+#define XIOU_SLCR_RAM_CAN0_EMASA2_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN0_EMASA2_MASK    0x00400000UL
+#define XIOU_SLCR_RAM_CAN0_EMASA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAB2_SHIFT   19UL
+#define XIOU_SLCR_RAM_CAN0_EMAB2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB2_MASK    0x00380000UL
+#define XIOU_SLCR_RAM_CAN0_EMAB2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAA2_SHIFT   16UL
+#define XIOU_SLCR_RAM_CAN0_EMAA2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAA2_MASK    0x00070000UL
+#define XIOU_SLCR_RAM_CAN0_EMAA2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_CAN0_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN0_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_CAN0_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_CAN0_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_CAN0_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_CAN0_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_CAN0_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_CAN0_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN0_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_CAN0_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_CAN0_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_CAN0_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_CAN0_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamCan1
+ */
+#define XIOU_SLCR_RAM_CAN1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000051CUL )
+#define XIOU_SLCR_RAM_CAN1_RSTVAL   0x005b5b5bUL
+
+#define XIOU_SLCR_RAM_CAN1_EMASA2_SHIFT   22UL
+#define XIOU_SLCR_RAM_CAN1_EMASA2_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN1_EMASA2_MASK    0x00400000UL
+#define XIOU_SLCR_RAM_CAN1_EMASA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAB2_SHIFT   19UL
+#define XIOU_SLCR_RAM_CAN1_EMAB2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB2_MASK    0x00380000UL
+#define XIOU_SLCR_RAM_CAN1_EMAB2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAA2_SHIFT   16UL
+#define XIOU_SLCR_RAM_CAN1_EMAA2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAA2_MASK    0x00070000UL
+#define XIOU_SLCR_RAM_CAN1_EMAA2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_CAN1_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN1_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_CAN1_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_CAN1_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_CAN1_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_CAN1_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_CAN1_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_CAN1_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN1_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_CAN1_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_CAN1_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_CAN1_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_CAN1_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamLqspi
+ */
+#define XIOU_SLCR_RAM_LQSPI    ( ( XIOU_SLCR_BASEADDR ) + 0x00000520UL )
+#define XIOU_SLCR_RAM_LQSPI_RSTVAL   0x00002ddbUL
+
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_SHIFT   13UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_MASK    0x00002000UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_SHIFT   10UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_MASK    0x00001c00UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_SHIFT   7UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_MASK    0x00000380UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXnandps8
+ */
+#define XIOU_SLCR_RAM_XNANDPS8    ( ( XIOU_SLCR_BASEADDR ) + 0x00000524UL )
+#define XIOU_SLCR_RAM_XNANDPS8_RSTVAL   0x0000005bUL
+
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrCtrl
+ */
+#define XIOU_SLCR_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000600UL )
+#define XIOU_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XIOU_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XIOU_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrIsr
+ */
+#define XIOU_SLCR_ISR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000700UL )
+#define XIOU_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrImr
+ */
+#define XIOU_SLCR_IMR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000704UL )
+#define XIOU_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrIer
+ */
+#define XIOU_SLCR_IER    ( ( XIOU_SLCR_BASEADDR ) + 0x00000708UL )
+#define XIOU_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrIdr
+ */
+#define XIOU_SLCR_IDR    ( ( XIOU_SLCR_BASEADDR ) + 0x0000070CUL )
+#define XIOU_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrItr
+ */
+#define XIOU_SLCR_ITR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000710UL )
+#define XIOU_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XIOU_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_slcr.h
new file mode 100644
index 000000000..cc05672e4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_slcr.h
@@ -0,0 +1,5667 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_SLCR_H__
+#define __XLPD_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdSlcr Base Address
+ */
+#define XLPD_SLCR_BASEADDR      0xFF410000UL
+
+/**
+ * Register: XlpdSlcrWprot0
+ */
+#define XLPD_SLCR_WPROT0    ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL )
+#define XLPD_SLCR_WPROT0_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_WPROT0_ACT_SHIFT   0UL
+#define XLPD_SLCR_WPROT0_ACT_WIDTH   1UL
+#define XLPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
+#define XLPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrCtrl
+ */
+#define XLPD_SLCR_CTRL    ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL )
+#define XLPD_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XLPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsr
+ */
+#define XLPD_SLCR_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL )
+#define XLPD_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrImr
+ */
+#define XLPD_SLCR_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XLPD_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrIer
+ */
+#define XLPD_SLCR_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL )
+#define XLPD_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIdr
+ */
+#define XLPD_SLCR_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL )
+#define XLPD_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrItr
+ */
+#define XLPD_SLCR_ITR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL )
+#define XLPD_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk0
+ */
+#define XLPD_SLCR_SAFETY_CHK0    ( ( XLPD_SLCR_BASEADDR ) + 0x00000040UL )
+#define XLPD_SLCR_SAFETY_CHK0_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK0_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK0_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK0_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK0_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk1
+ */
+#define XLPD_SLCR_SAFETY_CHK1    ( ( XLPD_SLCR_BASEADDR ) + 0x00000044UL )
+#define XLPD_SLCR_SAFETY_CHK1_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK1_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK1_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK1_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK1_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk2
+ */
+#define XLPD_SLCR_SAFETY_CHK2    ( ( XLPD_SLCR_BASEADDR ) + 0x00000048UL )
+#define XLPD_SLCR_SAFETY_CHK2_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK2_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK2_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK2_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK2_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk3
+ */
+#define XLPD_SLCR_SAFETY_CHK3    ( ( XLPD_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XLPD_SLCR_SAFETY_CHK3_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK3_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK3_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK3_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK3_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrXcsupmuWdtClkSel
+ */
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL    ( ( XLPD_SLCR_BASEADDR ) + 0x00000050UL )
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_SHIFT   0UL
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_WIDTH   1UL
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_MASK    0x00000001UL
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAdmaCfg
+ */
+#define XLPD_SLCR_ADMA_CFG    ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL )
+#define XLPD_SLCR_ADMA_CFG_RSTVAL   0x00000028UL
+
+#define XLPD_SLCR_ADMA_CFG_BUSWID_SHIFT   5UL
+#define XLPD_SLCR_ADMA_CFG_BUSWID_WIDTH   2UL
+#define XLPD_SLCR_ADMA_CFG_BUSWID_MASK    0x00000060UL
+#define XLPD_SLCR_ADMA_CFG_BUSWID_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT   0UL
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH   5UL
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK    0x0000001fUL
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL  0x8UL
+
+/**
+ * Register: XlpdSlcrAdmaRam
+ */
+#define XLPD_SLCR_ADMA_RAM    ( ( XLPD_SLCR_BASEADDR ) + 0x00002010UL )
+#define XLPD_SLCR_ADMA_RAM_RSTVAL   0x00003b3bUL
+
+#define XLPD_SLCR_ADMA_RAM1_EMAB_SHIFT   12UL
+#define XLPD_SLCR_ADMA_RAM1_EMAB_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM1_EMAB_MASK    0x00007000UL
+#define XLPD_SLCR_ADMA_RAM1_EMAB_DEFVAL  0x3UL
+
+#define XLPD_SLCR_ADMA_RAM1_EMASA_SHIFT   11UL
+#define XLPD_SLCR_ADMA_RAM1_EMASA_WIDTH   1UL
+#define XLPD_SLCR_ADMA_RAM1_EMASA_MASK    0x00000800UL
+#define XLPD_SLCR_ADMA_RAM1_EMASA_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ADMA_RAM1_EMAA_SHIFT   8UL
+#define XLPD_SLCR_ADMA_RAM1_EMAA_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM1_EMAA_MASK    0x00000700UL
+#define XLPD_SLCR_ADMA_RAM1_EMAA_DEFVAL  0x3UL
+
+#define XLPD_SLCR_ADMA_RAM0_EMAB_SHIFT   4UL
+#define XLPD_SLCR_ADMA_RAM0_EMAB_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM0_EMAB_MASK    0x00000070UL
+#define XLPD_SLCR_ADMA_RAM0_EMAB_DEFVAL  0x3UL
+
+#define XLPD_SLCR_ADMA_RAM0_EMASA_SHIFT   3UL
+#define XLPD_SLCR_ADMA_RAM0_EMASA_WIDTH   1UL
+#define XLPD_SLCR_ADMA_RAM0_EMASA_MASK    0x00000008UL
+#define XLPD_SLCR_ADMA_RAM0_EMASA_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ADMA_RAM0_EMAA_SHIFT   0UL
+#define XLPD_SLCR_ADMA_RAM0_EMAA_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM0_EMAA_MASK    0x00000007UL
+#define XLPD_SLCR_ADMA_RAM0_EMAA_DEFVAL  0x3UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiIsr
+ */
+#define XLPD_SLCR_ERR_AIBAXI_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003000UL )
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiImr
+ */
+#define XLPD_SLCR_ERR_AIBAXI_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003008UL )
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RSTVAL   0x1dcf000fUL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiIer
+ */
+#define XLPD_SLCR_ERR_AIBAXI_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00003010UL )
+#define XLPD_SLCR_ERR_AIBAXI_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiIdr
+ */
+#define XLPD_SLCR_ERR_AIBAXI_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003018UL )
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibapbIsr
+ */
+#define XLPD_SLCR_ERR_AIBAPB_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003020UL )
+#define XLPD_SLCR_ERR_AIBAPB_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibapbImr
+ */
+#define XLPD_SLCR_ERR_AIBAPB_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003024UL )
+#define XLPD_SLCR_ERR_AIBAPB_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrErrAibapbIer
+ */
+#define XLPD_SLCR_ERR_AIBAPB_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00003028UL )
+#define XLPD_SLCR_ERR_AIBAPB_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibapbIdr
+ */
+#define XLPD_SLCR_ERR_AIBAPB_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000302CUL )
+#define XLPD_SLCR_ERR_AIBAPB_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibaxiReq
+ */
+#define XLPD_SLCR_ISO_AIBAXI_REQ    ( ( XLPD_SLCR_BASEADDR ) + 0x00003030UL )
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_SHIFT   27UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibaxiType
+ */
+#define XLPD_SLCR_ISO_AIBAXI_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x00003038UL )
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RSTVAL   0x19cf000fUL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_SHIFT   27UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrIsoAibaxiAck
+ */
+#define XLPD_SLCR_ISO_AIBAXI_ACK    ( ( XLPD_SLCR_BASEADDR ) + 0x00003040UL )
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_SHIFT   27UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibapbReq
+ */
+#define XLPD_SLCR_ISO_AIBAPB_REQ    ( ( XLPD_SLCR_BASEADDR ) + 0x00003048UL )
+#define XLPD_SLCR_ISO_AIBAPB_REQ_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibapbType
+ */
+#define XLPD_SLCR_ISO_AIBAPB_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x0000304CUL )
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrIsoAibapbAck
+ */
+#define XLPD_SLCR_ISO_AIBAPB_ACK    ( ( XLPD_SLCR_BASEADDR ) + 0x00003050UL )
+#define XLPD_SLCR_ISO_AIBAPB_ACK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAtbIsr
+ */
+#define XLPD_SLCR_ERR_ATB_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00006000UL )
+#define XLPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAtbImr
+ */
+#define XLPD_SLCR_ERR_ATB_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00006004UL )
+#define XLPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrErrAtbIer
+ */
+#define XLPD_SLCR_ERR_ATB_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00006008UL )
+#define XLPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAtbIdr
+ */
+#define XLPD_SLCR_ERR_ATB_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000600CUL )
+#define XLPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAtbCmdStoreEn
+ */
+#define XLPD_SLCR_ATB_CMD_STORE_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00006010UL )
+#define XLPD_SLCR_ATB_CMD_STORE_EN_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrAtbRespEn
+ */
+#define XLPD_SLCR_ATB_RESP_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00006014UL )
+#define XLPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAtbRespType
+ */
+#define XLPD_SLCR_ATB_RESP_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x00006018UL )
+#define XLPD_SLCR_ATB_RESP_TYPE_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrAtbPrescale
+ */
+#define XLPD_SLCR_ATB_PRESCALE    ( ( XLPD_SLCR_BASEADDR ) + 0x00006020UL )
+#define XLPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
+
+#define XLPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
+#define XLPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
+#define XLPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
+#define XLPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
+#define XLPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
+#define XLPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
+#define XLPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
+
+/**
+ * Register: XlpdSlcrMutex0
+ */
+#define XLPD_SLCR_MUTEX0    ( ( XLPD_SLCR_BASEADDR ) + 0x00007000UL )
+#define XLPD_SLCR_MUTEX0_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX0_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX0_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX0_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX0_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrMutex1
+ */
+#define XLPD_SLCR_MUTEX1    ( ( XLPD_SLCR_BASEADDR ) + 0x00007004UL )
+#define XLPD_SLCR_MUTEX1_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX1_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX1_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX1_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX1_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrMutex2
+ */
+#define XLPD_SLCR_MUTEX2    ( ( XLPD_SLCR_BASEADDR ) + 0x00007008UL )
+#define XLPD_SLCR_MUTEX2_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX2_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX2_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX2_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX2_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrMutex3
+ */
+#define XLPD_SLCR_MUTEX3    ( ( XLPD_SLCR_BASEADDR ) + 0x0000700CUL )
+#define XLPD_SLCR_MUTEX3_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX3_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX3_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX3_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX3_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqSts
+ */
+#define XLPD_SLCR_GICP0_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008000UL )
+#define XLPD_SLCR_GICP0_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqMsk
+ */
+#define XLPD_SLCR_GICP0_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008004UL )
+#define XLPD_SLCR_GICP0_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqEn
+ */
+#define XLPD_SLCR_GICP0_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008008UL )
+#define XLPD_SLCR_GICP0_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqDis
+ */
+#define XLPD_SLCR_GICP0_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000800CUL )
+#define XLPD_SLCR_GICP0_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqTrig
+ */
+#define XLPD_SLCR_GICP0_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008010UL )
+#define XLPD_SLCR_GICP0_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqSts
+ */
+#define XLPD_SLCR_GICP1_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008014UL )
+#define XLPD_SLCR_GICP1_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqMsk
+ */
+#define XLPD_SLCR_GICP1_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008018UL )
+#define XLPD_SLCR_GICP1_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqEn
+ */
+#define XLPD_SLCR_GICP1_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x0000801CUL )
+#define XLPD_SLCR_GICP1_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqDis
+ */
+#define XLPD_SLCR_GICP1_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008020UL )
+#define XLPD_SLCR_GICP1_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqTrig
+ */
+#define XLPD_SLCR_GICP1_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008024UL )
+#define XLPD_SLCR_GICP1_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqSts
+ */
+#define XLPD_SLCR_GICP2_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008028UL )
+#define XLPD_SLCR_GICP2_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqMsk
+ */
+#define XLPD_SLCR_GICP2_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x0000802CUL )
+#define XLPD_SLCR_GICP2_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqEn
+ */
+#define XLPD_SLCR_GICP2_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008030UL )
+#define XLPD_SLCR_GICP2_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqDis
+ */
+#define XLPD_SLCR_GICP2_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008034UL )
+#define XLPD_SLCR_GICP2_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqTrig
+ */
+#define XLPD_SLCR_GICP2_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008038UL )
+#define XLPD_SLCR_GICP2_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqSts
+ */
+#define XLPD_SLCR_GICP3_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000803CUL )
+#define XLPD_SLCR_GICP3_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqMsk
+ */
+#define XLPD_SLCR_GICP3_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008040UL )
+#define XLPD_SLCR_GICP3_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqEn
+ */
+#define XLPD_SLCR_GICP3_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008044UL )
+#define XLPD_SLCR_GICP3_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqDis
+ */
+#define XLPD_SLCR_GICP3_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008048UL )
+#define XLPD_SLCR_GICP3_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqTrig
+ */
+#define XLPD_SLCR_GICP3_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x0000804CUL )
+#define XLPD_SLCR_GICP3_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqSts
+ */
+#define XLPD_SLCR_GICP4_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008050UL )
+#define XLPD_SLCR_GICP4_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqMsk
+ */
+#define XLPD_SLCR_GICP4_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008054UL )
+#define XLPD_SLCR_GICP4_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqEn
+ */
+#define XLPD_SLCR_GICP4_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008058UL )
+#define XLPD_SLCR_GICP4_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqDis
+ */
+#define XLPD_SLCR_GICP4_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000805CUL )
+#define XLPD_SLCR_GICP4_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqTrig
+ */
+#define XLPD_SLCR_GICP4_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008060UL )
+#define XLPD_SLCR_GICP4_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqSts
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A0UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqMsk
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A4UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_RSTVAL   0x000000ffUL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqEn
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A8UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqDis
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x000080ACUL )
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqTrig
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x000080B0UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAfiFs
+ */
+#define XLPD_SLCR_AFI_FS    ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL )
+#define XLPD_SLCR_AFI_FS_RSTVAL   0x00000200UL
+
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT   8UL
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH   2UL
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK    0x00000300UL
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL  0x2UL
+
+/**
+ * Register: XlpdSlcrCci
+ */
+#define XLPD_SLCR_CCI    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL )
+#define XLPD_SLCR_CCI_RSTVAL   0x03801c07UL
+
+#define XLPD_SLCR_CCI_SPR_SHIFT   28UL
+#define XLPD_SLCR_CCI_SPR_WIDTH   4UL
+#define XLPD_SLCR_CCI_SPR_MASK    0xf0000000UL
+#define XLPD_SLCR_CCI_SPR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVNVNETS4_SHIFT   27UL
+#define XLPD_SLCR_CCI_QVNVNETS4_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS4_MASK    0x08000000UL
+#define XLPD_SLCR_CCI_QVNVNETS4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVNVNETS3_SHIFT   26UL
+#define XLPD_SLCR_CCI_QVNVNETS3_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS3_MASK    0x04000000UL
+#define XLPD_SLCR_CCI_QVNVNETS3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVNVNETS2_SHIFT   25UL
+#define XLPD_SLCR_CCI_QVNVNETS2_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS2_MASK    0x02000000UL
+#define XLPD_SLCR_CCI_QVNVNETS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_QVNVNETS1_SHIFT   24UL
+#define XLPD_SLCR_CCI_QVNVNETS1_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS1_MASK    0x01000000UL
+#define XLPD_SLCR_CCI_QVNVNETS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_QVNVNETS0_SHIFT   23UL
+#define XLPD_SLCR_CCI_QVNVNETS0_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS0_MASK    0x00800000UL
+#define XLPD_SLCR_CCI_QVNVNETS0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_QOS_OVRRD_SHIFT   18UL
+#define XLPD_SLCR_CCI_QOS_OVRRD_WIDTH   5UL
+#define XLPD_SLCR_CCI_QOS_OVRRD_MASK    0x007c0000UL
+#define XLPD_SLCR_CCI_QOS_OVRRD_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVN_EN_M2_SHIFT   17UL
+#define XLPD_SLCR_CCI_QVN_EN_M2_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVN_EN_M2_MASK    0x00020000UL
+#define XLPD_SLCR_CCI_QVN_EN_M2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVN_EN_M1_SHIFT   16UL
+#define XLPD_SLCR_CCI_QVN_EN_M1_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVN_EN_M1_MASK    0x00010000UL
+#define XLPD_SLCR_CCI_QVN_EN_M1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_STRPG_GRAN_SHIFT   13UL
+#define XLPD_SLCR_CCI_STRPG_GRAN_WIDTH   3UL
+#define XLPD_SLCR_CCI_STRPG_GRAN_MASK    0x0000e000UL
+#define XLPD_SLCR_CCI_STRPG_GRAN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ACCHNLLEN4_SHIFT   12UL
+#define XLPD_SLCR_CCI_ACCHNLLEN4_WIDTH   1UL
+#define XLPD_SLCR_CCI_ACCHNLLEN4_MASK    0x00001000UL
+#define XLPD_SLCR_CCI_ACCHNLLEN4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_ACCHNLLEN3_SHIFT   11UL
+#define XLPD_SLCR_CCI_ACCHNLLEN3_WIDTH   1UL
+#define XLPD_SLCR_CCI_ACCHNLLEN3_MASK    0x00000800UL
+#define XLPD_SLCR_CCI_ACCHNLLEN3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_ACCHNLLEN0_SHIFT   10UL
+#define XLPD_SLCR_CCI_ACCHNLLEN0_WIDTH   1UL
+#define XLPD_SLCR_CCI_ACCHNLLEN0_MASK    0x00000400UL
+#define XLPD_SLCR_CCI_ACCHNLLEN0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_ECOREVNUM_SHIFT   6UL
+#define XLPD_SLCR_CCI_ECOREVNUM_WIDTH   4UL
+#define XLPD_SLCR_CCI_ECOREVNUM_MASK    0x000003c0UL
+#define XLPD_SLCR_CCI_ECOREVNUM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ASA2_SHIFT   5UL
+#define XLPD_SLCR_CCI_ASA2_WIDTH   1UL
+#define XLPD_SLCR_CCI_ASA2_MASK    0x00000020UL
+#define XLPD_SLCR_CCI_ASA2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ASA1_SHIFT   4UL
+#define XLPD_SLCR_CCI_ASA1_WIDTH   1UL
+#define XLPD_SLCR_CCI_ASA1_MASK    0x00000010UL
+#define XLPD_SLCR_CCI_ASA1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ASA0_SHIFT   3UL
+#define XLPD_SLCR_CCI_ASA0_WIDTH   1UL
+#define XLPD_SLCR_CCI_ASA0_MASK    0x00000008UL
+#define XLPD_SLCR_CCI_ASA0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_OWO2_SHIFT   2UL
+#define XLPD_SLCR_CCI_OWO2_WIDTH   1UL
+#define XLPD_SLCR_CCI_OWO2_MASK    0x00000004UL
+#define XLPD_SLCR_CCI_OWO2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_OWO1_SHIFT   1UL
+#define XLPD_SLCR_CCI_OWO1_WIDTH   1UL
+#define XLPD_SLCR_CCI_OWO1_MASK    0x00000002UL
+#define XLPD_SLCR_CCI_OWO1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_OWO0_SHIFT   0UL
+#define XLPD_SLCR_CCI_OWO0_WIDTH   1UL
+#define XLPD_SLCR_CCI_OWO0_MASK    0x00000001UL
+#define XLPD_SLCR_CCI_OWO0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrCciAddrmap
+ */
+#define XLPD_SLCR_CCI_ADDRMAP    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL )
+#define XLPD_SLCR_CCI_ADDRMAP_RSTVAL   0x00c000ffUL
+
+#define XLPD_SLCR_CCI_ADDRMAP_15_SHIFT   30UL
+#define XLPD_SLCR_CCI_ADDRMAP_15_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_15_MASK    0xc0000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_14_SHIFT   28UL
+#define XLPD_SLCR_CCI_ADDRMAP_14_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_14_MASK    0x30000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_13_SHIFT   26UL
+#define XLPD_SLCR_CCI_ADDRMAP_13_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_13_MASK    0x0c000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_12_SHIFT   24UL
+#define XLPD_SLCR_CCI_ADDRMAP_12_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_12_MASK    0x03000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_11_SHIFT   22UL
+#define XLPD_SLCR_CCI_ADDRMAP_11_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_11_MASK    0x00c00000UL
+#define XLPD_SLCR_CCI_ADDRMAP_11_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_10_SHIFT   20UL
+#define XLPD_SLCR_CCI_ADDRMAP_10_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_10_MASK    0x00300000UL
+#define XLPD_SLCR_CCI_ADDRMAP_10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_9_SHIFT   18UL
+#define XLPD_SLCR_CCI_ADDRMAP_9_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_9_MASK    0x000c0000UL
+#define XLPD_SLCR_CCI_ADDRMAP_9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_8_SHIFT   16UL
+#define XLPD_SLCR_CCI_ADDRMAP_8_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_8_MASK    0x00030000UL
+#define XLPD_SLCR_CCI_ADDRMAP_8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_7_SHIFT   14UL
+#define XLPD_SLCR_CCI_ADDRMAP_7_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_7_MASK    0x0000c000UL
+#define XLPD_SLCR_CCI_ADDRMAP_7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_6_SHIFT   12UL
+#define XLPD_SLCR_CCI_ADDRMAP_6_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_6_MASK    0x00003000UL
+#define XLPD_SLCR_CCI_ADDRMAP_6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_5_SHIFT   10UL
+#define XLPD_SLCR_CCI_ADDRMAP_5_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_5_MASK    0x00000c00UL
+#define XLPD_SLCR_CCI_ADDRMAP_5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_4_SHIFT   8UL
+#define XLPD_SLCR_CCI_ADDRMAP_4_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_4_MASK    0x00000300UL
+#define XLPD_SLCR_CCI_ADDRMAP_4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_3_SHIFT   6UL
+#define XLPD_SLCR_CCI_ADDRMAP_3_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_3_MASK    0x000000c0UL
+#define XLPD_SLCR_CCI_ADDRMAP_3_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_2_SHIFT   4UL
+#define XLPD_SLCR_CCI_ADDRMAP_2_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_2_MASK    0x00000030UL
+#define XLPD_SLCR_CCI_ADDRMAP_2_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_1_SHIFT   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_1_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_1_MASK    0x0000000cUL
+#define XLPD_SLCR_CCI_ADDRMAP_1_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_0_SHIFT   0UL
+#define XLPD_SLCR_CCI_ADDRMAP_0_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_0_MASK    0x00000003UL
+#define XLPD_SLCR_CCI_ADDRMAP_0_DEFVAL  0x3UL
+
+/**
+ * Register: XlpdSlcrCciQvnprealloc
+ */
+#define XLPD_SLCR_CCI_QVNPREALLOC    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL )
+#define XLPD_SLCR_CCI_QVNPREALLOC_RSTVAL   0x00330330UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_SHIFT   20UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_MASK    0x00f00000UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_SHIFT   16UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_MASK    0x000f0000UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_SHIFT   8UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_MASK    0x00000f00UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_SHIFT   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_MASK    0x000000f0UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_DEFVAL  0x3UL
+
+/**
+ * Register: XlpdSlcrSmmu
+ */
+#define XLPD_SLCR_SMMU    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL )
+#define XLPD_SLCR_SMMU_RSTVAL   0x0000003fUL
+
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_SHIFT   7UL
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_WIDTH   1UL
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_MASK    0x00000080UL
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SMMU_CTTW_SHIFT   6UL
+#define XLPD_SLCR_SMMU_CTTW_WIDTH   1UL
+#define XLPD_SLCR_SMMU_CTTW_MASK    0x00000040UL
+#define XLPD_SLCR_SMMU_CTTW_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_SHIFT   5UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_MASK    0x00000020UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_SHIFT   4UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_MASK    0x00000010UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_SHIFT   3UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_MASK    0x00000008UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_SHIFT   2UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_MASK    0x00000004UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_SHIFT   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_MASK    0x00000002UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_SHIFT   0UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_MASK    0x00000001UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrApu
+ */
+#define XLPD_SLCR_APU    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL )
+#define XLPD_SLCR_APU_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT   3UL
+#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_BARRIER_MASK    0x00000008UL
+#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL  0x0UL
+
+#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT   2UL
+#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_CMNT_MASK    0x00000004UL
+#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL  0x0UL
+
+#define XLPD_SLCR_APU_BRDC_INNER_SHIFT   1UL
+#define XLPD_SLCR_APU_BRDC_INNER_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_INNER_MASK    0x00000002UL
+#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL  0x0UL
+
+#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT   0UL
+#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_OUTER_MASK    0x00000001UL
+#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL  0x1UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_slcr_secure.h
new file mode 100644
index 000000000..aff3bf2fa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_slcr_secure.h
@@ -0,0 +1,141 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_SLCR_SECURE_H__
+#define __XLPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdSlcrSecure Base Address
+ */
+#define XLPD_SLCR_SECURE_BASEADDR      0xFF4B0000UL
+
+/**
+ * Register: XlpdSlcrSecCtrl
+ */
+#define XLPD_SLCR_SEC_CTRL    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XLPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIsr
+ */
+#define XLPD_SLCR_SEC_ISR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XLPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecImr
+ */
+#define XLPD_SLCR_SEC_IMR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XLPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrSecIer
+ */
+#define XLPD_SLCR_SEC_IER    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XLPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIdr
+ */
+#define XLPD_SLCR_SEC_IDR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XLPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecItr
+ */
+#define XLPD_SLCR_SEC_ITR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XLPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecRpu
+ */
+#define XLPD_SLCR_SEC_RPU    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XLPD_SLCR_SEC_RPU_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecAdma
+ */
+#define XLPD_SLCR_SEC_ADMA    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
+#define XLPD_SLCR_SEC_ADMA_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT   0UL
+#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH   8UL
+#define XLPD_SLCR_SEC_ADMA_TZ_MASK    0x000000ffUL
+#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecSafetyChk
+ */
+#define XLPD_SLCR_SEC_SAFETY_CHK    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT   0UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH   32UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecUsb
+ */
+#define XLPD_SLCR_SEC_USB    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
+#define XLPD_SLCR_SEC_USB_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL  0x1UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_xppu.h
new file mode 100644
index 000000000..a5145eac7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_xppu.h
@@ -0,0 +1,858 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_H__
+#define __XLPD_XPPU_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppu Base Address
+ */
+#define XLPD_XPPU_BASEADDR      0xFF980000UL
+
+/**
+ * Register: XlpdXppuCtrl
+ */
+#define XLPD_XPPU_CTRL    ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL )
+#define XLPD_XPPU_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT   2UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK    0x00000004UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK    0x00000002UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_EN_SHIFT   0UL
+#define XLPD_XPPU_CTRL_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_EN_MASK    0x00000001UL
+#define XLPD_XPPU_CTRL_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts1
+ */
+#define XLPD_XPPU_ERR_STS1    ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL )
+#define XLPD_XPPU_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts2
+ */
+#define XLPD_XPPU_ERR_STS2    ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL )
+#define XLPD_XPPU_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuPoison
+ */
+#define XLPD_XPPU_POISON    ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL )
+#define XLPD_XPPU_POISON_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_POISON_BASE_SHIFT   0UL
+#define XLPD_XPPU_POISON_BASE_WIDTH   20UL
+#define XLPD_XPPU_POISON_BASE_MASK    0x000fffffUL
+#define XLPD_XPPU_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIsr
+ */
+#define XLPD_XPPU_ISR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL )
+#define XLPD_XPPU_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ISR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_ISR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_ISR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_ISR_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_ISR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_ISR_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_ISR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_ISR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_ISR_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_ISR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_ISR_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_ISR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_ISR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuImr
+ */
+#define XLPD_XPPU_IMR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL )
+#define XLPD_XPPU_IMR_RSTVAL   0x000000efUL
+
+#define XLPD_XPPU_IMR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IMR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IMR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IMR_APER_TZ_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IMR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IMR_APER_PERM_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IMR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IMR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IMR_MID_RO_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IMR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IMR_MID_MISS_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IMR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IMR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuIen
+ */
+#define XLPD_XPPU_IEN    ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL )
+#define XLPD_XPPU_IEN_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IEN_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IEN_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IEN_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IEN_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IEN_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IEN_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IEN_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IEN_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IEN_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IEN_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IEN_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IEN_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IEN_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIds
+ */
+#define XLPD_XPPU_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL )
+#define XLPD_XPPU_IDS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IDS_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IDS_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IDS_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IDS_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IDS_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IDS_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IDS_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IDS_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IDS_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IDS_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IDS_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IDS_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IDS_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMMstrIds
+ */
+#define XLPD_XPPU_M_MSTR_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL )
+#define XLPD_XPPU_M_MSTR_IDS_RSTVAL   0x00000014UL
+
+#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT   0UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH   32UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL  0x14UL
+
+/**
+ * Register: XlpdXppuMAperture32b
+ */
+#define XLPD_XPPU_M_APERTURE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL )
+#define XLPD_XPPU_M_APERTURE_32B_RSTVAL   0x00000080UL
+
+#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMAperture64kb
+ */
+#define XLPD_XPPU_M_APERTURE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL )
+#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL   0x00000100UL
+
+#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL  0x100UL
+
+/**
+ * Register: XlpdXppuMAperture1mb
+ */
+#define XLPD_XPPU_M_APERTURE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL )
+#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL   0x00000010UL
+
+#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMAperture512mb
+ */
+#define XLPD_XPPU_M_APERTURE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL )
+#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuBase32b
+ */
+#define XLPD_XPPU_BASE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL )
+#define XLPD_XPPU_BASE_32B_RSTVAL   0xff990000UL
+
+#define XLPD_XPPU_BASE_32B_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_32B_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_32B_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL  0xff990000UL
+
+/**
+ * Register: XlpdXppuBase64kb
+ */
+#define XLPD_XPPU_BASE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL )
+#define XLPD_XPPU_BASE_64KB_RSTVAL   0xff000000UL
+
+#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_64KB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL  0xff000000UL
+
+/**
+ * Register: XlpdXppuBase1mb
+ */
+#define XLPD_XPPU_BASE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL )
+#define XLPD_XPPU_BASE_1MB_RSTVAL   0xfe000000UL
+
+#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_1MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL  0xfe000000UL
+
+/**
+ * Register: XlpdXppuBase512mb
+ */
+#define XLPD_XPPU_BASE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL )
+#define XLPD_XPPU_BASE_512MB_RSTVAL   0xc0000000UL
+
+#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_512MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL  0xc0000000UL
+
+/**
+ * Register: XlpdXppuMstrId00
+ */
+#define XLPD_XPPU_MSTR_ID00    ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL )
+#define XLPD_XPPU_MSTR_ID00_RSTVAL   0x83ff0040UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL  0x3ffUL
+
+#define XLPD_XPPU_MSTR_ID00_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID00_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL  0x40UL
+
+/**
+ * Register: XlpdXppuMstrId01
+ */
+#define XLPD_XPPU_MSTR_ID01    ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL )
+#define XLPD_XPPU_MSTR_ID01_RSTVAL   0x03f00000UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID01_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID01_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId02
+ */
+#define XLPD_XPPU_MSTR_ID02    ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL )
+#define XLPD_XPPU_MSTR_ID02_RSTVAL   0x83f00010UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID02_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID02_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMstrId03
+ */
+#define XLPD_XPPU_MSTR_ID03    ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL )
+#define XLPD_XPPU_MSTR_ID03_RSTVAL   0x83c00080UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL  0x3c0UL
+
+#define XLPD_XPPU_MSTR_ID03_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID03_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId04
+ */
+#define XLPD_XPPU_MSTR_ID04    ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL )
+#define XLPD_XPPU_MSTR_ID04_RSTVAL   0x83c30080UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID04_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID04_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId05
+ */
+#define XLPD_XPPU_MSTR_ID05    ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL )
+#define XLPD_XPPU_MSTR_ID05_RSTVAL   0x03c30081UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID05_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID05_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL  0x81UL
+
+/**
+ * Register: XlpdXppuMstrId06
+ */
+#define XLPD_XPPU_MSTR_ID06    ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL )
+#define XLPD_XPPU_MSTR_ID06_RSTVAL   0x03c30082UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID06_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID06_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL  0x82UL
+
+/**
+ * Register: XlpdXppuMstrId07
+ */
+#define XLPD_XPPU_MSTR_ID07    ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL )
+#define XLPD_XPPU_MSTR_ID07_RSTVAL   0x83c30083UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID07_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID07_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL  0x83UL
+
+/**
+ * Register: XlpdXppuMstrId08
+ */
+#define XLPD_XPPU_MSTR_ID08    ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL )
+#define XLPD_XPPU_MSTR_ID08_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID08_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId09
+ */
+#define XLPD_XPPU_MSTR_ID09    ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL )
+#define XLPD_XPPU_MSTR_ID09_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID09_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId10
+ */
+#define XLPD_XPPU_MSTR_ID10    ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL )
+#define XLPD_XPPU_MSTR_ID10_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID10_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId11
+ */
+#define XLPD_XPPU_MSTR_ID11    ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL )
+#define XLPD_XPPU_MSTR_ID11_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID11_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId12
+ */
+#define XLPD_XPPU_MSTR_ID12    ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL )
+#define XLPD_XPPU_MSTR_ID12_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID12_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId13
+ */
+#define XLPD_XPPU_MSTR_ID13    ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL )
+#define XLPD_XPPU_MSTR_ID13_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID13_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId14
+ */
+#define XLPD_XPPU_MSTR_ID14    ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL )
+#define XLPD_XPPU_MSTR_ID14_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID14_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId15
+ */
+#define XLPD_XPPU_MSTR_ID15    ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL )
+#define XLPD_XPPU_MSTR_ID15_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID15_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId16
+ */
+#define XLPD_XPPU_MSTR_ID16    ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL )
+#define XLPD_XPPU_MSTR_ID16_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID16_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId17
+ */
+#define XLPD_XPPU_MSTR_ID17    ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL )
+#define XLPD_XPPU_MSTR_ID17_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID17_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId18
+ */
+#define XLPD_XPPU_MSTR_ID18    ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL )
+#define XLPD_XPPU_MSTR_ID18_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID18_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId19
+ */
+#define XLPD_XPPU_MSTR_ID19    ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL )
+#define XLPD_XPPU_MSTR_ID19_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID19_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_xppu_sink.h
new file mode 100644
index 000000000..95f7e20a2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xlpd_xppu_sink.h
@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_SINK_H__
+#define __XLPD_XPPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppuSink Base Address
+ */
+#define XLPD_XPPU_SINK_BASEADDR      0xFF9C0000UL
+
+/**
+ * Register: XlpdXppuSinkErrSts
+ */
+#define XLPD_XPPU_SINK_ERR_STS    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XLPD_XPPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIsr
+ */
+#define XLPD_XPPU_SINK_ISR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XLPD_XPPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkImr
+ */
+#define XLPD_XPPU_SINK_IMR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XLPD_XPPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuSinkIer
+ */
+#define XLPD_XPPU_SINK_IER    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XLPD_XPPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIdr
+ */
+#define XLPD_XPPU_SINK_IDR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XLPD_XPPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xocm_xmpu_cfg.h
new file mode 100644
index 000000000..5e3631f3e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xocm_xmpu_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XOCM_XMPU_CFG_H__
+#define __XOCM_XMPU_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XocmXmpuCfg Base Address
+ */
+#define XOCM_XMPU_CFG_BASEADDR      0xFFA70000UL
+
+/**
+ * Register: XocmXmpuCfgCtrl
+ */
+#define XOCM_XMPU_CFG_CTRL    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000000UL )
+#define XOCM_XMPU_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XocmXmpuCfgErrSts1
+ */
+#define XOCM_XMPU_CFG_ERR_STS1    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000004UL )
+#define XOCM_XMPU_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgErrSts2
+ */
+#define XOCM_XMPU_CFG_ERR_STS2    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000008UL )
+#define XOCM_XMPU_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgPoison
+ */
+#define XOCM_XMPU_CFG_POISON    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000000CUL )
+#define XOCM_XMPU_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XOCM_XMPU_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XOCM_XMPU_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XOCM_XMPU_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_POISON_BASE_SHIFT   0UL
+#define XOCM_XMPU_CFG_POISON_BASE_WIDTH   20UL
+#define XOCM_XMPU_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XOCM_XMPU_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgIsr
+ */
+#define XOCM_XMPU_CFG_ISR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000010UL )
+#define XOCM_XMPU_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_ISR_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_ISR_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgImr
+ */
+#define XOCM_XMPU_CFG_IMR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000014UL )
+#define XOCM_XMPU_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_IMR_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_IMR_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XocmXmpuCfgIen
+ */
+#define XOCM_XMPU_CFG_IEN    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000018UL )
+#define XOCM_XMPU_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IEN_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_IEN_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgIds
+ */
+#define XOCM_XMPU_CFG_IDS    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000001CUL )
+#define XOCM_XMPU_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IDS_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_IDS_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgLock
+ */
+#define XOCM_XMPU_CFG_LOCK    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000020UL )
+#define XOCM_XMPU_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00Strt
+ */
+#define XOCM_XMPU_CFG_R00_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000100UL )
+#define XOCM_XMPU_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00End
+ */
+#define XOCM_XMPU_CFG_R00_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000104UL )
+#define XOCM_XMPU_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R00_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00Mstr
+ */
+#define XOCM_XMPU_CFG_R00_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000108UL )
+#define XOCM_XMPU_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00
+ */
+#define XOCM_XMPU_CFG_R00    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000010CUL )
+#define XOCM_XMPU_CFG_R00_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R00_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R00_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R00_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R00_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01Strt
+ */
+#define XOCM_XMPU_CFG_R01_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000110UL )
+#define XOCM_XMPU_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01End
+ */
+#define XOCM_XMPU_CFG_R01_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000114UL )
+#define XOCM_XMPU_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R01_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01Mstr
+ */
+#define XOCM_XMPU_CFG_R01_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000118UL )
+#define XOCM_XMPU_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01
+ */
+#define XOCM_XMPU_CFG_R01    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000011CUL )
+#define XOCM_XMPU_CFG_R01_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R01_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R01_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R01_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R01_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02Strt
+ */
+#define XOCM_XMPU_CFG_R02_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000120UL )
+#define XOCM_XMPU_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02End
+ */
+#define XOCM_XMPU_CFG_R02_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000124UL )
+#define XOCM_XMPU_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R02_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02Mstr
+ */
+#define XOCM_XMPU_CFG_R02_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000128UL )
+#define XOCM_XMPU_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02
+ */
+#define XOCM_XMPU_CFG_R02    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000012CUL )
+#define XOCM_XMPU_CFG_R02_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R02_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R02_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R02_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R02_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03Strt
+ */
+#define XOCM_XMPU_CFG_R03_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000130UL )
+#define XOCM_XMPU_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03End
+ */
+#define XOCM_XMPU_CFG_R03_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000134UL )
+#define XOCM_XMPU_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R03_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03Mstr
+ */
+#define XOCM_XMPU_CFG_R03_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000138UL )
+#define XOCM_XMPU_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03
+ */
+#define XOCM_XMPU_CFG_R03    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000013CUL )
+#define XOCM_XMPU_CFG_R03_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R03_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R03_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R03_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R03_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04Strt
+ */
+#define XOCM_XMPU_CFG_R04_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000140UL )
+#define XOCM_XMPU_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04End
+ */
+#define XOCM_XMPU_CFG_R04_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000144UL )
+#define XOCM_XMPU_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R04_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04Mstr
+ */
+#define XOCM_XMPU_CFG_R04_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000148UL )
+#define XOCM_XMPU_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04
+ */
+#define XOCM_XMPU_CFG_R04    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000014CUL )
+#define XOCM_XMPU_CFG_R04_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R04_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R04_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R04_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R04_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05Strt
+ */
+#define XOCM_XMPU_CFG_R05_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000150UL )
+#define XOCM_XMPU_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05End
+ */
+#define XOCM_XMPU_CFG_R05_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000154UL )
+#define XOCM_XMPU_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R05_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05Mstr
+ */
+#define XOCM_XMPU_CFG_R05_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000158UL )
+#define XOCM_XMPU_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05
+ */
+#define XOCM_XMPU_CFG_R05    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000015CUL )
+#define XOCM_XMPU_CFG_R05_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R05_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R05_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R05_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R05_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06Strt
+ */
+#define XOCM_XMPU_CFG_R06_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000160UL )
+#define XOCM_XMPU_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06End
+ */
+#define XOCM_XMPU_CFG_R06_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000164UL )
+#define XOCM_XMPU_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R06_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06Mstr
+ */
+#define XOCM_XMPU_CFG_R06_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000168UL )
+#define XOCM_XMPU_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06
+ */
+#define XOCM_XMPU_CFG_R06    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000016CUL )
+#define XOCM_XMPU_CFG_R06_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R06_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R06_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R06_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R06_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07Strt
+ */
+#define XOCM_XMPU_CFG_R07_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000170UL )
+#define XOCM_XMPU_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07End
+ */
+#define XOCM_XMPU_CFG_R07_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000174UL )
+#define XOCM_XMPU_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R07_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07Mstr
+ */
+#define XOCM_XMPU_CFG_R07_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000178UL )
+#define XOCM_XMPU_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07
+ */
+#define XOCM_XMPU_CFG_R07    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000017CUL )
+#define XOCM_XMPU_CFG_R07_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R07_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R07_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R07_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R07_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08Strt
+ */
+#define XOCM_XMPU_CFG_R08_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000180UL )
+#define XOCM_XMPU_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08End
+ */
+#define XOCM_XMPU_CFG_R08_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000184UL )
+#define XOCM_XMPU_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R08_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08Mstr
+ */
+#define XOCM_XMPU_CFG_R08_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000188UL )
+#define XOCM_XMPU_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08
+ */
+#define XOCM_XMPU_CFG_R08    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000018CUL )
+#define XOCM_XMPU_CFG_R08_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R08_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R08_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R08_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R08_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09Strt
+ */
+#define XOCM_XMPU_CFG_R09_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000190UL )
+#define XOCM_XMPU_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09End
+ */
+#define XOCM_XMPU_CFG_R09_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000194UL )
+#define XOCM_XMPU_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R09_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09Mstr
+ */
+#define XOCM_XMPU_CFG_R09_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000198UL )
+#define XOCM_XMPU_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09
+ */
+#define XOCM_XMPU_CFG_R09    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000019CUL )
+#define XOCM_XMPU_CFG_R09_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R09_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R09_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R09_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R09_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10Strt
+ */
+#define XOCM_XMPU_CFG_R10_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A0UL )
+#define XOCM_XMPU_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10End
+ */
+#define XOCM_XMPU_CFG_R10_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A4UL )
+#define XOCM_XMPU_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R10_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10Mstr
+ */
+#define XOCM_XMPU_CFG_R10_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A8UL )
+#define XOCM_XMPU_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10
+ */
+#define XOCM_XMPU_CFG_R10    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ACUL )
+#define XOCM_XMPU_CFG_R10_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R10_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R10_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R10_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R10_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11Strt
+ */
+#define XOCM_XMPU_CFG_R11_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B0UL )
+#define XOCM_XMPU_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11End
+ */
+#define XOCM_XMPU_CFG_R11_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B4UL )
+#define XOCM_XMPU_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R11_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11Mstr
+ */
+#define XOCM_XMPU_CFG_R11_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B8UL )
+#define XOCM_XMPU_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11
+ */
+#define XOCM_XMPU_CFG_R11    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001BCUL )
+#define XOCM_XMPU_CFG_R11_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R11_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R11_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R11_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R11_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12Strt
+ */
+#define XOCM_XMPU_CFG_R12_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C0UL )
+#define XOCM_XMPU_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12End
+ */
+#define XOCM_XMPU_CFG_R12_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C4UL )
+#define XOCM_XMPU_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R12_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12Mstr
+ */
+#define XOCM_XMPU_CFG_R12_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C8UL )
+#define XOCM_XMPU_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12
+ */
+#define XOCM_XMPU_CFG_R12    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001CCUL )
+#define XOCM_XMPU_CFG_R12_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R12_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R12_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R12_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R12_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13Strt
+ */
+#define XOCM_XMPU_CFG_R13_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D0UL )
+#define XOCM_XMPU_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13End
+ */
+#define XOCM_XMPU_CFG_R13_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D4UL )
+#define XOCM_XMPU_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R13_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13Mstr
+ */
+#define XOCM_XMPU_CFG_R13_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D8UL )
+#define XOCM_XMPU_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13
+ */
+#define XOCM_XMPU_CFG_R13    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001DCUL )
+#define XOCM_XMPU_CFG_R13_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R13_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R13_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R13_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R13_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14Strt
+ */
+#define XOCM_XMPU_CFG_R14_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E0UL )
+#define XOCM_XMPU_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14End
+ */
+#define XOCM_XMPU_CFG_R14_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E4UL )
+#define XOCM_XMPU_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R14_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14Mstr
+ */
+#define XOCM_XMPU_CFG_R14_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E8UL )
+#define XOCM_XMPU_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14
+ */
+#define XOCM_XMPU_CFG_R14    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ECUL )
+#define XOCM_XMPU_CFG_R14_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R14_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R14_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R14_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R14_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15Strt
+ */
+#define XOCM_XMPU_CFG_R15_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F0UL )
+#define XOCM_XMPU_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15End
+ */
+#define XOCM_XMPU_CFG_R15_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F4UL )
+#define XOCM_XMPU_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R15_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15Mstr
+ */
+#define XOCM_XMPU_CFG_R15_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F8UL )
+#define XOCM_XMPU_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15
+ */
+#define XOCM_XMPU_CFG_R15    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001FCUL )
+#define XOCM_XMPU_CFG_R15_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R15_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R15_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R15_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R15_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XOCM_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xparameters_ps.h
new file mode 100644
index 000000000..d86e6fc54
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xparameters_ps.h
@@ -0,0 +1,317 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A53 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XEMACPS_2_INTR		XPS_GEM2_INT_ID
+#define XPAR_XEMACPS_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
+#define XPAR_XEMACPS_3_INTR		XPS_GEM3_INT_ID
+#define XPAR_XEMACPS_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XTTCPS_6_INTR		XPS_TTC2_0_INT_ID
+#define XPAR_XTTCPS_7_INTR		XPS_TTC2_1_INT_ID
+#define XPAR_XTTCPS_8_INTR		XPS_TTC2_2_INT_ID
+#define XPAR_XTTCPS_9_INTR		XPS_TTC3_0_INT_ID
+#define XPAR_XTTCPS_10_INTR		XPS_TTC3_1_INT_ID
+#define XPAR_XTTCPS_11_INTR		XPS_TTC3_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+#define XPAR_XNANDPS8_0_INTR        	XPS_NAND_INT_ID
+#define XPAR_XADMAPS_0_INTR 		XPS_ADMA_CH0_INT_ID
+#define XPAR_XADMAPS_1_INTR 		XPS_ADMA_CH1_INT_ID
+#define XPAR_XADMAPS_2_INTR		XPS_ADMA_CH2_INT_ID
+#define XPAR_XADMAPS_3_INTR 		XPS_ADMA_CH3_INT_ID
+#define XPAR_XADMAPS_4_INTR		XPS_ADMA_CH4_INT_ID
+#define XPAR_XADMAPS_5_INTR 		XPS_ADMA_CH5_INT_ID
+#define XPAR_XADMAPS_6_INTR 		XPS_ADMA_CH6_INT_ID
+#define XPAR_XADMAPS_7_INTR 		XPS_ADMA_CH7_INT_ID
+#define XPAR_XCSUDMA_INTR 		XPS_CSU_DMA_INT_ID
+#define XPAR_XMPU_LPD_INTR 		XPS_XMPU_LPD_INT_ID
+#define XPAR_XZDMAPS_0_INTR		XPS_ZDMA_CH0_INT_ID
+#define XPAR_XZDMAPS_1_INTR		XPS_ZDMA_CH1_INT_ID
+#define XPAR_XZDMAPS_2_INTR 		XPS_ZDMA_CH2_INT_ID
+#define XPAR_XZDMAPS_3_INTR 		XPS_ZDMA_CH3_INT_ID
+#define XPAR_XZDMAPS_4_INTR		XPS_ZDMA_CH4_INT_ID
+#define XPAR_XZDMAPS_5_INTR 		XPS_ZDMA_CH5_INT_ID
+#define XPAR_XZDMAPS_6_INTR 		XPS_ZDMA_CH6_INT_ID
+#define XPAR_XZDMAPS_7_INTR 		XPS_ZDMA_CH7_INT_ID
+#define XPAR_XMPU_FPD_INTR 		XPS_XMPU_FPD_INT_ID
+#define XPAR_XCCI_FPD_INTR 		XPS_FPD_CCI_INT_ID
+#define XPAR_XSMMU_FPD_INTR 		XPS_FPD_SMMU_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB3_0_ENDPT_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB3_1_ENDPT_INT_ID
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00002000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for backwards compatibilty
+ */
+
+
+#define XPS_SYS_CTRL_BASEADDR	0xFF180000U
+#define XPS_SCU_PERIPH_BASE		0xF9000000U
+
+
+
+/* Shared Peripheral Interrupts (SPI) */
+
+/* FIXME */
+/*#define XPS_FPGA0_INT_ID		100U */
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+/* Updated Interrupt-IDs */
+#define XPS_OCMINTR_INT_ID		(10U + 32U)
+#define XPS_NAND_INT_ID        		(14U + 32U)
+#define XPS_QSPI_INT_ID			(15U + 32U)
+#define XPS_GPIO_INT_ID			(16U + 32U)
+#define XPS_I2C0_INT_ID			(17U + 32U)
+#define XPS_I2C1_INT_ID			(18U + 32U)
+#define XPS_SPI0_INT_ID			(19U + 32U)
+#define XPS_SPI1_INT_ID			(20U + 32U)
+#define XPS_UART0_INT_ID		(21U + 32U)
+#define XPS_UART1_INT_ID		(22U + 32U)
+#define XPS_CAN0_INT_ID			(23U + 32U)
+#define XPS_CAN1_INT_ID			(24U + 32U)
+#define XPS_WDT_INT_ID			(52U + 32U)
+#define XPS_TTC0_0_INT_ID		(36U + 32U)
+#define XPS_TTC0_1_INT_ID		(37U + 32U)
+#define XPS_TTC0_2_INT_ID 		(38U + 32U)
+#define XPS_TTC1_0_INT_ID		(39U + 32U)
+#define XPS_TTC1_1_INT_ID		(40U + 32U)
+#define XPS_TTC1_2_INT_ID		(41U + 32U)
+#define XPS_TTC2_0_INT_ID		(42U + 32U)
+#define XPS_TTC2_1_INT_ID		(43U + 32U)
+#define XPS_TTC2_2_INT_ID		(44U + 32U)
+#define XPS_TTC3_0_INT_ID		(45U + 32U)
+#define XPS_TTC3_1_INT_ID		(46U + 32U)
+#define XPS_TTC3_2_INT_ID		(47U + 32U)
+#define XPS_SDIO0_INT_ID		(48U + 32U)
+#define XPS_SDIO1_INT_ID		(49U + 32U)
+#define XPS_GEM0_INT_ID			(57U + 32U)
+#define XPS_GEM0_WAKE_INT_ID		(58U + 32U)
+#define XPS_GEM1_INT_ID			(59U + 32U)
+#define XPS_GEM1_WAKE_INT_ID		(60U + 32U)
+#define XPS_GEM2_INT_ID			(61U + 32U)
+#define XPS_GEM2_WAKE_INT_ID		(62U + 32U)
+#define XPS_GEM3_INT_ID			(63U + 32U)
+#define XPS_GEM3_WAKE_INT_ID		(64U + 32U)
+#define XPS_USB3_0_ENDPT_INT_ID		(65U + 32U)
+#define XPS_USB3_1_ENDPT_INT_ID		(70U + 32U)
+#define XPS_ADMA_CH0_INT_ID		(77U + 32U)
+#define XPS_ADMA_CH1_INT_ID		(78U + 32U)
+#define XPS_ADMA_CH2_INT_ID		(79U + 32U)
+#define XPS_ADMA_CH3_INT_ID		(80U + 32U)
+#define XPS_ADMA_CH4_INT_ID		(81U + 32U)
+#define XPS_ADMA_CH5_INT_ID		(82U + 32U)
+#define XPS_ADMA_CH6_INT_ID		(83U + 32U)
+#define XPS_ADMA_CH7_INT_ID		(84U + 32U)
+#define XPS_CSU_DMA_INT_ID		(86U + 32U)
+#define XPS_XMPU_LPD_INT_ID		(88U + 32U)
+#define XPS_ZDMA_CH0_INT_ID		(124U + 32U)
+#define XPS_ZDMA_CH1_INT_ID		(125U + 32U)
+#define XPS_ZDMA_CH2_INT_ID		(126U + 32U)
+#define XPS_ZDMA_CH3_INT_ID		(127U + 32U)
+#define XPS_ZDMA_CH4_INT_ID		(128U + 32U)
+#define XPS_ZDMA_CH5_INT_ID		(129U + 32U)
+#define XPS_ZDMA_CH6_INT_ID		(130U + 32U)
+#define XPS_ZDMA_CH7_INT_ID		(131U + 32U)
+#define XPS_XMPU_FPD_INT_ID		(134U + 32U)
+#define XPS_FPD_CCI_INT_ID		(154U + 32U)
+#define XPS_FPD_SMMU_INT_ID		(155U + 32U)
+
+/* Private Peripheral Interrupts (PPI) */
+/*#define XPS_GLOBAL_TMR_INT_ID		27	 SCU Global Timer interrupt */
+/*#define XPS_FIQ_INT_ID			28	 FIQ from FPGA fabric */
+/*#define XPS_SCU_TMR_INT_ID		29	 SCU Private Timer interrupt */
+/*#define XPS_SCU_WDT_INT_ID		30	 SCU Private WDT interrupt */
+/*#define XPS_IRQ_INT_ID			31	 IRQ from FPGA fabric */
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_2_INTR	XPS_GEM2_INT_ID
+#define XPAR_PS7_ETHERNET_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_3_INTR	XPS_GEM3_INT_ID
+#define XPAR_PS7_ETHERNET_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
+
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+
+#define XPAR_XADCPS_NUM_INSTANCES 1U
+#define XPAR_XADCPS_0_DEVICE_ID   0U
+#define XPAR_XADCPS_0_BASEADDR	  (0xF8007000U)
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xplatform_info.c
new file mode 100644
index 000000000..1a55b2f8b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xplatform_info.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about platform
+*
+* @param    None.
+*
+* @return   The information about platform defined in xplatform_info.h
+*
+* @note     None.
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+	u32 reg;
+#if defined (ARMR5) || (__aarch64__)
+	return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+	return XPLAT_MICROBLAZE;
+#else
+	return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about zynq ultrascale MP platform
+*
+* @param    None.
+*
+* @return   The information about zynq ultrascale MP platform defined in
+*			xplatform_info.h
+*
+* @note     None.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+	u32 reg;
+	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
+	return reg;
+}
+#endif
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xplatform_info.h
new file mode 100644
index 000000000..d71a692c1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xplatform_info.h
@@ -0,0 +1,81 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* This file contains definitions for various platforms available
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
+#define XPLATFORM_INFO_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define	XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPLAT_INFO_MASK (0xF)
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xpseudo_asm.h
new file mode 100644
index 000000000..e5e02751d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xpseudo_asm.h
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* This header file contains macros for using inline assembler code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+#include "xreg_cortexa53.h"
+#include "xpseudo_asm_gcc.h"
+
+#endif /* XPSEUDO_ASM_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xpseudo_asm_gcc.h
new file mode 100644
index 000000000..5f0e9c25c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xpseudo_asm_gcc.h
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval; \
+			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
+			  rval;\
+			 })
+
+#define mtcpsr(v) asm ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	/*__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)*/
+
+#define mfgpr(rn)	/*({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() asm ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() asm("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() asm("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define ldrb(adr)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "ldrb	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define str(adr, val)	__asm__ __volatile__(\
+			  "str	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+#define strb(adr, val)	__asm__ __volatile__(\
+			  "strb	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+/* Count leading zeroes (clz) */
+#define clz(arg)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "clz	%0,%1"\
+			    : "=r" (rval) : "r" (arg)\
+			  );\
+			  rval;\
+			 })
+#define mtcpdc(reg,val)	asm("dc " #reg ",%0"  : : "r" (val))
+#define mtcpic(reg,val)	asm("ic " #reg ",%0"  : : "r" (val))
+
+#define mtcpicall(reg)	asm("ic " #reg)
+#define mtcptlbi(reg)	asm("tlbi " #reg)
+#define mtcpat(reg,val)	asm("at " #reg ",%0"  : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg)	({u32 rval;\
+			asm("mrs	%0, " #reg : "=r" (rval));\
+			rval;\
+			})
+
+#define mtcp(reg,val)	asm("msr " #reg ",%0"  : : "r" (val))
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xreg_cortexa53.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xreg_cortexa53.h
new file mode 100644
index 000000000..dbc0134e6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xreg_cortexa53.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa53.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+******************************************************************************/
+#ifndef XREG_CORTEXA53_H
+#define XREG_CORTEXA53_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/* GPRs */
+#define XREG_GPR0				x0
+#define XREG_GPR1				x1
+#define XREG_GPR2				x2
+#define XREG_GPR3				x3
+#define XREG_GPR4				x4
+#define XREG_GPR5				x5
+#define XREG_GPR6				x6
+#define XREG_GPR7				x7
+#define XREG_GPR8				x8
+#define XREG_GPR9				x9
+#define XREG_GPR10				x10
+#define XREG_GPR11				x11
+#define XREG_GPR12				x12
+#define XREG_GPR13				x13
+#define XREG_GPR14				x14
+#define XREG_GPR15				x15
+#define XREG_GPR16				x16
+#define XREG_GPR17				x17
+#define XREG_GPR18				x18
+#define XREG_GPR19				x19
+#define XREG_GPR20				x20
+#define XREG_GPR21				x21
+#define XREG_GPR22				x22
+#define XREG_GPR23				x23
+#define XREG_GPR24				x24
+#define XREG_GPR25				x25
+#define XREG_GPR26				x26
+#define XREG_GPR27				x27
+#define XREG_GPR28				x28
+#define XREG_GPR29				x29
+#define XREG_GPR30				x30
+#define XREG_CPSR				cpsr
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_MODE_BITS			0x1F
+#define XREG_CPSR_EL3h_MODE			0xD
+#define XREG_CPSR_EL3t_MODE			0xC
+#define XREG_CPSR_EL2h_MODE			0x9
+#define XREG_CPSR_EL2t_MODE			0x8
+#define XREG_CPSR_EL1h_MODE			0x5
+#define XREG_CPSR_EL1t_MODE			0x4
+#define XREG_CPSR_EL0t_MODE			0x0
+
+#define XREG_CPSR_IRQ_ENABLE		0x80
+#define XREG_CPSR_FIQ_ENABLE		0x40
+
+#define XREG_CPSR_N_BIT				0x80000000U
+#define XREG_CPSR_Z_BIT				0x40000000U
+#define XREG_CPSR_C_BIT				0x20000000U
+#define XREG_CPSR_V_BIT				0x10000000U
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT	(24U)
+#define XREG_FPSID_IMPLEMENTER_MASK	(0x000000FFU << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE		(0X00000001U<<23U)
+#define XREG_FPSID_ARCH_BIT		(16U)
+#define XREG_FPSID_ARCH_MASK		(0x0000000FU  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT		(8U)
+#define XREG_FPSID_PART_MASK		(0x000000FFU << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT		(4U)
+#define XREG_FPSID_VARIANT_MASK		(0x0000000FU  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT		(0U)
+#define XREG_FPSID_REV_MASK		(0x0000000FU  << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT		(0X00000001U << 31U)
+#define XREG_FPSCR_Z_BIT		(0X00000001U << 30U)
+#define XREG_FPSCR_C_BIT		(0X00000001U << 29U)
+#define XREG_FPSCR_V_BIT		(0X00000001U << 28U)
+#define XREG_FPSCR_QC			(0X00000001U << 27U)
+#define XREG_FPSCR_AHP			(0X00000001U << 26U)
+#define XREG_FPSCR_DEFAULT_NAN		(0X00000001U << 25U)
+#define XREG_FPSCR_FLUSHTOZERO		(0X00000001U << 24U)
+#define XREG_FPSCR_ROUND_NEAREST	(0X00000000U << 22U)
+#define XREG_FPSCR_ROUND_PLUSINF	(0X00000001U << 22U)
+#define XREG_FPSCR_ROUND_MINUSINF	(0X00000002U << 22U)
+#define XREG_FPSCR_ROUND_TOZERO		(0X00000003U << 22U)
+#define XREG_FPSCR_RMODE_BIT		(22U)
+#define XREG_FPSCR_RMODE_MASK		(0X00000003U << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT		(20U)
+#define XREG_FPSCR_STRIDE_MASK		(0X00000003U << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT		(16U)
+#define XREG_FPSCR_LENGTH_MASK		(0X00000007U << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC			(0X00000001U << 7U)
+#define XREG_FPSCR_IXC			(0X00000001U << 4U)
+#define XREG_FPSCR_UFC			(0X00000001U << 3U)
+#define XREG_FPSCR_OFC			(0X00000001U << 2U)
+#define XREG_FPSCR_DZC			(0X00000001U << 1U)
+#define XREG_FPSCR_IOC			(0X00000001U << 0U)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT		(28U)
+#define XREG_MVFR0_RMODE_MASK		(0x0000000FU << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT	(24U)
+#define XREG_MVFR0_SHORT_VEC_MASK	(0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT		(20U)
+#define XREG_MVFR0_SQRT_MASK		(0x0000000FU << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT		(16U)
+#define XREG_MVFR0_DIVIDE_MASK		(0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT	(0X00000012U)
+#define XREG_MVFR0_EXEC_TRAP_MASK	(0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT		(8U)
+#define XREG_MVFR0_DP_MASK		(0x0000000FU << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT		(4U)
+#define XREG_MVFR0_SP_MASK		(0x0000000FU << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT		(0U)
+#define XREG_MVFR0_A_SIMD_MASK		(0x0000000FU << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX			(0X00000001U << 31U)
+#define XREG_FPEXC_EN			(0X00000001U << 30U)
+#define XREG_FPEXC_DEX			(0X00000001U << 29U)
+
+
+#define XREG_CONTROL_DCACHE_BIT	(0X00000001U<<2U)
+#define XREG_CONTROL_ICACHE_BIT	(0X00000001U<<12U)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA53_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xstatus.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xstatus.h
new file mode 100644
index 000000000..7db874c88
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xstatus.h
@@ -0,0 +1,430 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called int.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/* driver defined error */
+#define XST_RECV_ERROR                  27L	/* generic receive error */
+#define XST_SEND_ERROR                  28L	/* generic transmit error */
+#define XST_NOT_ENABLED                 29L	/* a requested service is not
+						   available because it has not
+						   been enabled */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/* packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/* general purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/* general buffer descriptor
+						   error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/* Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/* Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/* Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/* Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/* Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/* Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/* Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/* Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/* Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/* Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/* Flash is write protected
+						 */
+
+/**************************** Type Definitions *******************************/
+
+typedef int XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xtime_l.c
new file mode 100644
index 000000000..f0719da51
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xtime_l.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex A53 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note		None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************
+*
+* Set the time in the Global Timer Counter Register.
+*
+* @param	Value to be written to the Global Timer Counter Register.
+*
+* @return	None.
+*
+* @note		In multiprocessor environment reference time will reset/lost for
+*		all processors, when this function called by any one processor.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+/*As the generic timer of A53 runs constantly time can not be set as desired
+so the API is left unimplemented*/
+}
+
+/****************************************************************************
+*
+* Get the time from the Global Timer Counter Register.
+*
+* @param	Pointer to the location to be updated with the time.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+	*Xtime_Global = mfcp(CNTPCT_EL0);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xtime_l.h
new file mode 100644
index 000000000..fd75790a4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_0/src/xtime_l.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp	   05/29/14 First release
+* 

+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND          0x007A1200U
+
+#define XIOU_SCNTRS_BASEADDR      0XFF260000U
+#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET    0x00000000U
+#define XIOU_SCNTRS_FREQ_REG_OFFSET    0x00000020U
+#define XIOU_SCNTRS_FREQ		0x02FAF080U	/* 50 MHz */
+#define XIOU_SCNTRS_CNT_CNTRL_REG_EN    0X00000001U
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/Makefile
new file mode 100644
index 000000000..35c277dde
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner ttcps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ttcps"
+
+ttcps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: ttcps_includes
+
+ttcps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps.c
new file mode 100644
index 000000000..de19fcc66
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps.c
@@ -0,0 +1,431 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.c
+*
+* This file contains the implementation of the XTtcPs driver. This driver
+* controls the operation of one timer counter in the Triple Timer Counter (TTC)
+* module in the Ps block. Refer to xttcps.h for more detailed description
+* of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XTtcPs instance such that the driver is ready to use.
+* This function initializes a single timer counter in the triple timer counter
+* function block.
+*
+* The state of the device after initialization is:
+*  - Overflow Mode
+*  - Internal (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific TTC device.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, then use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return
+*
+* 		- XST_SUCCESS if the initialization is successful.
+*		- XST_DEVICE_IS_STARTED if the device is started. It must be
+*		  stopped to re-initialize.
+*
+* @note		Device has to be stopped first to call this function to
+*		initialize it.
+*
+******************************************************************************/
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
+			      u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 IsStartResult;
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+
+	IsStartResult = XTtcPs_IsStarted(InstancePtr);
+	/*
+	 * If the timer counter has already started, return an error
+	 * Device should be stopped first.
+	 */
+	if(IsStartResult == (u32)TRUE) {
+		Status = XST_DEVICE_IS_STARTED;
+	} else {
+		/*
+		 * Reset the count control register to it's default value.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET,
+				  XTTCPS_CNT_CNTRL_RESET_VALUE);
+
+		/*
+		 * Reset the rest of the registers to the default values.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_1_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_2_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_2_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_IER_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		/*
+		 * Reset the counter value
+		 */
+		XTtcPs_ResetCounterValue(InstancePtr);
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to set the match registers. There are three match
+* registers.
+*
+* The match 0 register is special. If the waveform output mode is enabled, the
+* waveform will change polarity when the count matches the value in the match 0
+* register. The polarity of the waveform output can also be set using the
+* XTtcPs_SetOptions() function.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+* @param	Value is the 16-bit value to be set in the match register.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
+{
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
+
+	/*
+	 * Write the value to the correct match register with MatchIndex
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTtcPs_Match_N_Offset(MatchIndex), Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to get the value of the match registers. There are
+* three match registers.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
+{
+	u32 MatchReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
+
+	MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			    XTtcPs_Match_N_Offset(MatchIndex));
+
+	return (u16) MatchReg;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler enable bit and if needed sets the prescaler
+* bits in the control register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	PrescalerValue is a number from 0-16 that sets the prescaler
+*		to use.
+*		If the parameter is 0 - 15, use a prescaler on the clock of
+*		2^(PrescalerValue+1), or 2-65536.
+*		If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
+*		prescaler.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
+{
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			   XTTCPS_CLK_CNTRL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register
+	 */
+	ClockReg &=
+		~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
+
+	if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
+		/*
+		 * Set the prescaler value and enable prescaler
+		 */
+		ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
+		ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
+	}
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the input clock prescaler
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* 
+* @return	The value(n) from which the prescalar value is calculated
+*		as 2^(n+1). Some example values are given below :
+*
+* 	Value		Prescaler
+* 	0		2
+* 	1		4
+* 	N		2^(n+1)
+* 	15		65536
+* 	16		1
+* 

+*
+* @note		None.
+*
+****************************************************************************/
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
+{
+	u8 Status;
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+
+	if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
+		/*
+		 * Prescaler is disabled. Return the correct flag value
+		 */
+		Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
+	}
+	else {
+
+		Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function calculates the interval value as well as the prescaler value
+* for a given frequency.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Freq is the requested output frequency for the device.
+* @param	Interval is the interval value for the given frequency,
+*		it is the output value for this function.
+* @param	Prescaler is the prescaler value for the given frequency,
+*		it is the output value for this function.
+*
+* @return	None.
+*
+* @note
+*  Upon successful calculation for the given frequency, Interval and Prescaler
+*  carry the settings for the timer counter; Upon unsuccessful calculation,
+*  Interval and Prescaler are set to 0xFF(FF) for their maximum values to
+*  signal the caller of failure. Therefore, caller needs to check the return
+*  interval or prescaler values for whether the function has succeeded.
+*
+****************************************************************************/
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        u16 *Interval, u8 *Prescaler)
+{
+	u8 TmpPrescaler;
+	u32 TempValue;
+	u32 InputClock;
+
+	InputClock = InstancePtr->Config.InputClockHz;
+	/*
+	 * Find the smallest prescaler that will work for a given frequency. The
+	 * smaller the prescaler, the larger the count and the more accurate the
+	 *  PWM setting.
+	 */
+	TempValue = InputClock/ Freq;
+
+	if (TempValue < 4U) {
+		/*
+		 * The frequency is too high, it is too close to the input
+		 * clock value. Use maximum values to signal caller.
+		 */
+		*Interval = 0xFFFFU;
+		*Prescaler = 0xFFU;
+		return;
+	}
+
+	/*
+	 * First, do we need a prescaler or not?
+	 */
+	if (((u32)65536U) > TempValue) {
+		/*
+		 * We do not need a prescaler, so set the values appropriately
+		 */
+		*Interval = (u16)TempValue;
+		*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
+		return;
+	}
+
+
+	for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
+	     TmpPrescaler++) {
+		TempValue =	InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
+
+		/*
+		 * The first value less than 2^16 is the best bet
+		 */
+		if (((u32)65536U) > TempValue) {
+			/*
+			 * Set the values appropriately
+			 */
+			*Interval = (u16)TempValue;
+			*Prescaler = TmpPrescaler;
+			return;
+		}
+	}
+
+	/* Can not find interval values that work for the given frequency.
+	 * Return maximum values to signal caller.
+	 */
+	*Interval = 0XFFFFU;
+	*Prescaler = 0XFFU;
+	return;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps.h
new file mode 100644
index 000000000..86bcb97cc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps.h
@@ -0,0 +1,408 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+*	. At a regular, predefined period, that is on a timed interval
+*	. When the counter registers overflow
+* 	. When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* Initialization & Configuration
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* Interrupts
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* @note
+* The default setting for a timer/counter is:
+*  - Overflow Mode
+*  - Internal clock (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+* 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+#ifndef XTTCPS_H		/* prevent circular inclusions */
+#define XTTCPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK	0x00000001U 	/**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG	0x00000002U	/**< Clock on trailing edge for
+						     external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE	0x00000004U	/**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT		0x00000008U	/**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE	0x00000010U	/**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE	0x00000020U 	/**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY	0x00000040U	/**< Waveform polarity */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	  /**< Unique ID for device */
+	u32 BaseAddress;  /**< Base address for device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+	XTtcPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+} XTtcPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+    (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+    (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr)	\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) &	\
+		 ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr)		\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) |	\
+		 XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance
+*
+* @return	Non-zero if the device has started, '0' otherwise.
+*
+* @note		C-style signature:
+*		int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+     ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+       XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	16-bit counter value.
+*
+* @note		C-style signature:
+*		u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_GetCounterValue(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Value is the 16-bit value to be set in the interval register.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value)	\
+		InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	16-bit interval value
+*
+* @note		C-style signature:
+*		u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_GetInterval(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+		 (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be enabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be enabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask)		\
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,		\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) |	\
+		 (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be disabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be disabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) &	\
+		 ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr)	 \
+		InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be cleared.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be cleared, cleared bits
+*		will not be cleared.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
+		 (InterruptMask))
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+         XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        u16 *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_g.c
new file mode 100644
index 000000000..da161db1e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_g.c
@@ -0,0 +1,111 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xttcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XTtcPs_Config XTtcPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_TTC_0_DEVICE_ID,
+		XPAR_PSU_TTC_0_BASEADDR,
+		XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_1_DEVICE_ID,
+		XPAR_PSU_TTC_1_BASEADDR,
+		XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_2_DEVICE_ID,
+		XPAR_PSU_TTC_2_BASEADDR,
+		XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_3_DEVICE_ID,
+		XPAR_PSU_TTC_3_BASEADDR,
+		XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_4_DEVICE_ID,
+		XPAR_PSU_TTC_4_BASEADDR,
+		XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_5_DEVICE_ID,
+		XPAR_PSU_TTC_5_BASEADDR,
+		XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_6_DEVICE_ID,
+		XPAR_PSU_TTC_6_BASEADDR,
+		XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_7_DEVICE_ID,
+		XPAR_PSU_TTC_7_BASEADDR,
+		XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_8_DEVICE_ID,
+		XPAR_PSU_TTC_8_BASEADDR,
+		XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_9_DEVICE_ID,
+		XPAR_PSU_TTC_9_BASEADDR,
+		XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_10_DEVICE_ID,
+		XPAR_PSU_TTC_10_BASEADDR,
+		XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_11_DEVICE_ID,
+		XPAR_PSU_TTC_11_BASEADDR,
+		XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_hw.h
new file mode 100644
index 000000000..8f12e3c10
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_hw.h
@@ -0,0 +1,209 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H		/* prevent circular inclusions */
+#define XTTCPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET		0x00000000U  /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET		0x0000000CU  /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET	0x00000018U  /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET	0x00000024U  /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET		0x00000030U  /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET		0x0000003CU  /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET		0x00000048U  /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET			0x00000054U  /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET			0x00000060U  /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK		0x00000001U  /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK	0x0000001EU  /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT			 1U  /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE				16U  /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK		0x00000020U  /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK	0x00000040U  /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK		0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK		0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK		0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK		0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK		0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK	0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK	0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE	0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#define XTTCPS_COUNT_VALUE_MASK		0x0000FFFFU /**< 16-bit counter value */
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#define XTTCPS_INTERVAL_VAL_MASK	0x0000FFFFU /**< 16-bit Interval value*/
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#define XTTCPS_MATCH_MASK		0x0000FFFFU /**< 16-bit Match value */
+#define XTTCPS_NUM_MATCH_REG			 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK	0x00000001U  /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK		0x00000002U  /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK		0x00000004U  /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK		0x00000008U  /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK		0x00000010U  /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK			0x0000001FU  /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+    (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param	MatchIndex is the 0-2 value of the match register
+*
+* @return	MATCH_N_OFFSET.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+		((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_options.c
new file mode 100644
index 000000000..26c7264e7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_options.c
@@ -0,0 +1,240 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_options.c
+*
+* This file contains functions to get or set option features for the device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 1.01a nm     03/05/2012 Removed break statement after return to remove
+*                         compilation warnings.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+	u32 Register;
+} OptionsMap;
+
+static OptionsMap TmrCtrOptionsTable[] = {
+	{XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+};
+
+#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
+				sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained
+*		in the mask. See the bit definitions named XTTCPS_*_OPTION in
+*		the file xttcps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_FAILURE if any of the options are unknown.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
+{
+	u32 CountReg;
+	u32 ClockReg;
+	u32 Index;
+	s32 Status = XST_SUCCESS;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+	CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CNT_CNTRL_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		if(Status != (s32)XST_FAILURE) {
+			if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
+
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Add option */
+				ClockReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Add option */
+				CountReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+			}
+		}
+		else {
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Remove option*/
+				ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Remove option*/
+				CountReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+				}
+			}
+		}
+	}
+
+	/*
+	 * Now write the registers. Leave it to the upper layers to restart the
+	 * device.
+	 */
+	if (Status != (s32)XST_FAILURE ) {
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET, CountReg);
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the settings for the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* The return u32 contains the specified options that are set. This is a bit
+* mask where a '1' means the option is on, and a'0' means the option is off.
+* One or more bit values may be contained in the mask. See the bit definitions
+* named XTTCPS_*_OPTION in the file xttcps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 Register;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Loop through the options table to determine which options are set
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		/*
+		 * Get the control register to determine which options are
+		 * currently set.
+		 */
+		Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+					      TmrCtrOptionsTable[Index].
+					      Register);
+
+		if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
+			OptionsFlag |= TmrCtrOptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_selftest.c
new file mode 100644
index 000000000..da4354fd3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_selftest.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_selftest.c
+*
+* This file contains the implementation of self test function for the
+* XTtcPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device.
+*
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+*	- XST_SUCCESS if successful
+*	- XST_FAILURE indicates a register did not read or write correctly
+*
+* @note		This test fails if it is not called right after initialization.
+*
+******************************************************************************/
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
+{
+	s32 Status;
+	u32 TempReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the TTC registers should be in their default state right now.
+	 */
+	TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XTTCPS_CNT_CNTRL_OFFSET);
+	if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
+		Status = XST_FAILURE;
+	}
+	else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_sinit.c
new file mode 100644
index 000000000..fe524ed16
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_0/src/xttcps_sinit.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_sinit.c
+*
+* The implementation of the XTtcPs driver's static initialization functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the unique ID of the device
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xttcps.h for the definition of XTtcPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
+{
+	XTtcPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
+		if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XTtcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XTtcPs_Config *)CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/Makefile
new file mode 100644
index 000000000..88b1e625c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xuartps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling uartps"
+
+xuartps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xuartps_includes
+
+xuartps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps.c
new file mode 100644
index 000000000..4090ef72e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps.c
@@ -0,0 +1,676 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	 Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE		 3U	/* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount);
+
+u32  XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+u32  XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Config is a reference to a structure containing information
+*		about a specific XUartPs driver.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, pass in the physical
+*		address instead.
+*
+* @return
+*
+*		- XST_SUCCESS if initialization was successful
+*		- XST_UART_BAUD_ERROR if the baud rate is not possible because
+*		  the inputclock frequency is not divisible with an acceptable
+*		  amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*   All interrupts are disabled.
+*
+*****************************************************************************/
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				   XUartPs_Config * Config, u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 ModeRegister;
+	u32 BaudRate;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Config != NULL);
+
+	/*
+	 * Setup the driver instance using passed in parameters
+	 */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = Config->InputClockHz;
+	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+	/*
+	 * Initialize other instance data to default values
+	 */
+	InstancePtr->Handler = XUartPs_StubHandler;
+
+	InstancePtr->SendBuffer.NextBytePtr = NULL;
+	InstancePtr->SendBuffer.RemainingBytes = 0U;
+	InstancePtr->SendBuffer.RequestedBytes = 0U;
+
+	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+	InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
+	InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
+
+	/*
+	 * Flag that the driver instance is ready to use
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Set the default baud rate here, can be changed prior to
+	 * starting the device
+	 */
+	BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
+	Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+	if (Status != (s32)XST_SUCCESS) {
+		InstancePtr->IsReady = 0U;
+	} else {
+
+		/*
+		 * Set up the default data format: 8 bit data, 1 stop bit, no
+		 * parity
+		 */
+		ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XUARTPS_MR_OFFSET);
+
+		/*
+		 * Mask off what's already there
+		 */
+		ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
+						 (u32)XUARTPS_MR_STOPMODE_MASK |
+						 (u32)XUARTPS_MR_PARITY_MASK));
+
+		/*
+		 * Set the register value to the desired data format
+		 */
+		ModeRegister |=	((u32)XUARTPS_MR_CHARLEN_8_BIT |
+						 (u32)XUARTPS_MR_STOPMODE_1_BIT |
+						 (u32)XUARTPS_MR_PARITY_NONE);
+
+		/*
+		 * Write the mode register out
+		 */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+				   ModeRegister);
+
+		/*
+		 * Set the RX FIFO trigger at 8 data bytes.
+		 */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXWM_OFFSET, 0x08U);
+
+		/*
+		 * Set the RX timeout to 1, which will be 4 character time
+		 */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXTOUT_OFFSET, 0x01U);
+
+		/*
+		 * Disable all interrupts, polled mode is the default
+		 */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+				   XUARTPS_IXR_MASK);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	BufferPtr is pointer to a buffer of data to be sent.
+* @param  	NumBytes contains the number of bytes to be sent. A value of
+*		zero will stop a previous send operation that is in progress
+*		in interrupt mode. Any data that was already put into the
+*		transmit FIFO will be sent.
+*
+* @return	The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+* 


+*
+*****************************************************************************/
+u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+			   u32 NumBytes)
+{
+	u32 BytesSent;
+
+	/*
+	 * Asserts validate the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the UART transmit interrupts to allow this call to stop a
+	 * previous operation that may be interrupt driven.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+					  (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+	/*
+	 * Setup the buffer parameters
+	 */
+	InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+	InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+	InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+	/*
+	 * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+	 * filling the TX FIFO.
+	 */
+	BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+	return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BufferPtr is pointer to buffer for data to be received into
+* @param	NumBytes is the number of bytes to be received. A value of zero
+*		will stop a previous receive operation that is in progress in
+*		interrupt mode.
+*
+* @return	The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+u32 XUartPs_Recv(XUartPs *InstancePtr,
+			  u8 *BufferPtr, u32 NumBytes)
+{
+	u32 ReceivedCount;
+	u32 ImrRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable all the interrupts.
+	 * This stops a previous operation that may be interrupt driven
+	 */
+	ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/*
+	 * Setup the buffer parameters
+	 */
+	InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+	/*
+	 * Receive the data from the device
+	 */
+	ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+	/*
+	 * Restore the interrupt state
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+		ImrRegister);
+
+	return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes actually sent
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+	u32 SentCount = 0U;
+	u32 ImrRegister;
+
+	/*
+	 * If the TX FIFO is full, send nothing.
+	 * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+	 * data has been put into the FIFO.
+	 */
+	while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+		   (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+		/*
+		 * Fill the FIFO from the buffer
+		 */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_FIFO_OFFSET,
+				   ((u32)InstancePtr->SendBuffer.
+				   NextBytePtr[SentCount]));
+
+		/*
+		 * Increment the send count.
+		 */
+		SentCount++;
+	}
+
+	/*
+	 * Update the buffer to reflect the bytes that were sent from it
+	 */
+	InstancePtr->SendBuffer.NextBytePtr += SentCount;
+	InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+	/*
+	 * If interrupts are enabled as indicated by the receive interrupt, then
+	 * enable the TX FIFO empty interrupt, so further action can be taken
+	 * for this sending.
+	 */
+	ImrRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
+		((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
+		((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
+
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XUARTPS_IER_OFFSET,
+					   ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
+	}
+
+	return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+	u32 CsrRegister;
+	u32 ReceivedCount = 0U;
+
+	/*
+	 * Read the Channel Status Register to determine if there is any data in
+	 * the RX FIFO
+	 */
+	CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_SR_OFFSET);
+
+	/*
+	 * Loop until there is no more data in RX FIFO or the specified
+	 * number of bytes has been received
+	 */
+	while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
+		(((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
+
+		InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+			XUartPs_ReadReg(InstancePtr->Config.
+				  BaseAddress,
+				  XUARTPS_FIFO_OFFSET);
+
+		ReceivedCount++;
+
+		CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+								XUARTPS_SR_OFFSET);
+	}
+
+	/*
+	 * Update the receive buffer to reflect the number of bytes just
+	 * received
+	 */
+	if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
+		InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+	}
+	InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+	return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BaudRate to be set
+*
+* @return
+*		- XST_SUCCESS if everything configured as expected
+*		- XST_UART_BAUD_ERROR if the requested rate is not available
+*		  because there was too much error
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+	u32 IterBAUDDIV;	/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 ModeReg;
+	u32 InputClk;
+
+	/*
+	 * Asserts validate the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
+	Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
+
+	/*
+	 * Make sure the baud rate is not impossilby large.
+	 * Fastest possible baud rate is Input Clock / 2.
+	 */
+	if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+		return XST_UART_BAUD_ERROR;
+	}
+	/*
+	 * Check whether the input clock is divided by 8
+	 */
+	ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+				 XUARTPS_MR_OFFSET);
+
+	InputClk = InstancePtr->Config.InputClockHz;
+	if(ModeReg & XUARTPS_MR_CLKSEL) {
+		InputClk = InstancePtr->Config.InputClockHz / 8;
+	}
+
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+		/*
+		 * Calculate the value for BRGR register
+		 */
+		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+		/*
+		 * Calculate the baud rate from the BRGR value
+		 */
+		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+		/*
+		 * Avoid unsigned integer underflow
+		 */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		}
+		else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/*
+		 * Find the calculated baud rate closest to requested baud rate.
+		 */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/*
+	 * Make sure the best error is not too large.
+	 */
+	PercentError = (Best_Error * 100) / BaudRate;
+	if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+		return XST_UART_BAUD_ERROR;
+	}
+
+	/*
+	 * Disable TX and RX to avoid glitches when setting the baud rate.
+	 */
+	XUartPs_DisableUart(InstancePtr);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+	/*
+	 * RX and TX SW reset
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+				XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+	/*
+	 * Enable device
+	 */
+	XUartPs_EnableUart(InstancePtr);
+
+	InstancePtr->BaudRate = BaudRate;
+
+	return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+* @param	ByteCount is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount)
+{
+	(void *) CallBackRef;
+	(void) Event;
+	(void) ByteCount;
+	/*
+	 * Assert occurs always since this is a stub and should never be called
+	 */
+	Xil_AssertVoidAlways();
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps.h
new file mode 100644
index 000000000..ae72e66d7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps.h
@@ -0,0 +1,509 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* 
+*	baud_rate = input_clock / (bgen * (bdiv + 1)
+* 

+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+*
+* 

+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H		/* prevent circular inclusions */
+#define XUARTPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE	 921600U
+#define XUARTPS_MIN_RATE	 110U
+
+#define XUARTPS_DFT_BAUDRATE  115200U   /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified.  These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK	0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK	0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT	0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX		0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX		0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS	0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR	0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM		0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL		(u8)0x00U	/**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO		(u8)0x01U	/**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP	(u8)0x02U	/**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP	(u8)0x03U	/**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS		0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS		2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS		3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY	4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY	3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY	2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY	1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY	0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT	2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT	1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT	0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA		1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT		2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA		3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR	4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM			5U /**< Modem status changed */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+	u32 InputClockHz;/**< Input clock frequency */
+	s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+				 *  to MIO or FMIO */
+} XUartPs_Config;
+
+/*
+ * Keep track of state information about a data buffer in the interrupt mode.
+ */
+typedef struct {
+	u8 *NextBytePtr;
+	u32 RequestedBytes;
+	u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+	u32 BaudRate;	/**< In bps, ie 1200 */
+	u32 DataBits;	/**< Number of data bits */
+	u32 Parity;		/**< Parity */
+	u8 StopBits;	/**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+				  u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XUartPs_Config Config;	/* Configuration data structure */
+	u32 InputClockHz;	/* Input clock frequency */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 BaudRate;		/* Current baud rate */
+
+	XUartPsBuffer SendBuffer;
+	XUartPsBuffer ReceiveBuffer;
+
+	XUartPs_Handler Handler;
+	void *CallBackRef;	/* Callback reference for event handler */
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr)   \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr)  \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+			(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if a byte can be sent
+*		- FALSE if the Transmitter Fifo is not empty
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr)				\
+	((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+	 (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Static lookup function implemented in xuartps_sinit.c
+ */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interface functions implemented in xuartps.c
+ */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				  XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/*
+ * Options functions in xuartps_options.c
+ */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/*
+ * interrupt functions in xuartps_intr.c
+ */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+			 void *CallBackRef);
+
+/*
+ * self-test functions in xuartps_selftest.c
+ */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_g.c
new file mode 100644
index 000000000..f117c6868
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_g.c
@@ -0,0 +1,63 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_UART_0_DEVICE_ID,
+		XPAR_PSU_UART_0_BASEADDR,
+		XPAR_PSU_UART_0_UART_CLK_FREQ_HZ,
+		XPAR_PSU_UART_0_HAS_MODEM
+	},
+	{
+		XPAR_PSU_UART_1_DEVICE_ID,
+		XPAR_PSU_UART_1_BASEADDR,
+		XPAR_PSU_UART_1_UART_CLK_FREQ_HZ,
+		XPAR_PSU_UART_1_HAS_MODEM
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_hw.c
new file mode 100644
index 000000000..3dd652c7f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_hw.c
@@ -0,0 +1,197 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.05a hk     08/22/13 Added reset function
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	Data contains the byte to be sent.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+	/*
+	 * Wait until there is space in TX FIFO
+	 */
+	while (XUartPs_IsTransmitFull(BaseAddress)) {
+		;
+	}
+
+	/*
+	 * Write the byte into the TX FIFO
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	The data byte received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+	u32 RecievedByte;
+	/*
+	 * Wait until there is data
+	 */
+	while (!XUartPs_IsReceiveData(BaseAddress)) {
+		;
+	}
+	RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+	/*
+	 * Return the byte received
+	 */
+	return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+	/*
+	 * Disable interrupts
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+	/*
+	 * Disable receive and transmit
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+	/*
+	 * Software reset of receive and transmit
+	 * This clears the FIFO.
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+	/*
+	 * Clear status flags - SW reset wont clear sticky flags.
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+	/*
+	 * Mode register reset value : All zeroes
+	 * Normal mode, even parity, 1 stop bit
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+				XUARTPS_MR_CHMODE_NORM);
+
+	/*
+	 * Rx and TX trigger register reset values
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+				XUARTPS_RXWM_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+				XUARTPS_TXWM_RESET_VAL);
+
+	/*
+	 * Rx timeout disabled by default
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+				XUARTPS_RXTOUT_DISABLE);
+
+	/*
+	 * Baud rate generator and dividor reset values
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+				XUARTPS_BAUDGEN_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+				XUARTPS_BAUDDIV_RESET_VAL);
+
+	/*
+	 * Control register reset value -
+	 * RX and TX are disable by default
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+						(u32)XUARTPS_CR_STOPBRK));
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_hw.h
new file mode 100644
index 000000000..a47629dae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_hw.h
@@ -0,0 +1,424 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
+#define XUARTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET		0x0000U  /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET		0x0004U  /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET		0x0008U  /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET		0x000CU  /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET		0x0010U  /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET		0x0014U  /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET	0x0018U  /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET	0x001CU  /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET		0x0020U  /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET	0x0024U  /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET	0x0028U  /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET		0x002CU  /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET		0x0030U  /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET	0x0034U  /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET	0x0038U  /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET		0x0044U  /**< TX FIFO Trigger Level [5:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK	0x00000100U  /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK	0x00000080U  /**< Set break */
+#define XUARTPS_CR_TORST	0x00000040U  /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS	0x00000020U  /**< TX disabled. */
+#define XUARTPS_CR_TX_EN	0x00000010U  /**< TX enabled */
+#define XUARTPS_CR_RX_DIS	0x00000008U  /**< RX disabled. */
+#define XUARTPS_CR_RX_EN	0x00000004U  /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK	0x0000003CU  /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST	0x00000002U  /**< TX logic reset */
+#define XUARTPS_CR_RXRST	0x00000001U  /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK				0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO		0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM		0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT				8U  /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK		0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT			6U  /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE		0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK		0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE		0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD		0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN		0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT				3U  /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK		0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT			1U  /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL			0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_TOVR	0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL	0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG	0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS		0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT	0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 	0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING	0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER	0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 	0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY	0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 	0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY	0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR  	0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK	0x00001FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE		0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK		0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL	0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK        0x000000FFU	/**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL   0x0000000FU	/**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE		0x00000000U  /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK			0x000000FFU  /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE	0x00000000U  /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM	0x00000010U  /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS	0x00000002U  /**< Request to send */
+#define XUARTPS_MODEMCR_DTR	0x00000001U  /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS	0x00000100U  /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD		0x00000080U  /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI		0x00000040U  /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR		0x00000020U  /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS		0x00000010U  /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD	0x00000008U  /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI  0x00000004U  /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR	0x00000002U  /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS	0x00000001U  /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL	0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG	0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL	0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE	0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE	0x00000400U /**< RX active */
+#define XUARTPS_SR_DMS		0x00000200U /**< Delta modem status change */
+#define XUARTPS_SR_TOUT		0x00000100U /**< RX timeout */
+#define XUARTPS_SR_PARITY	0x00000080U /**< RX parity error */
+#define XUARTPS_SR_FRAME	0x00000040U /**< RX frame error */
+#define XUARTPS_SR_OVER		0x00000020U /**< RX overflow error */
+#define XUARTPS_SR_TXFULL	0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY	0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL	0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY	0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR	0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK	XUARTPS_RXWM_MASK	/**< Valid bit mask */
+/* @} */
+
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX  XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX   XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX  XUARTPS_MODEMSR_DDSR
+#define	XUARTPS_MEDEMSR_CTSX  XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+*						   u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if there is receive data, FALSE otherwise.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress)			 \
+	!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+*		FIFO.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress)			 \
+	((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	 (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_intr.c
new file mode 100644
index 000000000..156d3e263
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_intr.c
@@ -0,0 +1,447 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+*
+* This file contains the functions for interrupt handling
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		The current interrupt mask. The mask indicates which interupts
+*		are enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+	/*
+	 * Assert validates the input argument
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/*
+	 * Read the Interrupt Mask register
+	 */
+	return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	Mask contains the interrupts to be enabled or disabled.
+*		A '1' enables an interupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+	u32 TempMask = Mask;
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	TempMask &= (u32)XUARTPS_IXR_MASK;
+
+	/*
+	 * Write the mask to the IER Register
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IER_OFFSET, TempMask);
+
+	/*
+	 * Write the inverse of the Mask to the IDR register
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IDR_OFFSET, (~TempMask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	FuncPtr is the pointer to the callback function.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+*
+* @return	None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+		 void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param	InstancePtr contains a pointer to the driver instance
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+	u32 IsrStatus;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the interrupt ID register to determine which
+	 * interrupt is active
+	 */
+	IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+
+	IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_ISR_OFFSET);
+
+	/*
+	 * Dispatch an appropriate handler.
+	 */
+	if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
+			(u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
+		/* Received data interrupt */
+		ReceiveDataHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
+									 != (u32)0) {
+		/* Transmit data interrupt */
+		SendDataHandler(InstancePtr, IsrStatus);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
+			(u32)XUARTPS_IXR_PARITY)) != (u32)0) {
+		/* Received Error Status interrupt */
+		ReceiveErrorHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
+		/* Received Timeout interrupt */
+		ReceiveTimeoutHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
+		/* Modem status interrupt */
+		ModemHandler(InstancePtr);
+	}
+
+	/*
+	 * Clear the interrupt status.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+		IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr)
+{
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	/*
+	 * Call the application handler to indicate that there is a receive
+	 * error or a break interrupt, if the application cares about the
+	 * error it call a function to get the last errors.
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef,
+				XUARTPS_EVENT_RECV_ERROR,
+				(InstancePtr->ReceiveBuffer.RequestedBytes -
+				InstancePtr->ReceiveBuffer.RemainingBytes));
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+	u32 Event;
+
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	/*
+	 * If there are no more bytes to receive then indicate that this is
+	 * not a receive timeout but the end of the buffer reached, a timeout
+	 * normally occurs if # of bytes is not divisible by FIFO threshold,
+	 * don't rely on previous test of remaining bytes since receive
+	 * function updates it
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		Event = XUARTPS_EVENT_RECV_TOUT;
+	} else {
+		Event = XUARTPS_EVENT_RECV_DATA;
+	}
+
+	/*
+	 * Call the application handler to indicate that there is a receive
+	 * timeout or data event
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+				 InstancePtr->ReceiveBuffer.RequestedBytes -
+				 InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	 if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	 /* If the last byte of a message was received then call the application
+	 * handler, this code should not use an else from the previous check of
+	 * the number of bytes to receive because the call to receive the buffer
+	 * updates the bytes ramained
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+				XUARTPS_EVENT_RECV_DATA,
+				(InstancePtr->ReceiveBuffer.RequestedBytes -
+				InstancePtr->ReceiveBuffer.RemainingBytes));
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	IsrStatus is the register value for channel status register
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+	/*
+	 * If there are not bytes to be sent from the specified buffer then disable
+	 * the transmit interrupt so it will stop interrupting as it interrupts
+	 * any time the FIFO is empty
+	 */
+	if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_IDR_OFFSET,
+				((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
+
+		/* Call the application handler to indicate the sending is done */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XUARTPS_EVENT_SENT_DATA,
+					InstancePtr->SendBuffer.RequestedBytes -
+					InstancePtr->SendBuffer.RemainingBytes);
+	}
+
+	/*
+	 * If TX FIFO is empty, send more.
+	 */
+	else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
+		(void)XUartPs_SendBuffer(InstancePtr);
+	}
+	else {
+		/* Else with dummy entry for MISRA-C Compliance.*/
+		;
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts.  It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+	u32 MsrRegister;
+
+	/*
+	 * Read the modem status register so that the interrupt is acknowledged
+	 * and it can be passed to the callback handler with the event
+	 */
+	MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			  XUARTPS_MODEMSR_OFFSET);
+
+	/*
+	 * Call the application handler to indicate the modem status changed,
+	 * passing the modem status and the event data in the call
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef,
+				  XUARTPS_EVENT_MODEM,
+				  MsrRegister);
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_options.c
new file mode 100644
index 000000000..d8ad1d7a7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_options.c
@@ -0,0 +1,814 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 1.00  sdm    09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+*			value was not being written to the register.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+	u16 Option;
+	u16 RegisterOffset;
+	u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+	{XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+	{XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+	{XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+	{XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+	{XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+	{XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_RTS},
+	{XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_DTR},
+	{XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS	  (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simulataneously.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The optionss are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+	u16 Options = 0U;
+	u32 Register;
+	u32 Index;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the physical options in the
+	 * registers of the UART to the logical options to be returned
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the bit in the register which correlates to the option
+		 * is set, then set the corresponding bit in the options,
+		 * ignoring any bits which are zero since the options variable
+		 * is initialized to zero
+		 */
+		if ((Register & OptionsTable[Index].Mask) != (u32)0) {
+			Options |= OptionsTable[Index].Option;
+		}
+	}
+
+	return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Options contains the options to be set which are bit masks
+*		contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+	u32 Index;
+	u32 Register;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the logical options to the
+	 * physical options in the registers of the UART.
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+		/*
+		 * Read the register which contains option so that the register
+		 * can be changed without destoying any other bits of the
+		 * register.
+		 */
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the option is set in the input, then set the corresponding
+		 * bit in the specified register, otherwise clear the bit in
+		 * the register.
+		 */
+		if ((Options & OptionsTable[Index].Option) != (u16)0) {
+			Register |= OptionsTable[Index].Mask;
+		}
+		else {
+			Register &= ~OptionsTable[Index].Mask;
+		}
+
+		/* Write the new value to the register to set the option */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   OptionsTable[Index].RegisterOffset,
+				   Register);
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current receive FIFO trigger level. This is a value
+*		from 0-31.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+	u8 RtrigRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the value of the FIFO control register so that the threshold
+	 * can be retrieved, this read takes special register processing
+	 */
+	RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XUARTPS_RXWM_OFFSET);
+
+	/* Return only the trigger level from the register value */
+
+	RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
+	return RtrigRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	TriggerLevel contains the trigger level to set.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+	u32 RtrigRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
+
+	/*
+	 * Write the new value for the FIFO control register to it such that the
+	 * threshold is changed
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+	u32 ModemStatusRegister;
+	u16 TmpRegister;
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the modem status register to return
+	 */
+	ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUARTPS_MODEMSR_OFFSET);
+	TmpRegister = (u16)ModemStatusRegister;
+	return TmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if the UART is sending data
+*		- FALSE if UART is not sending data
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+	u32 ChanStatRegister;
+	u32 ChanTmpSRegister;
+	u32 ActiveResult;
+	u32 EmptyResult;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel status register to determine if the transmitter is
+	 * active
+	 */
+	ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 XUARTPS_SR_OFFSET);
+
+	/*
+	 * If the transmitter is active, or the TX FIFO is not empty, then indicate
+	 * that the UART is still sending some data
+	 */
+	ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
+	EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
+	ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
+		(((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
+
+	return ChanTmpSRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+	u32 ModeRegister;
+	u8 OperMode;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Mode register.
+	 */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
+	/*
+	 * Return the constant
+	 */
+	switch (ModeRegister) {
+	case XUARTPS_MR_CHMODE_NORM:
+		OperMode = XUARTPS_OPER_MODE_NORMAL;
+		break;
+	case XUARTPS_MR_CHMODE_ECHO:
+		OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+		break;
+	case XUARTPS_MR_CHMODE_L_LOOP:
+		OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+		break;
+	case XUARTPS_MR_CHMODE_R_LOOP:
+		OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+		break;
+	default:
+		OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
+			XUARTPS_MR_CHMODE_SHIFT);
+		break;
+	}
+
+	return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	OperationMode is the mode of the UART.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+	u32 ModeRegister;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+	/*
+	 * Read the Mode register.
+	 */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/*
+	 * Set the correct value by masking the bits, then ORing the const.
+	 */
+	ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
+
+	switch (OperationMode) {
+		case XUARTPS_OPER_MODE_NORMAL:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
+			break;
+		case XUARTPS_OPER_MODE_AUTO_ECHO:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
+			break;
+		case XUARTPS_OPER_MODE_LOCAL_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
+			break;
+		case XUARTPS_OPER_MODE_REMOTE_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
+			break;
+		default:
+			/* Default case made for MISRA-C Compliance. */
+			break;
+	}
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+	u32 FdelTmpRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Mode register.
+	 */
+	FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XUARTPS_FLOWDEL_OFFSET);
+
+	/*
+	 * Return the contents of the flow delay register
+	 */
+	FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
+	return  FdelTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FlowDelayValue is the Setting for the flow delay.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+	u32 FdelRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the correct value by shifting the input constant, then masking
+	 * the bits
+	 */
+	FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current setting for receive time out.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+	u32 RtoRegister;
+	u8 RtoRTmpRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Receive Timeout register.
+	 */
+	RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUARTPS_RXTOUT_OFFSET);
+
+	/*
+	 * Return the contents of the mode register shifted appropriately
+	 */
+	RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
+	return RtoRTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RecvTimeout setting allows the UART to detect an idle connection
+*		on the reciever data line.
+*		Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+*		timeout function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+	u32 RtoRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the correct value by masking the bits
+	 */
+	RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+	/*
+	 * Configure CR to restart the receiver timeout counter
+	 */
+	RtoRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_CR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+			   (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure containing the data
+*		format to be set.
+*
+* @return
+*		- XST_SUCCESS if the data format was successfully set.
+*		- XST_UART_BAUD_ERROR indicates the baud rate could not be
+*		set because of the amount of error with the baud rate and
+*		the input clock frequency.
+*		- XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+* 


+*
+*****************************************************************************/
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
+			XUartPsFormat * FormatPtr)
+{
+	s32 Status;
+	u32 ModeRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FormatPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Verify the inputs specified are valid
+	 */
+	if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
+		(FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
+		(FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
+		Status = XST_INVALID_PARAM;
+	} else {
+
+		/*
+		 * Try to set the baud rate and if it's not successful then don't
+		 * continue altering the data format, this is done first to avoid the
+		 * format from being altered when an error occurs
+		 */
+		Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+		if (Status != (s32)XST_SUCCESS) {
+			;
+		} else {
+
+			ModeRegister =
+				XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						  XUARTPS_MR_OFFSET);
+
+			/*
+			 * Set the length of data (8,7,6) by first clearing out the bits
+			 * that control it in the register, then set the length in the register
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
+			ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+			/*
+			 * Set the number of stop bits in the mode register by first clearing
+			 * out the bits that control it in the register, then set the number
+			 * of stop bits in the register.
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
+			ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
+
+			/*
+			 * Set the parity by first clearing out the bits that control it in the
+			 * register, then set the bits in the register, the default is no parity
+			 * after clearing the register bits
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
+			ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+			/*
+			 * Update the mode register
+			 */
+			XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+					   ModeRegister);
+
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure that will contain
+*		the data format after this call completes.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+	u32 ModeRegister;
+
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FormatPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the baud rate from the instance, this is not retrieved from the
+	 * hardware because it is only kept as a divisor such that it is more
+	 * difficult to get back to the baud rate
+	 */
+	FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/*
+	 * Get the length of data (8,7,6,5)
+	 */
+	FormatPtr->DataBits =
+		((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
+		XUARTPS_MR_CHARLEN_SHIFT);
+
+	/*
+	 * Get the number of stop bits
+	 */
+	FormatPtr->StopBits =
+		(u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
+		XUARTPS_MR_STOPMODE_SHIFT);
+
+	/*
+	 * Determine what parity is
+	 */
+	FormatPtr->Parity =
+		(u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
+		XUARTPS_MR_PARITY_SHIFT);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_selftest.c
new file mode 100644
index 000000000..a5a4757f4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_selftest.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES (u8)32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+*		 - XST_SUCCESS if the test was successful
+*		- XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrRegister;
+	u32 ModeRegister;
+	u8 Index;
+	u32 ReceiveDataResult;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable all interrupts in the interrupt disable register
+	 */
+	IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/*
+	 * Setup for local loopback
+	 */
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_MR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
+				(u32)XUARTPS_MR_CHMODE_L_LOOP));
+
+	/*
+	 * Send a number of bytes and receive them, one at a time.
+	 */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		/*
+		 * Send out the byte and if it was not sent then the failure
+		 * will be caught in the comparison at the end
+		 */
+		(void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
+
+		/*
+		 * Wait until the byte is received. This can hang if the HW
+		 * is broken. Watch for the FIFO empty flag to be false.
+		 */
+		ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+				XUARTPS_SR_RXEMPTY;
+		while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
+			ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+					XUARTPS_SR_RXEMPTY;
+		}
+
+		/*
+		 * Receive the byte
+		 */
+		(void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
+	}
+
+	/*
+	 * Compare the bytes received to the bytes sent to verify the exact data
+	 * was received
+	 */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		if (TestString[Index] != ReturnString[Index]) {
+			Status = XST_UART_TEST_FAIL;
+		}
+	}
+
+	/*
+	 * Restore the registers which were altered to put into polling and
+	 * loopback modes so that this test is not destructive
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+			   IntrRegister);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_sinit.c
new file mode 100644
index 000000000..e9dfaa96e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_0/src/xuartps_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+*
+* The implementation of the XUartPs driver's static initialzation
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device
+*
+* @return	A pointer to the configuration structure or NULL if the
+*		specified device is not in the system.
+*
+* @note		None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+	XUartPs_Config *CfgPtr = NULL;
+
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+		if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XUartPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XUartPs_Config *)CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/Makefile
new file mode 100644
index 000000000..d30648814
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xusbps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling usbpsu"
+
+xusbps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xusbps_includes
+
+xusbps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu.c
new file mode 100644
index 000000000..1a67a0ffd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu.c
@@ -0,0 +1,689 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.c
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    01/22/15 First release
+* 1.00a bss    03/18/15 Added XUsbPsu_Wait_Clear_Timeout and
+*						XUsbPsu_Wait_Set_Timeout functions
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is cleared or timeout occurs
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	Offset is register offset.
+* @param	BitMask is bit mask of required bit to be checked.
+* @param	Timeout is the time to wait specified in micro seconds.
+*
+* @return
+*			- XST_SUCCESS when bit is cleared.
+*			- XST_FAILURE when timed out.
+*
+******************************************************************************/
+int XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout)
+{
+	u32 RegVal;
+
+	do {
+		RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+		if (!(RegVal & BitMask))
+			break;
+		Timeout--;
+		if (!Timeout)
+			return XST_FAILURE;
+		usleep(1);
+	} while (1);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is set or timeout occurs
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	Offset is register offset.
+* @param	BitMask is bit mask of required bit to be checked.
+* @param	Timeout is the time to wait specified in micro seconds.
+*
+* @return
+*			- XST_SUCCESS when bit is set.
+*			- XST_FAILURE when timed out.
+*
+******************************************************************************/
+int XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout)
+{
+	u32 RegVal;
+
+	do {
+		RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+		if (RegVal & BitMask)
+			break;
+		Timeout--;
+		if (!Timeout)
+			return XST_FAILURE;
+		usleep(1);
+	} while (1);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Sets mode of Core to USB Device/Host/OTG.
+*
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	Mode is mode to set
+*			- XUSBPSU_GCTL_PRTCAP_OTG
+*			- XUSBPSU_GCTL_PRTCAP_HOST
+*			- XUSBPSU_GCTL_PRTCAP_DEVICE
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode)
+{
+	u32 RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Mode <= XUSBPSU_GCTL_PRTCAP_OTG &&
+					Mode >= XUSBPSU_GCTL_PRTCAP_HOST);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+	RegVal &= ~(XUSBPSU_GCTL_PRTCAPDIR(XUSBPSU_GCTL_PRTCAP_OTG));
+	RegVal |= XUSBPSU_GCTL_PRTCAPDIR(Mode);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Issues core PHY reset.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr)
+{
+	u32		RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Before Resetting PHY, put Core in Reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+	RegVal |= XUSBPSU_GCTL_CORESOFTRESET;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+	/* Assert USB3 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+	RegVal |= XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+	/* Assert USB2 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+	RegVal |= XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+	usleep(XUSBPSU_PHY_TIMEOUT);
+
+	/* Clear USB3 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+	RegVal &= ~XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+	/* Clear USB2 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+	RegVal &= ~XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+	usleep(XUSBPSU_PHY_TIMEOUT);
+
+	/* After PHYs are stable we can take Core out of reset State */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+	RegVal &= ~XUSBPSU_GCTL_CORESOFTRESET;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Sets up Event buffers so that events are written by Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr)
+{
+    struct XUsbPsu_EvtBuffer *Evt;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	Evt = &InstancePtr->Evt;
+	Evt->BuffAddr = (void *)InstancePtr->EventBuffer;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0),
+						(UINTPTR)InstancePtr->EventBuffer);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0),
+						((UINTPTR)(InstancePtr->EventBuffer) >> 16) >> 16);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0),
+					XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer)));
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0);
+}
+
+/*****************************************************************************/
+/**
+* Resets Event buffer Registers to zero so that events are not written by Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0), 0);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0), 0);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0),
+			XUSBPSU_GEVNTSIZ_INTMASK | XUSBPSU_GEVNTSIZ_SIZE(0));
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0);
+}
+
+/*****************************************************************************/
+/**
+* Reads data from Hardware Params Registers of Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	RegIndex is Register number to read
+*			- XUSBPSU_GHWPARAMS0
+*			- XUSBPSU_GHWPARAMS1
+*			- XUSBPSU_GHWPARAMS2
+*			- XUSBPSU_GHWPARAMS3
+*			- XUSBPSU_GHWPARAMS4
+*			- XUSBPSU_GHWPARAMS5
+*			- XUSBPSU_GHWPARAMS6
+*			- XUSBPSU_GHWPARAMS7
+*
+* @return	One of the GHWPARAMS RegValister contents.
+*
+******************************************************************************/
+u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(RegIndex >= XUSBPSU_GHWPARAMS0 &&
+				RegIndex <= XUSBPSU_GHWPARAMS7);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, (XUSBPSU_GHWPARAMS0_OFFSET +
+							(RegIndex * 4)));
+	return RegVal;
+}
+
+/*****************************************************************************/
+/**
+* Initializes Core.
+*
+* @param  InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return
+*	 	- XST_SUCCESS if initialization was successful
+*		- XST_FAILURE if initialization was not successful
+*
+******************************************************************************/
+int XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr)
+{
+	u32		RegVal;
+	u32		Hwparams1;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* issue device SoftReset too */
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, XUSBPSU_DCTL_CSFTRST);
+
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DCTL,
+			XUSBPSU_DCTL_CSFTRST, 500) == XST_FAILURE) {
+		/* timed out return failure */
+		return XST_FAILURE;
+	}
+
+	XUsbPsu_PhyReset(InstancePtr);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+    RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK;
+    RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE;
+
+	Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1);
+
+	switch (XUSBPSU_GHWPARAMS1_EN_PWROPT(Hwparams1)) {
+    case XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK:
+	RegVal &= ~XUSBPSU_GCTL_DSBLCLKGTNG;
+        break;
+    case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB:
+	/* enable hibernation here */
+	break;
+    default:
+	break;
+	}
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Enables an interrupt in Event Enable RegValister.
+*
+* @param  InstancePtr is a pointer to the XUsbPsu instance to be worked on
+* @param  Mask is the OR of any Interrupt Enable Masks:
+*		- XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+*		- XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+*		- XUSBPSU_DEVTEN_CMDCMPLTEN
+*		- XUSBPSU_DEVTEN_ERRTICERREN
+*		- XUSBPSU_DEVTEN_SOFEN
+*		- XUSBPSU_DEVTEN_EOPFEN
+*		- XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+*		- XUSBPSU_DEVTEN_WKUPEVTEN
+*		- XUSBPSU_DEVTEN_ULSTCNGEN
+*		- XUSBPSU_DEVTEN_CONNECTDONEEN
+*		- XUSBPSU_DEVTEN_USBRSTEN
+*		- XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return  None
+*
+******************************************************************************/
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+    u32	RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+    RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+    RegVal |= Mask;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Disables an interrupt in Event Enable RegValister.
+*
+* @param  InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param  Mask is the OR of Interrupt Enable Masks
+*		- XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+*		- XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+*		- XUSBPSU_DEVTEN_CMDCMPLTEN
+*		- XUSBPSU_DEVTEN_ERRTICERREN
+*		- XUSBPSU_DEVTEN_SOFEN
+*		- XUSBPSU_DEVTEN_EOPFEN
+*		- XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+*		- XUSBPSU_DEVTEN_WKUPEVTEN
+*		- XUSBPSU_DEVTEN_ULSTCNGEN
+*		- XUSBPSU_DEVTEN_CONNECTDONEEN
+*		- XUSBPSU_DEVTEN_USBRSTEN
+*		- XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return  None
+*
+******************************************************************************/
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+	u32 RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+	RegVal &= ~Mask;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/****************************************************************************/
+/**
+*
+* This function does the following:
+*	- initializes a specific XUsbPsu instance.
+*	- sets up Event Buffer for Core to write events.
+*	- Core Reset and PHY Reset.
+*	- Sets core in Device Mode.
+*	- Sets default speed as HIGH_SPEED.
+*	- Sets Device Address to 0.
+*	- Enables interrupts.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	ConfigPtr points to the XUsbPsu device configuration structure.
+* @param	BaseAddress is the device base address in the virtual memory
+*			address space. If the address translation is not used then the
+*			physical address is passed.
+*			Unexpected errors may occur if the address mapping is changed
+*			after this function is invoked.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+			XUsbPsu_Config *ConfigPtr, u32 BaseAddress)
+{
+	int Ret;
+	u32 RegVal;
+	u32 IntrMask;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr   != NULL);
+
+	InstancePtr->ConfigPtr = ConfigPtr;
+
+	Ret = XUsbPsu_CoreInit(InstancePtr);
+	if (Ret) {
+		return XST_FAILURE;
+	}
+
+	RegVal = XUsbPsu_ReadHwParams(InstancePtr, 3);
+	InstancePtr->NumInEps = XUSBPSU_NUM_IN_EPS(RegVal);
+	InstancePtr->NumOutEps = XUSBPSU_NUM_EPS(RegVal) - InstancePtr->NumInEps;
+
+	/* Map USB and Physical Endpoints */
+	XUsbPsu_InitializeEps(InstancePtr);
+
+	XUsbPsu_EventBuffersSetup(InstancePtr);
+
+	XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE);
+
+	XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_HIGHSPEED);
+
+	XUsbPsu_SetDeviceAddress(InstancePtr, 0);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Starts the controller so that Host can detect this device.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_Start(struct XUsbPsu *InstancePtr)
+{
+	u32			RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+
+	RegVal |= XUSBPSU_DCTL_RUN_STOP;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+			XUSBPSU_DSTS_DEVCTRLHLT, 500) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Stops the controller so that Device disconnects from Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_Stop(struct XUsbPsu *InstancePtr)
+{
+	u32			RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_RUN_STOP;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	if (XUsbPsu_Wait_Set_Timeout(InstancePtr, XUSBPSU_DSTS,
+			XUSBPSU_DSTS_DEVCTRLHLT, 500) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+ * Enables USB2 Test Modes
+ *
+ * @param	InstancePtr is a pointer to the XUsbPsu instance.
+ * @param	Mode is Test mode to set.
+ *
+ * @return	XST_SUCCESS else XST_FAILURE
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+int XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, int Mode)
+{
+	u32		RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Mode >= TEST_J && Mode <= TEST_FORCE_ENABLE);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+
+	switch (Mode) {
+	case TEST_J:
+	case TEST_K:
+	case TEST_SE0_NAK:
+	case TEST_PACKET:
+	case TEST_FORCE_ENABLE:
+		RegVal |= Mode << 1;
+		break;
+	default:
+		return XST_FAILURE;
+	}
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+ * Gets current State of USB Link
+ *
+ * @param	InstancePtr is a pointer to the XUsbPsu instance.
+ *
+ * @return	Link State
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+u32 XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr)
+{
+	u32		RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+
+	return XUSBPSU_DSTS_USBLNKST(RegVal);
+}
+
+/****************************************************************************/
+/**
+ * Sets USB Link to a particular State
+ *
+ * @param	InstancePtr is a pointer to the XUsbPsu instance.
+ * @param	State is State of Link to set.
+ *
+ * @return	XST_SUCCESS else XST_FAILURE
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+int XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr, u8 State)
+{
+	u32		RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	 /* Wait until device controller is ready. */
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+			XUSBPSU_DSTS_DCNRD, 500) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_ULSTCHNGREQ_MASK;
+
+	RegVal |= XUSBPSU_DCTL_ULSTCHNGREQ(State);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sets speed of the Core for connecting to Host
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Speed is required speed
+*				- XUSBPSU_DCFG_HIGHSPEED
+*				- XUSBPSU_DCFG_FULLSPEED2
+*				- XUSBPSU_DCFG_LOWSPEED
+*				- XUSBPSU_DCFG_FULLSPEED1
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed)
+{
+	u32	RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Speed >= XUSBPSU_DCFG_HIGHSPEED &&
+			Speed <= XUSBPSU_DCFG_SUPERSPEED);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+	RegVal &= ~(XUSBPSU_DCFG_SPEED_MASK);
+	RegVal |= Speed;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Sets Device Address of the Core
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Addr is address to set.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+int XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Addr <= 127);
+
+	if (InstancePtr->State == XUSBPSU_STATE_CONFIGURED) {
+		return XST_FAILURE;
+	}
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+	RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+	RegVal |= XUSBPSU_DCFG_DEVADDR(Addr);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+
+	if (Addr != 0)
+		InstancePtr->State = XUSBPSU_STATE_ADDRESS;
+	else
+		InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+
+	return XST_FAILURE;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu.h
new file mode 100644
index 000000000..a7ad3d7e7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu.h
@@ -0,0 +1,569 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.h
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    01/22/15 First release
+* 1.00a bss    03/18/15 Added support for Non-control endpoints
+*						Added mass storage example
+*
+* 

+*
+*****************************************************************************/
+#ifndef XUSBPSU_H  /* Prevent circular inclusions */
+#define XUSBPSU_H  /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xusbpsu_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+#define ALIGNMENT_CACHELINE		__attribute__ ((aligned(64)))
+
+#define	XUSBPSU_PHY_TIMEOUT		5000 /* in micro seconds */
+
+#define XUSBPSU_EP_DIR_IN				1
+#define XUSBPSU_EP_DIR_OUT				0
+
+#define USB_ENDPOINT_NUMBER_MASK        0x0f    /* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK           0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK      0x03    /* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL       0
+#define USB_ENDPOINT_XFER_ISOC          1
+#define USB_ENDPOINT_XFER_BULK          2
+#define USB_ENDPOINT_XFER_INT           3
+#define USB_ENDPOINT_MAX_ADJUSTABLE     0x80
+
+#define	TEST_J							1
+#define	TEST_K							2
+#define	TEST_SE0_NAK					3
+#define	TEST_PACKET						4
+#define	TEST_FORCE_ENABLE				5
+
+#define XUSBPSU_NUM_TRBS				8
+
+#define XUSBPSU_EVENT_PENDING			(1 << 0)
+
+#define XUSBPSU_EP_ENABLED				(1 << 0)
+#define XUSBPSU_EP_STALL				(1 << 1)
+#define XUSBPSU_EP_WEDGE				(1 << 2)
+#define XUSBPSU_EP_BUSY					(1 << 4)
+#define XUSBPSU_EP_PENDING_REQUEST		(1 << 5)
+#define XUSBPSU_EP_MISSED_ISOC			(1 << 6)
+
+#define	XUSBPSU_GHWPARAMS0				0
+#define	XUSBPSU_GHWPARAMS1				1
+#define	XUSBPSU_GHWPARAMS2				2
+#define	XUSBPSU_GHWPARAMS3				3
+#define	XUSBPSU_GHWPARAMS4				4
+#define	XUSBPSU_GHWPARAMS5				5
+#define	XUSBPSU_GHWPARAMS6				6
+#define	XUSBPSU_GHWPARAMS7				7
+
+/* HWPARAMS0 */
+#define XUSBPSU_MODE(n)					((n) & 0x7)
+#define XUSBPSU_MDWIDTH(n)				(((n) & 0xff00) >> 8)
+
+/* HWPARAMS1 */
+#define XUSBPSU_NUM_INT(n)				(((n) & (0x3f << 15)) >> 15)
+
+/* HWPARAMS3 */
+#define XUSBPSU_NUM_IN_EPS_MASK			(0x1f << 18)
+#define XUSBPSU_NUM_EPS_MASK			(0x3f << 12)
+#define XUSBPSU_NUM_EPS(p)				(((p) &		\
+										(XUSBPSU_NUM_EPS_MASK)) >> 12)
+#define XUSBPSU_NUM_IN_EPS(p)			(((p) &		\
+										(XUSBPSU_NUM_IN_EPS_MASK)) >> 18)
+
+/* HWPARAMS7 */
+#define XUSBPSU_RAM1_DEPTH(n)			((n) & 0xffff)
+
+#define XUSBPSU_DEPEVT_XFERCOMPLETE		0x01
+#define XUSBPSU_DEPEVT_XFERINPROGRESS	0x02
+#define XUSBPSU_DEPEVT_XFERNOTREADY		0x03
+#define XUSBPSU_DEPEVT_STREAMEVT		0x06
+#define XUSBPSU_DEPEVT_EPCMDCMPLT		0x07
+
+/* Within XferNotReady */
+#define DEPEVT_STATUS_TRANSFER_ACTIVE	(1 << 3)
+
+/* Within XferComplete */
+#define DEPEVT_STATUS_BUSERR			(1 << 0)
+#define DEPEVT_STATUS_SHORT				(1 << 1)
+#define DEPEVT_STATUS_IOC				(1 << 2)
+#define DEPEVT_STATUS_LST				(1 << 3)
+
+/* Stream event only */
+#define DEPEVT_STREAMEVT_FOUND			1
+#define DEPEVT_STREAMEVT_NOTFOUND		2
+
+/* Control-only Status */
+#define DEPEVT_STATUS_CONTROL_DATA				1
+#define DEPEVT_STATUS_CONTROL_STATUS			2
+#define DEPEVT_STATUS_CONTROL_DATA_INVALTRB		9
+#define DEPEVT_STATUS_CONTROL_STATUS_INVALTRB	0xA
+
+#define XUSBPSU_ENDPOINTS_NUM			12
+
+#define XUSBPSU_EVENT_SIZE				4       /* bytes */
+#define XUSBPSU_EVENT_MAX_NUM			64      /* 2 events/endpoint */
+#define XUSBPSU_EVENT_BUFFERS_SIZE		(XUSBPSU_EVENT_SIZE * \
+										XUSBPSU_EVENT_MAX_NUM)
+
+#define XUSBPSU_EVENT_TYPE_MASK                 0xfe
+
+#define XUSBPSU_EVENT_TYPE_DEV                  0
+#define XUSBPSU_EVENT_TYPE_CARKIT               3
+#define XUSBPSU_EVENT_TYPE_I2C                  4
+
+#define XUSBPSU_DEVICE_EVENT_DISCONNECT         0
+#define XUSBPSU_DEVICE_EVENT_RESET              1
+#define XUSBPSU_DEVICE_EVENT_CONNECT_DONE       2
+#define XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE 3
+#define XUSBPSU_DEVICE_EVENT_WAKEUP             4
+#define XUSBPSU_DEVICE_EVENT_HIBER_REQ          5
+#define XUSBPSU_DEVICE_EVENT_EOPF               6
+#define XUSBPSU_DEVICE_EVENT_SOF                7
+#define XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR      9
+#define XUSBPSU_DEVICE_EVENT_CMD_CMPL           10
+#define XUSBPSU_DEVICE_EVENT_OVERFLOW           11
+
+#define XUSBPSU_GEVNTCOUNT_MASK                 0xfffc
+
+/*
+ * Control Endpoint state
+ */
+#define	XUSBPSU_EP0_SETUP_PHASE				1	/**< Setup Phase */
+#define	XUSBPSU_EP0_DATA_PHASE				2	/**< Data Phase */
+#define	XUSBPSU_EP0_STATUS_PHASE			3	/**< Status Pahse */
+
+/*
+ * Link State
+ */
+#define		XUSBPSU_LINK_STATE_U0			0x00 /**< in HS - ON */
+#define		XUSBPSU_LINK_STATE_U1			0x01
+#define		XUSBPSU_LINK_STATE_U2			0x02 /**< in HS - SLEEP */
+#define		XUSBPSU_LINK_STATE_U3			0x03 /**< in HS - SUSPEND */
+#define		XUSBPSU_LINK_STATE_SS_DIS		0x04
+#define		XUSBPSU_LINK_STATE_RX_DET		0x05
+#define		XUSBPSU_LINK_STATE_SS_INACT		0x06
+#define		XUSBPSU_LINK_STATE_POLL			0x07
+#define		XUSBPSU_LINK_STATE_RECOV		0x08
+#define		XUSBPSU_LINK_STATE_HRESET		0x09
+#define		XUSBPSU_LINK_STATE_CMPLY		0x0A
+#define		XUSBPSU_LINK_STATE_LPBK			0x0B
+#define		XUSBPSU_LINK_STATE_RESET		0x0E
+#define		XUSBPSU_LINK_STATE_RESUME		0x0F
+#define		XUSBPSU_LINK_STATE_MASK			0x0F
+
+/*
+ * Device States
+ */
+#define		XUSBPSU_STATE_ATTACHED			0
+#define		XUSBPSU_STATE_POWERED			1
+#define		XUSBPSU_STATE_DEFAULT			2
+#define		XUSBPSU_STATE_ADDRESS			3
+#define		XUSBPSU_STATE_CONFIGURED		4
+#define		XUSBPSU_STATE_SUSPENDED			5
+
+/*
+ * Device Speeds
+ */
+#define		XUSBPSU_SPEED_UNKNOWN			0
+#define		XUSBPSU_SPEED_LOW				1
+#define		XUSBPSU_SPEED_FULL				2
+#define		XUSBPSU_SPEED_HIGH				3
+#define		XUSBPSU_SPEED_SUPER				4
+
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XUSBPSU
+ * device.
+ */
+typedef struct {
+        u16 DeviceId;           /**< Unique ID of controller */
+        u32 BaseAddress;        /**< Core register base address */
+} XUsbPsu_Config;
+
+/**
+ * Software Event buffer representation
+ */
+struct XUsbPsu_EvtBuffer {
+	void	*BuffAddr;
+	u32		Offset;
+	u32		Count;
+	u32		Flags;
+};
+
+/**
+ * Transfer Request Block - Hardware format
+ */
+struct XUsbPsu_Trb {
+	u32		BufferPtrLow;
+	u32		BufferPtrHigh;
+	u32		Size;
+	u32		Ctrl;
+} __attribute__((packed));
+
+
+/*
+ * Endpoint Parameters
+ */
+struct XUsbPsu_EpParams {
+	u32	Param2;		/**< Parameter 2 */
+	u32	Param1;		/**< Parameter 1 */
+	u32	Param0;		/**< Parameter 0 */
+};
+
+/**
+ * USB Standard Control Request
+ */
+typedef struct {
+        u8  bRequestType;
+        u8  bRequest;
+        u16 wValue;
+        u16 wIndex;
+        u16 wLength;
+} __attribute__ ((packed)) SetupPacket;
+
+/**
+ * Endpoint representation
+ */
+struct XUsbPsu_Ep {
+	void (*Handler)(void *, u32, u32);
+						/** < User handler called
+						 *   when data is sent for IN Ep
+						 *   and received for OUT Ep
+						 */
+	struct XUsbPsu_Trb	EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */
+	u32	EpStatus;		/**< Flags to represent Endpoint status */
+	u32	RequestedBytes;	/**< RequestedBytes for transfer */
+	u32	BytesTxed;		/**< Actual Bytes transferred */
+	u32	Cmd;			/**< command issued to EP lately */
+	u16	MaxSize;		/**< Size of endpoint */
+	u8	*BufferPtr;		/**< Buffer location */
+	u8	ResourceIndex;	/**< Resource Index assigned to
+						 *  Endpoint by core
+						 */
+	u8	PhyEpNum;		/**< Physical Endpoint Number in core */
+	u8	UsbEpNum;		/**< USB Endpoint Number */
+	u8	Type;			/**< Type of Endpoint -
+						 *	 Control/BULK/INTERRUPT/ISOC
+						 */
+	u8	Direction;		/**< Direction - EP_DIR_OUT/EP_DIR_IN */
+	u8	UnalignedTx;
+};
+
+/**
+ * USB Device Controller representation
+ */
+struct XUsbPsu {
+	SetupPacket SetupData ALIGNMENT_CACHELINE;
+					/**< Setup Packet buffer */
+	struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE;
+					/**< TRB for control transfers */
+	XUsbPsu_Config *ConfigPtr;	/**< Configuration info pointer */
+	struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */
+	struct XUsbPsu_EvtBuffer Evt;
+	struct XUsbPsu_EpParams EpParams;
+	u32 BaseAddress;	/**< Core register base address */
+	u32 MaxSpeed;
+	u32 DevDescSize;
+	u32 ConfigDescSize;
+	void (*Chapter9)(struct XUsbPsu *, SetupPacket *);
+	void (*ClassHandler)(struct XUsbPsu *, SetupPacket *);
+	void *DevDesc;
+	void *ConfigDesc;
+	u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE]
+						__attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE)));
+	u8 NumOutEps;
+	u8 NumInEps;
+	u8 ControlDir;
+	u8 IsInTestMode;
+	u8 TestMode;
+	u8 Speed;
+	u8 State;
+	u8 Ep0State;
+	u8 LinkState;
+	u8 UnalignedTx;
+	u8 IsConfigDone;
+	u8 IsThreeStage;
+};
+
+struct XUsbPsu_Event_Type {
+	u32	Is_DevEvt:1;
+	u32	Type:7;
+	u32	Reserved8_31:24;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_depvt - Device Endpoint Events
+ * @Is_EpEvt: indicates this is an endpoint event
+ * @endpoint_number: number of the endpoint
+ * @endpoint_event: The event we have:
+ *	0x00	- Reserved
+ *	0x01	- XferComplete
+ *	0x02	- XferInProgress
+ *	0x03	- XferNotReady
+ *	0x04	- RxTxFifoEvt (IN->Underrun, OUT->Overrun)
+ *	0x05	- Reserved
+ *	0x06	- StreamEvt
+ *	0x07	- EPCmdCmplt
+ * @Reserved11_10: Reserved, don't use.
+ * @Status: Indicates the status of the event. Refer to databook for
+ *	more information.
+ * @Parameters: Parameters of the current event. Refer to databook for
+ *	more information.
+ */
+struct XUsbPsu_Event_Epevt {
+	u32	Is_EpEvt:1;
+	u32	Epnumber:5;
+	u32	Endpoint_Event:4;
+	u32	Reserved11_10:2;
+	u32	Status:4;
+	u32	Parameters:16;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_devt - Device Events
+ * @Is_DevEvt: indicates this is a non-endpoint event
+ * @Device_Event: indicates it's a device event. Should read as 0x00
+ * @Type: indicates the type of device event.
+ *	0	- DisconnEvt
+ *	1	- USBRst
+ *	2	- ConnectDone
+ *	3	- ULStChng
+ *	4	- WkUpEvt
+ *	5	- Reserved
+ *	6	- EOPF
+ *	7	- SOF
+ *	8	- Reserved
+ *	9	- ErrticErr
+ *	10	- CmdCmplt
+ *	11	- EvntOverflow
+ *	12	- VndrDevTstRcved
+ * @Reserved15_12: Reserved, not used
+ * @Event_Info: Information about this event
+ * @Reserved31_25: Reserved, not used
+ */
+struct XUsbPsu_Event_Devt {
+	u32	Is_DevEvt:1;
+	u32	Device_Event:7;
+	u32	Type:4;
+	u32	Reserved15_12:4;
+	u32	Event_Info:9;
+	u32	Reserved31_25:7;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_gevt - Other Core Events
+ * @one_bit: indicates this is a non-endpoint event (not used)
+ * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
+ * @phy_port_number: self-explanatory
+ * @reserved31_12: Reserved, not used.
+ */
+struct XUsbPsu_Event_Gevt {
+	u32	Is_GlobalEvt:1;
+	u32	Device_Event:7;
+	u32	Phy_Port_Number:4;
+	u32	Reserved31_12:20;
+} __attribute__((packed));
+
+/**
+ * union XUsbPsu_event - representation of Event Buffer contents
+ * @raw: raw 32-bit event
+ * @type: the type of the event
+ * @depevt: Device Endpoint Event
+ * @devt: Device Event
+ * @gevt: Global Event
+ */
+union XUsbPsu_Event {
+	u32				Raw;
+	struct XUsbPsu_Event_Type	Type;
+	struct XUsbPsu_Event_Epevt	Epevt;
+	struct XUsbPsu_Event_Devt	Devt;
+	struct XUsbPsu_Event_Gevt	Gevt;
+};
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define IS_ALIGNED(x, a)	(((x) & ((typeof(x))(a) - 1)) == 0)
+
+#define roundup(x, y) (                                 \
+{                                                       \
+        const typeof(y) __y = y;                        \
+        (((x) + (__y - 1)) / __y) * __y;                \
+}                                                       \
+)
+
+#define DECLARE_DEV_DESC(Instance, desc)			\
+	(Instance).DevDesc = &(desc); 					\
+	(Instance).DevDescSize = sizeof((desc))
+
+#define DECLARE_CONFIG_DESC(Instance, desc) 		\
+	(Instance).ConfigDesc = &(desc); 				\
+	(Instance).ConfigDescSize = sizeof((desc))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xusbpsu.c
+ */
+int XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout);
+int XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout);
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 mode);
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_CoreNumEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_cache_hwparams(struct XUsbPsu *InstancePtr);
+int XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+int XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+			XUsbPsu_Config *ConfigPtr, u32 BaseAddress);
+int XUsbPsu_Start(struct XUsbPsu *InstancePtr);
+int XUsbPsu_Stop(struct XUsbPsu *InstancePtr);
+int XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, int mode);
+u32 XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr);
+int XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
+				u8 state);
+int XUsbPsu_SendGenericCmd(struct XUsbPsu *InstancePtr,
+					int cmd, u32 param);
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed);
+int XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr);
+
+/*
+ * Functions in xusbpsu_endpoint.c
+ */
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr);
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+				u8 dir);
+const char *XUsbPsu_EpCmdString(u8 cmd);
+int XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 ep, u8 direction,
+			u32 cmd, struct XUsbPsu_EpParams *params);
+int XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 ep,
+				u8 dir);
+int XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 ep, u8 dir,
+				u16 size, u8 type);
+int XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 ep, u8 dir);
+int XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 dir,
+			u16 maxsize, u8 type);
+int XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 dir);
+int XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 size);
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 ep, u8 dir);
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr);
+int XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 EpNum,
+			u8 *BufferPtr, u32 BufferLen);
+int XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 EpNum,
+				u8 *BufferPtr, u32 length);
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 epnum, u8 Dir);
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 epnum, u8 Dir);
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 epnum,
+			u8 dir, void (*Handler)(void *, u32, u32));
+int XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+
+/*
+ * Functions in xusbpsu_controltransfers.c
+ */
+int XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr);
+int XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr,
+				SetupPacket *ctrl);
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *event);
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *event);
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+			const struct XUsbPsu_Event_Epevt *event);
+int XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+				const struct XUsbPsu_Event_Epevt *event);
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+					struct XUsbPsu_Ep *dep);
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *event);
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *event);
+int XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr,
+			u32 BufferLen);
+int XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length);
+
+/*
+ * Functions in xusbpsu_intr.c
+ */
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *event);
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr,
+				u32 evtinfo);
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Devt *event);
+void XUsbPsu_ProcessEvent(struct XUsbPsu *InstancePtr,
+                const union XUsbPsu_Event *event);
+void XUsbPsu_ProcessEvtBuffer(struct XUsbPsu *InstancePtr);
+void XUsbPsu_IntrHandler(void *XUsbPsu);
+
+/*
+ * Functions in xusbpsu_sinit.c
+ */
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_controltransfers.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_controltransfers.c
new file mode 100644
index 000000000..5d7d8060a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_controltransfers.c
@@ -0,0 +1,702 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_controltransfers.c
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bss  01/22/15 First release
+* 1.00a bss  03/18/15 Modified u32 pointer casts to UINTPTR.
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+#define USB_DIR_OUT				0		/* to device */
+#define USB_DIR_IN				0x80	/* to host */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Initiates DMA on Control Endpoint 0 to receive Setup packet.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Trb	*TrbPtr;
+	struct XUsbPsu_Ep	*Ept;
+	int	Ret;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	/* Setup packet always on EP0 */
+	Ept = &InstancePtr->eps[0];
+	if (Ept->EpStatus & XUSBPSU_EP_BUSY) {
+		return XST_FAILURE;
+	}
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+	TrbPtr->Size = 8;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_SETUP;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange(TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Params->Param0 = 0;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+
+	Ept->Cmd = XUSBPSU_DEPCMD_STARTTRANSFER;
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0, XUSBPSU_EP_DIR_OUT,
+				XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret < 0) {
+		return Ret;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = XUsbPsu_EpGetTransferIndex(InstancePtr,
+						Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls Control Endpoint and restarts to receive Setup packet.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_Ep		*Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* reinitialize physical ep1 */
+	Ept = &InstancePtr->eps[1];
+	Ept->EpStatus = XUSBPSU_EP_ENABLED;
+
+	/* stall is always issued on EP0 */
+	XUsbPsu_EpSetStall(InstancePtr, 0, XUSBPSU_EP_DIR_OUT);
+
+	Ept = &InstancePtr->eps[0];
+	Ept->EpStatus = XUSBPSU_EP_ENABLED;
+	InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+	XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Changes State of Core to USB configured State.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Ctrl is a pointer to the Setup packet data.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr, SetupPacket *Ctrl)
+{
+	u8 State;
+	int Ret;
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Ctrl != NULL);
+
+	State = InstancePtr->State;
+	InstancePtr->IsConfigDone = 0;
+
+	switch (State) {
+	case XUSBPSU_STATE_DEFAULT:
+		return XST_FAILURE;
+		break;
+
+	case XUSBPSU_STATE_ADDRESS:
+		InstancePtr->State = XUSBPSU_STATE_CONFIGURED;
+		break;
+
+	case XUSBPSU_STATE_CONFIGURED:
+		break;
+
+	default:
+		Ret = XST_FAILURE;
+		break;
+	}
+
+	return Ret;
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+						 const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32	Status;
+	u32	Length;
+	u32	EpNum;
+	u8	Dir;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	EpNum = Event->Epnumber;
+	Dir = !!EpNum;
+	Ept = &InstancePtr->eps[EpNum];
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	Xil_DCacheInvalidateRange(TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size);
+	if (Status == XUSBPSU_TRBSTS_SETUP_PENDING) {
+		return;
+	}
+
+	Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+	if (Length && Dir) { /* IN */
+		Ept->BytesTxed = Ept->RequestedBytes - Length;
+	}
+
+	if (!Length) {
+		Ept->BytesTxed = Ept->RequestedBytes;
+	}
+
+	if (Length && !Dir) { /* OUT */
+		/* may be  wLength < Maxpacketsize */
+		if (InstancePtr->UnalignedTx) {
+			Ept->BytesTxed = Ept->RequestedBytes;
+			InstancePtr->UnalignedTx = 0;
+		}
+	}
+
+	if (!Dir) {
+		/* Invalidate Cache */
+		Xil_DCacheInvalidateRange(Ept->BufferPtr, Ept->BytesTxed);
+	}
+
+	if (Ept->Handler) {
+		Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+	}
+}
+
+/****************************************************************************/
+/**
+* Checks the Status Phase and starts next Control transfer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32	Status;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	if (InstancePtr->IsInTestMode) {
+		int Ret;
+
+		Ret = XUsbPsu_SetTestMode(InstancePtr,
+					InstancePtr->TestMode);
+		if (Ret < 0) {
+			XUsbPsu_Ep0StallRestart(InstancePtr);
+			return;
+		}
+	}
+	Xil_DCacheInvalidateRange(TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size);
+	/* There is nothing driver can do for Setup Pending received */
+
+	XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer complete event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+							 const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep *Ept;
+	SetupPacket *Ctrl;
+	u16 Length;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Ept = &InstancePtr->eps[Event->Epnumber];
+	Ctrl = &InstancePtr->SetupData;
+
+	Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = 0;
+
+	switch (InstancePtr->Ep0State) {
+	case XUSBPSU_EP0_SETUP_PHASE:
+		Xil_DCacheInvalidateRange(&InstancePtr->SetupData,
+					sizeof(InstancePtr->SetupData));
+		Length = Ctrl->wLength;
+		if (!Length) {
+			InstancePtr->IsThreeStage = 0;
+			InstancePtr->ControlDir = XUSBPSU_EP_DIR_OUT;
+		} else {
+			InstancePtr->IsThreeStage = 1;
+			InstancePtr->ControlDir = !!(Ctrl->bRequestType &
+							USB_DIR_IN);
+		}
+
+		if (InstancePtr->Chapter9 == NULL) {
+				/* ? */
+		} else {
+			InstancePtr->Chapter9(InstancePtr,
+									&InstancePtr->SetupData);
+		}
+		break;
+
+	case XUSBPSU_EP0_DATA_PHASE:
+		XUsbPsu_Ep0DataDone(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_EP0_STATUS_PHASE:
+		XUsbPsu_Ep0StatusDone(InstancePtr, Event);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Starts Status Phase of Control Transfer
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+				const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep  *Ept;
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Trb *TrbPtr;
+	u32 Type;
+	int Ret;
+	u8 Dir;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Event != NULL);
+
+	Ept = &InstancePtr->eps[Event->Epnumber];
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	if (Ept->EpStatus & XUSBPSU_EP_BUSY) {
+		return XST_FAILURE;
+	}
+
+	Type = InstancePtr->IsThreeStage ? XUSBPSU_TRBCTL_CONTROL_STATUS3
+					: XUSBPSU_TRBCTL_CONTROL_STATUS2;
+	TrbPtr = &InstancePtr->Ep0_Trb;
+	/* we use same TrbPtr for setup packet */
+	TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+	TrbPtr->Size = 0;
+	TrbPtr->Ctrl = Type;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange(TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Params->Param0 = 0;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_STATUS_PHASE;
+
+	/*
+	 * Control OUT transfer - Status stage happens on EP0 IN - EP1
+	 * Control IN transfer - Status stage happens on EP0 OUT - EP0
+	 */
+	Dir = !InstancePtr->ControlDir;
+	Ept->Cmd = XUSBPSU_DEPCMD_STARTTRANSFER;
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0, Dir,
+							XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = XUsbPsu_EpGetTransferIndex(InstancePtr,
+							Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Ends Data Phase - used incase of error.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Dep is a pointer to the Endpoint structure.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+								struct XUsbPsu_Ep *Ept)
+{
+	struct XUsbPsu_EpParams *Params;
+	u32	Cmd;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Ept != NULL);
+
+	if (!Ept->ResourceIndex)
+		return;
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+	Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+	Ept->Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+	XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
+						Cmd, Params);
+	Ept->ResourceIndex = 0;
+	usleep(200);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer Not Ready event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+							 const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Ept = &InstancePtr->eps[Event->Epnumber];
+
+	switch (Event->Status) {
+	case DEPEVT_STATUS_CONTROL_DATA:
+		/*
+		 * We already have a DATA transfer in the controller's cache,
+		 * if we receive a XferNotReady(DATA) we will ignore it, unless
+		 * it's for the wrong direction.
+		 *
+		 * In that case, we must issue END_TRANSFER command to the Data
+		 * Phase we already have started and issue SetStall on the
+		 * control endpoint.
+		 */
+		if (Event->Epnumber != InstancePtr->ControlDir) {
+			XUsbPsu_Ep0_EndControlData(InstancePtr, Ept);
+			XUsbPsu_Ep0StallRestart(InstancePtr);
+		}
+		break;
+
+	case DEPEVT_STATUS_CONTROL_STATUS:
+		XUsbPsu_Ep0StartStatus(InstancePtr, Event);
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Handles Interrupts of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event)
+{
+	u32 EpNum;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	EpNum = Event->Epnumber;
+	switch (Event->Endpoint_Event) {
+	case XUSBPSU_DEPEVT_XFERCOMPLETE:
+		XUsbPsu_Ep0XferComplete(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_DEPEVT_XFERNOTREADY:
+		XUsbPsu_Ep0XferNotReady(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_DEPEVT_XFERINPROGRESS:
+	case XUSBPSU_DEPEVT_STREAMEVT:
+	case XUSBPSU_DEPEVT_EPCMDCMPLT:
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on Control Endpoint EP0 IN to Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	BufferPtr is pointer to data.
+* @param	BufferLen is Length of data buffer.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen)
+{
+	/* Control IN - EP1 */
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Ep 	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32 Type;
+	int Ret;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	Ept = &InstancePtr->eps[1];
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	if (Ept->EpStatus & XUSBPSU_EP_BUSY) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = BufferLen;
+	Ept->BytesTxed = 0;
+	Ept->BufferPtr = BufferPtr;
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	TrbPtr->BufferPtrLow  = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh  = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = BufferLen;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Params->Param0 = 0;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	Xil_DCacheFlushRange(TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheFlushRange(BufferPtr, BufferLen);
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+	Ept->Cmd = XUSBPSU_DEPCMD_STARTTRANSFER;
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0, XUSBPSU_EP_DIR_IN,
+							XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = XUsbPsu_EpGetTransferIndex(InstancePtr,
+						Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Control Endpoint EP0 OUT from Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	BufferPtr is pointer to data.
+* @param	Length is Length of data to be received.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length)
+{
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Ep 	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32 Type;
+	u32 Size;
+	int Ret;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	Ept = &InstancePtr->eps[0];
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	if (Ept->EpStatus & XUSBPSU_EP_BUSY) {
+		return XST_FAILURE;
+	}
+
+	Size = Ept->RequestedBytes = Length;
+	Ept->BytesTxed = 0;
+	Ept->BufferPtr = BufferPtr;
+
+	/*
+	 * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+	 * must be a multiple of MaxPacketSize even if software is expecting a
+	 * fixed non-multiple of MaxPacketSize transfer from the Host.
+	 */
+	if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+		Size = roundup(Length, Ept->MaxSize);
+		InstancePtr->UnalignedTx = 1;
+	}
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = Size;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange(TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Params->Param0 = 0;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+	Ept->Cmd = XUSBPSU_DEPCMD_STARTTRANSFER;
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0, XUSBPSU_EP_DIR_OUT,
+				XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret < 0) {
+		return Ret;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = XUsbPsu_EpGetTransferIndex(InstancePtr,
+							Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_endpoint.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_endpoint.c
new file mode 100644
index 000000000..8e7d4c5cd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_endpoint.c
@@ -0,0 +1,925 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_endpoint.c
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bss  01/22/15 First release
+* 1.00a bss  03/18/15 Added XUsbPsu_EpXferComplete function to handle Non
+*					  control endpoint interrupt.
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* return Physical EP number as dwc3 mapping */
+#define PhysicalEp(epnum, direction)	((epnum) << 1 ) | (direction)
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Returns zeroed parameters to be used by Endpoint commands
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	Zeroed Params structure pointer.
+*
+* @note		None.
+*
+*****************************************************************************/
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	InstancePtr->EpParams.Param0 = 0x00;
+	InstancePtr->EpParams.Param1 = 0x00;
+	InstancePtr->EpParams.Param2 = 0x00;
+
+	return &InstancePtr->EpParams;
+}
+
+/****************************************************************************/
+/**
+* Returns Transfer Index assigned by Core for an Endpoint transfer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT
+*
+* @return	Transfer Resource Index.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+								u8 Dir)
+{
+	u8 PhyEpNum;
+	u32 ResourceIndex;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum >= 0 && UsbEpNum <= 16);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+	ResourceIndex = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum));
+
+	return XUSBPSU_DEPCMD_GET_RSC_IDX(ResourceIndex);
+}
+
+/****************************************************************************/
+/**
+* Sends Endpoint command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint
+*			- XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+* @param	Cmd is Endpoint command.
+* @param	Params is Endpoint command parameters.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+					  u32 Cmd, struct XUsbPsu_EpParams *Params)
+{
+	u32	RegVal;
+	u32	PhyEpnum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum >= 0 && UsbEpNum <= 16);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+					  (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpnum = PhysicalEp(UsbEpNum, Dir);
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR0(PhyEpnum),
+					 Params->Param0);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR1(PhyEpnum),
+					 Params->Param1);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR2(PhyEpnum),
+					 Params->Param2);
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpnum),
+			Cmd | XUSBPSU_DEPCMD_CMDACT);
+
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DEPCMD(PhyEpnum),
+			XUSBPSU_DEPCMD_CMDACT, 500) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Start New Configuration command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint
+*			- XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note
+* 			As per data book this command should be issued by software
+*			under these conditions:
+*				1. After power-on-reset with XferRscIdx=0 before starting
+*				   to configure Physical Endpoints 0 and 1.
+*				2. With XferRscIdx=2 before starting to configure
+*				   Physical Endpoints > 1
+*				3. This command should always be issued to
+*				   Endpoint 0 (DEPCMD0).
+*
+*****************************************************************************/
+int XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir)
+{
+	struct XUsbPsu_EpParams *Params;
+	u32	Cmd;
+	u8 PhyEpNum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum >= 0 && UsbEpNum <= 16);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+					  (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+	Params =  XUsbPsu_GetEpParams(InstancePtr);
+
+	if (PhyEpNum != 1) {
+		Cmd = XUSBPSU_DEPCMD_DEPSTARTCFG;
+		/* XferRscIdx == 0 for EP0 and 2 for the remaining */
+		if (PhyEpNum > 1) {
+			if (InstancePtr->IsConfigDone)
+				return XST_SUCCESS;
+			InstancePtr->IsConfigDone = 1;
+			Cmd |= XUSBPSU_DEPCMD_PARAM(2);
+		}
+		InstancePtr->eps[0].Cmd = XUSBPSU_DEPCMD_DEPSTARTCFG;
+		return XUsbPsu_SendEpCmd(InstancePtr, 0, XUSBPSU_EP_DIR_OUT,
+								 Cmd, Params);
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Set Endpoint Configuration command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param	Size is size of Endpoint size.
+* @param	Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+						u16 Size, u8 Type)
+{
+	struct XUsbPsu_EpParams *Params;
+	u8 PhyEpnum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum >= 0 && UsbEpNum <= 16);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+	Xil_AssertNonvoid(Size >= 64 && Size <= 1024);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	PhyEpnum = PhysicalEp(UsbEpNum , Dir);
+
+	Params->Param0 = XUSBPSU_DEPCFG_EP_TYPE(Type)
+		| XUSBPSU_DEPCFG_MAX_PACKET_SIZE(Size);
+
+	Params->Param1 = XUSBPSU_DEPCFG_XFER_COMPLETE_EN
+		| XUSBPSU_DEPCFG_XFER_NOT_READY_EN;
+
+	/*
+	 * We are doing 1:1 mapping for endpoints, meaning
+	 * Physical Endpoints 2 maps to Logical Endpoint 2 and
+	 * so on. We consider the direction bit as part of the physical
+	 * endpoint number. So USB endpoint 0x81 is 0x03.
+	 */
+	Params->Param1 |= XUSBPSU_DEPCFG_EP_NUMBER(PhyEpnum);
+
+	if (Dir)
+		 Params->Param0 |= XUSBPSU_DEPCFG_FIFO_NUMBER(PhyEpnum >> 1);
+
+	InstancePtr->eps[PhyEpnum].Cmd = XUSBPSU_DEPCMD_SETEPCONFIG;
+
+	return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+							 XUSBPSU_DEPCMD_SETEPCONFIG, Params);
+}
+
+/****************************************************************************/
+/**
+* Sends Set Transfer Resource command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/
+*											XUSBPSU_EP_DIR_OUT.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+	struct XUsbPsu_EpParams *Params;
+	u8 PhyEpnum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum >= 0 && UsbEpNum <= 16);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpnum = PhysicalEp(UsbEpNum , Dir);
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+
+	Params->Param0 = XUSBPSU_DEPXFERCFG_NUM_XFER_RES(1);
+
+	InstancePtr->eps[PhyEpnum].Cmd = XUSBPSU_DEPCMD_SETTRANSFRESOURCE;
+
+	return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+							 XUSBPSU_DEPCMD_SETTRANSFRESOURCE, Params);
+}
+
+/****************************************************************************/
+/**
+* Enables Endpoint for sending/receiving data.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param	Maxsize is size of Endpoint size.
+* @param	Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+int XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+			u16 Maxsize, u8 Type)
+{
+	struct XUsbPsu_Ep *Ept;
+	u32 RegVal;
+	int Ret = XST_FAILURE;
+	u32 PhyEpnum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum >= 0 && UsbEpNum <= 16);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+					  (Dir == XUSBPSU_EP_DIR_OUT));
+	Xil_AssertNonvoid(Maxsize >= 64 && Maxsize <= 1024);
+
+	PhyEpnum = PhysicalEp(UsbEpNum , Dir);
+	Ept = &InstancePtr->eps[PhyEpnum];
+
+	Ept->UsbEpNum	= UsbEpNum;
+	Ept->Direction	= Dir;
+	Ept->Type	= Type;
+	Ept->MaxSize	= Maxsize;
+	Ept->PhyEpNum	= PhyEpnum;
+
+	if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) {
+		Ret = XUsbPsu_StartEpConfig(InstancePtr, UsbEpNum, Dir);
+		if (Ret)
+			return Ret;
+	}
+
+	Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, Type);
+	if (Ret)
+		return Ret;
+
+	if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) {
+		Ret = XUsbPsu_SetXferResource(InstancePtr, UsbEpNum, Dir);
+		if (Ret)
+			return Ret;
+
+		Ept->EpStatus |= XUSBPSU_EP_ENABLED;
+
+		RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+		RegVal |= XUSBPSU_DALEPENA_EP(Ept->PhyEpNum);
+		XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Disables Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint
+*			- XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+int XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+	u32	RegVal;
+	u8	PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum >= 0 && UsbEpNum <= 16);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+	RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+
+	Ept->Type = 0;
+	Ept->EpStatus = 0;
+	Ept->MaxSize = 0;
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enables USB Control Endpoint i.e., EP0OUT and EP0IN of Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Size is control endpoint size.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+int XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size)
+{
+	int RetVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Size >= 64 && Size <= 512);
+
+	RetVal = XUsbPsu_EpEnable(InstancePtr, 0, XUSBPSU_EP_DIR_OUT, Size,
+				USB_ENDPOINT_XFER_CONTROL);
+	if (RetVal) {
+		return XST_FAILURE;
+	}
+
+	RetVal = XUsbPsu_EpEnable(InstancePtr, 0, XUSBPSU_EP_DIR_IN, Size,
+				USB_ENDPOINT_XFER_CONTROL);
+	if (RetVal) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initializes Endpoints. All OUT endpoints are even numbered and all IN
+* endpoints are odd numbered. EP0 is for Control OUT and EP1 is for
+* Control IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_Ep	*Ept;
+	u8  i;
+	u8 epnum;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	for (i = 0; i < InstancePtr->NumOutEps; i++) {
+		epnum = (i << 1) | XUSBPSU_EP_DIR_OUT;
+		InstancePtr->eps[epnum].PhyEpNum = epnum;
+		InstancePtr->eps[epnum].Direction = XUSBPSU_EP_DIR_OUT;
+	}
+	for (i = 0; i < InstancePtr->NumInEps; i++) {
+		epnum = (i << 1) | XUSBPSU_EP_DIR_IN;
+		InstancePtr->eps[epnum].PhyEpNum = epnum;
+		InstancePtr->eps[epnum].Direction = XUSBPSU_EP_DIR_IN;
+	}
+}
+
+/****************************************************************************/
+/**
+* Stops transfer on Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+	u8 PhyEpNum;
+	u32 Cmd;
+	int Ret;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(UsbEpNum >= 0 && UsbEpNum <= 16);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	if (!Ept->ResourceIndex)
+		return;
+
+	/*
+	 * - Issue EndTransfer WITH CMDIOC bit set
+	 * - Wait 100us
+	 */
+	Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+	Cmd |= XUSBPSU_DEPCMD_CMDIOC;
+	Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+	Ept->Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+							Cmd, Params);
+	Ept->ResourceIndex = 0;
+	Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+	usleep(100);
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on all endpoints.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_EpParams *Params;
+	u32 epnum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	for (epnum = 1; epnum < XUSBPSU_ENDPOINTS_NUM; epnum++) {
+
+		Ept = &InstancePtr->eps[epnum];
+		if (!Ept)
+			continue;
+
+		if (!(Ept->EpStatus & XUSBPSU_EP_STALL))
+			continue;
+
+		Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+
+		Ept->Cmd = XUSBPSU_DEPCMD_CLEARSTALL;
+		XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum,
+						  Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL,
+						  Params);
+	}
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on endpoint to Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEp is USB endpoint number.
+* @param	BufferPtr is pointer to data.
+* @param	BufferLen is length of data buffer.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
+						 u8 *BufferPtr, u32 BufferLen)
+{
+	u8	PhyEpNum;
+	int	RetVal;
+	struct XUsbPsu_Trb	*TrbPtr;
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEp >= 0 && UsbEp <= 16);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_IN);
+	if (PhyEpNum == 1)
+	{
+		RetVal = XUsbPsu_Ep0Send(InstancePtr, BufferPtr, BufferLen);
+		return RetVal;
+	}
+
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	if (Ept->Direction != XUSBPSU_EP_DIR_IN) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = BufferLen;
+	Ept->BytesTxed = 0;
+	Ept->BufferPtr = BufferPtr;
+
+	TrbPtr = &Ept->EpTrb;
+
+	TrbPtr->BufferPtrLow  = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh  = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+					| XUSBPSU_TRB_CTRL_LST
+					| XUSBPSU_TRB_CTRL_IOC
+					| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange(TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheFlushRange(BufferPtr, BufferLen);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Params->Param0 = 0;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	Ept->Cmd = XUSBPSU_DEPCMD_STARTTRANSFER;
+	RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+								XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (RetVal != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	Ept->ResourceIndex = XUsbPsu_EpGetTransferIndex(InstancePtr,
+													Ept->UsbEpNum,
+													Ept->Direction);
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Endpoint from Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	BufferPtr is pointer to data.
+* @param	Length is length of data to be received.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
+						 u8 *BufferPtr, u32 Length)
+{
+	u8	PhyEpNum;
+	u32 Size;
+	int	RetVal;
+	struct XUsbPsu_Trb	*TrbPtr;
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEp >= 0 && UsbEp <= 16);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_OUT);
+	if (PhyEpNum == 0)
+	{
+		RetVal = XUsbPsu_Ep0Recv(InstancePtr, BufferPtr, Length);
+		return RetVal;
+	}
+
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	if (Ept->Direction != XUSBPSU_EP_DIR_OUT) {
+		return XST_FAILURE;
+	}
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+
+	Size = Ept->RequestedBytes = Length;
+	Ept->BytesTxed = 0;
+	Ept->BufferPtr = BufferPtr;
+
+	/*
+	 * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+	 * must be a multiple of MaxPacketSize even if software is expecting a
+	 * fixed non-multiple of MaxPacketSize transfer from the Host.
+	 */
+	if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+		Size = roundup(Length, Ept->MaxSize);
+		Ept->UnalignedTx = 1;
+	}
+
+	TrbPtr = &Ept->EpTrb;
+
+	TrbPtr->BufferPtrLow  = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = Size;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+					| XUSBPSU_TRB_CTRL_LST
+					| XUSBPSU_TRB_CTRL_IOC
+					| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Params->Param0 = 0;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	Xil_DCacheFlushRange(TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Params->Param0 = 0;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	Ept->Cmd = XUSBPSU_DEPCMD_STARTTRANSFER;
+
+	RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+								XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (RetVal != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	Ept->ResourceIndex = XUsbPsu_EpGetTransferIndex(InstancePtr,
+													Ept->UsbEpNum,
+													Ept->Direction);
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls an Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir	is direction.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+	u8	PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum >= 0 && Epnum <= 16);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+
+	if ((PhyEpNum == 0) || (PhyEpNum == 1)) {
+		/* Control Endpoint stall is issued on EP0 */
+		Ept = &InstancePtr->eps[0];
+	}
+
+	Ept->Cmd = XUSBPSU_DEPCMD_SETSTALL;
+	XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+							XUSBPSU_DEPCMD_SETSTALL, Params);
+
+	Ept->EpStatus |= XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on an Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir	is direction.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+	u8	PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum >= 0 && Epnum <= 16);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+
+	if ((PhyEpNum == 0) || (PhyEpNum == 1)) {
+		/* Control Endpoint stall is issued on EP0 */
+		Ept = &InstancePtr->eps[0];
+	}
+
+	Ept->Cmd = XUSBPSU_DEPCMD_CLEARSTALL;
+	XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+							XUSBPSU_DEPCMD_CLEARSTALL, Params);
+
+	Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Sets an user handler to be called after data is sent/received by an Endpoint
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param	Handler is user handler to be called.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
+			u8 Dir, void (*Handler)(void *, u32, u32))
+{
+	u8 PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum >= 0 && Epnum <= 16);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+	Ept->Handler = Handler;
+}
+
+/****************************************************************************/
+/**
+* Returns status of endpoint - Stalled or not
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return
+*			1 - if stalled
+*			0 - if not stalled
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+	u8 PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum >= 0 && Epnum <= 16);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	return !!(Ept->EpStatus & XUSBPSU_EP_STALL);
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
+							const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32	Status;
+	u32	Length;
+	u32	EpNum;
+	u8	Dir;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	EpNum = Event->Epnumber;
+	Ept = &InstancePtr->eps[EpNum];
+	Dir = Ept->Direction;
+	TrbPtr = &Ept->EpTrb;
+
+	Xil_DCacheInvalidateRange(TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size);
+	Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+	if (Length && Dir) { /* IN */
+		Ept->BytesTxed = Ept->RequestedBytes - Length;
+	}
+
+	if (!Length) {
+		Ept->BytesTxed = Ept->RequestedBytes;
+	}
+
+	if (Length && !Dir) { /* OUT */
+		if (Ept->UnalignedTx == 1) {
+			Ept->BytesTxed = Ept->RequestedBytes;
+			Ept->UnalignedTx = 0;
+		}
+	}
+
+	if (!Dir) {
+		/* Invalidate Cache */
+		Xil_DCacheInvalidateRange(Ept->BufferPtr, Ept->BytesTxed);
+	}
+
+	if (Ept->Handler) {
+		Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_g.c
new file mode 100644
index 000000000..801651e10
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPsu_Config XUsbPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_USB_0_DEVICE_ID,
+		XPAR_PSU_USB_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_hw.h
new file mode 100644
index 000000000..cd5cd33ec
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_hw.h
@@ -0,0 +1,457 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_hw.h
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    01/22/15 First release
+*
+* 

+*
+*****************************************************************************/
+
+#ifndef XUSBPSU_HW_H	/* Prevent circular inclusions */
+#define XUSBPSU_HW_H	/* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+/************************** Constant Definitions ****************************/
+
+/**@name Register offsets
+ *
+ * The following constants provide access to each of the registers of the
+ * USBPSU device.
+ * @{
+ */
+
+/* XUSBPSU registers memory space boundries */
+#define XUSBPSU_GLOBALS_REGS_START              0xc100
+#define XUSBPSU_GLOBALS_REGS_END                0xc6ff
+#define XUSBPSU_DEVICE_REGS_START               0xc700
+#define XUSBPSU_DEVICE_REGS_END                 0xcbff
+#define XUSBPSU_OTG_REGS_START                  0xcc00
+#define XUSBPSU_OTG_REGS_END                    0xccff
+
+/* Global Registers */
+#define XUSBPSU_GSBUSCFG0                       0xc100
+#define XUSBPSU_GSBUSCFG1                       0xc104
+#define XUSBPSU_GTXTHRCFG                       0xc108
+#define XUSBPSU_GRXTHRCFG                       0xc10c
+#define XUSBPSU_GCTL                            0xc110
+#define XUSBPSU_GEVTEN                          0xc114
+#define XUSBPSU_GSTS                            0xc118
+#define XUSBPSU_GSNPSID                         0xc120
+#define XUSBPSU_GGPIO                           0xc124
+#define XUSBPSU_GUID                            0xc128
+#define XUSBPSU_GUCTL                           0xc12c
+#define XUSBPSU_GBUSERRADDR0                    0xc130
+#define XUSBPSU_GBUSERRADDR1                    0xc134
+#define XUSBPSU_GPRTBIMAP0                      0xc138
+#define XUSBPSU_GPRTBIMAP1                      0xc13c
+#define XUSBPSU_GHWPARAMS0_OFFSET               0xc140
+#define XUSBPSU_GHWPARAMS1_OFFSET               0xc144
+#define XUSBPSU_GHWPARAMS2_OFFSET               0xc148
+#define XUSBPSU_GHWPARAMS3_OFFSET               0xc14c
+#define XUSBPSU_GHWPARAMS4_OFFSET               0xc150
+#define XUSBPSU_GHWPARAMS5_OFFSET               0xc154
+#define XUSBPSU_GHWPARAMS6_OFFSET               0xc158
+#define XUSBPSU_GHWPARAMS7_OFFSET               0xc15c
+#define XUSBPSU_GDBGFIFOSPACE                   0xc160
+#define XUSBPSU_GDBGLTSSM                       0xc164
+#define XUSBPSU_GPRTBIMAP_HS0                   0xc180
+#define XUSBPSU_GPRTBIMAP_HS1                   0xc184
+#define XUSBPSU_GPRTBIMAP_FS0                   0xc188
+#define XUSBPSU_GPRTBIMAP_FS1                   0xc18c
+
+#define XUSBPSU_GUSB2PHYCFG(n)                  (0xc200 + (n * 0x04))
+#define XUSBPSU_GUSB2I2CCTL(n)                  (0xc240 + (n * 0x04))
+
+#define XUSBPSU_GUSB2PHYACC(n)                  (0xc280 + (n * 0x04))
+
+#define XUSBPSU_GUSB3PIPECTL(n)                 (0xc2c0 + (n * 0x04))
+
+#define XUSBPSU_GTXFIFOSIZ(n)                   (0xc300 + (n * 0x04))
+#define XUSBPSU_GRXFIFOSIZ(n)                   (0xc380 + (n * 0x04))
+
+#define XUSBPSU_GEVNTADRLO(n)                   (0xc400 + (n * 0x10))
+#define XUSBPSU_GEVNTADRHI(n)                   (0xc404 + (n * 0x10))
+#define XUSBPSU_GEVNTSIZ(n)                     (0xc408 + (n * 0x10))
+#define XUSBPSU_GEVNTCOUNT(n)                   (0xc40c + (n * 0x10))
+
+#define XUSBPSU_GHWPARAMS8                      0xc600
+
+/* Device Registers */
+#define XUSBPSU_DCFG                            0xc700
+#define XUSBPSU_DCTL                            0xc704
+#define XUSBPSU_DEVTEN                          0xc708
+#define XUSBPSU_DSTS                            0xc70c
+#define XUSBPSU_DGCMDPAR                        0xc710
+#define XUSBPSU_DGCMD                           0xc714
+#define XUSBPSU_DALEPENA                        0xc720
+#define XUSBPSU_DEPCMDPAR2(n)                   (0xc800 + (n * 0x10))
+#define XUSBPSU_DEPCMDPAR1(n)                   (0xc804 + (n * 0x10))
+#define XUSBPSU_DEPCMDPAR0(n)                   (0xc808 + (n * 0x10))
+#define XUSBPSU_DEPCMD(n)                       (0xc80c + (n * 0x10))
+
+/* OTG Registers */
+#define XUSBPSU_OCFG                            0xcc00
+#define XUSBPSU_OCTL                            0xcc04
+#define XUSBPSU_OEVT                            0xcc08
+#define XUSBPSU_OEVTEN                          0xcc0C
+#define XUSBPSU_OSTS                            0xcc10
+
+/* Bit fields */
+
+/* Global Configuration Register */
+#define XUSBPSU_GCTL_PWRDNSCALE(n)              ((n) << 19)
+#define XUSBPSU_GCTL_U2RSTECN                   (1 << 16)
+#define XUSBPSU_GCTL_RAMCLKSEL(x)       (((x) & XUSBPSU_GCTL_CLK_MASK) << 6)
+#define XUSBPSU_GCTL_CLK_BUS                    (0)
+#define XUSBPSU_GCTL_CLK_PIPE                   (1)
+#define XUSBPSU_GCTL_CLK_PIPEHALF               (2)
+#define XUSBPSU_GCTL_CLK_MASK                   (3)
+
+#define XUSBPSU_GCTL_PRTCAP(n)                  (((n) & (3 << 12)) >> 12)
+#define XUSBPSU_GCTL_PRTCAPDIR(n)               ((n) << 12)
+#define XUSBPSU_GCTL_PRTCAP_HOST                1
+#define XUSBPSU_GCTL_PRTCAP_DEVICE              2
+#define XUSBPSU_GCTL_PRTCAP_OTG                 3
+
+#define XUSBPSU_GCTL_CORESOFTRESET              (1 << 11)
+#define XUSBPSU_GCTL_SOFITPSYNC                 (1 << 10)
+#define XUSBPSU_GCTL_SCALEDOWN(n)               ((n) << 4)
+#define XUSBPSU_GCTL_SCALEDOWN_MASK             XUSBPSU_GCTL_SCALEDOWN(3)
+#define XUSBPSU_GCTL_DISSCRAMBLE                (1 << 3)
+#define XUSBPSU_GCTL_GBLHIBERNATIONEN           (1 << 1)
+#define XUSBPSU_GCTL_DSBLCLKGTNG                (1 << 0)
+
+/* Global Status Register Device Interrupt Mask */
+#define XUSBPSU_GSTS_DEVICE_IP_MASK 			0x00000040
+
+/* Global USB2 PHY Configuration Register */
+#define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST          (1 << 31)
+#define XUSBPSU_GUSB2PHYCFG_SUSPHY              (1 << 6)
+
+/* Global USB3 PIPE Control Register */
+#define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST         (1 << 31)
+#define XUSBPSU_GUSB3PIPECTL_SUSPHY             (1 << 17)
+
+/* Global TX Fifo Size Register */
+#define XUSBPSU_GTXFIFOSIZ_TXFDEF(n)            ((n) & 0xffff)
+#define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n)         ((n) & 0xffff0000)
+
+/* Global Event Size Registers */
+#define XUSBPSU_GEVNTSIZ_INTMASK                (1 << 31)
+#define XUSBPSU_GEVNTSIZ_SIZE(n)                ((n) & 0xffff)
+
+/* Global HWPARAMS1 Register */
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT(n)         (((n) & (3 << 24)) >> 24)
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO         0
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK        1
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB        2
+#define XUSBPSU_GHWPARAMS1_PWROPT(n)            ((n) << 24)
+#define XUSBPSU_GHWPARAMS1_PWROPT_MASK          XUSBPSU_GHWPARAMS1_PWROPT(3)
+
+/* Global HWPARAMS4 Register */
+#define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
+#define XUSBPSU_MAX_HIBER_SCRATCHBUFS           15
+
+/* Device Configuration Register */
+#define XUSBPSU_DCFG_DEVADDR(addr)              ((addr) << 3)
+#define XUSBPSU_DCFG_DEVADDR_MASK               XUSBPSU_DCFG_DEVADDR(0x7f)
+
+#define XUSBPSU_DCFG_SPEED_MASK					7
+#define XUSBPSU_DCFG_SUPERSPEED					4
+#define XUSBPSU_DCFG_HIGHSPEED					0
+#define XUSBPSU_DCFG_FULLSPEED2					1
+#define XUSBPSU_DCFG_LOWSPEED					2
+#define XUSBPSU_DCFG_FULLSPEED1					3
+
+#define XUSBPSU_DCFG_LPM_CAP                    (1 << 22)
+
+/* Device Control Register */
+#define XUSBPSU_DCTL_RUN_STOP                   (1 << 31)
+#define XUSBPSU_DCTL_CSFTRST                    (1 << 30)
+#define XUSBPSU_DCTL_LSFTRST                    (1 << 29)
+
+#define XUSBPSU_DCTL_HIRD_THRES_MASK            (0x1f << 24)
+#define XUSBPSU_DCTL_HIRD_THRES(n)              ((n) << 24)
+
+#define XUSBPSU_DCTL_APPL1RES                   (1 << 23)
+
+/* These apply for core versions 1.87a and earlier */
+#define XUSBPSU_DCTL_TRGTULST_MASK              (0x0f << 17)
+#define XUSBPSU_DCTL_TRGTULST(n)                ((n) << 17)
+#define XUSBPSU_DCTL_TRGTULST_U2                (XUSBPSU_DCTL_TRGTULST(2))
+#define XUSBPSU_DCTL_TRGTULST_U3                (XUSBPSU_DCTL_TRGTULST(3))
+#define XUSBPSU_DCTL_TRGTULST_SS_DIS            (XUSBPSU_DCTL_TRGTULST(4))
+#define XUSBPSU_DCTL_TRGTULST_RX_DET            (XUSBPSU_DCTL_TRGTULST(5))
+#define XUSBPSU_DCTL_TRGTULST_SS_INACT          (XUSBPSU_DCTL_TRGTULST(6))
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DCTL_KEEP_CONNECT               (1 << 19)
+#define XUSBPSU_DCTL_L1_HIBER_EN                (1 << 18)
+#define XUSBPSU_DCTL_CRS                        (1 << 17)
+#define XUSBPSU_DCTL_CSS                        (1 << 16)
+
+#define XUSBPSU_DCTL_INITU2ENA                  (1 << 12)
+#define XUSBPSU_DCTL_ACCEPTU2ENA                (1 << 11)
+#define XUSBPSU_DCTL_INITU1ENA                  (1 << 10)
+#define XUSBPSU_DCTL_ACCEPTU1ENA                (1 << 9)
+#define XUSBPSU_DCTL_TSTCTRL_MASK               (0xf << 1)
+
+#define XUSBPSU_DCTL_ULSTCHNGREQ_MASK           (0x0f << 5)
+#define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK)
+
+#define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION         (XUSBPSU_DCTL_ULSTCHNGREQ(0))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED       (XUSBPSU_DCTL_ULSTCHNGREQ(4))
+#define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT         (XUSBPSU_DCTL_ULSTCHNGREQ(5))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE       (XUSBPSU_DCTL_ULSTCHNGREQ(6))
+#define XUSBPSU_DCTL_ULSTCHNG_RECOVERY          (XUSBPSU_DCTL_ULSTCHNGREQ(8))
+#define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE        (XUSBPSU_DCTL_ULSTCHNGREQ(10))
+#define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK          (XUSBPSU_DCTL_ULSTCHNGREQ(11))
+
+/* Device Event Enable Register */
+#define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN        (1 << 12)
+#define XUSBPSU_DEVTEN_EVNTOVERFLOWEN           (1 << 11)
+#define XUSBPSU_DEVTEN_CMDCMPLTEN               (1 << 10)
+#define XUSBPSU_DEVTEN_ERRTICERREN              (1 << 9)
+#define XUSBPSU_DEVTEN_SOFEN                    (1 << 7)
+#define XUSBPSU_DEVTEN_EOPFEN                   (1 << 6)
+#define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN      (1 << 5)
+#define XUSBPSU_DEVTEN_WKUPEVTEN                (1 << 4)
+#define XUSBPSU_DEVTEN_ULSTCNGEN                (1 << 3)
+#define XUSBPSU_DEVTEN_CONNECTDONEEN            (1 << 2)
+#define XUSBPSU_DEVTEN_USBRSTEN                 (1 << 1)
+#define XUSBPSU_DEVTEN_DISCONNEVTEN             (1 << 0)
+
+/* Device Status Register */
+#define XUSBPSU_DSTS_DCNRD                      (1 << 29)
+
+/* This applies for core versions 1.87a and earlier */
+#define XUSBPSU_DSTS_PWRUPREQ                   (1 << 24)
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DSTS_RSS                        (1 << 25)
+#define XUSBPSU_DSTS_SSS                        (1 << 24)
+
+#define XUSBPSU_DSTS_COREIDLE                   (1 << 23)
+#define XUSBPSU_DSTS_DEVCTRLHLT                 (1 << 22)
+
+#define XUSBPSU_DSTS_USBLNKST_MASK              (0x0f << 18)
+#define XUSBPSU_DSTS_USBLNKST(n) (((n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18)
+
+#define XUSBPSU_DSTS_RXFIFOEMPTY                (1 << 17)
+
+#define XUSBPSU_DSTS_SOFFN_MASK                 (0x3fff << 3)
+#define XUSBPSU_DSTS_SOFFN(n)           (((n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3)
+
+#define XUSBPSU_DSTS_CONNECTSPD                 (7 << 0)
+
+#define XUSBPSU_DSTS_SUPERSPEED                 (4 << 0)
+#define XUSBPSU_DSTS_HIGHSPEED                  (0 << 0)
+#define XUSBPSU_DSTS_FULLSPEED2                 (1 << 0)
+#define XUSBPSU_DSTS_LOWSPEED                   (2 << 0)
+#define XUSBPSU_DSTS_FULLSPEED1                 (3 << 0)
+
+/* Device Generic Command Register */
+#define XUSBPSU_DGCMD_SET_LMP                   0x01
+#define XUSBPSU_DGCMD_SET_PERIODIC_PAR          0x02
+#define XUSBPSU_DGCMD_XMIT_FUNCTION             0x03
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO    0x04
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI    0x05
+
+#define XUSBPSU_DGCMD_SELECTED_FIFO_FLUSH       0x09
+#define XUSBPSU_DGCMD_ALL_FIFO_FLUSH            0x0a
+#define XUSBPSU_DGCMD_SET_ENDPOINT_NRDY         0x0c
+#define XUSBPSU_DGCMD_RUN_SOC_BUS_LOOPBACK      0x10
+
+#define XUSBPSU_DGCMD_STATUS(n)                 (((n) >> 15) & 1)
+#define XUSBPSU_DGCMD_CMDACT                    (1 << 10)
+#define XUSBPSU_DGCMD_CMDIOC                    (1 << 8)
+
+/* Device Generic Command Parameter Register */
+#define XUSBPSU_DGCMDPAR_FORCE_LINKPM_ACCEPT    (1 << 0)
+#define XUSBPSU_DGCMDPAR_FIFO_NUM(n)            ((n) << 0)
+#define XUSBPSU_DGCMDPAR_RX_FIFO                (0 << 5)
+#define XUSBPSU_DGCMDPAR_TX_FIFO                (1 << 5)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_DIS           (0 << 0)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_ENA           (1 << 0)
+
+/* Device Endpoint Command Register */
+#define XUSBPSU_DEPCMD_PARAM_SHIFT              16
+#define XUSBPSU_DEPCMD_PARAM(x)         ((x) << XUSBPSU_DEPCMD_PARAM_SHIFT)
+#define XUSBPSU_DEPCMD_GET_RSC_IDX(x)	(((x) >> XUSBPSU_DEPCMD_PARAM_SHIFT) & \
+					0x7f)
+#define XUSBPSU_DEPCMD_STATUS(x)                (((x) >> 12) & 0xF)
+#define XUSBPSU_DEPCMD_HIPRI_FORCERM            (1 << 11)
+#define XUSBPSU_DEPCMD_CMDACT                   (1 << 10)
+#define XUSBPSU_DEPCMD_CMDIOC                   (1 << 8)
+
+#define XUSBPSU_DEPCMD_DEPSTARTCFG              0x09
+#define XUSBPSU_DEPCMD_ENDTRANSFER              0x08
+#define XUSBPSU_DEPCMD_UPDATETRANSFER           0x07
+#define XUSBPSU_DEPCMD_STARTTRANSFER            0x06
+#define XUSBPSU_DEPCMD_CLEARSTALL               0x05
+#define XUSBPSU_DEPCMD_SETSTALL                 0x04
+#define XUSBPSU_DEPCMD_GETEPSTATE               0x03
+#define XUSBPSU_DEPCMD_SETTRANSFRESOURCE        0x02
+#define XUSBPSU_DEPCMD_SETEPCONFIG              0x01
+
+/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
+#define XUSBPSU_DALEPENA_EP(n)                  (1 << n)
+
+#define XUSBPSU_DEPCFG_INT_NUM(n)               ((n) << 0)
+#define XUSBPSU_DEPCFG_XFER_COMPLETE_EN         (1 << 8)
+#define XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN      (1 << 9)
+#define XUSBPSU_DEPCFG_XFER_NOT_READY_EN        (1 << 10)
+#define XUSBPSU_DEPCFG_FIFO_ERROR_EN            (1 << 11)
+#define XUSBPSU_DEPCFG_STREAM_EVENT_EN          (1 << 13)
+#define XUSBPSU_DEPCFG_BINTERVAL_M1(n)          ((n) << 16)
+#define XUSBPSU_DEPCFG_STREAM_CAPABLE           (1 << 24)
+#define XUSBPSU_DEPCFG_EP_NUMBER(n)             ((n) << 25)
+#define XUSBPSU_DEPCFG_BULK_BASED               (1 << 30)
+#define XUSBPSU_DEPCFG_FIFO_BASED               (1 << 31)
+
+/* DEPCFG parameter 0 */
+#define XUSBPSU_DEPCFG_EP_TYPE(n)               ((n) << 1)
+#define XUSBPSU_DEPCFG_MAX_PACKET_SIZE(n)       ((n) << 3)
+#define XUSBPSU_DEPCFG_FIFO_NUMBER(n)           ((n) << 17)
+#define XUSBPSU_DEPCFG_BURST_SIZE(n)            ((n) << 22)
+#define XUSBPSU_DEPCFG_DATA_SEQ_NUM(n)          ((n) << 26)
+/* This applies for core versions earlier than 1.94a */
+#define XUSBPSU_DEPCFG_IGN_SEQ_NUM              (1 << 31)
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DEPCFG_ACTION_INIT              (0 << 30)
+#define XUSBPSU_DEPCFG_ACTION_RESTORE           (1 << 30)
+#define XUSBPSU_DEPCFG_ACTION_MODIFY            (2 << 30)
+
+/* DEPXFERCFG parameter 0 */
+#define XUSBPSU_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
+
+#define XUSBPSU_DEPCMD_TYPE_BULK                2
+#define XUSBPSU_DEPCMD_TYPE_INTR                3
+
+/* TRB Length, PCM and Status */
+#define XUSBPSU_TRB_SIZE_MASK           (0x00ffffff)
+#define XUSBPSU_TRB_SIZE_LENGTH(n)      ((n) & XUSBPSU_TRB_SIZE_MASK)
+#define XUSBPSU_TRB_SIZE_PCM1(n)        (((n) & 0x03) << 24)
+#define XUSBPSU_TRB_SIZE_TRBSTS(n)      (((n) & (0x0f << 28)) >> 28)
+
+#define XUSBPSU_TRBSTS_OK               0
+#define XUSBPSU_TRBSTS_MISSED_ISOC      1
+#define XUSBPSU_TRBSTS_SETUP_PENDING    2
+#define XUSBPSU_TRB_STS_XFER_IN_PROG    4
+
+/* TRB Control */
+#define XUSBPSU_TRB_CTRL_HWO            (1 << 0)
+#define XUSBPSU_TRB_CTRL_LST            (1 << 1)
+#define XUSBPSU_TRB_CTRL_CHN            (1 << 2)
+#define XUSBPSU_TRB_CTRL_CSP            (1 << 3)
+#define XUSBPSU_TRB_CTRL_TRBCTL(n)      (((n) & 0x3f) << 4)
+#define XUSBPSU_TRB_CTRL_ISP_IMI        (1 << 10)
+#define XUSBPSU_TRB_CTRL_IOC            (1 << 11)
+#define XUSBPSU_TRB_CTRL_SID_SOFN(n)    (((n) & 0xffff) << 14)
+
+#define XUSBPSU_TRBCTL_NORMAL                   XUSBPSU_TRB_CTRL_TRBCTL(1)
+#define XUSBPSU_TRBCTL_CONTROL_SETUP            XUSBPSU_TRB_CTRL_TRBCTL(2)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS2          XUSBPSU_TRB_CTRL_TRBCTL(3)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS3          XUSBPSU_TRB_CTRL_TRBCTL(4)
+#define XUSBPSU_TRBCTL_CONTROL_DATA             XUSBPSU_TRB_CTRL_TRBCTL(5)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST        XUSBPSU_TRB_CTRL_TRBCTL(6)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS              XUSBPSU_TRB_CTRL_TRBCTL(7)
+#define XUSBPSU_TRBCTL_LINK_TRB                 XUSBPSU_TRB_CTRL_TRBCTL(8)
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the USBPS8 device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Offset is the offset of the register to read.
+*
+* @return	The contents of the register.
+*
+* @note		C-style Signature:
+*		u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset);
+*
+******************************************************************************/
+#define XUsbPsu_ReadReg(InstancePtr, Offset) \
+	Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (Offset))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the USBPS8 device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	RegOffset is the offset of the register to write.
+* @param	Data is the value to write to the register.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr,
+*								u32 Offset,u32 Data)
+*
+******************************************************************************/
+#define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \
+	Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (Offset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_intr.c
new file mode 100644
index 000000000..a1840b6f8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_intr.c
@@ -0,0 +1,403 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_intr.c
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bss  01/22/15 First release
+* 1.00a bss  03/18/15 Added support for Non control endpoint interrupts.
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+* Endpoint interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is endpoint Event occured in the core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep *Ept;
+	u32 EpNum;
+
+	Xil_AssertVoid(Event != NULL);
+
+	EpNum = Event->Epnumber;
+	Ept = &InstancePtr->eps[EpNum];
+
+	if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED))
+		return;
+
+	if (EpNum == 0 || EpNum == 1) {
+		XUsbPsu_Ep0Intr(InstancePtr, Event);
+		return;
+	}
+
+	/* Handle other endpoint events */
+	switch (Event->Endpoint_Event) {
+	case XUSBPSU_DEPEVT_XFERCOMPLETE:
+		XUsbPsu_EpXferComplete(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_DEPEVT_XFERNOTREADY:
+		break;
+
+	default:
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Disconnect Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	InstancePtr->IsConfigDone = 0;
+	InstancePtr->Speed = XUSBPSU_SPEED_UNKNOWN;
+}
+
+/****************************************************************************/
+/**
+* Reset Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr)
+{
+	u32	RegVal;
+	int	Index;
+
+	InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+	InstancePtr->TestMode = 0;
+
+	for (Index = 0; Index < InstancePtr->NumInEps + InstancePtr->NumOutEps;
+			Index++)
+	{
+		InstancePtr->eps[Index].EpStatus = 0;
+	}
+
+	InstancePtr->IsConfigDone = 0;
+
+	/* Reset device address to zero */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+	RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Connection Done Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr)
+{
+	int			Ret;
+	u32			RegVal;
+	u16			Size;
+	u8			Speed;
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+	Speed = RegVal & XUSBPSU_DSTS_CONNECTSPD;
+	InstancePtr->Speed = Speed;
+	Size = 64;
+
+	switch (Speed) {
+	case XUSBPSU_DCFG_SUPERSPEED:
+		Size = 512;
+		InstancePtr->Speed = XUSBPSU_SPEED_SUPER;
+		break;
+	case XUSBPSU_DCFG_HIGHSPEED:
+		Size = 64;
+		InstancePtr->Speed = XUSBPSU_SPEED_HIGH;
+		break;
+	case XUSBPSU_DCFG_FULLSPEED2:
+	case XUSBPSU_DCFG_FULLSPEED1:
+		Size = 64;
+		InstancePtr->Speed = XUSBPSU_SPEED_FULL;
+		break;
+	case XUSBPSU_DCFG_LOWSPEED:
+		Size = 64;
+		InstancePtr->Speed = XUSBPSU_SPEED_LOW;
+		break;
+	}
+
+	XUsbPsu_EnableControlEp(InstancePtr, Size);
+	XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Link Status Change Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EvtInfo is Event information.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr, u32 EvtInfo)
+{
+	u8	State = EvtInfo & XUSBPSU_LINK_STATE_MASK;
+
+	InstancePtr->LinkState = State;
+}
+
+/****************************************************************************/
+/**
+* Interrupt handler for device specific events.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is the Device Event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Devt *Event)
+{
+	Xil_AssertVoid(Event != NULL);
+
+	switch (Event->Type) {
+	case XUSBPSU_DEVICE_EVENT_DISCONNECT:
+		XUsbPsu_DisconnectIntr(InstancePtr);
+		break;
+	case XUSBPSU_DEVICE_EVENT_RESET:
+		XUsbPsu_ResetIntr(InstancePtr);
+		break;
+	case XUSBPSU_DEVICE_EVENT_CONNECT_DONE:
+		XUsbPsu_ConnDoneIntr(InstancePtr);
+		break;
+	case XUSBPSU_DEVICE_EVENT_WAKEUP:
+		break;
+	case XUSBPSU_DEVICE_EVENT_HIBER_REQ:
+		break;
+	case XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE:
+		XUsbPsu_LinkStsChangeIntr(InstancePtr,
+				Event->Event_Info);
+		break;
+	case XUSBPSU_DEVICE_EVENT_EOPF:
+		break;
+	case XUSBPSU_DEVICE_EVENT_SOF:
+		break;
+	case XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR:
+		break;
+	case XUSBPSU_DEVICE_EVENT_CMD_CMPL:
+		break;
+	case XUSBPSU_DEVICE_EVENT_OVERFLOW:
+		break;
+	default:
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Processes an Event entry in Event Buffer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is the Event entry.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_ProcessEvent(struct XUsbPsu *InstancePtr,
+			const union XUsbPsu_Event *Event)
+{
+	Xil_AssertVoid(Event != NULL);
+
+	if (Event->Type.Is_DevEvt == 0) {
+		/* Device Endpoint Event */
+		return XUsbPsu_EpInterrupt(InstancePtr, &Event->Epevt);
+	}
+
+	switch (Event->Type.Type) {
+	case XUSBPSU_EVENT_TYPE_DEV:
+		XUsbPsu_DevInterrupt(InstancePtr, &Event->Devt);
+		break;
+	/* Carkit and I2C events not supported now */
+	default:
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Processes events in an Event Buffer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @bus		Event buffer number.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_ProcessEvtBuffer(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_EvtBuffer *Evt;
+	union XUsbPsu_Event Event;
+	int RemainingEvnts;
+	u32 RegVal;
+
+	Evt = &InstancePtr->Evt;
+	RemainingEvnts = Evt->Count;
+
+	Xil_DCacheInvalidateRange(Evt->BuffAddr, XUSBPSU_EVENT_BUFFERS_SIZE);
+
+	while (RemainingEvnts > 0) {
+		Event.Raw = *(u32 *) (Evt->BuffAddr + Evt->Offset);
+
+		XUsbPsu_ProcessEvent(InstancePtr, &Event);
+
+		Evt->Offset = (Evt->Offset + 4) % XUSBPSU_EVENT_BUFFERS_SIZE;
+		RemainingEvnts -= 4;
+		XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 4);
+	}
+
+	Evt->Count = 0;
+	Evt->Flags &= ~XUSBPSU_EVENT_PENDING;
+
+	/* Unmask interrupt */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+	RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+}
+
+/****************************************************************************/
+/**
+* Main Interrupt Handler.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_IntrHandler(void *XUsbPsu)
+{
+	struct XUsbPsu	*InstancePtr;
+	struct XUsbPsu_EvtBuffer *Evt;
+	u32 Count;
+	u32 RegVal;
+
+	Xil_AssertVoid(XUsbPsu != NULL);
+
+	InstancePtr = XUsbPsu;
+	Evt = &InstancePtr->Evt;
+
+	Count = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0));
+	Count &= XUSBPSU_GEVNTCOUNT_MASK;
+	/*
+	 * As per data book software should only process Events if Event count
+	 * is greater than zero.
+	 */
+	if (!Count)
+		return;
+
+	Evt->Count = Count;
+	Evt->Flags |= XUSBPSU_EVENT_PENDING;
+
+	/* Mask interrupt */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+	RegVal |= XUSBPSU_GEVNTSIZ_INTMASK;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+
+	XUsbPsu_ProcessEvtBuffer(InstancePtr);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_sinit.c
new file mode 100644
index 000000000..84bbc35b0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_0/src/xusbpsu_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_sinit.h
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bss  01/22/15 First release
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+extern XUsbPsu_Config XUsbPsu_ConfigTable[];
+
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId)
+{
+	XUsbPsu_Config *CfgPtr = NULL;
+	int i;
+
+	for (i = 0; i < XPAR_XUSBPSU_NUM_INSTANCES; i++) {
+		if (XUsbPsu_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XUsbPsu_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (CfgPtr);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/Makefile
new file mode 100644
index 000000000..8efa57289
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner wdtps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling wdtps"
+
+wdtps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: wdtps_includes
+
+wdtps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.c
new file mode 100644
index 000000000..1a3eb0834
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.c
@@ -0,0 +1,483 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xwdtps.c
+*
+* Contains the implementation of interface functions of the XWdtPs driver.
+* See xwdtps.h for a description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.02a  sg    07/15/12 Removed code/APIs related to  External Signal
+*			Length functionality for CR 658287
+*			Removed APIs XWdtPs_SetExternalSignalLength,
+*			XWdtPs_GetExternalSignalLength
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xwdtps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific watchdog timer instance/driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	ConfigPtr is the config structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XWdtPs_CfgInitialize(XWdtPs *InstancePtr,
+			XWdtPs_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		Status = XST_DEVICE_IS_STARTED;
+	} else {
+
+		/*
+		 * Copy configuration into instance.
+		 */
+		InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+		/*
+		 * Save the base address pointer such that the registers of the block
+		 * can be accessed and indicate it has not been started yet.
+		 */
+		InstancePtr->Config.BaseAddress = EffectiveAddress;
+		InstancePtr->IsStarted = 0U;
+
+		/*
+		 * Indicate the instance is ready to use, successfully initialized.
+		 */
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the watchdog timer of the device.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_Start(XWdtPs *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the ZMR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	/*
+	 * Enable the Timer field in the register and Set the access key so the
+	 * write takes place.
+	 */
+	Register |= XWDTPS_ZMR_WDEN_MASK;
+	Register |= XWDTPS_ZMR_ZKEY_VAL;
+
+	/*
+	 * Update the ZMR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Disable the watchdog timer.
+*
+* It is the caller's responsibility to disconnect the interrupt handler
+* of the watchdog timer from the interrupt source, typically an interrupt
+* controller, and disable the interrupt in the interrupt controller.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_Stop(XWdtPs *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the ZMR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	/*
+	 * Disable the Timer field in the register and
+	 * Set the access key for the write to be done the register.
+	 */
+	Register &= (u32)(~XWDTPS_ZMR_WDEN_MASK);
+	Register |= XWDTPS_ZMR_ZKEY_VAL;
+
+	/*
+	 * Update the ZMR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  Register);
+
+	InstancePtr->IsStarted = 0U;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Enables the indicated signal/output.
+* Performs a read/modify/write cycle to update the value correctly.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	Signal is the desired signal/output.
+*		Valid Signal Values are XWDTPS_RESET_SIGNAL and
+*		XWDTPS_IRQ_SIGNAL.
+*		Only one of them can be specified at a time.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_EnableOutput(XWdtPs *InstancePtr, u8 Signal)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Signal == XWDTPS_RESET_SIGNAL) ||
+			(Signal == XWDTPS_IRQ_SIGNAL));
+
+	/*
+	 * Read the contents of the ZMR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	if (Signal == XWDTPS_RESET_SIGNAL) {
+		/*
+		 * Enable the field in the register.
+		 */
+		Register |= XWDTPS_ZMR_RSTEN_MASK;
+
+	} else if (Signal == XWDTPS_IRQ_SIGNAL) {
+		/*
+		 * Enable the field in the register.
+		 */
+		Register |= XWDTPS_ZMR_IRQEN_MASK;
+
+	} else {
+		/* Else was made for misra-c compliance */
+		;
+	}
+
+	/*
+	 * Set the access key so the write takes.
+	 */
+	Register |= XWDTPS_ZMR_ZKEY_VAL;
+
+	/*
+	 * Update the ZMR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  Register);
+}
+
+/****************************************************************************/
+/**
+*
+* Disables the indicated signal/output.
+* Performs a read/modify/write cycle to update the value correctly.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	Signal is the desired signal/output.
+*		Valid Signal Values are XWDTPS_RESET_SIGNAL and
+*		XWDTPS_IRQ_SIGNAL
+*		Only one of them can be specified at a time.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_DisableOutput(XWdtPs *InstancePtr, u8 Signal)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Signal == XWDTPS_RESET_SIGNAL) ||
+			(Signal == XWDTPS_IRQ_SIGNAL));
+
+	/*
+	 * Read the contents of the ZMR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	if (Signal == XWDTPS_RESET_SIGNAL) {
+		/*
+		 * Disable the field in the register.
+		 */
+		Register &= (u32)(~XWDTPS_ZMR_RSTEN_MASK);
+
+	} else if (Signal == XWDTPS_IRQ_SIGNAL) {
+		/*
+		 * Disable the field in the register.
+		 */
+		Register &= (u32)(~XWDTPS_ZMR_IRQEN_MASK);
+
+	} else {
+		/* Else was made for misra-c compliance */
+		;
+	}
+
+	/*
+	 * Set the access key so the write takes place.
+	 */
+	Register |= XWDTPS_ZMR_ZKEY_VAL;
+
+	/*
+	 * Update the ZMR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  Register);
+}
+
+/****************************************************************************/
+/**
+*
+* Returns the current control setting for the indicated signal/output.
+* The register referenced is the Counter Control Register (XWDTPS_CCR_OFFSET)
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	Control is the desired signal/output.
+*		Valid Control Values are XWDTPS_CLK_PRESCALE and
+*		XWDTPS_COUNTER_RESET. Only one of them can be specified at a
+*		time.
+*
+* @return	The contents of the requested control field in the Counter
+*		Control Register (XWDTPS_CCR_OFFSET).
+*		If the Control is XWDTPS_CLK_PRESCALE then use the
+*		defintions XWDTEPB_CCR_PSCALE_XXXX.
+*		If the Control is XWDTPS_COUNTER_RESET then the values are
+*		0x0 to 0xFFF. This is the Counter Restart value in the CCR
+*		register.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XWdtPs_GetControlValue(XWdtPs *InstancePtr, u8 Control)
+{
+	u32 Register;
+	u32 ReturnValue = 0U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Control == XWDTPS_CLK_PRESCALE) ||
+			(Control == XWDTPS_COUNTER_RESET));
+
+	/*
+	 * Read the contents of the CCR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XWDTPS_CCR_OFFSET);
+
+	if (Control == XWDTPS_CLK_PRESCALE) {
+		/*
+		 * Mask off the field in the register.
+		 */
+		ReturnValue = Register & XWDTPS_CCR_CLKSEL_MASK;
+
+	} else if (Control == XWDTPS_COUNTER_RESET) {
+		/*
+		 * Mask off the field in the register.
+		 */
+		Register &= XWDTPS_CCR_CRV_MASK;
+
+		/*
+		 * Shift over to the right most positions.
+		 */
+		ReturnValue = Register >> XWDTPS_CCR_CRV_SHIFT;
+	} else {
+		/* Else was made for misra-c compliance */
+		;
+	}
+
+	return ReturnValue;
+}
+
+/****************************************************************************/
+/**
+*
+* Updates the current control setting for the indicated signal/output with
+* the provided value.
+*
+* Performs a read/modify/write cycle to update the value correctly.
+* The register referenced is the Counter Control Register (XWDTPS_CCR_OFFSET)
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	Control is the desired signal/output.
+*		Valid Control Values are XWDTPS_CLK_PRESCALE and
+*		XWDTPS_COUNTER_RESET. Only one of them can be specified at a
+*		time.
+* @param	Value is the desired control value.
+*		If the Control is XWDTPS_CLK_PRESCALE then use the
+*		defintions XWDTEPB_CCR_PSCALE_XXXX.
+*		If the Control is XWDTPS_COUNTER_RESET then the valid values
+*		are 0x0 to 0xFFF, this sets the counter restart value of the CCR
+*		register.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_SetControlValue(XWdtPs *InstancePtr, u8 Control, u32 Value)
+{
+	u32 Register;
+	u32 LocalValue = Value;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Control == XWDTPS_CLK_PRESCALE) ||
+			(Control == XWDTPS_COUNTER_RESET));
+
+	/*
+	 * Read the contents of the CCR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_CCR_OFFSET);
+
+	if (Control == XWDTPS_CLK_PRESCALE) {
+		/*
+		 * Zero the field in the register.
+		 */
+		Register &= (u32)(~XWDTPS_CCR_CLKSEL_MASK);
+
+	} else if (Control == XWDTPS_COUNTER_RESET) {
+		/*
+		 * Zero the field in the register.
+		 */
+		Register &= (u32)(~XWDTPS_CCR_CRV_MASK);
+
+		/*
+		 * Shift Value over to the proper positions.
+		 */
+		LocalValue = LocalValue << XWDTPS_CCR_CRV_SHIFT;
+	} else{
+		/* This was made for misrac compliance. */
+		;
+	}
+
+	Register |= LocalValue;
+
+	/*
+	 * Set the access key so the write takes.
+	 */
+	Register |= XWDTPS_CCR_CKEY_VAL;
+
+	/*
+	 * Update the CCR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_CCR_OFFSET,
+			  Register);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.h
new file mode 100644
index 000000000..498e60bee
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.h
@@ -0,0 +1,219 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xwdtps.h
+*
+* The Xilinx watchdog timer driver supports the Xilinx watchdog timer hardware.
+*
+* The Xilinx watchdog timer (WDT) driver supports the following features:
+*   - Both Interrupt driven and Polled mode
+*   - enabling and disabling the watchdog timer
+*   - restarting the watchdog.
+*   - initializing the most significant digit of the counter restart value.
+*   - multiple individually enabling/disabling outputs
+*
+* It is the responsibility of the application to provide an interrupt handler
+* for the watchdog timer and connect it to the interrupt system if interrupt
+* driven mode is desired.
+*
+* If interrupt is enabled, the watchdog timer device generates an interrupt
+* when the counter reaches zero.
+*
+* If the hardware interrupt signal is not connected/enabled, polled mode is the
+* only option (using IsWdtExpired) for the watchdog.
+*
+* The outputs from the WDT are individually enabled/disabled using
+* _EnableOutput()/_DisableOutput(). The clock divisor ratio and initial restart
+* value of the count is configurable using _SetControlValues().
+*
+* The reset condition of the hardware has the maximum initial count in the
+* Counter Reset Value (CRV) and the WDT is disabled with the reset enable
+* enabled and the reset length set to 32 clocks. i.e.
+* 
+*     register ZMR = 0x1C2
+*     register CCR = 0x3FC
+* 

+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.01a asa    02/15/12 Added tcl file to generate xparameters
+* 1.02a  sg    07/15/12 Removed code/APIs related to  External Signal
+*						Length functionality for CR 658287
+*						Removed APIs XWdtPs_SetExternalSignalLength,
+*						XWdtPs_GetExternalSignalLength
+*						Modified the Self Test to use the Reset Length mask
+*						for CR 658287
+* 3.0	pkp	   12/09/14 Added support for Zynq Ultrascale Mp.Also
+*			modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+#ifndef XWDTPS_H		/* prevent circular inclusions */
+#define XWDTPS_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xwdtps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * Choices for output selections for the device, used in
+ * XWdtPs_EnableOutput()/XWdtPs_DisableOutput() functions
+ */
+#define XWDTPS_RESET_SIGNAL	0x01U   /**< Reset signal request */
+#define XWDTPS_IRQ_SIGNAL	0x02U   /**< IRQ signal request */
+
+/*
+ * Control value setting flags, used in
+ * XWdtPs_SetControlValues()/XWdtPs_GetControlValues() functions
+ */
+#define XWDTPS_CLK_PRESCALE		0x01U   /**< Clock Prescale request */
+#define XWDTPS_COUNTER_RESET	0x02U   /**< Counter Reset request */
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddress;	/**< Base address of the device */
+} XWdtPs_Config;
+
+
+/**
+ * The XWdtPs driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XWdtPs_Config Config;   /**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device watchdog timer is running */
+} XWdtPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* Check if the watchdog timer has expired. This function is used for polled
+* mode and it is also used to check if the last reset was caused by the
+* watchdog timer.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XWdtPs_IsWdtExpired(XWdtPs *InstancePtr)
+*
+******************************************************************************/
+#define XWdtPs_IsWdtExpired(InstancePtr)				  \
+((XWdtPs_ReadReg((InstancePtr)->Config.BaseAddress, XWDTPS_SR_OFFSET) & \
+   XWDTPS_SR_WDZ_MASK) == XWDTPS_SR_WDZ_MASK)
+
+
+/****************************************************************************/
+/**
+*
+* Restart the watchdog timer. An application needs to call this function
+* periodically to keep the timer from asserting the enabled output.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XWdtPs_RestartWdt(XWdtPs *InstancePtr)
+*
+******************************************************************************/
+#define XWdtPs_RestartWdt(InstancePtr)					\
+	XWdtPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		XWDTPS_RESTART_OFFSET, XWDTPS_RESTART_KEY_VAL)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xwdtps_sinit.c.
+ */
+XWdtPs_Config *XWdtPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interface functions in xwdtps.c
+ */
+s32 XWdtPs_CfgInitialize(XWdtPs *InstancePtr,
+			XWdtPs_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XWdtPs_Start(XWdtPs *InstancePtr);
+
+void XWdtPs_Stop(XWdtPs *InstancePtr);
+
+void XWdtPs_EnableOutput(XWdtPs *InstancePtr, u8 Signal);
+
+void XWdtPs_DisableOutput(XWdtPs *InstancePtr, u8 Signal);
+
+u32 XWdtPs_GetControlValue(XWdtPs *InstancePtr, u8 Control);
+
+void XWdtPs_SetControlValue(XWdtPs *InstancePtr, u8 Control, u32 Value);
+
+/*
+ * Self-test function in xwdttb_selftest.c.
+ */
+s32 XWdtPs_SelfTest(XWdtPs *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
new file mode 100644
index 000000000..59625ec5f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
@@ -0,0 +1,59 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xwdtps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XWdtPs_Config XWdtPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_WDT_0_DEVICE_ID,
+		XPAR_PSU_WDT_0_BASEADDR
+	},
+	{
+		XPAR_PSU_WDT_1_DEVICE_ID,
+		XPAR_PSU_WDT_1_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_hw.h
new file mode 100644
index 000000000..2cd3b272b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_hw.h
@@ -0,0 +1,190 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xwdtps_hw.h
+*
+* This file contains the hardware interface to the System Watch Dog Timer (WDT).
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.02a  sg    07/15/12 Removed defines related to  External Signal
+*			Length functionality for CR 658287
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+#ifndef XWDTPS_HW_H		/* prevent circular inclusions */
+#define XWDTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XWDTPS_ZMR_OFFSET	0x00000000U /**< Zero Mode Register */
+#define XWDTPS_CCR_OFFSET	0x00000004U /**< Counter Control Register */
+#define XWDTPS_RESTART_OFFSET	0x00000008U /**< Restart Register */
+#define XWDTPS_SR_OFFSET	0x0000000CU /**< Status Register */
+/* @} */
+
+
+/** @name Zero Mode Register
+ * This register controls how the time out is indicated and also contains
+ * the access code (0xABC) to allow writes to the register
+ * @{
+ */
+#define XWDTPS_ZMR_WDEN_MASK	0x00000001U /**< enable the WDT */
+#define XWDTPS_ZMR_RSTEN_MASK	0x00000002U /**< enable the reset output */
+#define XWDTPS_ZMR_IRQEN_MASK	0x00000004U /**< enable the IRQ output */
+
+#define XWDTPS_ZMR_RSTLN_MASK	0x00000070U /**< set length of reset pulse */
+#define XWDTPS_ZMR_RSTLN_SHIFT	4U	   /**< shift for reset pulse */
+
+#define XWDTPS_ZMR_IRQLN_MASK	0x00000180U /**< set length of interrupt pulse */
+#define XWDTPS_ZMR_IRQLN_SHIFT	7U	   /**< shift for interrupt pulse */
+
+#define XWDTPS_ZMR_ZKEY_MASK	0x00FFF000U /**< mask for writing access key */
+#define XWDTPS_ZMR_ZKEY_VAL		0x00ABC000U /**< access key, 0xABC << 12 */
+
+/* @} */
+
+/** @name  Counter Control register
+ * This register controls how fast the timer runs and the reset value
+ * and also contains the access code (0x248) to allow writes to the
+ * register
+ * @{
+ */
+
+#define XWDTPS_CCR_CLKSEL_MASK	0x00000003U /**< counter clock prescale */
+
+#define XWDTPS_CCR_CRV_MASK	0x00003FFCU /**< counter reset value */
+#define XWDTPS_CCR_CRV_SHIFT	2U	   /**< shift for writing value */
+
+#define XWDTPS_CCR_CKEY_MASK	0x03FFC000U /**< mask for writing access key */
+#define XWDTPS_CCR_CKEY_VAL	0x00920000U /**< access key, 0x248 << 14 */
+
+/* Bit patterns for Clock prescale divider values */
+
+#define XWDTPS_CCR_PSCALE_0008  0x00000000U /**< divide clock by 8 */
+#define XWDTPS_CCR_PSCALE_0064  0x00000001U /**< divide clock by 64 */
+#define XWDTPS_CCR_PSCALE_0512  0x00000002U /**< divide clock by 512 */
+#define XWDTPS_CCR_PSCALE_4096  0x00000003U /**< divide clock by 4096 */
+
+/* @} */
+
+/** @name  Restart register
+ * This register resets the timer preventing a timeout. Value is specific
+ * 0x1999
+ * @{
+ */
+
+#define XWDTPS_RESTART_KEY_VAL	0x00001999U /**< valid key */
+
+/*@}*/
+
+/** @name Status register
+ * This register indicates timer reached zero count.
+ * @{
+ */
+#define XWDTPS_SR_WDZ_MASK	0x00000001U /**< time out occurred */
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XWdtPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XWdtPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XWdtPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XWdtPs_WriteReg(BaseAddress, RegOffset, Data) \
+	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_selftest.c
new file mode 100644
index 000000000..e6bf838f8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_selftest.c
@@ -0,0 +1,170 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xwdtps_selftest.c
+*
+* Contains diagnostic self-test functions for the XWdtPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.02a sg     08/01/12 Modified it use the Reset Length mask for the self
+*		        test for CR 658287
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xwdtps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timebase. This test verifies that the register access
+* locking functions. This is tested by trying to alter a register without
+* setting the key value and verifying that the register contents did not
+* change.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if self-test was not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XWdtPs_SelfTest(XWdtPs *InstancePtr)
+{
+	u32 ZmrOrig;
+	u32 ZmrValue1;
+	u32 ZmrValue2;
+	s32 Status;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the ZMR register at start the test.
+	 */
+	ZmrOrig = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	/*
+	 * EX-OR in the length of the interrupt pulse,
+	 * do not set the key value.
+	 */
+	ZmrValue1 = ZmrOrig ^ (u32)XWDTPS_ZMR_RSTLN_MASK;
+
+
+	/*
+	 * Try to write to register w/o key value then read back.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  ZmrValue1);
+
+	ZmrValue2 =	XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	if (ZmrValue1 == ZmrValue2) {
+		/*
+		 * If the values match, the hw failed the test,
+		 * return orig register value.
+		 */
+		XWdtPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XWDTPS_ZMR_OFFSET,
+				  (ZmrOrig | (u32)XWDTPS_ZMR_ZKEY_VAL));
+		Status = XST_FAILURE;
+	} else {
+
+
+		/*
+		 * Try to write to register with key value then read back.
+		 */
+		XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+				  (ZmrValue1 | XWDTPS_ZMR_ZKEY_VAL));
+
+		ZmrValue2 =	XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XWDTPS_ZMR_OFFSET);
+
+		if (ZmrValue1 != ZmrValue2) {
+			/*
+			 * If the values do not match, the hw failed the test,
+			 * return orig register value.
+			 */
+			XWdtPs_WriteReg(InstancePtr->Config.BaseAddress,
+					  XWDTPS_ZMR_OFFSET,
+					  ZmrOrig | XWDTPS_ZMR_ZKEY_VAL);
+			Status = XST_FAILURE;
+
+		} else {
+
+			/*
+			 * The hardware locking feature is functional, return the original value
+			 * and return success.
+			 */
+			XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+					  ZmrOrig | XWDTPS_ZMR_ZKEY_VAL);
+
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_sinit.c
new file mode 100644
index 000000000..6794aa2f3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_sinit.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xwdtps_sinit.c
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xwdtps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*************************** Variable Definitions ****************************/
+extern XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XWdtPs_Config *XWdtPs_LookupConfig(u16 DeviceId)
+{
+	XWdtPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XWDTPS_NUM_INSTANCES; Index++) {
+		if (XWdtPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XWdtPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XWdtPs_Config *)CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/Makefile
new file mode 100644
index 000000000..9cd372526
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner zdma_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling zdma"
+
+zdma_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: zdma_includes
+
+zdma_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma.c
new file mode 100644
index 000000000..3e80d2a72
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma.c
@@ -0,0 +1,1267 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma.c
+*
+* This file contains the implementation of the interface functions for ZDMA
+* driver. Refer to the header file xzdma.h for more detailed information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+
+/************************** Function Prototypes ******************************/
+
+static void StubCallBack(void *CallBackRef, u32 Mask);
+static void StubDoneCallBack(void *CallBackRef);
+static void XZDma_SimpleMode(XZDma *InstancePtr, XZDma_Transfer *Data);
+static void XZDma_ScatterGather(XZDma *InstancePtr, XZDma_Transfer *Data,
+								u32 Num);
+static void XZDma_LinearMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+	XZDma_LiDscr *SrcDscrPtr,XZDma_LiDscr *DstDscrPtr, u8 IsLast);
+static void XZDma_ConfigLinear(XZDma_LiDscr *DscrPtr, u64 Addr, u32 Size,
+								u32 CtrlValue);
+static void XZDma_LinkedListMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+	XZDma_LlDscr *SrcDscrPtr,XZDma_LlDscr *DstDscrPtr, u8 IsLast);
+static void XZDma_ConfigLinkedList(XZDma_LlDscr *DscrPtr, u64 Addr, u32 Size,
+					u32 CtrlValue, u64 NextDscrAddr);
+static void XZDma_Enable(XZDma *InstancePtr);
+static void XZDma_GetConfigurations(XZDma *InstancePtr);
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes an ZDMA core. This function must be called
+* prior to using an ZDMA core. Initialization of an ZDMA includes setting
+* up the instance data and ensuring the hardware is in a quiescent state and
+* resets all the hardware configurations.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	CfgPtr is a reference to a structure containing information
+*		about a specific XZDma instance.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the
+*		address mapping from EffectiveAddr to the device physical
+*		base address unchanged once this function is invoked.
+*		Unexpected errors may occur if the address mapping changes
+*		after this function is called. If address translation is not
+*		used, pass in the physical address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr,
+			u32 EffectiveAddr)
+{
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddr != ((u32)0x00));
+
+	InstancePtr->Config.BaseAddress = CfgPtr->BaseAddress;
+	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+	InstancePtr->Config.DmaType = CfgPtr->DmaType;
+
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+	InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
+
+	InstancePtr->IsSgDma = FALSE;
+	InstancePtr->Mode = XZDMA_NORMAL_MODE;
+	InstancePtr->IntrMask = 0x00U;
+	InstancePtr->ChannelState = XZDMA_IDLE;
+
+	/*
+	 * Set all handlers to stub values, let user configure this
+	 * data later
+	 */
+	InstancePtr->DoneHandler =
+				(XZDma_DoneHandler)((void *)StubDoneCallBack);
+	InstancePtr->ErrorHandler =
+				(XZDma_ErrorHandler)((void *)StubCallBack);
+
+	XZDma_Reset(InstancePtr);
+	XZDma_GetConfigurations(InstancePtr);
+
+	return (XST_SUCCESS);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the pointer type and mode in which ZDMA needs to transfer
+* the data.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	IsSgDma is a variable which specifies whether transfer has to
+*		to be done in scatter gather mode or simple mode.
+*		- TRUE  - Scatter gather pointer type
+*		- FALSE - Simple pointer type
+* @param	Mode is the type of the mode in which data has to be initiated
+*		- XZDMA_NORMAL_MODE   - Normal data transfer from source to
+*					destination (Valid for both Scatter
+*					gather and simple types)
+*		- XZDMA_WRONLY_MODE  - Write only mode (Valid only for Simple)
+*		- XZDMA_RDONLY_MODE  - Read only mode (Valid only for Simple)
+*
+* @return
+*		- XST_SUCCESS - If mode has been set successfully.
+*		- XST_FAILURE - If mode has not been set.
+*
+* @note		Mode cannot be changed while ZDMA is not in IDLE state.
+*
+******************************************************************************/
+s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode)
+{
+	u32 Data;
+	s32 Status;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((IsSgDma == TRUE) || (IsSgDma == FALSE));
+	Xil_AssertNonvoid(Mode <= XZDMA_RDONLY_MODE);
+
+	if (InstancePtr->ChannelState != XZDMA_IDLE) {
+		Status = XST_FAILURE;
+	}
+	else {
+		Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL0_OFFSET);
+		/* Simple mode */
+		if (IsSgDma != TRUE) {
+			Data = (Data & (~XZDMA_CTRL0_POINT_TYPE_MASK));
+			if (Mode == XZDMA_NORMAL_MODE) {
+				Data &= (~XZDMA_CTRL0_MODE_MASK);
+			}
+			else if (Mode == XZDMA_WRONLY_MODE) {
+				Data |= XZDMA_CTRL0_WRONLY_MASK;
+			}
+			else {
+				Data |= XZDMA_CTRL0_RDONLY_MASK;
+			}
+			XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL0_OFFSET, Data);
+			InstancePtr->IsSgDma = FALSE;
+			InstancePtr->Mode = Mode;
+		}
+
+		else {
+			if (Mode != XZDMA_NORMAL_MODE) {
+				Status = XST_FAILURE;
+			}
+			else {
+				Data |= (XZDMA_CTRL0_POINT_TYPE_MASK);
+				Data &= ~(XZDMA_CTRL0_MODE_MASK);
+				XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL0_OFFSET, Data);
+
+				InstancePtr->IsSgDma = TRUE;
+				InstancePtr->Mode = Mode;
+			}
+		}
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the descriptor type and descriptor pointer's start address
+* of both source and destination based on the memory allocated by user and also
+* calculates no of descriptors(BDs) can be created in the allocated memory.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	TypeOfDscr is a variable which specifies descriptor type
+*		whether Linear or linked list type of descriptor.
+*		- XZDMA_LINEAR    - Linear type of descriptor.
+*		- XZDMA_LINKEDLIST- Linked list type of descriptor.
+* @param	Dscr_MemPtr is a pointer to the allocated memory for creating
+*		descriptors. It Should be aligned to 64 bytes.
+*
+* @param	NoOfBytes specifies the number of bytes allocated for
+*		descriptors
+*
+* @return	The Count of the descriptors can be created.
+*
+* @note		User should allocate the memory for descriptors which should
+*		be capable of how many transfers he wish to do in one start.
+*		For Linear mode each descriptor needs 128 bit memory so for
+*		one data transfer it requires 2*128 = 256 bits i.e. 32 bytes
+*		Similarly for Linked list mode for each descriptor it needs
+*		256 bit, so for one data transfer it require 2*256 = 512 bits
+*		i.e. 64 bytes.
+*
+******************************************************************************/
+u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr,
+					UINTPTR Dscr_MemPtr, u32 NoOfBytes)
+{
+	XZDma_LiDscr *LocalLinearPtr = (XZDma_LiDscr *)(void *)Dscr_MemPtr;
+	XZDma_LlDscr *LocalLinklistPtr = (XZDma_LlDscr *)(void *)Dscr_MemPtr;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((TypeOfDscr == XZDMA_LINEAR) ||
+					(TypeOfDscr == XZDMA_LINKEDLIST));
+	Xil_AssertNonvoid(Dscr_MemPtr != 0x00);
+	Xil_AssertNonvoid(NoOfBytes != 0x00U);
+
+	InstancePtr->Descriptor.DscrType = TypeOfDscr;
+
+	if (TypeOfDscr == XZDMA_LINEAR) {
+		InstancePtr->Descriptor.SrcDscrPtr = (void *)Dscr_MemPtr;
+		LocalLinearPtr = ((LocalLinearPtr + (NoOfBytes >> 1)) + 1U);
+		InstancePtr->Descriptor.DstDscrPtr = (void *)LocalLinearPtr;
+		InstancePtr->Descriptor.DscrCount =
+				(NoOfBytes >> 1) / sizeof(XZDma_LiDscr);
+	}
+	else {
+		InstancePtr->Descriptor.SrcDscrPtr = (void *)Dscr_MemPtr;
+		LocalLinklistPtr =
+				((LocalLinklistPtr + (NoOfBytes >> 1)) + 1U);
+		InstancePtr->Descriptor.DstDscrPtr = (void *)LocalLinklistPtr;
+		InstancePtr->Descriptor.DscrCount =
+				(NoOfBytes >> 1) / sizeof(XZDma_LlDscr);
+	}
+
+	Xil_DCacheInvalidateRange((INTPTR)Dscr_MemPtr, NoOfBytes);
+
+	return (InstancePtr->Descriptor.DscrCount);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the data attributes and control configurations of a
+* ZDMA core based on the inputs provided.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Configure is a pointer to the XZDma_ChDataConfig structure
+*		which has all the configuration fields.
+*		The fields of the structure are:
+*		- OverFetch - Allows over fetch or not
+*			- 0 - Not allowed to over-fetch on SRC
+*			- 1 - Allowed to over-fetch on SRC
+*		- SrcIssue  - Outstanding transaction on SRC
+*			- Range is 1 to 32
+*		- SrcBurstType - Burst Type for SRC AXI transaction
+*			- XZDMA_FIXED_BURST - Fixed burst
+*			- XZDMA_INCR_BURST  - Incremental burst
+*		- SrcBurstLen - AXI Length for Data Read.
+*			- Range of values is (1,2,4,8,16).
+*		- DstBurstType - Burst Type for SRC AXI transaction
+*			- XZDMA_FIXED_BURST - Fixed burst
+*			- XZDMA_INCR_BURST - Incremental burst
+*		- DstBurstLen     - AXI Length for Data write.
+*			- Range of values is (1,2,4,8,16).
+*		- SrcCache - AXI cache bits for Data read
+*		- SrcQos - Configurable QoS bits for AXI Data read
+*		- DstCache - AXI cache bits for Data write
+*		- DstQos - configurable QoS bits for AXI Data write
+*
+* @return
+* 		- XST_FAILURE  If ZDMA Core is not in Idle state and
+* 		- XST_SUCCESS If Configurations are made successfully
+*
+* @note
+* 		- These configurations will last till we modify or Reset
+*		  by XZDma_Reset(XZDma *InstancePtr).
+* 		- Configurations should be modified only when ZDMA channel
+* 		  is IDLE this can be confirmed by using
+*		  XZDma_ChannelState(XZDma *InstancePtr) API.
+*
+******************************************************************************/
+s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure)
+{
+	u32 Data;
+	s32 Status;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Configure != NULL);
+
+	if (InstancePtr->ChannelState != XZDMA_IDLE) {
+		Status = XST_FAILURE;
+	}
+	else {
+		InstancePtr->DataConfig.DstBurstType = Configure->DstBurstType;
+		InstancePtr->DataConfig.DstBurstLen = Configure->DstBurstLen;
+		InstancePtr->DataConfig.SrcBurstType = Configure->SrcBurstType;
+		InstancePtr->DataConfig.SrcBurstLen = Configure->SrcBurstLen;
+		InstancePtr->DataConfig.OverFetch = Configure->OverFetch;
+		InstancePtr->DataConfig.SrcIssue = Configure->SrcIssue;
+		InstancePtr->DataConfig.SrcCache = Configure->SrcCache;
+		InstancePtr->DataConfig.SrcQos = Configure->SrcQos;
+		InstancePtr->DataConfig.DstCache = Configure->DstCache;
+		InstancePtr->DataConfig.DstQos = Configure->DstQos;
+
+		/* Setting over fetch */
+		Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL0_OFFSET);
+
+		Data |= (((u32)(Configure->OverFetch) <<
+				XZDMA_CTRL0_OVR_FETCH_SHIFT) &
+					XZDMA_CTRL0_OVR_FETCH_MASK);
+
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+					XZDMA_CH_CTRL0_OFFSET, Data);
+
+		/* Setting source issue */
+		Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL1_OFFSET);
+		Data = (u32)(Configure->SrcIssue & XZDMA_CTRL1_SRC_ISSUE_MASK);
+
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL1_OFFSET, Data);
+
+		/* Setting Burst length and burst type */
+		Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_DATA_ATTR_OFFSET);
+		Data = (Data & (~(XZDMA_DATA_ATTR_ARBURST_MASK |
+				 XZDMA_DATA_ATTR_ARLEN_MASK |
+				 XZDMA_DATA_ATTR_AWBURST_MASK |
+				 XZDMA_DATA_ATTR_AWLEN_MASK |
+				 XZDMA_DATA_ATTR_ARCACHE_MASK |
+				 XZDMA_DATA_ATTR_AWCACHE_MASK |
+				 XZDMA_DATA_ATTR_AWQOS_MASK |
+				 XZDMA_DATA_ATTR_ARQOS_MASK)));
+
+		Data |= ((((u32)(Configure->SrcBurstType) <<
+				XZDMA_DATA_ATTR_ARBURST_SHIFT) &
+				XZDMA_DATA_ATTR_ARBURST_MASK) |
+				(((u32)(Configure->SrcCache) <<
+				XZDMA_DATA_ATTR_ARCACHE_SHIFT) &
+				XZDMA_DATA_ATTR_ARCACHE_MASK) |
+				(((u32)(Configure->SrcQos) <<
+				XZDMA_DATA_ATTR_ARQOS_SHIFT) &
+				XZDMA_DATA_ATTR_ARQOS_MASK) |
+			(((u32)(Configure->SrcBurstLen) <<
+				XZDMA_DATA_ATTR_ARLEN_SHIFT) &
+				XZDMA_DATA_ATTR_ARLEN_MASK) |
+			(((u32)(Configure->DstBurstType) <<
+				XZDMA_DATA_ATTR_AWBURST_SHIFT) &
+				XZDMA_DATA_ATTR_AWBURST_MASK) |
+			(((u32)(Configure->DstCache) <<
+				XZDMA_DATA_ATTR_AWCACHE_SHIFT) &
+				XZDMA_DATA_ATTR_AWCACHE_MASK) |
+			(((u32)(Configure->DstQos) <<
+				XZDMA_DATA_ATTR_AWQOS_SHIFT) &
+				XZDMA_DATA_ATTR_AWQOS_MASK) |
+			(((u32)(Configure->DstBurstLen)) &
+				XZDMA_DATA_ATTR_AWLEN_MASK));
+
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+					XZDMA_CH_DATA_ATTR_OFFSET, Data);
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the data attributes and control configurations of a
+* ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Configure is a pointer to the XZDma_ChDataConfig structure
+*		which has all the configuration fields.
+*		The fields of the structure are:
+*		- OverFetch - Allows over fetch or not
+*			- 0 - Not allowed to over-fetch on SRC
+*			- 1 - Allowed to over-fetch on SRC
+*		- SrcIssue  - Outstanding transaction on SRC
+*			- Range is 1 to 32
+*		- SrcBurstType - Burst Type for SRC AXI transaction
+*			- XZDMA_FIXED_BURST - Fixed burst
+*			- XZDMA_INCR_BURST  - Incremental burst
+*		- SrcBurstLen - AXI Length for Data Read.
+*			- Can be max of 16 to be compatible with AXI3
+*		- DstBurstType - Burst Type for SRC AXI transaction
+*			- XZDMA_FIXED_BURST - Fixed burst
+*			- XZDMA_INCR_BURST - Incremental burst
+*		- DstBurstLen     - AXI Length for Data write.
+*			- Can be max of 16 to be compatible with AXI3
+*		- SrcCache - AXI cache bits for Data read
+*		- SrcQos - Configurable QoS bits for AXI Data read
+*		- DstCache - AXI cache bits for Data write
+*		- DstQos - Configurable QoS bits for AXI Data write
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure)
+{
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Configure != NULL);
+
+	Configure->SrcBurstType = InstancePtr->DataConfig.SrcBurstType;
+	Configure->SrcCache = InstancePtr->DataConfig.SrcCache;
+	Configure->SrcQos = InstancePtr->DataConfig.SrcQos;
+	Configure->SrcBurstLen = InstancePtr->DataConfig.SrcBurstLen;
+
+	Configure->DstBurstType = InstancePtr->DataConfig.DstBurstType;
+	Configure->DstCache = InstancePtr->DataConfig.DstCache;
+	Configure->DstQos = InstancePtr->DataConfig.DstQos;
+	Configure->DstBurstLen = InstancePtr->DataConfig.DstBurstLen;
+
+	Configure->OverFetch = InstancePtr->DataConfig.OverFetch;
+	Configure->SrcIssue = InstancePtr->DataConfig.SrcIssue;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the descriptor attributes based on the inputs provided
+* in the structure.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Configure is a pointer to the XZDma_ChDscrConfig structure
+*		which has all the configuration fields.
+*		The fields of the structure are:
+*		- AxCoherent - AXI transactions generated for the descriptor.
+*			- 0 - Non coherent
+*			- 1 - Coherent
+*		- AXCache    - AXI cache bit used for DSCR fetch
+*				(both on SRC and DST Side)
+*		- AXQos      - QoS bit used for DSCR fetch
+*				(both on SRC and DST Side)
+*
+* @return
+*		- XST_FAILURE  If ZDMA core is not in Idle state and
+* 		- XST_SUCCESS If Configurations are made successfully
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure)
+{
+	u32 Data;
+	s32 Status;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Configure != NULL);
+
+	if (InstancePtr->ChannelState != XZDMA_IDLE) {
+		Status = XST_FAILURE;
+	}
+
+	else {
+		InstancePtr->DscrConfig.AXCache = Configure->AXCache;
+		InstancePtr->DscrConfig.AXQos = Configure->AXQos;
+		InstancePtr->DscrConfig.AxCoherent = Configure->AxCoherent;
+
+		Data = ((((u32)(Configure->AxCoherent) <<
+				XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT) &
+				XZDMA_DSCR_ATTR_AXCOHRNT_MASK) |
+			(((u32)(Configure->AXCache) <<
+				XZDMA_DSCR_ATTR_AXCACHE_SHIFT) &
+				XZDMA_DSCR_ATTR_AXCACHE_MASK) |
+			(((u32)Configure->AXQos) &
+				XZDMA_DSCR_ATTR_AXQOS_MASK));
+
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_DSCR_ATTR_OFFSET, Data);
+
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the descriptor attributes of the channel.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Configure is a pointer to the XZDma_ChDscrConfig structure
+*		which has all the configuration fields.
+*		The fields of the structure are:
+*		- AxCoherent - AXI transactions generated for the descriptor.
+*			- 0 - Non coherent
+*			- 1 - Coherent
+*		- AXCache    - AXI cache bit used for DSCR fetch
+*				(both on SRC and DST Side)
+*		- AXQos      - QoS bit used for DSCR fetch
+*				(both on SRC and DST Side)
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure)
+{
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Configure != NULL);
+
+	Configure->AXCache = InstancePtr->DscrConfig.AXCache;
+	Configure->AXQos = InstancePtr->DscrConfig.AXQos;
+	Configure->AxCoherent = InstancePtr->DscrConfig.AxCoherent;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function preloads the buffers which will be used in write only mode.
+* In write only mode the data in the provided buffer will be written in
+* destination address for specified size.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Buffer is a pointer to an array of 64/128 bit data.
+*		i.e. pointer to 32 bit array of size 2/4
+*		 - Array of Size 2 for ADMA
+*		 - Array of Size 4 for GDMA
+*
+* @return	None.
+*
+* @note		Valid only in simple mode.
+* 		Prior to call this function ZDMA instance should be set in
+* 		Write only mode by using
+*		XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma,
+*							XZDma_Mode Mode)
+*		To initiate data transfer after this API need to call
+*		XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num)
+*		In which only destination fields has to be filled.
+*
+******************************************************************************/
+void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer)
+{
+	u32 *LocBuf = Buffer;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Buffer != NULL);
+
+	if (InstancePtr->Config.DmaType == (u8)0) {
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD0_OFFSET, *LocBuf);
+		LocBuf++;
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD1_OFFSET, *LocBuf);
+		LocBuf++;
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD2_OFFSET, *LocBuf);
+		LocBuf++;
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD3_OFFSET, *LocBuf);
+	}
+
+	else {
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD0_OFFSET, *LocBuf);
+		LocBuf++;
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD1_OFFSET, *LocBuf);
+	}
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resume the paused state of ZDMA core and starts the transfer
+* from where it has paused.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		Valid only for scatter gather mode.
+*
+******************************************************************************/
+void XZDma_Resume(XZDma *InstancePtr)
+{
+	u32 Value;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsSgDma == TRUE);
+	Xil_AssertVoid(InstancePtr->ChannelState == XZDMA_PAUSE);
+
+	Value = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_CTRL0_OFFSET) & (~XZDMA_CTRL0_CONT_ADDR_MASK);
+	Value |= XZDMA_CTRL0_CONT_MASK;
+	InstancePtr->ChannelState = XZDMA_BUSY;
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_CTRL0_OFFSET, Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This function resets all the configurations made previously.
+*		Disables all the interrupts and clears interrupt status.
+*
+*****************************************************************************/
+void XZDma_Reset(XZDma *InstancePtr)
+{
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->ChannelState == XZDMA_IDLE);
+
+	/* Disable's the channel */
+	XZDma_DisableCh(InstancePtr);
+
+	/* Disables all interrupts */
+	XZDma_DisableIntr(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
+	XZDma_IntrClear(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
+	InstancePtr->IntrMask = 0x00U;
+
+	/* All configurations are being reset */
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
+					XZDMA_CTRL0_RESET_VALUE);
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL1_OFFSET,
+					XZDMA_CTRL1_RESET_VALUE);
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_DATA_ATTR_OFFSET, XZDMA_DATA_ATTR_RESET_VALUE);
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_DSCR_ATTR_OFFSET, XZDMA_DSCR_ATTR_RESET_VALUE);
+
+	/* Clears total byte */
+	XZDma_TotalByteClear(InstancePtr);
+
+	/* Clears interrupt count of both source and destination channels */
+	(void)XZDma_GetSrcIntrCnt(InstancePtr);
+	(void)XZDma_GetDstIntrCnt(InstancePtr);
+
+	InstancePtr->ChannelState = XZDMA_IDLE;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the state of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	This function returns state of ZDMA core
+*		- XZDMA_IDLE - If ZDMA core is in idle state.
+*		- XZDMA_PAUSE - If ZDMA is in paused state.
+*		- XZDMA_BUSY - If ZDMA is in busy state.
+* @note		None.
+*		C-style signature:
+*		XZDmaState XZDma_ChannelState(XZDma *InstancePtr)
+*
+******************************************************************************/
+XZDmaState XZDma_ChannelState(XZDma *InstancePtr)
+{
+	XZDmaState Status;
+	u32 Value;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	Value = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+			(XZDMA_CH_STS_OFFSET)) & (XZDMA_STS_ALL_MASK);
+
+	if ((Value == XZDMA_STS_DONE_MASK) ||
+			(Value == XZDMA_STS_DONE_ERR_MASK)) {
+		Status = XZDMA_IDLE;
+	}
+	else if (Value == XZDMA_STS_PAUSE_MASK) {
+		Status = XZDMA_PAUSE;
+	}
+	else {
+		Status = XZDMA_BUSY;
+	}
+
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets all the required fields for initiating data transfer. Data
+* transfer elements needs to be passed through structure pointer.
+* Data transfer can be done in any of the three modes (simple, Linear or Linked
+* List) based on the selected mode but before calling this API make sure that
+* ZDMA is in Idle state.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure which
+*		has all the configuration fields for initiating data transfer.
+*		The fields of the structure are:
+*		- SrcAddr      - Source address
+*		- DstAddr     - Destination address
+*		- Size      - size of the data to be transferred in bytes
+*		- SrcCoherent  - AXI transactions generated to process the
+*				descriptor payload for source channel
+*			- 0 - Non coherent
+*			- 1 - Coherent
+*		- DstCoherent - AXI transactions generated to process the
+*				descriptor payload for destination channel
+*			- 0 - Non coherent
+*			- 1 - Coherent
+*		- Pause 	-  Valid only for scatter gather mode.
+*				Will pause after completion of this descriptor.
+* @param	Num specifies number of array elements of Data pointer.
+*		- For simple mode Num should be equal to 1
+*		- For Scatter gather mode (either linear or linked list) Num
+*		  can be any choice. (But based on which memory should be
+*		  allocated by Application) It should be less than the return
+*		  value of XZDma_CreateBDList.
+*
+* @return
+*		- XST_SUCCESS - if ZDMA initiated the transfer.
+*		- XST_FAILURE - if ZDMA has not initiated data transfer.
+*
+* @note		After Pause to resume the transfer need to use the following
+*		API
+*		- XZDma_Resume
+*		User should provide allocated memory and descriptor type in
+*		scatter gather mode through the following API before calling
+*		the start API.
+*		- XZDma_SetDescriptorType(XZDma *InstancePtr,
+*			XZDma_DscrType TypeOfDscr, UINTPTR Dscr_MemPtr,
+*							u32 NoOfBytes)
+*
+******************************************************************************/
+s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num)
+{
+	s32 Status;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Data != NULL);
+	Xil_AssertNonvoid(Num != 0x00U);
+
+	if ((InstancePtr->ChannelState == XZDMA_BUSY) &&
+			(Num >= InstancePtr->Descriptor.DscrCount)) {
+		Status = XST_FAILURE;
+	}
+	else {
+		if (InstancePtr->IsSgDma != TRUE) {
+			XZDma_SimpleMode(InstancePtr, Data);
+			Status = XST_SUCCESS;
+		}
+		else {
+
+			XZDma_ScatterGather(InstancePtr, Data, Num);
+			Status = XST_SUCCESS;
+		}
+
+		XZDma_Enable(InstancePtr);
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in simple mode.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure
+*		which has all the configuration fields for initiating data
+*		transfer.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_SimpleMode(XZDma *InstancePtr, XZDma_Transfer *Data)
+{
+
+	u32 Value;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Data != NULL);
+
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_SRC_DSCR_WORD0_OFFSET,
+			(Data->SrcAddr & XZDMA_WORD0_LSB_MASK));
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_SRC_DSCR_WORD1_OFFSET,
+		(((u64)Data->SrcAddr >> XZDMA_WORD1_MSB_SHIFT) &
+		XZDMA_WORD1_MSB_MASK));
+
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_DST_DSCR_WORD0_OFFSET,
+		(Data->DstAddr & XZDMA_WORD0_LSB_MASK));
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_DST_DSCR_WORD1_OFFSET,
+		(((u64)Data->DstAddr >> XZDMA_WORD1_MSB_SHIFT) &
+		XZDMA_WORD1_MSB_MASK));
+
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_SRC_DSCR_WORD2_OFFSET,
+		(Data->Size & XZDMA_WORD2_SIZE_MASK));
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_DST_DSCR_WORD2_OFFSET,
+		(Data->Size & XZDMA_WORD2_SIZE_MASK));
+
+	Value = (u32)(Data->SrcCoherent & XZDMA_WORD3_COHRNT_MASK);
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_SRC_DSCR_WORD3_OFFSET, Value);
+
+	Value = (u32)(Data->DstCoherent & XZDMA_WORD3_COHRNT_MASK);
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+			XZDMA_CH_DST_DSCR_WORD3_OFFSET, Value);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in scatter gather mode.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure
+*		which has all the configuration fields for initiating data
+*		transfer.
+* @param	Num specifies number of array elements of Data pointer.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_ScatterGather(XZDma *InstancePtr, XZDma_Transfer *Data,
+								u32 Num)
+{
+	u32 Count = 0x00U;
+	u8 Last;
+	XZDma_Transfer *LocalData = Data;
+	XZDma_LiDscr *LiSrcDscr =
+		(XZDma_LiDscr *)(void *)(InstancePtr->Descriptor.SrcDscrPtr);
+	XZDma_LiDscr *LiDstDscr =
+		(XZDma_LiDscr *)(void *)(InstancePtr->Descriptor.DstDscrPtr);
+	XZDma_LlDscr *LlSrcDscr =
+		(XZDma_LlDscr *)(void *)(InstancePtr->Descriptor.SrcDscrPtr);
+	XZDma_LlDscr *LlDstDscr =
+		(XZDma_LlDscr *)(void *)(InstancePtr->Descriptor.DstDscrPtr);
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Data != NULL);
+	Xil_AssertVoid(Num != 0x00U);
+
+	if (InstancePtr->Descriptor.DscrType == XZDMA_LINEAR) {
+		Last = FALSE;
+		do {
+			if (Count == (Num- 1)) {
+				Last = TRUE;
+			}
+			XZDma_LinearMode(InstancePtr, LocalData, LiSrcDscr,
+							LiDstDscr, Last);
+			Count++;
+			LiSrcDscr++;
+			LiDstDscr++;
+			LocalData++;
+		} while(Count < Num);
+	}
+	else {
+		Last = FALSE;
+		do {
+			if (Count == (Num - 1)) {
+				Last = TRUE;
+			}
+			XZDma_LinkedListMode(InstancePtr, LocalData, LlSrcDscr,
+							LlDstDscr, Last);
+			Count++;
+			LlDstDscr++;
+			LlSrcDscr++;
+			LocalData++;
+		} while(Count < Num);
+	}
+
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_SRC_START_LSB_OFFSET,
+		((UINTPTR)(InstancePtr->Descriptor.SrcDscrPtr) &
+					XZDMA_WORD0_LSB_MASK));
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_SRC_START_MSB_OFFSET,
+		(((u64)(UINTPTR)(InstancePtr->Descriptor.SrcDscrPtr) >>
+			XZDMA_WORD1_MSB_SHIFT) & XZDMA_WORD1_MSB_MASK));
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_DST_START_LSB_OFFSET,
+		((UINTPTR)(InstancePtr->Descriptor.DstDscrPtr) &
+					XZDMA_WORD0_LSB_MASK));
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_DST_START_MSB_OFFSET,
+		(((u64)(UINTPTR)(InstancePtr->Descriptor.DstDscrPtr) >>
+			XZDMA_WORD1_MSB_SHIFT) & XZDMA_WORD1_MSB_MASK));
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linear descriptor type.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure which
+*		has all the configuration fields for initiating data transfer.
+* @param	SrcDscrPtr is descriptor pointer of source in which Data fields
+*		has to be filled.
+* @param	DstDscrPtr is descriptor pointer of destination in which Data
+*		fields has to be filled.
+* @param	IsLast specifies whether provided descriptor pointer is last
+*		one or not.
+*		- XZDMA_TRUE - If descriptor is last
+*		- XZDMA_FALSE - If descriptor is not last
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_LinearMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+	XZDma_LiDscr *SrcDscrPtr, XZDma_LiDscr *DstDscrPtr, u8 IsLast)
+{
+	u32 Value;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Data != NULL);
+	Xil_AssertVoid(SrcDscrPtr != NULL);
+	Xil_AssertVoid(DstDscrPtr != NULL);
+	Xil_AssertVoid((IsLast == TRUE) || (IsLast == FALSE));
+
+	if (Data->Pause == TRUE) {
+		Value = XZDMA_WORD3_CMD_PAUSE_MASK;
+	}
+	else if (IsLast == TRUE) {
+		Value = XZDMA_WORD3_CMD_STOP_MASK;
+	}
+	else {
+		Value = XZDMA_WORD3_CMD_NXTVALID_MASK;
+	}
+	if (Data->SrcCoherent == TRUE) {
+		Value |= XZDMA_WORD3_COHRNT_MASK;
+	}
+
+	XZDma_ConfigLinear(SrcDscrPtr, (u64)Data->SrcAddr, Data->Size, Value);
+
+	Value = 0U;
+
+	if (Data->DstCoherent == TRUE) {
+		Value |= XZDMA_WORD3_COHRNT_MASK;
+	}
+
+	XZDma_ConfigLinear(DstDscrPtr, (u64)Data->DstAddr, Data->Size, Value);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linear descriptor type.
+*
+* @param	DscrPtr is a pointer to source/destination descriptor.
+* @param	Addr is a 64 bit variable which denotes the address of data.
+* @param	Size specifies the amount of the data to be transferred.
+* @param	CtrlValue contains all the control fields of descriptor.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_ConfigLinear(XZDma_LiDscr *DscrPtr, u64 Addr, u32 Size,
+								u32 CtrlValue)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(DscrPtr != NULL);
+	Xil_AssertVoid(Addr != 0x00U);
+
+	DscrPtr->Address = Addr;
+	DscrPtr->Size = Size & XZDMA_WORD2_SIZE_MASK;
+	DscrPtr->Cntl = CtrlValue;
+
+	Xil_DCacheFlushRange((UINTPTR)DscrPtr, sizeof(XZDma_LlDscr));
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linked list descriptor type.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure which
+*		has all the configuration fields for initiating data transfer.
+* @param	SrcDscrPtr is descriptor pointer of source in which Data fields
+*		has to be filled.
+* @param	DstDscrPtr is descriptor pointer of destination in which Data
+*		fields has to be filled.
+* @param	IsLast specifies whether provided descriptor pointer is last
+*		one or not.
+*		- TRUE - If descriptor is last
+*		- FALSE - If descriptor is not last
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_LinkedListMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+	XZDma_LlDscr *SrcDscrPtr,XZDma_LlDscr *DstDscrPtr, u8 IsLast)
+{
+	u32 Value;
+	XZDma_LlDscr *NextSrc = SrcDscrPtr;
+	XZDma_LlDscr *NextDst = DstDscrPtr;
+	u64 NextSrcAdrs = 0x00U;
+	u64 NextDstAdrs = 0x00U;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Data != NULL);
+	Xil_AssertVoid(SrcDscrPtr != NULL);
+	Xil_AssertVoid(DstDscrPtr != NULL);
+	Xil_AssertVoid((IsLast == TRUE) || (IsLast == FALSE));
+
+	NextDst++;
+	NextSrc++;
+
+	if (Data->Pause == TRUE) {
+		Value = XZDMA_WORD3_CMD_PAUSE_MASK;
+		if (IsLast != TRUE) {
+			NextSrcAdrs = (u64)(UINTPTR)NextSrc;
+			NextDstAdrs = (u64)(UINTPTR)NextDst;
+		}
+	}
+	else if (IsLast == TRUE) {
+		Value = XZDMA_WORD3_CMD_STOP_MASK;
+	}
+	else {
+		Value = XZDMA_WORD3_CMD_NXTVALID_MASK;
+		NextSrcAdrs = (u64)(UINTPTR)NextSrc;
+		NextDstAdrs = (u64)(UINTPTR)NextDst;
+	}
+	if (Data->SrcCoherent == TRUE) {
+		Value |= XZDMA_WORD3_COHRNT_MASK;
+	}
+
+	XZDma_ConfigLinkedList(SrcDscrPtr, (u64)Data->SrcAddr,
+					Data->Size, Value, NextSrcAdrs);
+
+	Value = 0U;
+
+	if (Data->DstCoherent == TRUE) {
+		Value |= XZDMA_WORD3_COHRNT_MASK;
+	}
+
+	XZDma_ConfigLinkedList(DstDscrPtr, (u64)Data->DstAddr,
+					Data->Size, Value, NextDstAdrs);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linked list descriptor type.
+*
+* @param	DscrPtr is a pointer to source/destination descriptor.
+* @param	Addr is a 64 bit variable which denotes the address of data.
+* @param	Size specifies the amount of the data to be transferred.
+* @param	CtrlValue contains all the control fields of descriptor.
+* @param	NextDscrAddr is the address of next descriptor.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_ConfigLinkedList(XZDma_LlDscr *DscrPtr, u64 Addr, u32 Size,
+			u32 CtrlValue, u64 NextDscrAddr)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(DscrPtr != NULL);
+	Xil_AssertVoid(Addr != 0x00U);
+
+	DscrPtr->Address = Addr;
+	DscrPtr->Size = Size & XZDMA_WORD2_SIZE_MASK;
+	DscrPtr->Cntl = CtrlValue;
+	DscrPtr->NextDscr = NextDscrAddr;
+	DscrPtr->Reserved = 0U;
+
+	Xil_DCacheFlushRange((UINTPTR)DscrPtr, sizeof(XZDma_LlDscr));
+}
+
+/*****************************************************************************/
+/**
+* This static function enable's all the interrupts which user intended to
+* enable and enables the ZDMA channel for initiating data transfer.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+
+static void XZDma_Enable(XZDma *InstancePtr)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_IEN_OFFSET,
+			(InstancePtr->IntrMask & XZDMA_IXR_ALL_INTR_MASK));
+	InstancePtr->ChannelState = XZDMA_BUSY;
+	XZDma_EnableCh(InstancePtr);
+
+}
+
+/*****************************************************************************/
+/**
+* This static function gets all the reset configurations of ZDMA.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_GetConfigurations(XZDma *InstancePtr)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	InstancePtr->DataConfig.SrcIssue = (u8)XZDMA_CTRL1_SRC_ISSUE_MASK;
+	InstancePtr->DataConfig.SrcBurstType = XZDMA_INCR_BURST;
+	InstancePtr->DataConfig.SrcBurstLen = 0xFU;
+	InstancePtr->DataConfig.OverFetch = 1U;
+	InstancePtr->DataConfig.DstBurstType = XZDMA_INCR_BURST;
+	InstancePtr->DataConfig.DstBurstLen = 0xFU;
+	InstancePtr->DataConfig.SrcCache = 0x2U;
+	InstancePtr->DataConfig.DstCache = 0x2U;
+	InstancePtr->DataConfig.SrcQos = 0x0U;
+	InstancePtr->DataConfig.DstQos = 0x0U;
+
+	InstancePtr->DscrConfig.AXCache = 0U;
+	InstancePtr->DscrConfig.AXQos = 0U;
+	InstancePtr->DscrConfig.AxCoherent = 0U;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine is a stub for the asynchronous callbacks. The stub is here in
+* case the upper layer forgot to set the handlers. On initialization, All
+* handlers are set to this callback. It is considered an error for this
+* handler to be invoked.
+*
+* @param	CallBackRef is a callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked.
+* @param	Mask is the type of the interrupts to enable. Use OR'ing of
+*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+*		this parameter value.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubCallBack(void *CallBackRef, u32 Mask)
+{
+	/* Verify arguments. */
+	Xil_AssertVoid(CallBackRef != NULL);
+	Xil_AssertVoid(Mask != (u32)0x00);
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine is a stub for the DMA done callback. The stub is here in
+* case the upper layer forgot to set the handlers. On initialization, Done
+* handler are set to this callback.
+*
+* @param	CallBackRef is a callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubDoneCallBack(void *CallBackRef)
+{
+	/* Verify arguments. */
+	Xil_AssertVoid(CallBackRef != NULL);
+	Xil_AssertVoidAlways();
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma.h
new file mode 100644
index 000000000..af8430e66
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma.h
@@ -0,0 +1,669 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* ZDMA is a general purpose DMA designed to support memory to memory and memory
+* to IO buffer transfers. ALTO has two instance of general purpose ZDMA.
+* One is located in FPD (full power domain) which is GDMA and other is located
+* in LPD (low power domain) which is ADMA.
+*
+* GMDA & ADMA are configured each with 8 DMA channels and and each channel can
+* be programmed secure or non-secure.
+* Each channel is divided into two functional sides, Source (Read) and
+* Destination (Write). Each DMA channel can be independently programmed
+* in one of following DMA modes.
+*	- Simple DMA
+*		- Normal data transfer from source to destination.
+*		- Write Only mode.
+*		- Read Only mode.
+*	- Scatter Gather DMA
+*		- Only Normal mode it can't support other two modes.
+* In Scatter gather descriptor can be of 3 types
+*	- Linear descriptor.
+*	- Linked list descriptor
+*	- Hybrid descriptor (Combination of both Linear and Linked list)
+* Our driver will not support Hybrid type of descriptor.
+*
+* Initialization & Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the ZDMA core.
+*
+* XZDma_CfgInitialize() API is used to initialize the ZDMA core.
+* The user needs to first call the XZDma_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to the
+* XZDma_CfgInitialize() API.
+*
+*  Interrupts 
+* The driver provides an interrupt handler XZDma_IntrHandler for handling
+* the interrupt from the ZDMA core. The users of this driver have to
+* register this handler with the interrupt system and provide the callback
+* functions by using XZDma_SetCallBack API. In this version Descriptor done
+* option is disabled.
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*  Building the driver 
+*
+* The XZDma driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* @file xzdma.h
+*
+* This header file contains identifiers and register-level driver functions (or
+* macros), range macros, structure typedefs that can be used to access the
+* Xilinx ZDMA core instance.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+#ifndef XZDMA_H_
+#define XZDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xzdma_hw.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_cache.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/** @name ZDMA Handler Types
+ * @{
+ */
+typedef enum {
+	XZDMA_HANDLER_DONE,	/**< For Done Handler */
+	XZDMA_HANDLER_ERROR,	/**< For Error Handler */
+} XZDma_Handler;
+/*@}*/
+
+/** @name ZDMA Descriptors Types
+ * @{
+ */
+typedef enum {
+	XZDMA_LINEAR,		/**< Linear descriptor */
+	XZDMA_LINKEDLIST,	/**< Linked list descriptor */
+} XZDma_DscrType;
+/*@}*/
+
+/** @name ZDMA Operation modes
+ * @{
+ */
+typedef enum {
+	XZDMA_NORMAL_MODE,	/**< Normal transfer from source to
+				  *  destination*/
+	XZDMA_WRONLY_MODE,	/**< Write only mode */
+	XZDMA_RDONLY_MODE	/**< Read only mode */
+} XZDma_Mode;
+/*@}*/
+
+/** @name ZDMA state
+ * @{
+ */
+typedef enum {
+	XZDMA_IDLE,		/**< ZDMA is in Idle state */
+	XZDMA_PAUSE,		/**< Paused state */
+	XZDMA_BUSY,		/**< Busy state */
+} XZDmaState;
+/*@}*/
+
+/** @name ZDMA AXI Burst type
+ * @{
+ */
+typedef enum {
+	XZDMA_FIXED_BURST = 0,	/**< Fixed burst type */
+	XZDMA_INCR_BURST	/**< Increment burst type */
+} XZDma_BurstType;
+/*@}*/
+
+/******************************************************************************/
+/**
+* This typedef contains scatter gather descriptor fields for ZDMA core.
+*/
+typedef struct {
+	void *SrcDscrPtr;	/**< Source Descriptor pointer */
+	void *DstDscrPtr;	/**< Destination Descriptor pointer */
+	u32 DscrCount;		/**< Count of descriptors available */
+	XZDma_DscrType DscrType;/**< Type of descriptor either Linear or
+				  *  Linked list type */
+} XZDma_Descriptor;
+
+/******************************************************************************/
+/**
+* This typedef contains scatter gather descriptor fields for ZDMA core.
+*/
+typedef struct {
+	u64 Address;	/**< Address */
+	u32 Size;	/**< Word2, Size of data */
+	u32 Cntl;	/**< Word3 Control data */
+	u64 NextDscr; 	/**< Address of next descriptor */
+	u64 Reserved;	/**< Reserved address */
+} __attribute__ ((packed)) XZDma_LlDscr;
+
+/******************************************************************************/
+/**
+* This typedef contains Linear descriptor fields for ZDMA core.
+*/
+typedef struct {
+	u64 Address;	/**< Address */
+	u32 Size;	/**< Word3, Size of data */
+	u32 Cntl;	/**< Word4, control data */
+}  __attribute__ ((packed)) XZDma_LiDscr;
+
+/******************************************************************************/
+/**
+*
+* This typedef contains the data configurations of ZDMA core
+*/
+typedef struct {
+	u8 OverFetch;		/**< Enable Over fetch */
+	u8 SrcIssue;		/**< Outstanding transactions for Source */
+	XZDma_BurstType SrcBurstType;
+				/**< Burst type for SRC */
+	u8 SrcBurstLen;		/**< AXI length for data read */
+	XZDma_BurstType DstBurstType;
+				/**< Burst type for DST */
+	u8 DstBurstLen;		/**< AXI length for data write */
+	u8 SrcCache;		/**< AXI cache bits for data read */
+	u8 SrcQos;		/**< AXI QOS bits for data read */
+	u8 DstCache;		/**< AXI cache bits for data write */
+	u8 DstQos;		/**< AXI QOS bits for data write */
+} XZDma_DataConfig;
+
+/******************************************************************************/
+/**
+*
+* This typedef contains the descriptor configurations of ZDMA core
+*/
+typedef struct{
+	u8 AxCoherent;	/**< AXI transactions are coherent or non-coherent */
+	u8 AXCache;	/**< AXI cache for DSCR fetch */
+	u8 AXQos;	/**< Qos bit for DSCR fetch */
+} XZDma_DscrConfig;
+
+/******************************************************************************/
+/**
+* Callback type for Completion of all data transfers.
+*
+* @param 	CallBackRef is a callback reference passed in by the upper layer
+*		when setting the callback functions, and passed back to the
+*		upper layer when the callback is invoked.
+*******************************************************************************/
+typedef void (*XZDma_DoneHandler) (void *CallBackRef);
+
+/******************************************************************************/
+/**
+* Callback type for all error interrupts.
+*
+* @param 	CallBackRef is a callback reference passed in by the upper layer
+*		when setting the callback functions, and passed back to the
+*		upper layer when the callback is invoked.
+* @param	ErrorMask is a bit mask indicating the cause of the error. Its
+*		value equals 'OR'ing one or more XZDMA_IXR_* values defined in
+*		xzdma_hw.h
+****************************************************************************/
+typedef void (*XZDma_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
+
+/**
+* This typedef contains configuration information for a ZDMA core
+* Each ZDMA core should have a configuration structure associated.
+*/
+typedef struct {
+	u16 DeviceId;		/**< Device Id of ZDMA */
+	u32 BaseAddress;	/**< BaseAddress of ZDMA */
+	u8 DmaType;		/**< Type of DMA */
+} XZDma_Config;
+
+/******************************************************************************/
+/**
+*
+* The XZDma driver instance data structure. A pointer to an instance data
+* structure is passed around by functions to refer to a specific driver
+* instance.
+*/
+typedef struct {
+	XZDma_Config Config;	/**< Hardware configuration */
+	u32 IsReady;		/**< Device and the driver instance
+				  *  are initialized */
+	u32 IntrMask;		/**< Mask for enabling interrupts */
+
+	XZDma_Mode Mode;	/**< Mode of ZDMA core to be operated */
+	u8 IsSgDma;		/**< Is ZDMA core is in scatter gather or
+				  *  not will be specified */
+	XZDma_Descriptor Descriptor;	/**< It contains information about
+					  * descriptors */
+
+	XZDma_DoneHandler DoneHandler;	/**< Call back for transfer
+					  *  done interrupt */
+	void *DoneRef;			/**< To be passed to the done
+					  * interrupt callback */
+
+	XZDma_ErrorHandler ErrorHandler;/**< Call back for error
+					  *  interrupt */
+	void *ErrorRef;			/**< To be passed to the error
+					  * interrupt callback */
+	XZDma_DataConfig DataConfig;	/**< Current configurations */
+	XZDma_DscrConfig DscrConfig;	/**< Current configurations */
+	XZDmaState ChannelState;	 /**< ZDMA channel is busy */
+
+} XZDma;
+
+/******************************************************************************/
+/**
+*
+* This typedef contains the fields for transfer of data.
+*/
+typedef struct {
+	UINTPTR SrcAddr;	/**< Source address */
+	UINTPTR DstAddr;	/**< Destination Address */
+	u32 Size;		/**< Size of the data to be transferred */
+	u8 SrcCoherent;		/**< Source coherent */
+	u8 DstCoherent;		/**< Destination coherent */
+	u8 Pause;		/**< Will pause data transmission after
+				  *  this transfer only for SG mode */
+} XZDma_Transfer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+* Use the XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to interpret the
+* returned value.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	The pending interrupts of the ZDMA core.
+*		Use the masks specified in xzdma_hw.h to interpret
+*		the returned value.
+* @note
+* 		C-style signature:
+*		void XZDma_IntrGetStatus(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_IntrGetStatus(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, XZDMA_CH_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears interrupt(s). Every bit set in Interrupt Status
+* Register indicates that a specific type of interrupt is occurring, and this
+* function clears one or more interrupts by writing a bit mask to Interrupt
+* Clear Register.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Mask is the type of the interrupts to enable. Use OR'ing of
+*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+*		this parameter value.
+*
+* @return	None.
+*
+* @note
+* 		C-style signature:
+*		void XZDma_IntrClear(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_IntrClear(InstancePtr, Mask) \
+	XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_ISR_OFFSET, ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function returns interrupt mask to know which interrupts are
+* enabled and which of them were disabled.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	The current interrupt mask. The mask indicates which interrupts
+*		are enabled/disabled.
+*		0 bit represents .....corresponding interrupt is enabled.
+*		1 bit represents .....Corresponding interrupt is disabled.
+*
+* @note
+* 		C-style signature:
+*		void XZDma_GetIntrMask(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetIntrMask(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress,  \
+			(u32)(XZDMA_CH_IMR_OFFSET))
+
+/*****************************************************************************/
+/**
+*
+* This function enables individual interrupts of the ZDMA core by updating
+* the Interrupt Enable register.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Mask is the type of the interrupts to enable. Use OR'ing of
+*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+*		this parameter value.
+*
+* @return	None.
+*
+* @note		The existing enabled interrupt(s) will remain enabled.
+* 		C-style signature:
+*		void XZDma_EnableIntr(XZDma *InstancePtr, u32 Mask)
+*
+******************************************************************************/
+#define XZDma_EnableIntr(InstancePtr, Mask) \
+	(InstancePtr)->IntrMask = ((InstancePtr)->IntrMask | (Mask))
+
+/*****************************************************************************/
+/**
+*
+* This function disables individual interrupts of the ZDMA core by updating
+* the Interrupt Disable register.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Mask is the type of the interrupts to disable. Use OR'ing of
+*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+*		this parameter value.
+*
+* @return	None.
+*
+* @note		The existing disabled interrupt(s) will remain disabled.
+* 		C-style signature:
+*		void XZDma_DisableIntr(XZDma *InstancePtr, u32 Mask)
+*
+******************************************************************************/
+#define XZDma_DisableIntr(InstancePtr, Mask) \
+	XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_IDS_OFFSET, \
+	((u32)XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_IDS_OFFSET) | ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function returns source current payload address under process
+* of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This address may not be precise due to ZDMA pipeline structure
+*		C-style signature:
+*		u64 XZDma_SrcCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_SrcCurPyld(InstancePtr) \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET)) | \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function returns destination current payload address under process
+* of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This address may not be precise due to ZDMA pipeline structure
+*		C-style signature:
+*		u64 XZDma_DstCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_DstCurPyld(InstancePtr) \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET)) | \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function returns source descriptor current payload address under
+* process of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This address may not be precise due to ZDMA pipeline structure
+*		C-style signature:
+*		u64 XZDma_SrcDscrCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_SrcDscrCurPyld(InstancePtr) \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET)) | \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+
+/*****************************************************************************/
+/**
+*
+* This function returns destination descriptor current payload address under
+* process of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This address may not be precise due to ZDMA pipeline structure
+*		C-style signature:
+*		u64 XZDma_DstDscrCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_DstDscrCurPyld(InstancePtr) \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET)) | \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the count of total bytes transferred through core
+* since last clear in ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note
+*		C-style signature:
+*		void XZDma_GetTotalByte(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetTotalByte(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_TOTAL_BYTE_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the count of total bytes transferred in ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note
+*		C-style signature:
+*		void XZDma_TotalByteClear(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_TotalByteClear(InstancePtr) \
+	XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XZDMA_CH_TOTAL_BYTE_OFFSET, \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XZDMA_CH_TOTAL_BYTE_OFFSET))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the total number of Interrupt count for source after last
+* call of this API.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		Once this API is called then count will become zero.
+*		C-style signature:
+*		void XZDma_GetSrcIntrCnt(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetSrcIntrCnt(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_IRQ_SRC_ACCT_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function gets the total number of Interrupt count for destination
+* after last call of this API.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		Once this API is called then count will become zero.
+*		C-style signature:
+*		void XZDma_GetDstIntrCnt(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetDstIntrCnt(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_IRQ_DST_ACCT_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function Enable's the ZDMA core for initiating the data transfer once the
+* data transfer completes it will be automatically disabled.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		None.
+*		C-style signature:
+*		void XZDma_EnableCh(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_EnableCh(InstancePtr) \
+	XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
+			(XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_EN_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function Disable's the ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		None.
+*		C-style signature:
+*		void XZDma_DisableCh(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_DisableCh(InstancePtr) \
+	XZDma_WriteReg((InstancePtr)->Config.BaseAddress,\
+		(XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_DIS_MASK))
+
+/************************ Prototypes of functions **************************/
+
+XZDma_Config *XZDma_LookupConfig(u16 DeviceId);
+
+s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr,
+			u32 EffectiveAddr);
+s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode);
+u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr,
+					UINTPTR Dscr_MemPtr, u32 NoOfBytes);
+s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
+void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
+s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
+void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
+s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num);
+void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer);
+void XZDma_Resume(XZDma *InstancePtr);
+void XZDma_Reset(XZDma *InstancePtr);
+XZDmaState XZDma_ChannelState(XZDma *InstancePtr);
+
+s32 XZDma_SelfTest(XZDma *InstancePtr);
+
+void XZDma_IntrHandler(void *Instance);
+s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
+	void *CallBackFunc, void *CallBackRef);
+
+/*@}*/
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif /* XZDMA_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_g.c
new file mode 100644
index 000000000..0a7fa6523
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_g.c
@@ -0,0 +1,131 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xzdma.h"
+
+/*
+* The configuration table for devices
+*/
+
+XZDma_Config XZDma_ConfigTable[] =
+{
+	{
+		XPAR_PSU_ADMA_0_DEVICE_ID,
+		XPAR_PSU_ADMA_0_BASEADDR,
+		XPAR_PSU_ADMA_0_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_1_DEVICE_ID,
+		XPAR_PSU_ADMA_1_BASEADDR,
+		XPAR_PSU_ADMA_1_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_2_DEVICE_ID,
+		XPAR_PSU_ADMA_2_BASEADDR,
+		XPAR_PSU_ADMA_2_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_3_DEVICE_ID,
+		XPAR_PSU_ADMA_3_BASEADDR,
+		XPAR_PSU_ADMA_3_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_4_DEVICE_ID,
+		XPAR_PSU_ADMA_4_BASEADDR,
+		XPAR_PSU_ADMA_4_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_5_DEVICE_ID,
+		XPAR_PSU_ADMA_5_BASEADDR,
+		XPAR_PSU_ADMA_5_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_6_DEVICE_ID,
+		XPAR_PSU_ADMA_6_BASEADDR,
+		XPAR_PSU_ADMA_6_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_7_DEVICE_ID,
+		XPAR_PSU_ADMA_7_BASEADDR,
+		XPAR_PSU_ADMA_7_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_0_DEVICE_ID,
+		XPAR_PSU_GDMA_0_BASEADDR,
+		XPAR_PSU_GDMA_0_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_1_DEVICE_ID,
+		XPAR_PSU_GDMA_1_BASEADDR,
+		XPAR_PSU_GDMA_1_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_2_DEVICE_ID,
+		XPAR_PSU_GDMA_2_BASEADDR,
+		XPAR_PSU_GDMA_2_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_3_DEVICE_ID,
+		XPAR_PSU_GDMA_3_BASEADDR,
+		XPAR_PSU_GDMA_3_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_4_DEVICE_ID,
+		XPAR_PSU_GDMA_4_BASEADDR,
+		XPAR_PSU_GDMA_4_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_5_DEVICE_ID,
+		XPAR_PSU_GDMA_5_BASEADDR,
+		XPAR_PSU_GDMA_5_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_6_DEVICE_ID,
+		XPAR_PSU_GDMA_6_BASEADDR,
+		XPAR_PSU_GDMA_6_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_7_DEVICE_ID,
+		XPAR_PSU_GDMA_7_BASEADDR,
+		XPAR_PSU_GDMA_7_DMA_MODE
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_hw.h
new file mode 100644
index 000000000..22a006e19
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_hw.h
@@ -0,0 +1,380 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_hw.h
+*
+* This header file contains identifiers and register-level driver functions (or
+* macros) that can be used to access the Xilinx ZDMA core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+#ifndef XZDMA_HW_H_
+#define XZDMA_HW_H_		/**< Prevent circular inclusions
+				  *  by using protection macros	*/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers offsets
+ * @{
+ */
+#define XZDMA_ERR_CTRL				(0x000U)
+#define XZDMA_CH_ECO				(0x004U)
+#define XZDMA_CH_ISR_OFFSET			(0x100U)
+#define XZDMA_CH_IMR_OFFSET			(0x104U)
+#define XZDMA_CH_IEN_OFFSET			(0x108U)
+#define XZDMA_CH_IDS_OFFSET			(0x10CU)
+#define XZDMA_CH_CTRL0_OFFSET			(0x110U)
+#define XZDMA_CH_CTRL1_OFFSET			(0x114U)
+#define XZDMA_CH_PERIF_OFFSET			(0x118U)
+#define XZDMA_CH_STS_OFFSET			(0x11CU)
+#define XZDMA_CH_DATA_ATTR_OFFSET		(0x120U)
+#define XZDMA_CH_DSCR_ATTR_OFFSET		(0x124U)
+#define XZDMA_CH_SRC_DSCR_WORD0_OFFSET		(0x128U)
+#define XZDMA_CH_SRC_DSCR_WORD1_OFFSET		(0x12CU)
+#define XZDMA_CH_SRC_DSCR_WORD2_OFFSET		(0x130U)
+#define XZDMA_CH_SRC_DSCR_WORD3_OFFSET		(0x134U)
+#define XZDMA_CH_DST_DSCR_WORD0_OFFSET		(0x138U)
+#define XZDMA_CH_DST_DSCR_WORD1_OFFSET		(0x13CU)
+#define XZDMA_CH_DST_DSCR_WORD2_OFFSET		(0x140U)
+#define XZDMA_CH_DST_DSCR_WORD3_OFFSET		(0x144U)
+#define XZDMA_CH_WR_ONLY_WORD0_OFFSET		(0x148U)
+#define XZDMA_CH_WR_ONLY_WORD1_OFFSET		(0x14CU)
+#define XZDMA_CH_WR_ONLY_WORD2_OFFSET		(0x150U)
+#define XZDMA_CH_WR_ONLY_WORD3_OFFSET		(0x154U)
+#define XZDMA_CH_SRC_START_LSB_OFFSET		(0x158U)
+#define XZDMA_CH_SRC_START_MSB_OFFSET		(0x15CU)
+#define XZDMA_CH_DST_START_LSB_OFFSET		(0x160U)
+#define XZDMA_CH_DST_START_MSB_OFFSET		(0x164U)
+#define XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET	(0x168U)
+#define XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET	(0x16CU)
+#define XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET	(0x170U)
+#define XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET	(0x174U)
+#define XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET	(0x178U)
+#define XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET	(0x17CU)
+#define XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET	(0x180U)
+#define XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET	(0x184U)
+#define XZDMA_CH_TOTAL_BYTE_OFFSET		(0x188U)
+#define XZDMA_CH_RATE_CNTL_OFFSET		(0x18CU)
+#define XZDMA_CH_IRQ_SRC_ACCT_OFFSET		(0x190U)
+#define XZDMA_CH_IRQ_DST_ACCT_OFFSET		(0x194U)
+#define XZDMA_CH_CTRL2_OFFSET			(0x200U)
+/*@}*/
+
+/** @name Interrupt Enable/Disable/Mask/Status registers bit masks and shifts
+ * @{
+ */
+#define XZDMA_IXR_DMA_PAUSE_MASK	(0x00000800U) /**< IXR pause mask */
+#define XZDMA_IXR_DMA_DONE_MASK		(0x00000400U) /**< IXR done mask */
+#define XZDMA_IXR_AXI_WR_DATA_MASK	(0x00000200U) /**< IXR AXI write data
+							*  error mask */
+#define XZDMA_IXR_AXI_RD_DATA_MASK	(0x00000100U) /**< IXR AXI read data
+							*  error mask */
+#define XZDMA_IXR_AXI_RD_DST_DSCR_MASK	(0x00000080U) /**< IXR AXI read
+							*  descriptor error
+							*  mask */
+#define XZDMA_IXR_AXI_RD_SRC_DSCR_MASK	(0x00000040U) /**< IXR AXI write
+							*  descriptor error
+							*  mask */
+#define XZDMA_IXR_DST_ACCT_ERR_MASK	(0x00000020U) /**< IXR DST interrupt
+							*  count overflow
+							*  mask */
+#define XZDMA_IXR_SRC_ACCT_ERR_MASK	(0x00000010U) /**< IXR SRC interrupt
+							*  count overflow
+							*  mask */
+#define XZDMA_IXR_BYTE_CNT_OVRFL_MASK	(0x00000008U) /**< IXR byte count over
+							* flow mask */
+#define XZDMA_IXR_DST_DSCR_DONE_MASK	(0x00000004U) /**< IXR destination
+							*  descriptor done
+							*  mask */
+#define XZDMA_IXR_SRC_DSCR_DONE_MASK	(0x00000002U) /**< IXR source
+							*  descriptor done
+							*  mask */
+#define XZDMA_IXR_INV_APB_MASK		(0x00000001U) /**< IXR invalid APB
+							*  access mask */
+#define XZDMA_IXR_ALL_INTR_MASK		(0x00000FFFU) /**< IXR OR of all the
+							*  interrupts mask */
+#define XZDMA_IXR_DONE_MASK		(0x00000400U) /**< IXR All done mask */
+
+#define XZDMA_IXR_ERR_MASK		(0x00000BF9U) /**< IXR all Error mask*/
+					/**< Or of XZDMA_IXR_AXI_WR_DATA_MASK,
+					  * XZDMA_IXR_AXI_RD_DATA_MASK,
+					  * XZDMA_IXR_AXI_RD_DST_DSCR_MASK,
+					  * XZDMA_IXR_AXI_RD_SRC_DSCR_MASK,
+					  * XZDMA_IXR_INV_APB_MASK,
+					  * XZDMA_IXR_DMA_PAUSE_MASK,
+					  * XZDMA_IXR_BYTE_CNT_OVRFL_MASK,
+					  * XZDMA_IXR_SRC_ACCT_ERR_MASK,
+					  *  XZDMA_IXR_DST_ACCT_ERR_MASK */
+/*@}*/
+
+/** @name Channel Control0 register bit masks and shifts
+ * @{
+ */
+#define XZDMA_CTRL0_OVR_FETCH_MASK	(0x00000080U) /**< Over fetch mask */
+#define XZDMA_CTRL0_POINT_TYPE_MASK	(0x00000040U) /**< Pointer type mask */
+#define XZDMA_CTRL0_MODE_MASK		(0x00000030U) /**< Mode mask */
+#define XZDMA_CTRL0_WRONLY_MASK		(0x00000010U) /**< Write only mask */
+#define XZDMA_CTRL0_RDONLY_MASK		(0x00000020U) /**< Read only mask */
+#define XZDMA_CTRL0_RATE_CNTL_MASK	(0x00000008U) /**< Rate control mask */
+#define XZDMA_CTRL0_CONT_ADDR_MASK	(0x00000004U) /**< Continue address
+							*  specified mask */
+#define XZDMA_CTRL0_CONT_MASK		(0x00000002U) /**< Continue mask */
+
+#define XZDMA_CTRL0_OVR_FETCH_SHIFT	(7U)	/**< Over fetch shift */
+#define XZDMA_CTRL0_POINT_TYPE_SHIFT	(6U)	/**< Pointer type shift */
+#define XZDMA_CTRL0_MODE_SHIFT		(4U)	/**< Mode type shift */
+#define XZDMA_CTRL0_RESET_VALUE		(0x00000080U) /**< CTRL0 reset value */
+
+/*@}*/
+
+/** @name Channel Control1 register bit masks and shifts
+ * @{
+ */
+#define XZDMA_CTRL1_SRC_ISSUE_MASK	(0x0000001FU) /**< Source issue mask */
+#define XZDMA_CTRL1_RESET_VALUE		(0x000003FFU) /**< CTRL1 reset value */
+/*@}*/
+
+/** @name Channel Peripheral register bit masks and shifts
+ * @{
+ */
+#define XZDMA_PERIF_PROG_CELL_CNT_MASK	(0x0000003EU) /**< Peripheral program
+							*  cell count */
+#define XZDMA_PERIF_SIDE_MASK		(0x00000002U) /**< Interface attached
+							* the side mask */
+#define XZDMA_PERIF_EN_MASK		(0x00000001U) /**< Peripheral flow
+							* control mask */
+/*@}*/
+
+/** @name Channel Status register bit masks and shifts
+ * @{
+ */
+#define XZDMA_STS_DONE_ERR_MASK	(0x00000003U) /**< Done with errors mask */
+#define XZDMA_STS_BUSY_MASK	(0x00000002U) /**< ZDMA is busy in transfer
+						*  mask */
+#define XZDMA_STS_PAUSE_MASK	(0x00000001U) /**< ZDMA is in Pause state
+						*  mask */
+#define XZDMA_STS_DONE_MASK	(0x00000000U) /**< ZDMA done mask */
+#define XZDMA_STS_ALL_MASK	(0x00000003U) /**< ZDMA status mask */
+
+/*@}*/
+
+/** @name Channel Data Attribute register bit masks and shifts
+ * @{
+ */
+#define XZDMA_DATA_ATTR_ARBURST_MASK	(0x0C000000U) /**< Data ArBurst mask */
+#define XZDMA_DATA_ATTR_ARCACHE_MASK	(0x03C00000U) /**< Data ArCache mask */
+#define XZDMA_DATA_ATTR_ARQOS_MASK	(0x003C0000U) /**< Data ARQos masks */
+#define XZDMA_DATA_ATTR_ARLEN_MASK	(0x0003C000U) /**< Data Arlen mask */
+#define XZDMA_DATA_ATTR_AWBURST_MASK	(0x00003000U) /**< Data Awburst mask */
+#define XZDMA_DATA_ATTR_AWCACHE_MASK	(0x00000F00U) /**< Data AwCache mask */
+#define XZDMA_DATA_ATTR_AWQOS_MASK	(0x000000F0U) /**< Data AwQos mask */
+#define XZDMA_DATA_ATTR_AWLEN_MASK	(0x0000000FU) /**< Data Awlen mask */
+
+#define XZDMA_DATA_ATTR_ARBURST_SHIFT	(26U) /**< Data Arburst shift */
+#define XZDMA_DATA_ATTR_ARCACHE_SHIFT	(22U) /**< Data ArCache shift */
+#define XZDMA_DATA_ATTR_ARQOS_SHIFT	(18U) /**< Data ARQos shift */
+#define XZDMA_DATA_ATTR_ARLEN_SHIFT	(14U) /**< Data Arlen shift */
+#define XZDMA_DATA_ATTR_AWBURST_SHIFT	(12U) /**< Data Awburst shift  */
+#define XZDMA_DATA_ATTR_AWCACHE_SHIFT	(8U)  /**< Data Awcache shift */
+#define XZDMA_DATA_ATTR_AWQOS_SHIFT	(4U)  /**< Data Awqos shift */
+#define XZDMA_DATA_ATTR_RESET_VALUE	(0x0483D20FU) /**< Data Attributes
+							*  reset value */
+
+/*@}*/
+
+/** @name Channel DSCR Attribute register bit masks and shifts
+ * @{
+ */
+#define XZDMA_DSCR_ATTR_AXCOHRNT_MASK	(0x00000100U) /**< Descriptor coherent
+							*  mask */
+#define XZDMA_DSCR_ATTR_AXCACHE_MASK	(0x000000F0U) /**< Descriptor cache
+							* mask */
+#define XZDMA_DSCR_ATTR_AXQOS_MASK	(0x0000000FU) /**< Descriptor AxQos
+							*  mask */
+
+#define XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT	(8U) /**< Descriptor coherent shift */
+#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT	(7U) /**< Descriptor cache shift */
+#define XZDMA_DSCR_ATTR_RESET_VALUE	(0x00000000U) /**< Dscr Attributes
+							*  reset value */
+
+/*@}*/
+
+/** @name Channel Source/Destination Word0 register bit mask
+ * @{
+ */
+#define XZDMA_WORD0_LSB_MASK	(0xFFFFFFFFU)	/**< LSB Address mask */
+/*@}*/
+
+/** @name Channel Source/Destination Word1 register bit mask
+ * @{
+ */
+#define XZDMA_WORD1_MSB_MASK	(0x0001FFFFU)	/**< MSB Address mask */
+#define XZDMA_WORD1_MSB_SHIFT	(32U)		/**< MSB Address shift */
+/*@}*/
+
+/** @name Channel Source/Destination Word2 register bit mask
+ * @{
+ */
+#define XZDMA_WORD2_SIZE_MASK	(0x3FFFFFFFU) /**< Size mask */
+/*@}*/
+
+/** @name Channel Source/Destination Word3 register bit masks and shifts
+ * @{
+ */
+#define XZDMA_WORD3_CMD_MASK		(0x00000018U)	/**< Cmd mask */
+#define XZDMA_WORD3_CMD_SHIFT		(3U)		/**< Cmd shift */
+#define XZDMA_WORD3_CMD_NXTVALID_MASK	(0x00000000U)	/**< Next Dscr is valid
+							  *  mask */
+#define XZDMA_WORD3_CMD_PAUSE_MASK	(0x00000008U)	/**< Pause after this
+							  * dscr mask */
+#define XZDMA_WORD3_CMD_STOP_MASK	(0x00000010U)	/**< Stop after this
+							..*  dscr mask */
+#define XZDMA_WORD3_INTR_MASK		(0x00000004U)	/**< Interrupt
+							  *  enable or disable
+							  *  mask */
+#define XZDMA_WORD3_INTR_SHIFT		(2U)		/**< Interrupt enable
+							  *  disable
+							  *  shift */
+#define XZDMA_WORD3_TYPE_MASK		(0x00000002U)	/**< Type of Descriptor
+							  *  mask */
+#define XZDMA_WORD3_TYPE_SHIFT		(1U)		/**< Type of Descriptor
+							  *  Shift */
+#define XZDMA_WORD3_COHRNT_MASK		(0x00000001U)	/**< Coherence mask */
+/*@}*/
+
+/** @name Channel Source/Destination start address or current payload
+ *  MSB register bit mask
+ * @{
+ */
+#define XZDMA_START_MSB_ADDR_MASK	(0x0001FFFFU)	/**< Start msb address
+							  *  mask */
+/*@}*/
+
+/** @name Channel Rate control count register bit mask
+ * @{
+ */
+#define XZDMA_CH_RATE_CNTL_MASK		(0x00000FFFU) /**< Channel rate control
+							*  mask */
+/*@}*/
+
+/** @name Channel Source/Destination Interrupt account count register bit mask
+ * @{
+ */
+#define XZDMA_CH_IRQ_ACCT_MASK		(0x000000FFU) /**< Interrupt count
+							*  mask */
+/*@}*/
+
+/** @name Channel debug register 0/1 bit mask
+ * @{
+ */
+#define XZDMA_CH_DBG_CMN_BUF_MASK	(0x000001FFU) /**< Common buffer count
+							* mask */
+/*@}*/
+
+/** @name Channel control2 register bit mask
+ * @{
+ */
+#define XZDMA_CH_CTRL2_EN_MASK		(0x00000001U) /**< Channel enable
+							*  mask */
+#define XZDMA_CH_CTRL2_DIS_MASK		(0x00000000U) /**< Channel disable
+							*  mask */
+/*@}*/
+
+/** @name Channel control2 register bit mask
+ * @{
+ */
+ #define XZDMA_WRITE_TO_CLEAR_MASK	(0x00000000U) /**< Write to clear
+							*  mask */
+ /*@}*/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XZDma_In32		Xil_In32	/**< Input operation */
+#define XZDma_Out32		Xil_Out32	/**< Output operation */
+
+/*****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the Xilinx base address of the ZDMA core.
+* @param	RegOffset is the register offset of the register.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XZDma_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XZDma_ReadReg(BaseAddress, RegOffset) \
+		XZDma_In32((BaseAddress) + (u32)(RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* This macro writes the value into the given register.
+*
+* @param	BaseAddress is the Xilinx base address of the ZDMA core.
+* @param	RegOffset is the register offset of the register.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XZDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XZDma_WriteReg(BaseAddress, RegOffset, Data) \
+		XZDma_Out32(((BaseAddress) + (u32)(RegOffset)), (u32)(Data))
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif /* XZDMA_HW_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_intr.c
new file mode 100644
index 000000000..3543ad74f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_intr.c
@@ -0,0 +1,202 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_intr.c
+*
+* This file contains interrupt related functions of Xilinx ZDMA core.
+* Please see xzdma.h for more details of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the ZDMA core.
+*
+* This handler reads the pending interrupt from Status register, determines the
+* source of the interrupts and calls the respective callbacks for the
+* interrupts that are enabled in IRQ_ENABLE register, and finally clears the
+* interrupts.
+*
+* The application is responsible for connecting this function to the interrupt
+* system. Application beyond this driver is also responsible for providing
+* callbacks to handle interrupts and installing the callbacks using
+* XZDma_SetCallBack() during initialization phase. .
+*
+* @param	Instance is a pointer to the XZDma instance to be worked on.
+*
+* @return	None.
+*
+* @note		To generate interrupt required interrupts should be enabled.
+*
+******************************************************************************/
+void XZDma_IntrHandler(void *Instance)
+{
+	u32 PendingIntr;
+	u32 ErrorStatus;
+	XZDma *InstancePtr = NULL;
+	InstancePtr = (XZDma *)((void *)Instance);
+
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Get pending interrupts */
+	PendingIntr = (u32)(XZDma_IntrGetStatus(InstancePtr));
+	PendingIntr &= (~XZDma_GetIntrMask(InstancePtr));
+
+	/* ZDMA transfer has completed */
+	ErrorStatus = (PendingIntr) & (XZDMA_IXR_DMA_DONE_MASK);
+	if ((ErrorStatus) != 0U) {
+		XZDma_DisableIntr(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
+		InstancePtr->ChannelState = XZDMA_IDLE;
+		InstancePtr->DoneHandler(InstancePtr->DoneRef);
+	}
+
+	/* An error has been occurred */
+	ErrorStatus = PendingIntr & (XZDMA_IXR_ERR_MASK);
+	if ((ErrorStatus) != 0U) {
+		if ((ErrorStatus & XZDMA_IXR_DMA_PAUSE_MASK) ==
+				XZDMA_IXR_DMA_PAUSE_MASK) {
+			InstancePtr->ChannelState = XZDMA_PAUSE;
+		}
+		else {
+			if ((ErrorStatus & (XZDMA_IXR_AXI_WR_DATA_MASK |
+				XZDMA_IXR_AXI_RD_DATA_MASK |
+				XZDMA_IXR_AXI_RD_DST_DSCR_MASK |
+				XZDMA_IXR_AXI_RD_SRC_DSCR_MASK)) != 0x00U) {
+				InstancePtr->ChannelState = XZDMA_IDLE;
+			}
+		}
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, ErrorStatus);
+	}
+
+	/* Clear pending interrupt(s) */
+	XZDma_IntrClear(InstancePtr, PendingIntr);
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine installs an asynchronous callback function for the given
+* HandlerType.
+*
+* 
+* HandlerType              Callback Function Type
+* -----------------------  --------------------------------------------------
+* XZDMA_HANDLER_DONE	   Done handler
+* XZDMA_HANDLER_ERROR	   Error handler
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XZDma instance to be worked on.
+* @param	HandlerType specifies which callback is to be attached.
+* @param	CallBackFunc is the address of the callback function.
+* @param	CallBackRef is a user data item that will be passed to the
+* 		callback function when it is invoked.
+*
+* @return
+*		- XST_SUCCESS when handler is installed.
+*		- XST_INVALID_PARAM when HandlerType is invalid.
+*
+* @note		Invoking this function for a handler that already has been
+*		installed replaces it with the new handler.
+*
+******************************************************************************/
+s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
+	void *CallBackFunc, void *CallBackRef)
+{
+	s32 Status;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CallBackFunc != NULL);
+	Xil_AssertNonvoid(CallBackRef != NULL);
+	Xil_AssertNonvoid((HandlerType == XZDMA_HANDLER_DONE) ||
+				(HandlerType == XZDMA_HANDLER_ERROR));
+	Xil_AssertNonvoid(InstancePtr->IsReady ==
+				(u32)(XIL_COMPONENT_IS_READY));
+
+	/*
+	 * Calls the respective callback function corresponding to
+	 * the handler type
+	 */
+	switch (HandlerType) {
+		case XZDMA_HANDLER_DONE:
+			InstancePtr->DoneHandler =
+				(XZDma_DoneHandler)((void *)CallBackFunc);
+			InstancePtr->DoneRef = CallBackRef;
+			Status = (XST_SUCCESS);
+			break;
+
+		case XZDMA_HANDLER_ERROR:
+			InstancePtr->ErrorHandler =
+				(XZDma_ErrorHandler)((void *)CallBackFunc);
+			InstancePtr->ErrorRef = CallBackRef;
+			Status = (XST_SUCCESS);
+			break;
+
+		default:
+			Status = (XST_INVALID_PARAM);
+			break;
+	}
+
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_selftest.c
new file mode 100644
index 000000000..7c2957e19
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_selftest.c
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_selftest.c
+*
+* This file contains the self-test function for the ZDMA core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This file contains a diagnostic self-test function for the ZDMA driver.
+* Refer to the header file xzdma.h for more detailed information.
+*
+* @param	InstancePtr is a pointer to XZDma instance.
+*
+* @return
+*		- XST_SUCCESS if the test is successful.
+*		- XST_FAILURE if the test is failed.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XZDma_SelfTest(XZDma *InstancePtr)
+{
+
+	u32 Data;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_CTRL0_OFFSET);
+
+	/* Changing DMA channel to over fetch */
+
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
+			(Data | XZDMA_CTRL0_OVR_FETCH_MASK));
+
+	if (((u32)XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_CTRL0_OFFSET) & XZDMA_CTRL0_OVR_FETCH_MASK) !=
+						XZDMA_CTRL0_OVR_FETCH_MASK) {
+		Status = (s32)XST_FAILURE;
+	}
+	else {
+		Status = (s32)XST_SUCCESS;
+	}
+
+	/* Retrieving the change settings */
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
+				Data);
+
+	return Status;
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_sinit.c
new file mode 100644
index 000000000..fa71fe6e1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_sinit.c
+*
+* This file contains static initialization methods for Xilinx ZDMA core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* XZDma_LookupConfig returns a reference to an XZDma_Config structure
+* based on the unique device id, DeviceId. The return value will refer
+* to an entry in the device configuration table defined in the xzdma_g.c
+* file.
+*
+* @param	DeviceId is the unique device ID of the device for the lookup
+*		operation.
+*
+* @return	CfgPtr is a reference to a config record in the configuration
+*		table (in xzdma_g.c) corresponding to DeviceId, or
+*		NULL if no match is found.
+*
+* @note		None.
+******************************************************************************/
+XZDma_Config *XZDma_LookupConfig(u16 DeviceId)
+{
+	extern XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES];
+	XZDma_Config *CfgPtr = NULL;
+	u32 Index;
+
+	/* Checks all the instances */
+	for (Index = (u32)0x0; Index < (u32)(XPAR_XZDMA_NUM_INSTANCES);
+								Index++) {
+		if (XZDma_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XZDma_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XZDma_Config *)CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss
new file mode 100644
index 000000000..a8eb8bb54
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss
@@ -0,0 +1,736 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 5.0
+ PARAMETER PROC_INSTANCE = psu_cortexa53_0
+ PARAMETER stdin = psu_uart_0
+ PARAMETER stdout = psu_uart_0
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_cortexa53
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_cortexa53_0
+ PARAMETER extra_compiler_flags = -g -O0
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_acpu_gic
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_adma_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_adma_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_adma_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_adma_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_adma_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_adma_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_adma_6
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_adma_7
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_6
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ams
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.2
+ PARAMETER HW_INSTANCE = psu_apm_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.2
+ PARAMETER HW_INSTANCE = psu_apm_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.2
+ PARAMETER HW_INSTANCE = psu_apm_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.2
+ PARAMETER HW_INSTANCE = psu_apm_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_apu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_bbram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = canps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_can_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = canps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_can_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_cci_gpv
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_cci_reg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_coresight_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_crf_apb
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_crl_apb
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = csudma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_csudma
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_phy
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_qos_ctrl
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu0_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu1_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu2_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu3_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu4_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu5_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddrc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_dp
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_dpdma
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_efuse
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_ethernet_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_ethernet_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_ethernet_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_ethernet_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_gpv
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_slcr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_slcr_secure
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_xmpu_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_xmpu_sink
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_gdma_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_gdma_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_gdma_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_gdma_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_gdma_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_gdma_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_gdma_6
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_gdma_7
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpiops
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_gpu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_i2c_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_i2c_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iou_s
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iou_scntr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iou_scntrs
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iousecure_slcr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iouslcr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ipipsu
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_ipi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ipipsu
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_ipi_7
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_lpd_slcr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_lpd_slcr_secure
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_lpd_xppu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_lpd_xppu_sink
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_mbistjtag
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = nandpsu
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_nand_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ocm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ocm_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ocm_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ocm_xmpu_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pcie
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pcie_attrib_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pcie_dma
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pmu_global_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pmu_iomodule
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pmu_ram
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = qspipsu
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_qspi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_qspi_linear_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_atcm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_atcm_lockstep
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_btcm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_btcm_lockstep
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_1_atcm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_1_btcm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_ddr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_rcpu_gic
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_rpu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_rsa
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_rtc
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_sata
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sdps
+ PARAMETER DRIVER_VER = 2.4
+ PARAMETER HW_INSTANCE = psu_sd_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sdps
+ PARAMETER DRIVER_VER = 2.4
+ PARAMETER HW_INSTANCE = psu_sd_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_serdes
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_siou
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_smmu_gpv
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_smmu_reg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = spips
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_spi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = spips
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_spi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_ttc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_ttc_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_ttc_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_ttc_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_uart_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_uart_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = usbpsu
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_usb_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = wdtps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_wdt_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = wdtps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_wdt_1
+END
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/.project b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/.project
new file mode 100644
index 000000000..7c49632ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/.project
@@ -0,0 +1,41 @@
+
+
+	ZynqMP_hw_platform
+	Created by SDK v2015.1
+	
+	
+	
+	
+	
+		com.xilinx.sdk.hw.HwProject
+	
+	
+		
+			1436883660925
+			
+			6
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-*.xml
+			
+		
+		
+			1436883660925
+			
+			6
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-*.svd
+			
+		
+		
+			1436883660925
+			
+			6
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-*.hwh
+			
+		
+	
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/design_1.hwh b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/design_1.hwh
new file mode 100644
index 000000000..e6a7bb31f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/design_1.hwh
@@ -0,0 +1,3511 @@
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+    
+  
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/design_1_bd.tcl b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/design_1_bd.tcl
new file mode 100644
index 000000000..973aa6a48
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/design_1_bd.tcl
@@ -0,0 +1,180 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2015.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If you do not already have a project created,
+# you can create a project using the following command:
+#    create_project project_1 myproj -part xc7vx485tffg1761-2
+#    set_property BOARD_PART xilinx.com:vc707:part0:1.2 [current_project]
+
+# CHECKING IF PROJECT EXISTS
+if { [get_projects -quiet] eq "" } {
+   puts "ERROR: Please open or create a project!"
+   return 1
+}
+
+
+
+# CHANGE DESIGN NAME HERE
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "ERROR: Please set the variable  to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      puts "INFO: Changing value of  from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   puts "INFO: Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable  to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable  to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   puts "INFO: Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+puts "INFO: Currently the variable  is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   puts $errMsg
+   return $nRet
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     puts "ERROR: Unable to find parent cell <$parentCell>!"
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set MAXIGP0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 MAXIGP0 ]
+  set_property -dict [ list CONFIG.ADDR_WIDTH {40} CONFIG.DATA_WIDTH {128} CONFIG.NUM_READ_OUTSTANDING {8} CONFIG.NUM_WRITE_OUTSTANDING {8} CONFIG.PROTOCOL {AXI4}  ] $MAXIGP0
+
+  # Create ports
+  set maxigp0_aclk [ create_bd_port -dir I -type clk maxigp0_aclk ]
+
+  # Create instance: processing_system8_0, and set properties
+  set processing_system8_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system8:1.0 processing_system8_0 ]
+  set_property -dict [ list CONFIG.preset {Remus}  ] $processing_system8_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net processing_system8_0_MAXIGP0 [get_bd_intf_ports MAXIGP0] [get_bd_intf_pins processing_system8_0/MAXIGP0]
+
+  # Create port connections
+  connect_bd_net -net maxigp0_aclk_1 [get_bd_ports maxigp0_aclk] [get_bd_pins processing_system8_0/config_loop_in] [get_bd_pins processing_system8_0/dp_s_axis_audio_clk] [get_bd_pins processing_system8_0/maxigp0_aclk] [get_bd_pins processing_system8_0/maxigp1_aclk] [get_bd_pins processing_system8_0/ref_clk_in_n] [get_bd_pins processing_system8_0/ref_clk_in_p] [get_bd_pins processing_system8_0/rx_clk_iou17_user_13_n] [get_bd_pins processing_system8_0/rx_clk_iou17_user_13_p] [get_bd_pins processing_system8_0/sacefpd_aclk] [get_bd_pins processing_system8_0/saxiacp_aclk] [get_bd_pins processing_system8_0/saxigp0_rclk] [get_bd_pins processing_system8_0/saxigp0_wclk] [get_bd_pins processing_system8_0/saxigp1_rclk] [get_bd_pins processing_system8_0/saxigp1_wclk] [get_bd_pins processing_system8_0/saxigp2_rclk] [get_bd_pins processing_system8_0/saxigp2_wclk] [get_bd_pins processing_system8_0/saxigp3_rclk] [get_bd_pins processing_system8_0/saxigp3_wclk] [get_bd_pins processing_system8_0/saxigp4_rclk] [get_bd_pins processing_system8_0/saxigp4_wclk] [get_bd_pins processing_system8_0/saxigp5_rclk] [get_bd_pins processing_system8_0/saxigp5_wclk] [get_bd_pins processing_system8_0/saxigp6_rclk] [get_bd_pins processing_system8_0/saxigp6_wclk] [get_bd_pins processing_system8_0/serdes_clk_in_n] [get_bd_pins processing_system8_0/serdes_clk_in_p] [get_bd_pins processing_system8_0/sys_1x_clk_in_n] [get_bd_pins processing_system8_0/sys_1x_clk_in_p] [get_bd_pins processing_system8_0/sys_2x_clk_in_n] [get_bd_pins processing_system8_0/sys_2x_clk_in_p]
+
+  # Create address segments
+  
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/hwdef.xml b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/hwdef.xml
new file mode 100644
index 000000000..bee036280
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/hwdef.xml
@@ -0,0 +1,11 @@
+
+
+	
+	
+	
+	
+	
+	
+	
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.c
new file mode 100644
index 000000000..267d1aee7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.c
@@ -0,0 +1,6352 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file psu_init.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include 
+#include "psu_init.h"
+
+static unsigned int RegMask = 0x0;
+
+static unsigned int RegVal = 0x0;
+
+unsigned long psu_pll_init_data() {
+		// : RPLL INIT
+		// : UPDATE FB_DIV
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRL_APB_RPLL_CTRL_FBDIV                                                     0x30
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRL_APB_RPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00017F00U ,0x00013000U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000030U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Asserts Reset to the PLL
+		PSU_CRL_APB_RPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Asserts Reset to the PLL
+		PSU_CRL_APB_RPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFF5E0040

+
+		RPLL is locked
+		PSU_CRL_APB_PLL_STATUS_RPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000002U ,0x00000002U)  */
+		while(!(Xil_In32 ( CRL_APB_PLL_STATUS_OFFSET) & 0x00000002U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

+
+		Divisor value for this clock.
+		PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFF5E0048, 0x00003F00U ,0x00000300U)  */
+		RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_TO_FPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : RPLL FRAC CFG
+		// : IOPLL INIT
+		// : UPDATE FB_DIV
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRL_APB_IOPLL_CTRL_FBDIV                                                    0x3c
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRL_APB_IOPLL_CTRL_DIV2                                                     0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00017F00U ,0x00013C00U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000003CU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Asserts Reset to the PLL
+		PSU_CRL_APB_IOPLL_CTRL_RESET                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Asserts Reset to the PLL
+		PSU_CRL_APB_IOPLL_CTRL_RESET                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFF5E0040

+
+		IOPLL is locked
+		PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK                                               1
+		(OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000001U ,0x00000001U)  */
+		while(!(Xil_In32 ( CRL_APB_PLL_STATUS_OFFSET) & 0x00000001U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044

+
+		Divisor value for this clock.
+		PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0                                          0x4
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFF5E0044, 0x00003F00U ,0x00000400U)  */
+		RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000004U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : IOPLL FRAC CFG
+		// : APU_PLL INIT
+		// : UPDATE FB_DIV
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_APLL_CTRL_FBDIV                                                     0x3c
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_APLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00017F00U ,0x00013C00U)  */
+		RegMask = (CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000003CU << CRF_APB_APLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_APLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_APLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_APLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044

+
+		APLL is locked
+		PSU_CRF_APB_PLL_STATUS_APLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000001U ,0x00000001U)  */
+		while(!(Xil_In32 ( CRF_APB_PLL_STATUS_OFFSET) & 0x00000001U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_APLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048

+
+		Divisor value for this clock.
+		PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0                                           0x4
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A0048, 0x00003F00U ,0x00000400U)  */
+		RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_TO_LPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000004U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_TO_LPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : APLL FRAC CFG
+		// : DDR_PLL INIT
+		// : UPDATE FB_DIV
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_DPLL_CTRL_FBDIV                                                     0x3c
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_DPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00017F00U ,0x00013C00U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000003CU << CRF_APB_DPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_DPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_DPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044

+
+		DPLL is locked
+		PSU_CRF_APB_PLL_STATUS_DPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000002U ,0x00000002U)  */
+		while(!(Xil_In32 ( CRF_APB_PLL_STATUS_OFFSET) & 0x00000002U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

+
+		Divisor value for this clock.
+		PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0                                           0x4
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A004C, 0x00003F00U ,0x00000400U)  */
+		RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000004U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_TO_LPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DPLL FRAC CFG
+		// : VIDEO_PLL INIT
+		// : UPDATE FB_DIV
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_VPLL_CTRL_FBDIV                                                     0x3f
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_VPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00017F00U ,0x00013F00U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000003FU << CRF_APB_VPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_VPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_VPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044

+
+		VPLL is locked
+		PSU_CRF_APB_PLL_STATUS_VPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000004U ,0x00000004U)  */
+		while(!(Xil_In32 ( CRF_APB_PLL_STATUS_OFFSET) & 0x00000004U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050

+
+		Divisor value for this clock.
+		PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0                                           0x4
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A0050, 0x00003F00U ,0x00000400U)  */
+		RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000004U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_TO_LPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : VIDEO FRAC CFG
+
+}
+unsigned long psu_clock_init_data() {
+		// : CLOCK CONTROL SLCR REGISTER
+		/*Register : GEM0_REF_CTRL @ 0XFF5E0050

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0050, 0x063F3F07U ,0x06022800U)  */
+		RegMask = (CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_GEM0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_GEM0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GEM1_REF_CTRL @ 0XFF5E0054

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0054, 0x063F3F07U ,0x06022800U)  */
+		RegMask = (CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_GEM1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_GEM1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GEM2_REF_CTRL @ 0XFF5E0058

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM2_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0058, 0x063F3F07U ,0x06022800U)  */
+		RegMask = (CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_GEM2_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_GEM2_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GEM3_REF_CTRL @ 0XFF5E005C

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM3_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E005C, 0x063F3F07U ,0x06022800U)  */
+		RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_GEM3_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_GEM3_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT                                            0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0                                          0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL                                            0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0060, 0x023F3F07U ,0x02013200U)  */
+		RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_USB0_BUS_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_USB0_BUS_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT                                           0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1                                         0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0                                         0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL                                           0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E004C, 0x023F3F07U ,0x02010800U)  */
+		RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000008U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_USB3_DUAL_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : QSPI_REF_CTRL @ 0XFF5E0068

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_QSPI_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01023200U)  */
+		RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_QSPI_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_QSPI_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SDIO0_REF_CTRL @ 0XFF5E006C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0                                             0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E006C, 0x013F3F07U ,0x01023200U)  */
+		RegMask = (CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_SDIO0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_SDIO0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SDIO1_REF_CTRL @ 0XFF5E0070

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                                             0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01023200U)  */
+		RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_SDIO1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_SDIO1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : UART0_REF_CTRL @ 0XFF5E0074

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_UART0_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0                                             0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_UART0_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0074, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_UART0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_UART0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : UART1_REF_CTRL @ 0XFF5E0078

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_UART1_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0                                             0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_UART1_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0078, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_UART1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_UART1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : I2C0_REF_CTRL @ 0XFF5E0120

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_I2C0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0120, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_I2C0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_I2C0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : I2C1_REF_CTRL @ 0XFF5E0124

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_I2C1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1                                              0xa
+
+		6 bit divider
+		PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0                                              0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0124, 0x013F3F07U ,0x010A3200U)  */
+		RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_I2C1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
+			| 0x0000000AU << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_I2C1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SPI0_REF_CTRL @ 0XFF5E007C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SPI0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E007C, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_SPI0_REF_CTRL_CLKACT_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_SPI0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_SPI0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SPI1_REF_CTRL @ 0XFF5E0080

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SPI1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1                                              0xa
+
+		6 bit divider
+		PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0                                              0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0080, 0x013F3F07U ,0x010A3200U)  */
+		RegMask = (CRL_APB_SPI1_REF_CTRL_CLKACT_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_SPI1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
+			| 0x0000000AU << CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_SPI1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : CAN0_REF_CTRL @ 0XFF5E0084

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CAN0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0084, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_CAN0_REF_CTRL_CLKACT_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_CAN0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_CAN0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : CAN1_REF_CTRL @ 0XFF5E0088

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CAN1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0088, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_CAN1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_CAN1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : CPU_R5_CTRL @ 0XFF5E0090

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CPU_R5_CTRL_CLKACT                                                  0x1
+
+		6 bit divider
+		PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0                                                0x1f4
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CPU_R5_CTRL_SRCSEL                                                  0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0090, 0x01003F07U ,0x01003F02U)  */
+		RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_CPU_R5_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
+			| 0x000001F4U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_CPU_R5_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : IOU_SWITCH_CTRL @ 0XFF5E009C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0                                            0x6
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL                                              0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E009C, 0x01003F07U ,0x01000600U)  */
+		RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOU_SWITCH_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
+			| 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOU_SWITCH_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : PCAP_CTRL @ 0XFF5E00A4

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PCAP_CTRL_CLKACT                                                    0x1
+
+		6 bit divider
+		PSU_CRL_APB_PCAP_CTRL_DIVISOR0                                                  0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PCAP_CTRL_SRCSEL                                                    0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000800U)  */
+		RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_PCAP_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT
+			| 0x00000008U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_PCAP_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0                                            0x4
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A8, 0x01003F07U ,0x01000402U)  */
+		RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_LPD_SWITCH_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
+			| 0x00000004U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_LPD_SWITCH_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0                                             0x14
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00AC, 0x01003F07U ,0x01001402U)  */
+		RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_LPD_LSBUS_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
+			| 0x00000014U << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_LPD_LSBUS_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DBG_LPD_CTRL @ 0XFF5E00B0

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_DBG_LPD_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0                                               0x190
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL                                                 0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B0, 0x01003F07U ,0x01003F00U)  */
+		RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_DBG_LPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
+			| 0x00000190U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_DBG_LPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : NAND_REF_CTRL @ 0XFF5E00B4

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_NAND_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0                                              0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_NAND_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B4, 0x013F3F07U ,0x01023200U)  */
+		RegMask = (CRL_APB_NAND_REF_CTRL_CLKACT_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK | CRL_APB_NAND_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_NAND_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_NAND_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : ADMA_REF_CTRL @ 0XFF5E00B8

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_ADMA_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0                                              0x4
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL                                                0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B8, 0x01003F07U ,0x01000402U)  */
+		RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_ADMA_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
+			| 0x00000004U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_ADMA_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : AMS_REF_CTRL @ 0XFF5E0108

+
+		6 bit divider
+		PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0                                               0x28
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_AMS_REF_CTRL_SRCSEL                                                 0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_AMS_REF_CTRL_CLKACT                                                 0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0108, 0x013F3F07U ,0x01012800U)  */
+		RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_AMS_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_AMS_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DLL_REF_CTRL @ 0XFF5E0104

+
+		000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
+		is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_DLL_REF_CTRL_SRCSEL                                                 0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0104, 0x00000007U ,0x00000000U)  */
+		RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_DLL_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_DLL_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128

+
+		6 bit divider
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                                         0x14
+
+		1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 
+		 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                                           0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                                           0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01001402U)  */
+		RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000014U << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_TIMESTAMP_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : PCIE_REF_CTRL @ 0XFD1A00B4

+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL                                                0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_PCIE_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0                                              0x7d
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00B4, 0x01003F07U ,0x01003F00U)  */
+		RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_PCIE_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
+			| 0x0000007DU << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_PCIE_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070

+
+		6 bit divider
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                                          0x15
+
+		6 bit divider
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                                          0x32
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
+		k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                                            0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                                            0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01153200U)  */
+		RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000015U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DP_VIDEO_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

+
+		6 bit divider
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                                          0x2
+
+		6 bit divider
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                                          0x2a
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
+		k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                                            0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                                            0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01022A00U)  */
+		RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000002U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000002AU << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DP_AUDIO_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DP_STC_REF_CTRL @ 0XFD1A007C

+
+		6 bit divider
+		PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                                            0x2
+
+		6 bit divider
+		PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                                            0x2a
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL                                              0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                                              0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01022A00U)  */
+		RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DP_STC_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000002U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000002AU << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DP_STC_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : ACPU_CTRL @ 0XFD1A0060

+
+		6 bit divider
+		PSU_CRF_APB_ACPU_CTRL_DIVISOR0                                                  0xfa
+
+		000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_ACPU_CTRL_SRCSEL                                                    0x0
+
+		Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
+		PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF                                               0x1
+
+		Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
+		 to the entire APU
+		PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0060, 0x03003F07U ,0x03003F00U)  */
+		RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_ACPU_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x000000FAU << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
+			| 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_ACPU_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DBG_TRACE_CTRL @ 0XFD1A0064

+
+		6 bit divider
+		PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0                                             0x1f4
+
+		000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL                                               0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0064, 0x01003F07U ,0x01003F02U)  */
+		RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DBG_TRACE_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x000001F4U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DBG_TRACE_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DBG_FPD_CTRL @ 0XFD1A0068

+
+		6 bit divider
+		PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0                                               0x1f4
+
+		000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL                                                 0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DBG_FPD_CTRL_CLKACT                                                 0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0068, 0x01003F07U ,0x01003F02U)  */
+		RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DBG_FPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x000001F4U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DBG_FPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DDR_CTRL @ 0XFD1A0080

+
+		6 bit divider
+		PSU_CRF_APB_DDR_CTRL_DIVISOR0                                                   0xa
+
+		000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 
+		s not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DDR_CTRL_SRCSEL                                                     0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0080, 0x00003F07U ,0x00000A00U)  */
+		RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DDR_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000000AU << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DDR_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GPU_REF_CTRL @ 0XFD1A0084

+
+		6 bit divider
+		PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0                                               0x20d
+
+		000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GPU_REF_CTRL_SRCSEL                                                 0x2
+
+		Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below
+		PSU_CRF_APB_GPU_REF_CTRL_CLKACT                                                 0x1
+
+		Clock active signal for Pixel Processor. Switch to 0 to disable the clock
+		PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT                                             0x1
+
+		Clock active signal for Pixel Processor. Switch to 0 to disable the clock
+		PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0084, 0x07003F07U ,0x07003F02U)  */
+		RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_GPU_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000020DU << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_GPU_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GDMA_REF_CTRL @ 0XFD1A00B8

+
+		6 bit divider
+		PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0                                              0x3
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL                                                0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_GDMA_REF_CTRL_CLKACT                                                0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00B8, 0x01003F07U ,0x01000303U)  */
+		RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_GDMA_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000003U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_GDMA_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DPDMA_REF_CTRL @ 0XFD1A00BC

+
+		6 bit divider
+		PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0                                             0x3
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL                                               0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00BC, 0x01003F07U ,0x01000303U)  */
+		RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPDMA_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000003U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPDMA_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0

+
+		6 bit divider
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0                                            0x3
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                                              0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                                              0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000303U)  */
+		RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_TOPSW_MAIN_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000003U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_TOPSW_MAIN_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

+
+		6 bit divider
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0                                           0x14
+
+		000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL                                             0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C4, 0x01003F07U ,0x01001400U)  */
+		RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000014U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_TOPSW_LSBUS_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GTGREF0_REF_CTRL @ 0XFD1A00C8

+
+		6 bit divider
+		PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0                                           0x11
+
+		000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL                                             0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C8, 0x01003F07U ,0x01001102U)  */
+		RegMask = (CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK | CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK | CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_GTGREF0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000011U << CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_GTGREF0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8

+
+		6 bit divider
+		PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0                                             0x8
+
+		000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00F8, 0x00003F07U ,0x00000802U)  */
+		RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DBG_TSTMP_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000008U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DBG_TSTMP_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+
+}
+unsigned long psu_ddr_init_data_3_0() {
+
+}
+unsigned long psu_mio_init_data() {
+		// : MIO PROGRAMMING
+		/*Register : MIO_PIN_0 @ 0XFF180000

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_0_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_0_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[0]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_0_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_0_L3_SEL                                                   0
+
+		Configures MIO Pin 0 peripheral interface mapping. S
+		(OFFSET, MASK, VALUE)      (0XFF180000, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_1 @ 0XFF180004

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
+		us)
+		PSU_IOU_SLCR_MIO_PIN_1_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_1_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[1]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_1_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)
+		PSU_IOU_SLCR_MIO_PIN_1_L3_SEL                                                   0
+
+		Configures MIO Pin 1 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180004, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_1_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_1_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_2 @ 0XFF180008

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
+		PSU_IOU_SLCR_MIO_PIN_2_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_2_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[2]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_2_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_2_L3_SEL                                                   0
+
+		Configures MIO Pin 2 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180008, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_3 @ 0XFF18000C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
+		PSU_IOU_SLCR_MIO_PIN_3_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_3_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[3]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_3_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_3_L3_SEL                                                   0
+
+		Configures MIO Pin 3 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18000C, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_3_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_3_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_4 @ 0XFF180010

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
+		us)
+		PSU_IOU_SLCR_MIO_PIN_4_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_4_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[4]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_4_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_4_L3_SEL                                                   0
+
+		Configures MIO Pin 4 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180010, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_4_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_4_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_5 @ 0XFF180014

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
+		PSU_IOU_SLCR_MIO_PIN_5_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_5_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[5]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_5_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_5_L3_SEL                                                   0
+
+		Configures MIO Pin 5 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180014, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_5_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_5_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_6 @ 0XFF180018

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
+		PSU_IOU_SLCR_MIO_PIN_6_L0_SEL                                                   0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_6_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[6]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_6_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
+		sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
+		Output, tracedq[4]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_6_L3_SEL                                                   0
+
+		Configures MIO Pin 6 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180018, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_6_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_6_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_7 @ 0XFF18001C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
+		PSU_IOU_SLCR_MIO_PIN_7_L0_SEL                                                   0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_7_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[7]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_7_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 
+		tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 
+		racedq[5]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_7_L3_SEL                                                   0
+
+		Configures MIO Pin 7 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18001C, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_7_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_7_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_8 @ 0XFF180020

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[0]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_8_L0_SEL                                                   0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_8_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[8]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_8_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
+		, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
+		ce Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_8_L3_SEL                                                   0
+
+		Configures MIO Pin 8 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180020, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_8_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_8_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_9 @ 0XFF180024

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[1]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_9_L0_SEL                                                   0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_9_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[9]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_9_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 
+		utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
+		RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_9_L3_SEL                                                   0
+
+		Configures MIO Pin 9 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180024, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_9_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_9_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_10 @ 0XFF180028

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[2]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_10_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_10_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[10]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_10_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_10_L3_SEL                                                  0
+
+		Configures MIO Pin 10 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180028, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_10_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_10_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_11 @ 0XFF18002C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[3]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_11_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_11_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[11]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_11_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_11_L3_SEL                                                  0
+
+		Configures MIO Pin 11 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18002C, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_11_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_11_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_12 @ 0XFF180030

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
+		PSU_IOU_SLCR_MIO_PIN_12_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		
+		PSU_IOU_SLCR_MIO_PIN_12_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[12]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_12_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
+		ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
+		dq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_12_L3_SEL                                                  0
+
+		Configures MIO Pin 12 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180030, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_12_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_12_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_13 @ 0XFF180034

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_13_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_13_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_13_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
+		out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
+		bus)
+		PSU_IOU_SLCR_MIO_PIN_13_L3_SEL                                                  0
+
+		Configures MIO Pin 13 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180034, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_13_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_13_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_14 @ 0XFF180038

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_14_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
+		PSU_IOU_SLCR_MIO_PIN_14_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_14_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
+		n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_14_L3_SEL                                                  0
+
+		Configures MIO Pin 14 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180038, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_14_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_14_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_15 @ 0XFF18003C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_15_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
+		PSU_IOU_SLCR_MIO_PIN_15_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_15_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
+		0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
+		l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_15_L3_SEL                                                  0
+
+		Configures MIO Pin 15 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18003C, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_15_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_15_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_16 @ 0XFF180040

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_16_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_16_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_16_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_16_L3_SEL                                                  0
+
+		Configures MIO Pin 16 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180040, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_16_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_16_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_17 @ 0XFF180044

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_17_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_17_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_17_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_17_L3_SEL                                                  0
+
+		Configures MIO Pin 17 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180044, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_17_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_17_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_18 @ 0XFF180048

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_18_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_18_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_18_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_18_L3_SEL                                                  0
+
+		Configures MIO Pin 18 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180048, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_18_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_18_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_19 @ 0XFF18004C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_19_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_19_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_19_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_19_L3_SEL                                                  0
+
+		Configures MIO Pin 19 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18004C, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_19_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_19_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_20 @ 0XFF180050

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_20_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_20_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_20_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
+		c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_20_L3_SEL                                                  0
+
+		Configures MIO Pin 20 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180050, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_20_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_20_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_21 @ 0XFF180054

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_21_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_21_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 
+		= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_21_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 
+		UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_21_L3_SEL                                                  0
+
+		Configures MIO Pin 21 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180054, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_21_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_21_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_22 @ 0XFF180058

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_22_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
+		PSU_IOU_SLCR_MIO_PIN_22_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
+		(Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_22_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed
+		PSU_IOU_SLCR_MIO_PIN_22_L3_SEL                                                  0
+
+		Configures MIO Pin 22 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180058, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_22_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_22_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_23 @ 0XFF18005C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_23_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_23_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
+		23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
+		
+		PSU_IOU_SLCR_MIO_PIN_23_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_23_L3_SEL                                                  0
+
+		Configures MIO Pin 23 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18005C, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_23_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_23_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_24 @ 0XFF180060

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_24_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_24_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
+		scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
+		 Tamper)
+		PSU_IOU_SLCR_MIO_PIN_24_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
+		Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_24_L3_SEL                                                  0
+
+		Configures MIO Pin 24 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180060, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_24_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_24_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_25 @ 0XFF180064

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_25_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
+		PSU_IOU_SLCR_MIO_PIN_25_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
+		test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
+		U Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_25_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 
+		lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_25_L3_SEL                                                  0
+
+		Configures MIO Pin 25 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180064, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_25_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_25_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_26 @ 0XFF180068

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_26_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_26_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_26_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_26_L3_SEL                                                  0
+
+		Configures MIO Pin 26 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180068, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_26_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_26_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_27 @ 0XFF18006C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_27_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_27_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_27_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)
+		PSU_IOU_SLCR_MIO_PIN_27_L3_SEL                                                  0
+
+		Configures MIO Pin 27 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18006C, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_27_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_27_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_28 @ 0XFF180070

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_28_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_28_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_28_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_28_L3_SEL                                                  0
+
+		Configures MIO Pin 28 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180070, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_28_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_28_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_29 @ 0XFF180074

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_29_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_29_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_29_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_29_L3_SEL                                                  4
+
+		Configures MIO Pin 29 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180074, 0x000000FEU ,0x00000080U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_29_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
+			| 0x00000004U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_29_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_30 @ 0XFF180078

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_30_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_30_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_30_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
+		 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
+		 tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_30_L3_SEL                                                  0
+
+		Configures MIO Pin 30 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180078, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_30_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_30_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_31 @ 0XFF18007C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_31_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_31_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_31_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
+		_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
+		ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_31_L3_SEL                                                  0
+
+		Configures MIO Pin 31 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18007C, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_31_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_31_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_32 @ 0XFF180080

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_32_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		
+		PSU_IOU_SLCR_MIO_PIN_32_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_32_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
+		_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 
+		race, Output, tracedq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_32_L3_SEL                                                  0
+
+		Configures MIO Pin 32 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180080, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_32_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_32_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_33 @ 0XFF180084

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_33_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_33_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_33_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
+		c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
+		[11]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_33_L3_SEL                                                  0
+
+		Configures MIO Pin 33 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180084, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_33_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_33_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_34 @ 0XFF180088

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_34_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_34_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_34_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
+		 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
+		rt Databus)
+		PSU_IOU_SLCR_MIO_PIN_34_L3_SEL                                                  0
+
+		Configures MIO Pin 34 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180088, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_34_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_34_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_35 @ 0XFF18008C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_35_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_35_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_35_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
+		Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 
+		UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_35_L3_SEL                                                  4
+
+		Configures MIO Pin 35 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18008C, 0x000000FEU ,0x00000080U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_35_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
+			| 0x00000004U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_35_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_36 @ 0XFF180090

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_36_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_36_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_36_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_36_L3_SEL                                                  0
+
+		Configures MIO Pin 36 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180090, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_36_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_36_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_37 @ 0XFF180094

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_37_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_37_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_37_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_37_L3_SEL                                                  0
+
+		Configures MIO Pin 37 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180094, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_37_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_37_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_38 @ 0XFF180098

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_38_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_38_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_38_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
+		k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
+		(Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_38_L3_SEL                                                  0
+
+		Configures MIO Pin 38 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180098, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_38_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_38_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_39 @ 0XFF18009C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_39_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_39_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
+		[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_39_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
+		_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
+		Control Signal)
+		PSU_IOU_SLCR_MIO_PIN_39_L3_SEL                                                  0
+
+		Configures MIO Pin 39 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18009C, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_39_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_39_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_40 @ 0XFF1800A0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_40_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_40_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_40_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
+		in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_40_L3_SEL                                                  0
+
+		Configures MIO Pin 40 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A0, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_40_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_40_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_41 @ 0XFF1800A4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_41_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_41_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_41_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
+		]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
+		ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_41_L3_SEL                                                  0
+
+		Configures MIO Pin 41 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A4, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_41_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_41_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_42 @ 0XFF1800A8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_42_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_42_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_42_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_42_L3_SEL                                                  0
+
+		Configures MIO Pin 42 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A8, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_42_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_42_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_43 @ 0XFF1800AC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_43_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_43_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_43_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
+		i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_43_L3_SEL                                                  0
+
+		Configures MIO Pin 43 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800AC, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_43_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_43_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_44 @ 0XFF1800B0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_44_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
+		i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L3_SEL                                                  0
+
+		Configures MIO Pin 44 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B0, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_44_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_44_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_45 @ 0XFF1800B4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_45_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L3_SEL                                                  0
+
+		Configures MIO Pin 45 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B4, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_45_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_45_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_46 @ 0XFF1800B8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_46_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
+		0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L3_SEL                                                  0
+
+		Configures MIO Pin 46 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B8, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_46_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_46_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_47 @ 0XFF1800BC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_47_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L3_SEL                                                  0
+
+		Configures MIO Pin 47 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800BC, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_47_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_47_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_48 @ 0XFF1800C0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_48_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_48_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_48_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
+		ed
+		PSU_IOU_SLCR_MIO_PIN_48_L3_SEL                                                  0
+
+		Configures MIO Pin 48 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C0, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_48_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_48_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_49 @ 0XFF1800C4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_49_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
+		bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L3_SEL                                                  0
+
+		Configures MIO Pin 49 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C4, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_49_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_49_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_50 @ 0XFF1800C8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		PSU_IOU_SLCR_MIO_PIN_50_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
+		d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
+		clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L3_SEL                                                  0
+
+		Configures MIO Pin 50 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C8, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_50_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_50_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_51 @ 0XFF1800CC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		PSU_IOU_SLCR_MIO_PIN_51_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
+		t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
+		serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L3_SEL                                                  0
+
+		Configures MIO Pin 51 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800CC, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_51_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_51_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_52 @ 0XFF1800D0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_52_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L3_SEL                                                  0
+
+		Configures MIO Pin 52 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D0, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_52_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_52_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_53 @ 0XFF1800D4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_53_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
+		PSU_IOU_SLCR_MIO_PIN_53_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_53_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)
+		PSU_IOU_SLCR_MIO_PIN_53_L3_SEL                                                  0
+
+		Configures MIO Pin 53 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D4, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_53_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_53_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_54 @ 0XFF1800D8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_54_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[2]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_54_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_54_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_54_L3_SEL                                                  0
+
+		Configures MIO Pin 54 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D8, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_54_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_54_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_55 @ 0XFF1800DC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_55_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
+		PSU_IOU_SLCR_MIO_PIN_55_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_55_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_55_L3_SEL                                                  0
+
+		Configures MIO Pin 55 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800DC, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_55_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_55_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_56 @ 0XFF1800E0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_56_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[0]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_56_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_56_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_56_L3_SEL                                                  0
+
+		Configures MIO Pin 56 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E0, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_56_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_56_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_57 @ 0XFF1800E4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_57_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[1]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_57_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_57_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_57_L3_SEL                                                  0
+
+		Configures MIO Pin 57 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E4, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_57_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_57_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_58 @ 0XFF1800E8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_58_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
+		PSU_IOU_SLCR_MIO_PIN_58_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_58_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_58_L3_SEL                                                  0
+
+		Configures MIO Pin 58 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E8, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_58_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_58_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_59 @ 0XFF1800EC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_59_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[3]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_59_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_59_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)
+		PSU_IOU_SLCR_MIO_PIN_59_L3_SEL                                                  0
+
+		Configures MIO Pin 59 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800EC, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_59_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_59_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_60 @ 0XFF1800F0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_60_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[4]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_60_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_60_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_60_L3_SEL                                                  0
+
+		Configures MIO Pin 60 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F0, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_60_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_60_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_61 @ 0XFF1800F4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_61_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[5]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_61_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_61_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_61_L3_SEL                                                  0
+
+		Configures MIO Pin 61 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F4, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_61_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_61_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_62 @ 0XFF1800F8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_62_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[6]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_62_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_62_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_62_L3_SEL                                                  0
+
+		Configures MIO Pin 62 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F8, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_62_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_62_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_63 @ 0XFF1800FC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_63_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[7]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_63_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_63_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_63_L3_SEL                                                  0
+
+		Configures MIO Pin 63 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800FC, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_63_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_63_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_64 @ 0XFF180100

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_64_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_64_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_64_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
+		i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 trace, Output, tracedq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_64_L3_SEL                                                  0
+
+		Configures MIO Pin 64 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180100, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_64_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_64_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_65 @ 0XFF180104

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_65_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
+		PSU_IOU_SLCR_MIO_PIN_65_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_65_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
+		dq[11]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_65_L3_SEL                                                  0
+
+		Configures MIO Pin 65 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180104, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_65_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_65_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_66 @ 0XFF180108

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_66_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[2]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_66_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_66_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
+		2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
+		Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_66_L3_SEL                                                  0
+
+		Configures MIO Pin 66 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180108, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_66_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_66_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_67 @ 0XFF18010C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_67_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
+		PSU_IOU_SLCR_MIO_PIN_67_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_67_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_67_L3_SEL                                                  0
+
+		Configures MIO Pin 67 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18010C, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_67_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_67_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_68 @ 0XFF180110

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_68_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[0]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_68_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_68_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_68_L3_SEL                                                  0
+
+		Configures MIO Pin 68 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180110, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_68_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_68_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_69 @ 0XFF180114

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_69_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[1]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_69_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_69_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_69_L3_SEL                                                  0
+
+		Configures MIO Pin 69 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180114, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_69_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_69_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_70 @ 0XFF180118

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_70_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
+		PSU_IOU_SLCR_MIO_PIN_70_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_70_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed
+		PSU_IOU_SLCR_MIO_PIN_70_L3_SEL                                                  0
+
+		Configures MIO Pin 70 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180118, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_70_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_70_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_71 @ 0XFF18011C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_71_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[3]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_71_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_71_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_71_L3_SEL                                                  0
+
+		Configures MIO Pin 71 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18011C, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_71_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_71_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_72 @ 0XFF180120

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_72_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[4]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_72_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_72_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
+		t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_72_L3_SEL                                                  0
+
+		Configures MIO Pin 72 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180120, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_72_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_72_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_73 @ 0XFF180124

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_73_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[5]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_73_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_73_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_73_L3_SEL                                                  0
+
+		Configures MIO Pin 73 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180124, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_73_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_73_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_74 @ 0XFF180128

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_74_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[6]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_74_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_74_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_74_L3_SEL                                                  0
+
+		Configures MIO Pin 74 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180128, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_74_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_74_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_75 @ 0XFF18012C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_75_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[7]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_75_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
+		d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_75_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_75_L3_SEL                                                  0
+
+		Configures MIO Pin 75 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18012C, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_75_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_75_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_76 @ 0XFF180130

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
+		_clk_out- (SDSDIO clock) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
+		 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L3_SEL                                                  0
+
+		Configures MIO Pin 76 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180130, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_76_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_76_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_77 @ 0XFF180134

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
+		O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
+		t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L3_SEL                                                  0
+
+		Configures MIO Pin 77 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180134, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_77_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_77_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI0 @ 0XFF180204

+
+		Master Tri-state Enable for pin 0, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI                                            0
+
+		Master Tri-state Enable for pin 1, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI                                            0
+
+		Master Tri-state Enable for pin 2, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI                                            0
+
+		Master Tri-state Enable for pin 3, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI                                            0
+
+		Master Tri-state Enable for pin 4, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI                                            0
+
+		Master Tri-state Enable for pin 5, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI                                            0
+
+		Master Tri-state Enable for pin 6, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI                                            0
+
+		Master Tri-state Enable for pin 7, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI                                            0
+
+		Master Tri-state Enable for pin 8, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI                                            0
+
+		Master Tri-state Enable for pin 9, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI                                            0
+
+		Master Tri-state Enable for pin 10, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI                                            1
+
+		Master Tri-state Enable for pin 11, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI                                            1
+
+		Master Tri-state Enable for pin 12, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI                                            0
+
+		Master Tri-state Enable for pin 13, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI                                            0
+
+		Master Tri-state Enable for pin 14, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI                                            0
+
+		Master Tri-state Enable for pin 15, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI                                            0
+
+		Master Tri-state Enable for pin 16, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI                                            0
+
+		Master Tri-state Enable for pin 17, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI                                            0
+
+		Master Tri-state Enable for pin 18, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI                                            0
+
+		Master Tri-state Enable for pin 19, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI                                            0
+
+		Master Tri-state Enable for pin 20, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI                                            0
+
+		Master Tri-state Enable for pin 21, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI                                            0
+
+		Master Tri-state Enable for pin 22, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI                                            0
+
+		Master Tri-state Enable for pin 23, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI                                            0
+
+		Master Tri-state Enable for pin 24, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI                                            0
+
+		Master Tri-state Enable for pin 25, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI                                            0
+
+		Master Tri-state Enable for pin 26, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI                                            0
+
+		Master Tri-state Enable for pin 27, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI                                            0
+
+		Master Tri-state Enable for pin 28, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI                                            0
+
+		Master Tri-state Enable for pin 29, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI                                            0
+
+		Master Tri-state Enable for pin 30, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI                                            0
+
+		Master Tri-state Enable for pin 31, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI                                            0
+
+		MIO pin Tri-state Enables, 31:0
+		(OFFSET, MASK, VALUE)      (0XFF180204, 0xFFFFFFFFU ,0x00000C00U)  */
+		RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_MST_TRI0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_MST_TRI0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI1 @ 0XFF180208

+
+		Master Tri-state Enable for pin 32, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI                                            0
+
+		Master Tri-state Enable for pin 33, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI                                            0
+
+		Master Tri-state Enable for pin 34, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI                                            0
+
+		Master Tri-state Enable for pin 35, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI                                            0
+
+		Master Tri-state Enable for pin 36, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI                                            0
+
+		Master Tri-state Enable for pin 37, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI                                            0
+
+		Master Tri-state Enable for pin 38, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI                                            0
+
+		Master Tri-state Enable for pin 39, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI                                            0
+
+		Master Tri-state Enable for pin 40, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI                                            0
+
+		Master Tri-state Enable for pin 41, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI                                            0
+
+		Master Tri-state Enable for pin 42, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI                                            0
+
+		Master Tri-state Enable for pin 43, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI                                            0
+
+		Master Tri-state Enable for pin 44, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI                                            0
+
+		Master Tri-state Enable for pin 45, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI                                            0
+
+		Master Tri-state Enable for pin 46, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI                                            0
+
+		Master Tri-state Enable for pin 47, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI                                            0
+
+		Master Tri-state Enable for pin 48, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI                                            0
+
+		Master Tri-state Enable for pin 49, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI                                            0
+
+		Master Tri-state Enable for pin 50, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI                                            0
+
+		Master Tri-state Enable for pin 51, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI                                            0
+
+		Master Tri-state Enable for pin 52, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI                                            1
+
+		Master Tri-state Enable for pin 53, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI                                            1
+
+		Master Tri-state Enable for pin 54, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI                                            0
+
+		Master Tri-state Enable for pin 55, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI                                            1
+
+		Master Tri-state Enable for pin 56, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI                                            0
+
+		Master Tri-state Enable for pin 57, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI                                            0
+
+		Master Tri-state Enable for pin 58, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI                                            0
+
+		Master Tri-state Enable for pin 59, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI                                            0
+
+		Master Tri-state Enable for pin 60, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI                                            0
+
+		Master Tri-state Enable for pin 61, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI                                            0
+
+		Master Tri-state Enable for pin 62, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI                                            0
+
+		Master Tri-state Enable for pin 63, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI                                            0
+
+		MIO pin Tri-state Enables, 63:32
+		(OFFSET, MASK, VALUE)      (0XFF180208, 0xFFFFFFFFU ,0x00B00000U)  */
+		RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_MST_TRI1_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_MST_TRI1_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI2 @ 0XFF18020C

+
+		Master Tri-state Enable for pin 64, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI                                            0
+
+		Master Tri-state Enable for pin 65, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI                                            1
+
+		Master Tri-state Enable for pin 66, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI                                            0
+
+		Master Tri-state Enable for pin 67, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI                                            0
+
+		Master Tri-state Enable for pin 68, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI                                            0
+
+		Master Tri-state Enable for pin 69, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI                                            0
+
+		Master Tri-state Enable for pin 70, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI                                            0
+
+		Master Tri-state Enable for pin 71, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI                                            0
+
+		Master Tri-state Enable for pin 72, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI                                            0
+
+		Master Tri-state Enable for pin 73, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI                                            0
+
+		Master Tri-state Enable for pin 74, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI                                            0
+
+		Master Tri-state Enable for pin 75, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI                                            0
+
+		Master Tri-state Enable for pin 76, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI                                            1
+
+		Master Tri-state Enable for pin 77, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI                                            0
+
+		MIO pin Tri-state Enables, 77:64
+		(OFFSET, MASK, VALUE)      (0XFF18020C, 0x00003FFFU ,0x00001002U)  */
+		RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_MST_TRI2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_MST_TRI2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : LOOPBACK
+		/*Register : MIO_LOOPBACK @ 0XFF180200

+
+		I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
+		ts to I2C 0 inputs.
+		PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1                                        0
+
+		CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
+		.
+		PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1                                        0
+
+		UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
+		outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
+		PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1                                          0
+
+		SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
+		ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
+		PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1                                        0
+
+		Loopback function within MIO
+		(OFFSET, MASK, VALUE)      (0XFF180200, 0x0000000FU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_LOOPBACK_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_LOOPBACK_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+
+}
+unsigned long psu_peripherals_init_data_3_0() {
+		// : ENET
+		/*Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		GEM 0 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM0_RESET                                             0
+
+		GEM 1 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM1_RESET                                             0
+
+		GEM 2 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM2_RESET                                             0
+
+		GEM 3 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0
+
+		Software controlled reset for the GEMs
+		(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x0000000FU ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK | CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK | CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK | CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : QSPI
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : NAND
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_NAND_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00010000U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : USB
+		/*Register : RST_LPD_TOP @ 0XFF5E023C

+
+		USB 0 reset for control registers
+		PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0
+
+		USB 0 sleep circuit reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0
+
+		USB 0 reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_TOP_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_TOP_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : SD
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SDIO0_RESET                                            0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET                                            0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000060U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK | CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : CTRL_REG_SD @ 0XFF180310

+
+		SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled
+		PSU_IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL                                           0
+
+		SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
+		PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL                                           0
+
+		SD eMMC selection
+		(OFFSET, MASK, VALUE)      (0XFF180310, 0x00008001U ,0x00000000U)  */
+		RegMask = (IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_MASK | IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_CTRL_REG_SD_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_CTRL_REG_SD_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SD_CONFIG_REG2 @ 0XFF180320

+
+		Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE                                        0
+
+		Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE                                        0
+
+		1.8V Support 1: 1.8V supported 0: 1.8V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V                                            1
+
+		3.0V Support 1: 3.0V supported 0: 3.0V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V                                            0
+
+		3.3V Support 1: 3.3V supported 0: 3.3V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V                                            1
+
+		1.8V Support 1: 1.8V supported 0: 1.8V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V                                            1
+
+		3.0V Support 1: 3.0V supported 0: 3.0V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V                                            0
+
+		3.3V Support 1: 3.3V supported 0: 3.3V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V                                            1
+
+		SD Config Register 2
+		(OFFSET, MASK, VALUE)      (0XFF180320, 0x33803380U ,0x02800280U)  */
+		RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_SD_CONFIG_REG2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_SD_CONFIG_REG2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CAN
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_CAN0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000180U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK | CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : I2C
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000600U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : SWDT
+		// : SPI
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SPI0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SPI1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000018U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK | CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : TTC
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00007800U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : UART
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET                                            0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET                                            0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000006U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_divider_reg0 @ 0XFF000034

+
+		Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x0
+
+		Baud Rate Divider Register
+		(OFFSET, MASK, VALUE)      (0XFF000034, 0x000000FFU ,0x00000000U)  */
+		RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
+
+		RegVal = Xil_In32 (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART0_BAUD_RATE_DIVIDER_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_gen_reg0 @ 0XFF000018

+
+		Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		PSU_UART0_BAUD_RATE_GEN_REG0_CD                                                 0x0
+
+		Baud Rate Generator Register.
+		(OFFSET, MASK, VALUE)      (0XFF000018, 0x0000FFFFU ,0x00000000U)  */
+		RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
+
+		RegVal = Xil_In32 (UART0_BAUD_RATE_GEN_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART0_BAUD_RATE_GEN_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Control_reg0 @ 0XFF000000

+
+		Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		PSU_UART0_CONTROL_REG0_STPBRK                                                   0x0
+
+		Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		PSU_UART0_CONTROL_REG0_STTBRK                                                   0x0
+
+		Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.
+		PSU_UART0_CONTROL_REG0_RSTTO                                                    0x0
+
+		Transmit disable: 0: enable transmitter 1: disable transmitter
+		PSU_UART0_CONTROL_REG0_TXDIS                                                    0x0
+
+		Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		PSU_UART0_CONTROL_REG0_TXEN                                                     0x1
+
+		Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		PSU_UART0_CONTROL_REG0_RXDIS                                                    0x0
+
+		Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		PSU_UART0_CONTROL_REG0_RXEN                                                     0x1
+
+		Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.
+		PSU_UART0_CONTROL_REG0_TXRES                                                    0x1
+
+		Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.
+		PSU_UART0_CONTROL_REG0_RXRES                                                    0x1
+
+		UART Control Register
+		(OFFSET, MASK, VALUE)      (0XFF000000, 0x000001FFU ,0x00000017U)  */
+		RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK |  0 );
+
+		RegVal = Xil_In32 (UART0_CONTROL_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART0_CONTROL_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : mode_reg0 @ 0XFF000004

+
+		Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		PSU_UART0_MODE_REG0_CHMODE                                                      0x0
+
+		Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved
+		PSU_UART0_MODE_REG0_NBSTOP                                                      0x0
+
+		Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		PSU_UART0_MODE_REG0_PAR                                                         0x4
+
+		Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		PSU_UART0_MODE_REG0_CHRL                                                        0x0
+
+		Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		PSU_UART0_MODE_REG0_CLKS                                                        0x0
+
+		UART Mode Register
+		(OFFSET, MASK, VALUE)      (0XFF000004, 0x000003FFU ,0x00000020U)  */
+		RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK |  0 );
+
+		RegVal = Xil_In32 (UART0_MODE_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT
+			| 0x00000004U << UART0_MODE_REG0_PAR_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART0_MODE_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_divider_reg0 @ 0XFF010034

+
+		Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x0
+
+		Baud Rate Divider Register
+		(OFFSET, MASK, VALUE)      (0XFF010034, 0x000000FFU ,0x00000000U)  */
+		RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
+
+		RegVal = Xil_In32 (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART1_BAUD_RATE_DIVIDER_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_gen_reg0 @ 0XFF010018

+
+		Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		PSU_UART1_BAUD_RATE_GEN_REG0_CD                                                 0x0
+
+		Baud Rate Generator Register.
+		(OFFSET, MASK, VALUE)      (0XFF010018, 0x0000FFFFU ,0x00000000U)  */
+		RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
+
+		RegVal = Xil_In32 (UART1_BAUD_RATE_GEN_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART1_BAUD_RATE_GEN_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Control_reg0 @ 0XFF010000

+
+		Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		PSU_UART1_CONTROL_REG0_STPBRK                                                   0x0
+
+		Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		PSU_UART1_CONTROL_REG0_STTBRK                                                   0x0
+
+		Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.
+		PSU_UART1_CONTROL_REG0_RSTTO                                                    0x0
+
+		Transmit disable: 0: enable transmitter 1: disable transmitter
+		PSU_UART1_CONTROL_REG0_TXDIS                                                    0x0
+
+		Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		PSU_UART1_CONTROL_REG0_TXEN                                                     0x1
+
+		Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		PSU_UART1_CONTROL_REG0_RXDIS                                                    0x0
+
+		Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		PSU_UART1_CONTROL_REG0_RXEN                                                     0x1
+
+		Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.
+		PSU_UART1_CONTROL_REG0_TXRES                                                    0x1
+
+		Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.
+		PSU_UART1_CONTROL_REG0_RXRES                                                    0x1
+
+		UART Control Register
+		(OFFSET, MASK, VALUE)      (0XFF010000, 0x000001FFU ,0x00000017U)  */
+		RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK |  0 );
+
+		RegVal = Xil_In32 (UART1_CONTROL_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART1_CONTROL_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : mode_reg0 @ 0XFF010004

+
+		Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		PSU_UART1_MODE_REG0_CHMODE                                                      0x0
+
+		Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved
+		PSU_UART1_MODE_REG0_NBSTOP                                                      0x0
+
+		Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		PSU_UART1_MODE_REG0_PAR                                                         0x4
+
+		Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		PSU_UART1_MODE_REG0_CHRL                                                        0x0
+
+		Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		PSU_UART1_MODE_REG0_CLKS                                                        0x0
+
+		UART Mode Register
+		(OFFSET, MASK, VALUE)      (0XFF010004, 0x000003FFU ,0x00000020U)  */
+		RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK |  0 );
+
+		RegVal = Xil_In32 (UART1_MODE_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT
+			| 0x00000004U << UART1_MODE_REG0_PAR_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART1_MODE_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : GPIO
+		// : ADMA TZ
+		/*Register : slcr_adma @ 0XFF4B0024

+
+		TrustZone Classification for ADMA
+		PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ                                                0XFF
+
+		RPU TrustZone settings
+		(OFFSET, MASK, VALUE)      (0XFF4B0024, 0x000000FFU ,0x000000FFU)  */
+		RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_SLCR_SECURE_SLCR_ADMA_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CSU TAMPERING
+		// : CSU TAMPER STATUS
+		/*Register : tamper_status @ 0XFFCA5000

+
+		CSU regsiter
+		PSU_CSU_TAMPER_STATUS_TAMPER_0                                                  0
+
+		External MIO
+		PSU_CSU_TAMPER_STATUS_TAMPER_1                                                  0
+
+		JTAG toggle detect
+		PSU_CSU_TAMPER_STATUS_TAMPER_2                                                  0
+
+		PL SEU error
+		PSU_CSU_TAMPER_STATUS_TAMPER_3                                                  0
+
+		AMS over temperature alarm for LPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_4                                                  0
+
+		AMS over temperature alarm for APU
+		PSU_CSU_TAMPER_STATUS_TAMPER_5                                                  0
+
+		AMS voltage alarm for VCCPINT_FPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_6                                                  0
+
+		AMS voltage alarm for VCCPINT_LPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_7                                                  0
+
+		AMS voltage alarm for VCCPAUX
+		PSU_CSU_TAMPER_STATUS_TAMPER_8                                                  0
+
+		AMS voltage alarm for DDRPHY
+		PSU_CSU_TAMPER_STATUS_TAMPER_9                                                  0
+
+		AMS voltage alarm for PSIO bank 0/1/2
+		PSU_CSU_TAMPER_STATUS_TAMPER_10                                                 0
+
+		AMS voltage alarm for PSIO bank 3 (dedicated pins)
+		PSU_CSU_TAMPER_STATUS_TAMPER_11                                                 0
+
+		AMS voltaage alarm for GT
+		PSU_CSU_TAMPER_STATUS_TAMPER_12                                                 0
+
+		Tamper Response Status
+		(OFFSET, MASK, VALUE)      (0XFFCA5000, 0x00001FFFU ,0x00000000U)  */
+		RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK |  0 );
+
+		RegVal = Xil_In32 (CSU_TAMPER_STATUS_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CSU_TAMPER_STATUS_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CSU TAMPER RESPONSE
+
+}
+unsigned long psu_post_config() {
+
+}
+unsigned long psu_peripherals_powerdwn_data_3_0() {
+		// : POWER DOWN REQUEST INTERRUPT ENABLE
+		// : POWER DOWN TRIGGER
+
+}
+unsigned long psu_security_data_3_0() {
+		// : DDR XMPU0
+		// : DDR XMPU1
+		// : DDR XMPU2
+		// : DDR XMPU3
+		// : DDR XMPU4
+		// : DDR XMPU5
+		// : FPD XMPU
+		// : OCM XMPU
+		// : XPPU
+		// : MASTER ID LIST
+		/*Register : MASTER_ID00 @ 0XFF980100

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID00_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID00_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID00_MIDM                                               0
+
+		Predefined Master ID for PMU
+		PSU_LPD_XPPU_CFG_MASTER_ID00_MID                                                0
+
+		Master ID 00 Register
+		(OFFSET, MASK, VALUE)      (0XFF980100, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID00_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID00_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID00_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID00_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID01 @ 0XFF980104

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID01_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID01_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID01_MIDM                                               0
+
+		Predefined Master ID for RPU0
+		PSU_LPD_XPPU_CFG_MASTER_ID01_MID                                                0
+
+		Master ID 01 Register
+		(OFFSET, MASK, VALUE)      (0XFF980104, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID01_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID01_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID01_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID01_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID02 @ 0XFF980108

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID02_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID02_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID02_MIDM                                               0
+
+		Predefined Master ID for RPU1
+		PSU_LPD_XPPU_CFG_MASTER_ID02_MID                                                0
+
+		Master ID 02 Register
+		(OFFSET, MASK, VALUE)      (0XFF980108, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID02_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID02_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID02_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID02_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID03 @ 0XFF98010C

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID03_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID03_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID03_MIDM                                               0
+
+		Predefined Master ID for APU
+		PSU_LPD_XPPU_CFG_MASTER_ID03_MID                                                0
+
+		Master ID 03 Register
+		(OFFSET, MASK, VALUE)      (0XFF98010C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID03_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID03_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID03_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID03_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID04 @ 0XFF980110

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID04_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID04_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID04_MIDM                                               0
+
+		Predefined Master ID for A53 Core 0
+		PSU_LPD_XPPU_CFG_MASTER_ID04_MID                                                0
+
+		Master ID 04 Register
+		(OFFSET, MASK, VALUE)      (0XFF980110, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID04_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID04_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID04_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID04_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID05 @ 0XFF980114

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID05_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID05_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID05_MIDM                                               0
+
+		Predefined Master ID for A53 Core 1
+		PSU_LPD_XPPU_CFG_MASTER_ID05_MID                                                0
+
+		Master ID 05 Register
+		(OFFSET, MASK, VALUE)      (0XFF980114, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID05_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID05_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID05_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID05_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID06 @ 0XFF980118

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID06_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID06_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID06_MIDM                                               0
+
+		Predefined Master ID for A53 Core 2
+		PSU_LPD_XPPU_CFG_MASTER_ID06_MID                                                0
+
+		Master ID 06 Register
+		(OFFSET, MASK, VALUE)      (0XFF980118, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID06_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID06_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID06_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID06_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID07 @ 0XFF98011C

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID07_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID07_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID07_MIDM                                               0
+
+		Predefined Master ID for A53 Core 3
+		PSU_LPD_XPPU_CFG_MASTER_ID07_MID                                                0
+
+		Master ID 07 Register
+		(OFFSET, MASK, VALUE)      (0XFF98011C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID07_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID07_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID07_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID07_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID08 @ 0XFF980120

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID08_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID08_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID08_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID08_MID                                                0
+
+		Master ID 08 Register
+		(OFFSET, MASK, VALUE)      (0XFF980120, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID08_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID08_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID08_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID08_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID08_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID08_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID09 @ 0XFF980124

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID09_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID09_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID09_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID09_MID                                                0
+
+		Master ID 09 Register
+		(OFFSET, MASK, VALUE)      (0XFF980124, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID09_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID09_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID09_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID09_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID09_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID09_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID10 @ 0XFF980128

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID10_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID10_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID10_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID10_MID                                                0
+
+		Master ID 10 Register
+		(OFFSET, MASK, VALUE)      (0XFF980128, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID10_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID10_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID10_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID10_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID10_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID10_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID11 @ 0XFF98012C

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID11_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID11_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID11_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID11_MID                                                0
+
+		Master ID 11 Register
+		(OFFSET, MASK, VALUE)      (0XFF98012C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID11_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID11_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID11_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID11_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID11_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID11_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID12 @ 0XFF980130

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID12_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID12_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID12_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID12_MID                                                0
+
+		Master ID 12 Register
+		(OFFSET, MASK, VALUE)      (0XFF980130, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID12_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID12_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID12_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID12_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID12_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID12_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID13 @ 0XFF980134

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID13_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID13_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID13_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID13_MID                                                0
+
+		Master ID 13 Register
+		(OFFSET, MASK, VALUE)      (0XFF980134, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID13_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID13_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID13_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID13_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID13_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID13_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID14 @ 0XFF980138

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID14_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID14_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID14_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID14_MID                                                0
+
+		Master ID 14 Register
+		(OFFSET, MASK, VALUE)      (0XFF980138, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID14_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID14_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID14_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID14_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID14_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID14_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID15 @ 0XFF98013C

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID15_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID15_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID15_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID15_MID                                                0
+
+		Master ID 15 Register
+		(OFFSET, MASK, VALUE)      (0XFF98013C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID15_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID15_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID15_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID15_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID15_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID15_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID16 @ 0XFF980140

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID16_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID16_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID16_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID16_MID                                                0
+
+		Master ID 16 Register
+		(OFFSET, MASK, VALUE)      (0XFF980140, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID16_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID16_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID16_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID16_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID16_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID16_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID17 @ 0XFF980144

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID17_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID17_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID17_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID17_MID                                                0
+
+		Master ID 17 Register
+		(OFFSET, MASK, VALUE)      (0XFF980144, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID17_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID17_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID17_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID17_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID17_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID17_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID18 @ 0XFF980148

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID18_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID18_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID18_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID18_MID                                                0
+
+		Master ID 18 Register
+		(OFFSET, MASK, VALUE)      (0XFF980148, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID18_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID18_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID18_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID18_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID18_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID18_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID19 @ 0XFF98014C

+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID19_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID19_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID19_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID19_MID                                                0
+
+		Master ID 19 Register
+		(OFFSET, MASK, VALUE)      (0XFF98014C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID19_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID19_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID19_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID19_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : APERTURE PERMISIION LIST
+
+}
+/**
+ * CRL_APB Base Address
+ */
+#define CRL_APB_BASEADDR      0XFF5E0000U
+#define CRL_APB_RST_LPD_IOU0    ( ( CRL_APB_BASEADDR ) + 0X00000230U )
+#define CRL_APB_RST_LPD_IOU1    ( ( CRL_APB_BASEADDR ) + 0X00000234U )
+#define CRL_APB_RST_LPD_IOU2    ( ( CRL_APB_BASEADDR ) + 0X00000238U )
+#define CRL_APB_RST_LPD_TOP    ( ( CRL_APB_BASEADDR ) + 0X0000023CU )
+#define CRL_APB_IOU_SWITCH_CTRL    ( ( CRL_APB_BASEADDR ) + 0X0000009CU )
+
+/**
+ * CRF_APB Base Address
+ */
+#define CRF_APB_BASEADDR      0XFD1A0000U
+
+#define CRF_APB_RST_FPD_TOP    ( ( CRF_APB_BASEADDR ) + 0X00000100U )
+#define CRF_APB_GPU_REF_CTRL    ( ( CRF_APB_BASEADDR ) + 0X00000084U )
+#define CRF_APB_RST_DDR_SS    ( ( CRF_APB_BASEADDR ) + 0X00000108U )
+
+void init_ddrc()
+{
+
+	Xil_Out32(  0XFD1A0108, 0x0000000F)  ; //#RST_DDR_SS 0xFE500108
+		Xil_Out32(  0xFD070000, 0x41040001)  ; //#MSTR
+		Xil_Out32(  0xFD070034, 0x00404310)  ; //#PWRTMG
+		Xil_Out32(  0xFD070064, 0x0040001E)  ; //#RFSHTMG 
+		Xil_Out32(  0xFD070070, 0x00000010)  ; //#ECCCFG0
+		Xil_Out32(  0xFD070074, 0x00000000)  ; //#ECCCFG1
+		Xil_Out32(  0xFD0700C4, 0x10000200)  ; //#CRCPARCTL1
+		Xil_Out32(  0xFD0700C8, 0x0030051F)  ; //#CRCPARCTL2
+		Xil_Out32(  0xFD0700D0, 0x40020004)  ; //#INIT0  
+		Xil_Out32(  0xFD0700D4, 0x00010000)  ; //#INIT1 
+		Xil_Out32(  0xFD0700D8, 0x00001205)  ; //#INIT2
+		Xil_Out32(  0xFD0700DC, 0x09300000)  ; //#INIT3
+		Xil_Out32(  0xFD0700E0, 0x02080000)  ; //#INIT4
+		Xil_Out32(  0xFD0700E4, 0x00110004)  ; //#INIT5
+		Xil_Out32(  0xFD070100, 0x090E110A)  ; //#DRAMTMG0
+		Xil_Out32(  0xFD070104, 0x0007020E)  ; //#DRAMTMG1
+		Xil_Out32(  0xFD070108, 0x03040407)  ; //#DRAMTMG2
+		Xil_Out32(  0xFD07010C, 0x00502006)  ; //#DRAMTMG3
+		Xil_Out32(  0xFD070110, 0x04020205)  ; //#DRAMTMG4
+		Xil_Out32(  0xFD070114, 0x03030202)  ; //#DRAMTMG5
+		Xil_Out32(  0xFD070118, 0x01010003)  ; //#DRAMTMG6
+		Xil_Out32(  0xFD07011C, 0x00000101)  ; //#DRAMTMG7
+		Xil_Out32(  0xFD070120, 0x03030903)  ; //#DRAMTMG8
+		Xil_Out32(  0xFD070130, 0x00020608)  ; //#DRAMTMG12
+		Xil_Out32(  0xFD070180, 0x00800020)  ; //#ZQCTL0
+		Xil_Out32(  0xFD070184, 0x0200CB52)  ; //#ZQCTL1
+		Xil_Out32(  0xFD070190, 0x02838204)  ; //#DFITMG0 
+		Xil_Out32(  0xFD070194, 0x00020404)  ; //#DFITMG1 
+		Xil_Out32(  0xFD0701A4, 0x00010087)  ; //#DFIUPD1
+		Xil_Out32(  0xFD0701B0, 0x00000001)  ; //#DFIMISC #change-reset value
+		Xil_Out32(  0xFD0701B4, 0x00000202)  ; //#DFITMG2
+		Xil_Out32(  0xFD0701C0, 0x00000000)  ; //#DBICTL
+		Xil_Out32(  0xFD070200, 0x0000001F)  ; //#ADDRMAP0
+		Xil_Out32(  0xFD070204, 0x00080808)  ; //#ADDRMAP1
+		Xil_Out32(  0xFD070208, 0x00000000)  ; //#ADDRMAP2
+		Xil_Out32(  0xFD07020C, 0x00000000)  ; //#ADDRMAP3
+		Xil_Out32(  0xFD070210, 0x00000F0F)  ; //#ADDRMAP4
+		Xil_Out32(  0xFD070214, 0x07070707)  ; //#ADDRMAP5 
+		Xil_Out32(  0xFD070218, 0x07070707)  ; //#ADDRMAP6
+		Xil_Out32(  0xFD07021C, 0x00000F0F)  ; //#ADDRMAP7
+		Xil_Out32(  0xFD070220, 0x00000000)  ; //#ADDRMAP8
+		Xil_Out32(  0xFD070240, 0x06000604)  ; //#ODTCFG
+		Xil_Out32(  0xFD070244, 0x00000001)  ; //#ODTMAP
+		Xil_Out32(  0xFD070250, 0x01002001)  ; //#SCHED
+		Xil_Out32(  0xFD070264, 0x08000040)  ; //#PERFLPR1
+		Xil_Out32(  0xFD07026C, 0x08000040)  ; //#PERFWR1
+		Xil_Out32(  0xFD070294, 0x00000001)  ; //#DQMAP5
+		Xil_Out32(  0xFD07030C, 0x00000000)  ; //#DBGCMD
+		Xil_Out32(  0xFD070320, 0x00000000)  ; //#SWCTL
+		Xil_Out32(  0xFD070400, 0x00000001)  ; //#PCCFG
+		Xil_Out32(  0xFD070404, 0x0000600F)  ; //#PCFGR_0
+		Xil_Out32(  0xFD070408, 0x0000600F)  ; //#PCFGW_0
+		Xil_Out32(  0xFD070490, 0x00000001)  ; //#PCTRL_0
+		Xil_Out32(  0xFD070494, 0x0021000B)  ; //#PCFGQOS0_0
+		Xil_Out32(  0xFD070498, 0x004F004F)  ; //#PCFGQOS1_0
+		Xil_Out32(  0xFD0704B4, 0x0000600F)  ; //#PCFGR_1
+		Xil_Out32(  0xFD0704B8, 0x0000600F)  ; //#PCFGW_1
+		Xil_Out32(  0xFD070540, 0x00000001)  ; //#PCTRL_1
+		Xil_Out32(  0xFD070544, 0x02000B03)  ; //#PCFGQOS0_1
+		Xil_Out32(  0xFD070548, 0x00010040)  ; //#PCFGQOS1_1
+		Xil_Out32(  0xFD070564, 0x0000600F)  ; //#PCFGR_2
+		Xil_Out32(  0xFD070568, 0x0000600F)  ; //#PCFGW_2
+		Xil_Out32(  0xFD0705F0, 0x00000001)  ; //#PCTRL_2
+		Xil_Out32(  0xFD0705F4, 0x02000B03)  ; //#PCFGQOS0_2
+		Xil_Out32(  0xFD0705F8, 0x00010040)  ; //#PCFGQOS1_2
+		Xil_Out32(  0xFD070614, 0x0000600F)  ; //#PCFGR_3
+		Xil_Out32(  0xFD070618, 0x0000600F)  ; //#PCFGW_3
+		Xil_Out32(  0xFD0706A0, 0x00000001)  ; //#PCTRL_3
+		Xil_Out32(  0xFD0706A4, 0x00100003)  ; //#PCFGQOS0_3
+		Xil_Out32(  0xFD0706A8, 0x002F004F)  ; //#PCFGQOS1_3
+		Xil_Out32(  0xFD0706AC, 0x00100007)  ; //#PCFGWQOS0_3
+		Xil_Out32(  0xFD0706B0, 0x0000004F)  ; //#PCFGWQOS1_3
+		Xil_Out32(  0xFD0706C4, 0x0000600F)  ; //#PCFGR_4
+		Xil_Out32(  0xFD0706C8, 0x0000600F)  ; //#PCFGW_4
+		Xil_Out32(  0xFD070750, 0x00000001)  ; //#PCTRL_4
+		Xil_Out32(  0xFD070754, 0x00100003)  ; //#PCFGQOS0_4
+		Xil_Out32(  0xFD070758, 0x002F004F)  ; //#PCFGQOS1_4
+		Xil_Out32(  0xFD07075C, 0x00100007)  ; //#PCFGWQOS0_4
+		Xil_Out32(  0xFD070760, 0x0000004F)  ; //#PCFGWQOS1_4
+		Xil_Out32(  0xFD070774, 0x0000600F)  ; //#PCFGR_5
+		Xil_Out32(  0xFD070778, 0x0000600F)  ; //#PCFGW_5
+		Xil_Out32(  0xFD070800, 0x00000001)  ; //#PCTRL_5
+		Xil_Out32(  0xFD070804, 0x00100003)  ; //#PCFGQOS0_5
+		Xil_Out32(  0xFD070808, 0x002F004F)  ; //#PCFGQOS1_5
+		Xil_Out32(  0xFD07080C, 0x00100007)  ; //#PCFGWQOS0_5
+		Xil_Out32(  0xFD070810, 0x0000004F)  ; //#PCFGWQOS1_5
+		Xil_Out32(  0xFD070F04, 0x00000000)  ; //#SARBASE0
+		Xil_Out32(  0xFD070F08, 0x00000000)  ; //#SARSIZE0
+		Xil_Out32(  0xFD070F0C, 0x00000010)  ; //#SARBASE1
+		Xil_Out32(  0xFD070F10, 0x0000000F)  ; //#SARSIZE1
+		      
+		Xil_In32( 0XFD1A0108)  ; //#RST_DDR_SS 0xFE500108
+		Xil_Out32(  0XFD1A0108, 0x00000000)  ; //#RST_DDR_SS 0xFE500108 0
+		Xil_In32( 0XFD1A0108           )  ; //#RST_DDR_SS 0xFE500108  
+
+	/* Take DDR out of reset */
+	Xil_Out32( CRF_APB_RST_DDR_SS, 0x00000000);
+}
+
+void init_peripheral()
+{
+	unsigned int RegValue;
+
+	/* Turn on IOU Clock */
+	Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500);
+
+	/* Release all resets in the IOU */
+	Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000);
+	Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000);
+	Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000);
+
+	/* Activate GPU clocks */
+	Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500);
+
+	/* Take LPD out of reset except R5 */
+	RegValue = Xil_In32(CRL_APB_RST_LPD_TOP);
+	RegValue &= 0x3;
+	Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue);
+
+	/* Take most of FPD out of reset */
+	Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000);
+}
+int
+psu_init() 
+{
+    psu_mio_init_data ();
+    psu_pll_init_data ();
+    psu_clock_init_data ();
+    psu_ddr_init_data_3_0 ();
+    init_ddrc();
+    init_peripheral ();
+    psu_peripherals_init_data_3_0 ();
+    psu_peripherals_powerdwn_data_3_0 ();
+    psu_security_data_3_0();
+    return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.h
new file mode 100644
index 000000000..1903eb60f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.h
@@ -0,0 +1,6859 @@
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET                                            0XFF5E0048
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET                                           0XFF5E0044
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0048
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A004C
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0050
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_RPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRL_APB_RPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_RPLL_CTRL_DIV2_MASK 
+#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL                                              0x00012C09
+#define CRL_APB_RPLL_CTRL_DIV2_SHIFT                                               16
+#define CRL_APB_RPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*RPLL is locked*/
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL                                        0x00000018
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT                                         1
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK                                          0x00000002U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT                                             8
+#define CRL_APB_IOPLL_CTRL_FBDIV_MASK                                              0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_DIV2_MASK 
+#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL                                             0x00012C09
+#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT                                              16
+#define CRL_APB_IOPLL_CTRL_DIV2_MASK                                               0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
+
+/*IOPLL is locked*/
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL                                       0x00000018
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT                                        0
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK                                         0x00000001U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                  0x00000400
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_APLL_CTRL_FBDIV_MASK 
+#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_APLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_APLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_APLL_CTRL_DIV2_MASK 
+#define CRF_APB_APLL_CTRL_DIV2_DEFVAL                                              0x00012C09
+#define CRF_APB_APLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_APLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*APLL is locked*/
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT                                         0
+#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK                                          0x00000001U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_DPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_DPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_DPLL_CTRL_DIV2_MASK 
+#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL                                              0x00002C09
+#define CRF_APB_DPLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_DPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*DPLL is locked*/
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT                                         1
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK                                          0x00000002U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_VPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_VPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_VPLL_CTRL_DIV2_MASK 
+#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL                                              0x00012809
+#define CRF_APB_VPLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_VPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*VPLL is locked*/
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT                                         2
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK                                          0x00000004U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+#undef CRL_APB_GEM0_REF_CTRL_OFFSET 
+#define CRL_APB_GEM0_REF_CTRL_OFFSET                                               0XFF5E0050
+#undef CRL_APB_GEM1_REF_CTRL_OFFSET 
+#define CRL_APB_GEM1_REF_CTRL_OFFSET                                               0XFF5E0054
+#undef CRL_APB_GEM2_REF_CTRL_OFFSET 
+#define CRL_APB_GEM2_REF_CTRL_OFFSET                                               0XFF5E0058
+#undef CRL_APB_GEM3_REF_CTRL_OFFSET 
+#define CRL_APB_GEM3_REF_CTRL_OFFSET                                               0XFF5E005C
+#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET 
+#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET                                           0XFF5E0060
+#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 
+#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET                                          0XFF5E004C
+#undef CRL_APB_QSPI_REF_CTRL_OFFSET 
+#define CRL_APB_QSPI_REF_CTRL_OFFSET                                               0XFF5E0068
+#undef CRL_APB_SDIO0_REF_CTRL_OFFSET 
+#define CRL_APB_SDIO0_REF_CTRL_OFFSET                                              0XFF5E006C
+#undef CRL_APB_SDIO1_REF_CTRL_OFFSET 
+#define CRL_APB_SDIO1_REF_CTRL_OFFSET                                              0XFF5E0070
+#undef CRL_APB_UART0_REF_CTRL_OFFSET 
+#define CRL_APB_UART0_REF_CTRL_OFFSET                                              0XFF5E0074
+#undef CRL_APB_UART1_REF_CTRL_OFFSET 
+#define CRL_APB_UART1_REF_CTRL_OFFSET                                              0XFF5E0078
+#undef CRL_APB_I2C0_REF_CTRL_OFFSET 
+#define CRL_APB_I2C0_REF_CTRL_OFFSET                                               0XFF5E0120
+#undef CRL_APB_I2C1_REF_CTRL_OFFSET 
+#define CRL_APB_I2C1_REF_CTRL_OFFSET                                               0XFF5E0124
+#undef CRL_APB_SPI0_REF_CTRL_OFFSET 
+#define CRL_APB_SPI0_REF_CTRL_OFFSET                                               0XFF5E007C
+#undef CRL_APB_SPI1_REF_CTRL_OFFSET 
+#define CRL_APB_SPI1_REF_CTRL_OFFSET                                               0XFF5E0080
+#undef CRL_APB_CAN0_REF_CTRL_OFFSET 
+#define CRL_APB_CAN0_REF_CTRL_OFFSET                                               0XFF5E0084
+#undef CRL_APB_CAN1_REF_CTRL_OFFSET 
+#define CRL_APB_CAN1_REF_CTRL_OFFSET                                               0XFF5E0088
+#undef CRL_APB_CPU_R5_CTRL_OFFSET 
+#define CRL_APB_CPU_R5_CTRL_OFFSET                                                 0XFF5E0090
+#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET 
+#define CRL_APB_IOU_SWITCH_CTRL_OFFSET                                             0XFF5E009C
+#undef CRL_APB_PCAP_CTRL_OFFSET 
+#define CRL_APB_PCAP_CTRL_OFFSET                                                   0XFF5E00A4
+#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET 
+#define CRL_APB_LPD_SWITCH_CTRL_OFFSET                                             0XFF5E00A8
+#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET 
+#define CRL_APB_LPD_LSBUS_CTRL_OFFSET                                              0XFF5E00AC
+#undef CRL_APB_DBG_LPD_CTRL_OFFSET 
+#define CRL_APB_DBG_LPD_CTRL_OFFSET                                                0XFF5E00B0
+#undef CRL_APB_NAND_REF_CTRL_OFFSET 
+#define CRL_APB_NAND_REF_CTRL_OFFSET                                               0XFF5E00B4
+#undef CRL_APB_ADMA_REF_CTRL_OFFSET 
+#define CRL_APB_ADMA_REF_CTRL_OFFSET                                               0XFF5E00B8
+#undef CRL_APB_AMS_REF_CTRL_OFFSET 
+#define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
+#undef CRL_APB_DLL_REF_CTRL_OFFSET 
+#define CRL_APB_DLL_REF_CTRL_OFFSET                                                0XFF5E0104
+#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 
+#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET                                          0XFF5E0128
+#undef CRF_APB_PCIE_REF_CTRL_OFFSET 
+#define CRF_APB_PCIE_REF_CTRL_OFFSET                                               0XFD1A00B4
+#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET                                           0XFD1A0070
+#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET                                           0XFD1A0074
+#undef CRF_APB_DP_STC_REF_CTRL_OFFSET 
+#define CRF_APB_DP_STC_REF_CTRL_OFFSET                                             0XFD1A007C
+#undef CRF_APB_ACPU_CTRL_OFFSET 
+#define CRF_APB_ACPU_CTRL_OFFSET                                                   0XFD1A0060
+#undef CRF_APB_DBG_TRACE_CTRL_OFFSET 
+#define CRF_APB_DBG_TRACE_CTRL_OFFSET                                              0XFD1A0064
+#undef CRF_APB_DBG_FPD_CTRL_OFFSET 
+#define CRF_APB_DBG_FPD_CTRL_OFFSET                                                0XFD1A0068
+#undef CRF_APB_DDR_CTRL_OFFSET 
+#define CRF_APB_DDR_CTRL_OFFSET                                                    0XFD1A0080
+#undef CRF_APB_GPU_REF_CTRL_OFFSET 
+#define CRF_APB_GPU_REF_CTRL_OFFSET                                                0XFD1A0084
+#undef CRF_APB_GDMA_REF_CTRL_OFFSET 
+#define CRF_APB_GDMA_REF_CTRL_OFFSET                                               0XFD1A00B8
+#undef CRF_APB_DPDMA_REF_CTRL_OFFSET 
+#define CRF_APB_DPDMA_REF_CTRL_OFFSET                                              0XFD1A00BC
+#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET 
+#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET                                             0XFD1A00C0
+#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 
+#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET                                            0XFD1A00C4
+#undef CRF_APB_GTGREF0_REF_CTRL_OFFSET 
+#define CRF_APB_GTGREF0_REF_CTRL_OFFSET                                            0XFD1A00C8
+#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET 
+#define CRF_APB_DBG_TSTMP_CTRL_OFFSET                                              0XFD1A00F8
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL                                    0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT                                     25
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK                                      0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL                                  0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL                                  0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL                                    0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL                                   0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT                                    25
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK                                     0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL                                 0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT                                  16
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK                                   0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL                                 0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT                                  8
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL                                   0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT                                    0
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK                                     0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL                                        0x01000800
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL                                        0x01000800
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK 
+#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL                                          0x03000600
+#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT                                           24
+#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK                                            0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL                                        0x03000600
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT                                         8
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK                                          0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL                                          0x03000600
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT                                           0
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK                                            0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL                                      0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT                                       24
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT                                       0
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PCAP_CTRL_CLKACT_MASK 
+#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL                                            0x00001500
+#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT                                             24
+#define CRL_APB_PCAP_CTRL_CLKACT_MASK                                              0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL                                          0x00001500
+#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT                                           8
+#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK                                            0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK 
+#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL                                            0x00001500
+#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT                                             0
+#define CRL_APB_PCAP_CTRL_SRCSEL_MASK                                              0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL                                      0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT                                       24
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT                                       0
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL                                         0x01002000
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL                                       0x01002000
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL                                         0x01002000
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL                                        0x00052000
+#define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_NAND_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL                                      0x00052000
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL                                      0x00052000
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL                                        0x00052000
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL                                        0x00002000
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002000
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL                                        0x00002000
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                                       0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                                       0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                                         0x01001800
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                                         0x01001800
+#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
+		is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL                                         0x00000000
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL                                 0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT                                  8
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
+
+/*1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 
+		 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL                                   0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT                                    0
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK                                     0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL                                   0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT                                    24
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK                                     0x01000000U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL                                        0x00001500
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL                                        0x00001500
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL                                      0x00001500
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
+		k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL                                    0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL                                    0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT                                     24
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK                                      0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
+		k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL                                    0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL                                    0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT                                     24
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK                                      0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL                                    0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT                                     16
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK                                      0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL                                    0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT                                     8
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL                                      0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT                                       0
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL                                      0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT                                       24
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK 
+#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL                                          0x03000400
+#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT                                           8
+#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK                                            0x00003F00U
+
+/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK 
+#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL                                            0x03000400
+#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT                                             0
+#define CRF_APB_ACPU_CTRL_SRCSEL_MASK                                              0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL                                       0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT                                        25
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK                                         0x02000000U
+
+/*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
+		 to the entire APU*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL                                       0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT                                        24
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL                                     0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL                                       0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL                                       0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT                                        24
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL                                       0x01002500
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT                                        8
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL                                         0x01002500
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT                                          0
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL                                         0x01002500
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT                                          24
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL                                           0x01000500
+#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT                                            8
+#define CRF_APB_DDR_CTRL_DIVISOR0_MASK                                             0x00003F00U
+
+/*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 
+		s not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DDR_CTRL_SRCSEL_MASK 
+#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL                                             0x01000500
+#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT                                              0
+#define CRF_APB_DDR_CTRL_SRCSEL_MASK                                               0x00000007U
+
+/*6 bit divider*/
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL                                       0x00001500
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL                                         0x00001500
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below*/
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL                                         0x00001500
+#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock*/
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL                                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT                                      25
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK                                       0x02000000U
+
+/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock*/
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL                                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT                                      26
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK                                       0x04000000U
+
+/*6 bit divider*/
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL                                       0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL                                       0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL                                    0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT                                     8
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL                                      0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT                                       0
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL                                      0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT                                       24
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL                                   0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL                                     0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT                                      0
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL                                     0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT                                      24
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL                                   0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL                                     0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT                                      0
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL                                     0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT                                      24
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL                                     0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL                                       0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK                                         0x00000007U
+#undef IOU_SLCR_MIO_PIN_0_OFFSET 
+#define IOU_SLCR_MIO_PIN_0_OFFSET                                                  0XFF180000
+#undef IOU_SLCR_MIO_PIN_1_OFFSET 
+#define IOU_SLCR_MIO_PIN_1_OFFSET                                                  0XFF180004
+#undef IOU_SLCR_MIO_PIN_2_OFFSET 
+#define IOU_SLCR_MIO_PIN_2_OFFSET                                                  0XFF180008
+#undef IOU_SLCR_MIO_PIN_3_OFFSET 
+#define IOU_SLCR_MIO_PIN_3_OFFSET                                                  0XFF18000C
+#undef IOU_SLCR_MIO_PIN_4_OFFSET 
+#define IOU_SLCR_MIO_PIN_4_OFFSET                                                  0XFF180010
+#undef IOU_SLCR_MIO_PIN_5_OFFSET 
+#define IOU_SLCR_MIO_PIN_5_OFFSET                                                  0XFF180014
+#undef IOU_SLCR_MIO_PIN_6_OFFSET 
+#define IOU_SLCR_MIO_PIN_6_OFFSET                                                  0XFF180018
+#undef IOU_SLCR_MIO_PIN_7_OFFSET 
+#define IOU_SLCR_MIO_PIN_7_OFFSET                                                  0XFF18001C
+#undef IOU_SLCR_MIO_PIN_8_OFFSET 
+#define IOU_SLCR_MIO_PIN_8_OFFSET                                                  0XFF180020
+#undef IOU_SLCR_MIO_PIN_9_OFFSET 
+#define IOU_SLCR_MIO_PIN_9_OFFSET                                                  0XFF180024
+#undef IOU_SLCR_MIO_PIN_10_OFFSET 
+#define IOU_SLCR_MIO_PIN_10_OFFSET                                                 0XFF180028
+#undef IOU_SLCR_MIO_PIN_11_OFFSET 
+#define IOU_SLCR_MIO_PIN_11_OFFSET                                                 0XFF18002C
+#undef IOU_SLCR_MIO_PIN_12_OFFSET 
+#define IOU_SLCR_MIO_PIN_12_OFFSET                                                 0XFF180030
+#undef IOU_SLCR_MIO_PIN_13_OFFSET 
+#define IOU_SLCR_MIO_PIN_13_OFFSET                                                 0XFF180034
+#undef IOU_SLCR_MIO_PIN_14_OFFSET 
+#define IOU_SLCR_MIO_PIN_14_OFFSET                                                 0XFF180038
+#undef IOU_SLCR_MIO_PIN_15_OFFSET 
+#define IOU_SLCR_MIO_PIN_15_OFFSET                                                 0XFF18003C
+#undef IOU_SLCR_MIO_PIN_16_OFFSET 
+#define IOU_SLCR_MIO_PIN_16_OFFSET                                                 0XFF180040
+#undef IOU_SLCR_MIO_PIN_17_OFFSET 
+#define IOU_SLCR_MIO_PIN_17_OFFSET                                                 0XFF180044
+#undef IOU_SLCR_MIO_PIN_18_OFFSET 
+#define IOU_SLCR_MIO_PIN_18_OFFSET                                                 0XFF180048
+#undef IOU_SLCR_MIO_PIN_19_OFFSET 
+#define IOU_SLCR_MIO_PIN_19_OFFSET                                                 0XFF18004C
+#undef IOU_SLCR_MIO_PIN_20_OFFSET 
+#define IOU_SLCR_MIO_PIN_20_OFFSET                                                 0XFF180050
+#undef IOU_SLCR_MIO_PIN_21_OFFSET 
+#define IOU_SLCR_MIO_PIN_21_OFFSET                                                 0XFF180054
+#undef IOU_SLCR_MIO_PIN_22_OFFSET 
+#define IOU_SLCR_MIO_PIN_22_OFFSET                                                 0XFF180058
+#undef IOU_SLCR_MIO_PIN_23_OFFSET 
+#define IOU_SLCR_MIO_PIN_23_OFFSET                                                 0XFF18005C
+#undef IOU_SLCR_MIO_PIN_24_OFFSET 
+#define IOU_SLCR_MIO_PIN_24_OFFSET                                                 0XFF180060
+#undef IOU_SLCR_MIO_PIN_25_OFFSET 
+#define IOU_SLCR_MIO_PIN_25_OFFSET                                                 0XFF180064
+#undef IOU_SLCR_MIO_PIN_26_OFFSET 
+#define IOU_SLCR_MIO_PIN_26_OFFSET                                                 0XFF180068
+#undef IOU_SLCR_MIO_PIN_27_OFFSET 
+#define IOU_SLCR_MIO_PIN_27_OFFSET                                                 0XFF18006C
+#undef IOU_SLCR_MIO_PIN_28_OFFSET 
+#define IOU_SLCR_MIO_PIN_28_OFFSET                                                 0XFF180070
+#undef IOU_SLCR_MIO_PIN_29_OFFSET 
+#define IOU_SLCR_MIO_PIN_29_OFFSET                                                 0XFF180074
+#undef IOU_SLCR_MIO_PIN_30_OFFSET 
+#define IOU_SLCR_MIO_PIN_30_OFFSET                                                 0XFF180078
+#undef IOU_SLCR_MIO_PIN_31_OFFSET 
+#define IOU_SLCR_MIO_PIN_31_OFFSET                                                 0XFF18007C
+#undef IOU_SLCR_MIO_PIN_32_OFFSET 
+#define IOU_SLCR_MIO_PIN_32_OFFSET                                                 0XFF180080
+#undef IOU_SLCR_MIO_PIN_33_OFFSET 
+#define IOU_SLCR_MIO_PIN_33_OFFSET                                                 0XFF180084
+#undef IOU_SLCR_MIO_PIN_34_OFFSET 
+#define IOU_SLCR_MIO_PIN_34_OFFSET                                                 0XFF180088
+#undef IOU_SLCR_MIO_PIN_35_OFFSET 
+#define IOU_SLCR_MIO_PIN_35_OFFSET                                                 0XFF18008C
+#undef IOU_SLCR_MIO_PIN_36_OFFSET 
+#define IOU_SLCR_MIO_PIN_36_OFFSET                                                 0XFF180090
+#undef IOU_SLCR_MIO_PIN_37_OFFSET 
+#define IOU_SLCR_MIO_PIN_37_OFFSET                                                 0XFF180094
+#undef IOU_SLCR_MIO_PIN_38_OFFSET 
+#define IOU_SLCR_MIO_PIN_38_OFFSET                                                 0XFF180098
+#undef IOU_SLCR_MIO_PIN_39_OFFSET 
+#define IOU_SLCR_MIO_PIN_39_OFFSET                                                 0XFF18009C
+#undef IOU_SLCR_MIO_PIN_40_OFFSET 
+#define IOU_SLCR_MIO_PIN_40_OFFSET                                                 0XFF1800A0
+#undef IOU_SLCR_MIO_PIN_41_OFFSET 
+#define IOU_SLCR_MIO_PIN_41_OFFSET                                                 0XFF1800A4
+#undef IOU_SLCR_MIO_PIN_42_OFFSET 
+#define IOU_SLCR_MIO_PIN_42_OFFSET                                                 0XFF1800A8
+#undef IOU_SLCR_MIO_PIN_43_OFFSET 
+#define IOU_SLCR_MIO_PIN_43_OFFSET                                                 0XFF1800AC
+#undef IOU_SLCR_MIO_PIN_44_OFFSET 
+#define IOU_SLCR_MIO_PIN_44_OFFSET                                                 0XFF1800B0
+#undef IOU_SLCR_MIO_PIN_45_OFFSET 
+#define IOU_SLCR_MIO_PIN_45_OFFSET                                                 0XFF1800B4
+#undef IOU_SLCR_MIO_PIN_46_OFFSET 
+#define IOU_SLCR_MIO_PIN_46_OFFSET                                                 0XFF1800B8
+#undef IOU_SLCR_MIO_PIN_47_OFFSET 
+#define IOU_SLCR_MIO_PIN_47_OFFSET                                                 0XFF1800BC
+#undef IOU_SLCR_MIO_PIN_48_OFFSET 
+#define IOU_SLCR_MIO_PIN_48_OFFSET                                                 0XFF1800C0
+#undef IOU_SLCR_MIO_PIN_49_OFFSET 
+#define IOU_SLCR_MIO_PIN_49_OFFSET                                                 0XFF1800C4
+#undef IOU_SLCR_MIO_PIN_50_OFFSET 
+#define IOU_SLCR_MIO_PIN_50_OFFSET                                                 0XFF1800C8
+#undef IOU_SLCR_MIO_PIN_51_OFFSET 
+#define IOU_SLCR_MIO_PIN_51_OFFSET                                                 0XFF1800CC
+#undef IOU_SLCR_MIO_PIN_52_OFFSET 
+#define IOU_SLCR_MIO_PIN_52_OFFSET                                                 0XFF1800D0
+#undef IOU_SLCR_MIO_PIN_53_OFFSET 
+#define IOU_SLCR_MIO_PIN_53_OFFSET                                                 0XFF1800D4
+#undef IOU_SLCR_MIO_PIN_54_OFFSET 
+#define IOU_SLCR_MIO_PIN_54_OFFSET                                                 0XFF1800D8
+#undef IOU_SLCR_MIO_PIN_55_OFFSET 
+#define IOU_SLCR_MIO_PIN_55_OFFSET                                                 0XFF1800DC
+#undef IOU_SLCR_MIO_PIN_56_OFFSET 
+#define IOU_SLCR_MIO_PIN_56_OFFSET                                                 0XFF1800E0
+#undef IOU_SLCR_MIO_PIN_57_OFFSET 
+#define IOU_SLCR_MIO_PIN_57_OFFSET                                                 0XFF1800E4
+#undef IOU_SLCR_MIO_PIN_58_OFFSET 
+#define IOU_SLCR_MIO_PIN_58_OFFSET                                                 0XFF1800E8
+#undef IOU_SLCR_MIO_PIN_59_OFFSET 
+#define IOU_SLCR_MIO_PIN_59_OFFSET                                                 0XFF1800EC
+#undef IOU_SLCR_MIO_PIN_60_OFFSET 
+#define IOU_SLCR_MIO_PIN_60_OFFSET                                                 0XFF1800F0
+#undef IOU_SLCR_MIO_PIN_61_OFFSET 
+#define IOU_SLCR_MIO_PIN_61_OFFSET                                                 0XFF1800F4
+#undef IOU_SLCR_MIO_PIN_62_OFFSET 
+#define IOU_SLCR_MIO_PIN_62_OFFSET                                                 0XFF1800F8
+#undef IOU_SLCR_MIO_PIN_63_OFFSET 
+#define IOU_SLCR_MIO_PIN_63_OFFSET                                                 0XFF1800FC
+#undef IOU_SLCR_MIO_PIN_64_OFFSET 
+#define IOU_SLCR_MIO_PIN_64_OFFSET                                                 0XFF180100
+#undef IOU_SLCR_MIO_PIN_65_OFFSET 
+#define IOU_SLCR_MIO_PIN_65_OFFSET                                                 0XFF180104
+#undef IOU_SLCR_MIO_PIN_66_OFFSET 
+#define IOU_SLCR_MIO_PIN_66_OFFSET                                                 0XFF180108
+#undef IOU_SLCR_MIO_PIN_67_OFFSET 
+#define IOU_SLCR_MIO_PIN_67_OFFSET                                                 0XFF18010C
+#undef IOU_SLCR_MIO_PIN_68_OFFSET 
+#define IOU_SLCR_MIO_PIN_68_OFFSET                                                 0XFF180110
+#undef IOU_SLCR_MIO_PIN_69_OFFSET 
+#define IOU_SLCR_MIO_PIN_69_OFFSET                                                 0XFF180114
+#undef IOU_SLCR_MIO_PIN_70_OFFSET 
+#define IOU_SLCR_MIO_PIN_70_OFFSET                                                 0XFF180118
+#undef IOU_SLCR_MIO_PIN_71_OFFSET 
+#define IOU_SLCR_MIO_PIN_71_OFFSET                                                 0XFF18011C
+#undef IOU_SLCR_MIO_PIN_72_OFFSET 
+#define IOU_SLCR_MIO_PIN_72_OFFSET                                                 0XFF180120
+#undef IOU_SLCR_MIO_PIN_73_OFFSET 
+#define IOU_SLCR_MIO_PIN_73_OFFSET                                                 0XFF180124
+#undef IOU_SLCR_MIO_PIN_74_OFFSET 
+#define IOU_SLCR_MIO_PIN_74_OFFSET                                                 0XFF180128
+#undef IOU_SLCR_MIO_PIN_75_OFFSET 
+#define IOU_SLCR_MIO_PIN_75_OFFSET                                                 0XFF18012C
+#undef IOU_SLCR_MIO_PIN_76_OFFSET 
+#define IOU_SLCR_MIO_PIN_76_OFFSET                                                 0XFF180130
+#undef IOU_SLCR_MIO_PIN_77_OFFSET 
+#define IOU_SLCR_MIO_PIN_77_OFFSET                                                 0XFF180134
+#undef IOU_SLCR_MIO_MST_TRI0_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI0_OFFSET                                               0XFF180204
+#undef IOU_SLCR_MIO_MST_TRI1_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI1_OFFSET                                               0XFF180208
+#undef IOU_SLCR_MIO_MST_TRI2_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI2_OFFSET                                               0XFF18020C
+#undef IOU_SLCR_MIO_LOOPBACK_OFFSET 
+#define IOU_SLCR_MIO_LOOPBACK_OFFSET                                               0XFF180200
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
+		us)*/
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)*/
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
+		us)*/
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
+		sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
+		Output, tracedq[4]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 
+		tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 
+		racedq[5]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[0]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
+		, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
+		ce Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[1]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 
+		utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
+		RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[2]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[3]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		*/
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
+		ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
+		dq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
+		out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
+		bus)*/
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
+		n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
+		0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
+		l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
+		c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 
+		= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 
+		UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
+		(Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed*/
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
+		23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
+		*/
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
+		scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
+		 Tamper)*/
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
+		Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
+		test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
+		U Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 
+		lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)*/
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
+		 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
+		 tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
+		_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
+		ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		*/
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
+		_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 
+		race, Output, tracedq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
+		c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
+		[11]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
+		 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
+		rt Databus)*/
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
+		Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 
+		UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
+		k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
+		(Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
+		[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
+		_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
+		Control Signal)*/
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
+		in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
+		]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
+		ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
+		i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
+		i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
+		0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
+		ed*/
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
+		bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
+		d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
+		clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
+		t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
+		serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)*/
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[2]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[0]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[1]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[3]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)*/
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[4]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[5]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[6]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[7]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
+		i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 trace, Output, tracedq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
+		dq[11]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[2]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
+		2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
+		Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[0]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[1]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed*/
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[3]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[4]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
+		t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[5]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[6]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[7]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
+		d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
+		_clk_out- (SDSDIO clock) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
+		 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
+		O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
+		t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK                                            0x000000E0U
+
+/*Master Tri-state Enable for pin 0, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 1, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 2, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 3, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 4, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 5, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 6, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 7, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 8, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 9, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 10, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 11, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 12, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 13, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK                                      0x00002000U
+
+/*Master Tri-state Enable for pin 14, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT                                     14
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK                                      0x00004000U
+
+/*Master Tri-state Enable for pin 15, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT                                     15
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK                                      0x00008000U
+
+/*Master Tri-state Enable for pin 16, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT                                     16
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK                                      0x00010000U
+
+/*Master Tri-state Enable for pin 17, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT                                     17
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK                                      0x00020000U
+
+/*Master Tri-state Enable for pin 18, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT                                     18
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK                                      0x00040000U
+
+/*Master Tri-state Enable for pin 19, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT                                     19
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK                                      0x00080000U
+
+/*Master Tri-state Enable for pin 20, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT                                     20
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK                                      0x00100000U
+
+/*Master Tri-state Enable for pin 21, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT                                     21
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK                                      0x00200000U
+
+/*Master Tri-state Enable for pin 22, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT                                     22
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK                                      0x00400000U
+
+/*Master Tri-state Enable for pin 23, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT                                     23
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK                                      0x00800000U
+
+/*Master Tri-state Enable for pin 24, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT                                     24
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK                                      0x01000000U
+
+/*Master Tri-state Enable for pin 25, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT                                     25
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK                                      0x02000000U
+
+/*Master Tri-state Enable for pin 26, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT                                     26
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK                                      0x04000000U
+
+/*Master Tri-state Enable for pin 27, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT                                     27
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK                                      0x08000000U
+
+/*Master Tri-state Enable for pin 28, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT                                     28
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK                                      0x10000000U
+
+/*Master Tri-state Enable for pin 29, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT                                     29
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK                                      0x20000000U
+
+/*Master Tri-state Enable for pin 30, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT                                     30
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK                                      0x40000000U
+
+/*Master Tri-state Enable for pin 31, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT                                     31
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK                                      0x80000000U
+
+/*Master Tri-state Enable for pin 32, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 33, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 34, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 35, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 36, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 37, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 38, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 39, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 40, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 41, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 42, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 43, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 44, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 45, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK                                      0x00002000U
+
+/*Master Tri-state Enable for pin 46, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT                                     14
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK                                      0x00004000U
+
+/*Master Tri-state Enable for pin 47, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT                                     15
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK                                      0x00008000U
+
+/*Master Tri-state Enable for pin 48, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT                                     16
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK                                      0x00010000U
+
+/*Master Tri-state Enable for pin 49, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT                                     17
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK                                      0x00020000U
+
+/*Master Tri-state Enable for pin 50, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT                                     18
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK                                      0x00040000U
+
+/*Master Tri-state Enable for pin 51, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT                                     19
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK                                      0x00080000U
+
+/*Master Tri-state Enable for pin 52, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT                                     20
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK                                      0x00100000U
+
+/*Master Tri-state Enable for pin 53, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT                                     21
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK                                      0x00200000U
+
+/*Master Tri-state Enable for pin 54, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT                                     22
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK                                      0x00400000U
+
+/*Master Tri-state Enable for pin 55, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT                                     23
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK                                      0x00800000U
+
+/*Master Tri-state Enable for pin 56, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT                                     24
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK                                      0x01000000U
+
+/*Master Tri-state Enable for pin 57, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT                                     25
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK                                      0x02000000U
+
+/*Master Tri-state Enable for pin 58, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT                                     26
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK                                      0x04000000U
+
+/*Master Tri-state Enable for pin 59, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT                                     27
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK                                      0x08000000U
+
+/*Master Tri-state Enable for pin 60, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT                                     28
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK                                      0x10000000U
+
+/*Master Tri-state Enable for pin 61, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT                                     29
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK                                      0x20000000U
+
+/*Master Tri-state Enable for pin 62, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT                                     30
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK                                      0x40000000U
+
+/*Master Tri-state Enable for pin 63, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT                                     31
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK                                      0x80000000U
+
+/*Master Tri-state Enable for pin 64, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 65, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 66, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 67, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 68, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 69, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 70, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 71, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 72, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 73, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 74, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 75, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 76, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 77, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK                                      0x00002000U
+
+/*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
+		ts to I2C 0 inputs.*/
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT                                 3
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK                                  0x00000008U
+
+/*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
+		.*/
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT                                 2
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK                                  0x00000004U
+
+/*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
+		outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL                                  0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT                                   1
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK                                    0x00000002U
+
+/*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
+		ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT                                 0
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK                                  0x00000001U
+#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef IOU_SLCR_CTRL_REG_SD_OFFSET 
+#define IOU_SLCR_CTRL_REG_SD_OFFSET                                                0XFF180310
+#undef IOU_SLCR_SD_CONFIG_REG2_OFFSET 
+#define IOU_SLCR_SD_CONFIG_REG2_OFFSET                                             0XFF180320
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF000034
+#undef UART0_BAUD_RATE_GEN_REG0_OFFSET 
+#define UART0_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF000018
+#undef UART0_CONTROL_REG0_OFFSET 
+#define UART0_CONTROL_REG0_OFFSET                                                  0XFF000000
+#undef UART0_MODE_REG0_OFFSET 
+#define UART0_MODE_REG0_OFFSET                                                     0XFF000004
+#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF010034
+#undef UART1_BAUD_RATE_GEN_REG0_OFFSET 
+#define UART1_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF010018
+#undef UART1_CONTROL_REG0_OFFSET 
+#define UART1_CONTROL_REG0_OFFSET                                                  0XFF010000
+#undef UART1_MODE_REG0_OFFSET 
+#define UART1_MODE_REG0_OFFSET                                                     0XFF010004
+#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 
+#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
+#undef CSU_TAMPER_STATUS_OFFSET 
+#define CSU_TAMPER_STATUS_OFFSET                                                   0XFFCA5000
+
+/*GEM 0 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT                                      0
+#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK                                       0x00000001U
+
+/*GEM 1 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT                                      1
+#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK                                       0x00000002U
+
+/*GEM 2 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT                                      2
+#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK                                       0x00000004U
+
+/*GEM 3 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT                                      0
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK                                       0x00000001U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_NAND_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_NAND_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT                                      16
+#define CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK                                       0x00010000U
+
+/*USB 0 reset for control registers*/
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
+
+/*USB 0 sleep circuit reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
+
+/*USB 0 reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SDIO0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT                                     5
+#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK                                      0x00000020U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT                                     6
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK                                      0x00000040U
+
+/*SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled*/
+#undef IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_DEFVAL 
+#undef IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_SHIFT 
+#undef IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_MASK 
+#define IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_SHIFT                                    0
+#define IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_MASK                                     0x00000001U
+
+/*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT                                    15
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK                                     0x00008000U
+
+/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_DEFVAL                                0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT                                 12
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_MASK                                  0x00003000U
+
+/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL                                0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT                                 28
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK                                  0x30000000U
+
+/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_SHIFT                                     9
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_MASK                                      0x00000200U
+
+/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_SHIFT                                     8
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_MASK                                      0x00000100U
+
+/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_SHIFT                                     7
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_MASK                                      0x00000080U
+
+/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT                                     25
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK                                      0x02000000U
+
+/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT                                     24
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK                                      0x01000000U
+
+/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT                                     23
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK                                      0x00800000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT                                      7
+#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK                                       0x00000080U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT                                      8
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK                                       0x00000100U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT                                      9
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK                                       0x00000200U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT                                      10
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK                                       0x00000400U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK                                       0x00000008U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT                                      4
+#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK                                       0x00000010U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT                                      11
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK                                       0x00000800U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT                                      12
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK                                       0x00001000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT                                      13
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK                                       0x00002000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT                                      14
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK                                       0x00004000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT                                     1
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK                                      0x00000002U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT                                     2
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK                                      0x00000004U
+
+/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
+
+/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
+#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 
+#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 
+#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK 
+#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
+#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
+#define UART0_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
+
+/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
+#undef UART0_CONTROL_REG0_STPBRK_DEFVAL 
+#undef UART0_CONTROL_REG0_STPBRK_SHIFT 
+#undef UART0_CONTROL_REG0_STPBRK_MASK 
+#define UART0_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
+#define UART0_CONTROL_REG0_STPBRK_SHIFT                                            8
+#define UART0_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
+
+/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
+#undef UART0_CONTROL_REG0_STTBRK_DEFVAL 
+#undef UART0_CONTROL_REG0_STTBRK_SHIFT 
+#undef UART0_CONTROL_REG0_STTBRK_MASK 
+#define UART0_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
+#define UART0_CONTROL_REG0_STTBRK_SHIFT                                            7
+#define UART0_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
+
+/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.*/
+#undef UART0_CONTROL_REG0_RSTTO_DEFVAL 
+#undef UART0_CONTROL_REG0_RSTTO_SHIFT 
+#undef UART0_CONTROL_REG0_RSTTO_MASK 
+#define UART0_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RSTTO_SHIFT                                             6
+#define UART0_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
+
+/*Transmit disable: 0: enable transmitter 1: disable transmitter*/
+#undef UART0_CONTROL_REG0_TXDIS_DEFVAL 
+#undef UART0_CONTROL_REG0_TXDIS_SHIFT 
+#undef UART0_CONTROL_REG0_TXDIS_MASK 
+#define UART0_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_TXDIS_SHIFT                                             5
+#define UART0_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
+
+/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
+#undef UART0_CONTROL_REG0_TXEN_DEFVAL 
+#undef UART0_CONTROL_REG0_TXEN_SHIFT 
+#undef UART0_CONTROL_REG0_TXEN_MASK 
+#define UART0_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
+#define UART0_CONTROL_REG0_TXEN_SHIFT                                              4
+#define UART0_CONTROL_REG0_TXEN_MASK                                               0x00000010U
+
+/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
+#undef UART0_CONTROL_REG0_RXDIS_DEFVAL 
+#undef UART0_CONTROL_REG0_RXDIS_SHIFT 
+#undef UART0_CONTROL_REG0_RXDIS_MASK 
+#define UART0_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RXDIS_SHIFT                                             3
+#define UART0_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
+
+/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
+#undef UART0_CONTROL_REG0_RXEN_DEFVAL 
+#undef UART0_CONTROL_REG0_RXEN_SHIFT 
+#undef UART0_CONTROL_REG0_RXEN_MASK 
+#define UART0_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
+#define UART0_CONTROL_REG0_RXEN_SHIFT                                              2
+#define UART0_CONTROL_REG0_RXEN_MASK                                               0x00000004U
+
+/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.*/
+#undef UART0_CONTROL_REG0_TXRES_DEFVAL 
+#undef UART0_CONTROL_REG0_TXRES_SHIFT 
+#undef UART0_CONTROL_REG0_TXRES_MASK 
+#define UART0_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_TXRES_SHIFT                                             1
+#define UART0_CONTROL_REG0_TXRES_MASK                                              0x00000002U
+
+/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.*/
+#undef UART0_CONTROL_REG0_RXRES_DEFVAL 
+#undef UART0_CONTROL_REG0_RXRES_SHIFT 
+#undef UART0_CONTROL_REG0_RXRES_MASK 
+#define UART0_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RXRES_SHIFT                                             0
+#define UART0_CONTROL_REG0_RXRES_MASK                                              0x00000001U
+
+/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
+#undef UART0_MODE_REG0_CHMODE_DEFVAL 
+#undef UART0_MODE_REG0_CHMODE_SHIFT 
+#undef UART0_MODE_REG0_CHMODE_MASK 
+#define UART0_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
+#define UART0_MODE_REG0_CHMODE_SHIFT                                               8
+#define UART0_MODE_REG0_CHMODE_MASK                                                0x00000300U
+
+/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved*/
+#undef UART0_MODE_REG0_NBSTOP_DEFVAL 
+#undef UART0_MODE_REG0_NBSTOP_SHIFT 
+#undef UART0_MODE_REG0_NBSTOP_MASK 
+#define UART0_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
+#define UART0_MODE_REG0_NBSTOP_SHIFT                                               6
+#define UART0_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
+
+/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
+#undef UART0_MODE_REG0_PAR_DEFVAL 
+#undef UART0_MODE_REG0_PAR_SHIFT 
+#undef UART0_MODE_REG0_PAR_MASK 
+#define UART0_MODE_REG0_PAR_DEFVAL                                                 0x00000000
+#define UART0_MODE_REG0_PAR_SHIFT                                                  3
+#define UART0_MODE_REG0_PAR_MASK                                                   0x00000038U
+
+/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
+#undef UART0_MODE_REG0_CHRL_DEFVAL 
+#undef UART0_MODE_REG0_CHRL_SHIFT 
+#undef UART0_MODE_REG0_CHRL_MASK 
+#define UART0_MODE_REG0_CHRL_DEFVAL                                                0x00000000
+#define UART0_MODE_REG0_CHRL_SHIFT                                                 1
+#define UART0_MODE_REG0_CHRL_MASK                                                  0x00000006U
+
+/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
+#undef UART0_MODE_REG0_CLKS_DEFVAL 
+#undef UART0_MODE_REG0_CLKS_SHIFT 
+#undef UART0_MODE_REG0_CLKS_MASK 
+#define UART0_MODE_REG0_CLKS_DEFVAL                                                0x00000000
+#define UART0_MODE_REG0_CLKS_SHIFT                                                 0
+#define UART0_MODE_REG0_CLKS_MASK                                                  0x00000001U
+
+/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
+
+/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
+#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 
+#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 
+#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK 
+#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
+#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
+#define UART1_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
+
+/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
+#undef UART1_CONTROL_REG0_STPBRK_DEFVAL 
+#undef UART1_CONTROL_REG0_STPBRK_SHIFT 
+#undef UART1_CONTROL_REG0_STPBRK_MASK 
+#define UART1_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
+#define UART1_CONTROL_REG0_STPBRK_SHIFT                                            8
+#define UART1_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
+
+/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
+#undef UART1_CONTROL_REG0_STTBRK_DEFVAL 
+#undef UART1_CONTROL_REG0_STTBRK_SHIFT 
+#undef UART1_CONTROL_REG0_STTBRK_MASK 
+#define UART1_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
+#define UART1_CONTROL_REG0_STTBRK_SHIFT                                            7
+#define UART1_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
+
+/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.*/
+#undef UART1_CONTROL_REG0_RSTTO_DEFVAL 
+#undef UART1_CONTROL_REG0_RSTTO_SHIFT 
+#undef UART1_CONTROL_REG0_RSTTO_MASK 
+#define UART1_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RSTTO_SHIFT                                             6
+#define UART1_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
+
+/*Transmit disable: 0: enable transmitter 1: disable transmitter*/
+#undef UART1_CONTROL_REG0_TXDIS_DEFVAL 
+#undef UART1_CONTROL_REG0_TXDIS_SHIFT 
+#undef UART1_CONTROL_REG0_TXDIS_MASK 
+#define UART1_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_TXDIS_SHIFT                                             5
+#define UART1_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
+
+/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
+#undef UART1_CONTROL_REG0_TXEN_DEFVAL 
+#undef UART1_CONTROL_REG0_TXEN_SHIFT 
+#undef UART1_CONTROL_REG0_TXEN_MASK 
+#define UART1_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
+#define UART1_CONTROL_REG0_TXEN_SHIFT                                              4
+#define UART1_CONTROL_REG0_TXEN_MASK                                               0x00000010U
+
+/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
+#undef UART1_CONTROL_REG0_RXDIS_DEFVAL 
+#undef UART1_CONTROL_REG0_RXDIS_SHIFT 
+#undef UART1_CONTROL_REG0_RXDIS_MASK 
+#define UART1_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RXDIS_SHIFT                                             3
+#define UART1_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
+
+/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
+#undef UART1_CONTROL_REG0_RXEN_DEFVAL 
+#undef UART1_CONTROL_REG0_RXEN_SHIFT 
+#undef UART1_CONTROL_REG0_RXEN_MASK 
+#define UART1_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
+#define UART1_CONTROL_REG0_RXEN_SHIFT                                              2
+#define UART1_CONTROL_REG0_RXEN_MASK                                               0x00000004U
+
+/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.*/
+#undef UART1_CONTROL_REG0_TXRES_DEFVAL 
+#undef UART1_CONTROL_REG0_TXRES_SHIFT 
+#undef UART1_CONTROL_REG0_TXRES_MASK 
+#define UART1_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_TXRES_SHIFT                                             1
+#define UART1_CONTROL_REG0_TXRES_MASK                                              0x00000002U
+
+/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.*/
+#undef UART1_CONTROL_REG0_RXRES_DEFVAL 
+#undef UART1_CONTROL_REG0_RXRES_SHIFT 
+#undef UART1_CONTROL_REG0_RXRES_MASK 
+#define UART1_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RXRES_SHIFT                                             0
+#define UART1_CONTROL_REG0_RXRES_MASK                                              0x00000001U
+
+/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
+#undef UART1_MODE_REG0_CHMODE_DEFVAL 
+#undef UART1_MODE_REG0_CHMODE_SHIFT 
+#undef UART1_MODE_REG0_CHMODE_MASK 
+#define UART1_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
+#define UART1_MODE_REG0_CHMODE_SHIFT                                               8
+#define UART1_MODE_REG0_CHMODE_MASK                                                0x00000300U
+
+/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved*/
+#undef UART1_MODE_REG0_NBSTOP_DEFVAL 
+#undef UART1_MODE_REG0_NBSTOP_SHIFT 
+#undef UART1_MODE_REG0_NBSTOP_MASK 
+#define UART1_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
+#define UART1_MODE_REG0_NBSTOP_SHIFT                                               6
+#define UART1_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
+
+/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
+#undef UART1_MODE_REG0_PAR_DEFVAL 
+#undef UART1_MODE_REG0_PAR_SHIFT 
+#undef UART1_MODE_REG0_PAR_MASK 
+#define UART1_MODE_REG0_PAR_DEFVAL                                                 0x00000000
+#define UART1_MODE_REG0_PAR_SHIFT                                                  3
+#define UART1_MODE_REG0_PAR_MASK                                                   0x00000038U
+
+/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
+#undef UART1_MODE_REG0_CHRL_DEFVAL 
+#undef UART1_MODE_REG0_CHRL_SHIFT 
+#undef UART1_MODE_REG0_CHRL_MASK 
+#define UART1_MODE_REG0_CHRL_DEFVAL                                                0x00000000
+#define UART1_MODE_REG0_CHRL_SHIFT                                                 1
+#define UART1_MODE_REG0_CHRL_MASK                                                  0x00000006U
+
+/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
+#undef UART1_MODE_REG0_CLKS_DEFVAL 
+#undef UART1_MODE_REG0_CLKS_SHIFT 
+#undef UART1_MODE_REG0_CLKS_MASK 
+#define UART1_MODE_REG0_CLKS_DEFVAL                                                0x00000000
+#define UART1_MODE_REG0_CLKS_SHIFT                                                 0
+#define UART1_MODE_REG0_CLKS_MASK                                                  0x00000001U
+
+/*TrustZone Classification for ADMA*/
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL                                        
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                                         0
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                                          0x000000FFU
+
+/*CSU regsiter*/
+#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_0_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT                                           0
+#define CSU_TAMPER_STATUS_TAMPER_0_MASK                                            0x00000001U
+
+/*External MIO*/
+#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_1_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT                                           1
+#define CSU_TAMPER_STATUS_TAMPER_1_MASK                                            0x00000002U
+
+/*JTAG toggle detect*/
+#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_2_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT                                           2
+#define CSU_TAMPER_STATUS_TAMPER_2_MASK                                            0x00000004U
+
+/*PL SEU error*/
+#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_3_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT                                           3
+#define CSU_TAMPER_STATUS_TAMPER_3_MASK                                            0x00000008U
+
+/*AMS over temperature alarm for LPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_4_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT                                           4
+#define CSU_TAMPER_STATUS_TAMPER_4_MASK                                            0x00000010U
+
+/*AMS over temperature alarm for APU*/
+#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_5_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT                                           5
+#define CSU_TAMPER_STATUS_TAMPER_5_MASK                                            0x00000020U
+
+/*AMS voltage alarm for VCCPINT_FPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_6_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT                                           6
+#define CSU_TAMPER_STATUS_TAMPER_6_MASK                                            0x00000040U
+
+/*AMS voltage alarm for VCCPINT_LPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_7_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT                                           7
+#define CSU_TAMPER_STATUS_TAMPER_7_MASK                                            0x00000080U
+
+/*AMS voltage alarm for VCCPAUX*/
+#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_8_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT                                           8
+#define CSU_TAMPER_STATUS_TAMPER_8_MASK                                            0x00000100U
+
+/*AMS voltage alarm for DDRPHY*/
+#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_9_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT                                           9
+#define CSU_TAMPER_STATUS_TAMPER_9_MASK                                            0x00000200U
+
+/*AMS voltage alarm for PSIO bank 0/1/2*/
+#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_10_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT                                          10
+#define CSU_TAMPER_STATUS_TAMPER_10_MASK                                           0x00000400U
+
+/*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/
+#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_11_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT                                          11
+#define CSU_TAMPER_STATUS_TAMPER_11_MASK                                           0x00000800U
+
+/*AMS voltaage alarm for GT*/
+#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_12_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT                                          12
+#define CSU_TAMPER_STATUS_TAMPER_12_MASK                                           0x00001000U
+#undef LPD_XPPU_CFG_MASTER_ID00_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID00_OFFSET                                            0XFF980100
+#undef LPD_XPPU_CFG_MASTER_ID01_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID01_OFFSET                                            0XFF980104
+#undef LPD_XPPU_CFG_MASTER_ID02_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID02_OFFSET                                            0XFF980108
+#undef LPD_XPPU_CFG_MASTER_ID03_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID03_OFFSET                                            0XFF98010C
+#undef LPD_XPPU_CFG_MASTER_ID04_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID04_OFFSET                                            0XFF980110
+#undef LPD_XPPU_CFG_MASTER_ID05_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID05_OFFSET                                            0XFF980114
+#undef LPD_XPPU_CFG_MASTER_ID06_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID06_OFFSET                                            0XFF980118
+#undef LPD_XPPU_CFG_MASTER_ID07_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID07_OFFSET                                            0XFF98011C
+#undef LPD_XPPU_CFG_MASTER_ID08_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID08_OFFSET                                            0XFF980120
+#undef LPD_XPPU_CFG_MASTER_ID09_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID09_OFFSET                                            0XFF980124
+#undef LPD_XPPU_CFG_MASTER_ID10_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID10_OFFSET                                            0XFF980128
+#undef LPD_XPPU_CFG_MASTER_ID11_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID11_OFFSET                                            0XFF98012C
+#undef LPD_XPPU_CFG_MASTER_ID12_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID12_OFFSET                                            0XFF980130
+#undef LPD_XPPU_CFG_MASTER_ID13_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID13_OFFSET                                            0XFF980134
+#undef LPD_XPPU_CFG_MASTER_ID14_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID14_OFFSET                                            0XFF980138
+#undef LPD_XPPU_CFG_MASTER_ID15_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID15_OFFSET                                            0XFF98013C
+#undef LPD_XPPU_CFG_MASTER_ID16_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID16_OFFSET                                            0XFF980140
+#undef LPD_XPPU_CFG_MASTER_ID17_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID17_OFFSET                                            0XFF980144
+#undef LPD_XPPU_CFG_MASTER_ID18_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID18_OFFSET                                            0XFF980148
+#undef LPD_XPPU_CFG_MASTER_ID19_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID19_OFFSET                                            0XFF98014C
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID00_MIDP_DEFVAL                                       0x83FF0040
+#define LPD_XPPU_CFG_MASTER_ID00_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID00_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID00_MIDR_DEFVAL                                       0x83FF0040
+#define LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID00_MIDM_DEFVAL                                       0x83FF0040
+#define LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for PMU*/
+#undef LPD_XPPU_CFG_MASTER_ID00_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID00_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID00_MID_DEFVAL                                        0x83FF0040
+#define LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID00_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID01_MIDP_DEFVAL                                       0x03F00000
+#define LPD_XPPU_CFG_MASTER_ID01_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID01_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID01_MIDR_DEFVAL                                       0x03F00000
+#define LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID01_MIDM_DEFVAL                                       0x03F00000
+#define LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for RPU0*/
+#undef LPD_XPPU_CFG_MASTER_ID01_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID01_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID01_MID_DEFVAL                                        0x03F00000
+#define LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID01_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID02_MIDP_DEFVAL                                       0x83F00010
+#define LPD_XPPU_CFG_MASTER_ID02_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID02_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID02_MIDR_DEFVAL                                       0x83F00010
+#define LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID02_MIDM_DEFVAL                                       0x83F00010
+#define LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for RPU1*/
+#undef LPD_XPPU_CFG_MASTER_ID02_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID02_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID02_MID_DEFVAL                                        0x83F00010
+#define LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID02_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID03_MIDP_DEFVAL                                       0x83C00080
+#define LPD_XPPU_CFG_MASTER_ID03_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID03_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID03_MIDR_DEFVAL                                       0x83C00080
+#define LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID03_MIDM_DEFVAL                                       0x83C00080
+#define LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for APU*/
+#undef LPD_XPPU_CFG_MASTER_ID03_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID03_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID03_MID_DEFVAL                                        0x83C00080
+#define LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID03_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID04_MIDP_DEFVAL                                       0x83C30080
+#define LPD_XPPU_CFG_MASTER_ID04_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID04_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID04_MIDR_DEFVAL                                       0x83C30080
+#define LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID04_MIDM_DEFVAL                                       0x83C30080
+#define LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for A53 Core 0*/
+#undef LPD_XPPU_CFG_MASTER_ID04_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID04_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID04_MID_DEFVAL                                        0x83C30080
+#define LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID04_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID05_MIDP_DEFVAL                                       0x03C30081
+#define LPD_XPPU_CFG_MASTER_ID05_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID05_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID05_MIDR_DEFVAL                                       0x03C30081
+#define LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID05_MIDM_DEFVAL                                       0x03C30081
+#define LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for A53 Core 1*/
+#undef LPD_XPPU_CFG_MASTER_ID05_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID05_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID05_MID_DEFVAL                                        0x03C30081
+#define LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID05_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID06_MIDP_DEFVAL                                       0x03C30082
+#define LPD_XPPU_CFG_MASTER_ID06_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID06_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID06_MIDR_DEFVAL                                       0x03C30082
+#define LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID06_MIDM_DEFVAL                                       0x03C30082
+#define LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for A53 Core 2*/
+#undef LPD_XPPU_CFG_MASTER_ID06_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID06_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID06_MID_DEFVAL                                        0x03C30082
+#define LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID06_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID07_MIDP_DEFVAL                                       0x83C30083
+#define LPD_XPPU_CFG_MASTER_ID07_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID07_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID07_MIDR_DEFVAL                                       0x83C30083
+#define LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID07_MIDM_DEFVAL                                       0x83C30083
+#define LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for A53 Core 3*/
+#undef LPD_XPPU_CFG_MASTER_ID07_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID07_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID07_MID_DEFVAL                                        0x83C30083
+#define LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID07_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID08_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID08_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID08_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID08_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID08_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID08_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID08_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID08_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID08_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID08_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID08_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID08_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID08_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID08_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID08_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID09_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID09_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID09_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID09_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID09_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID09_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID09_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID09_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID09_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID09_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID09_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID09_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID09_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID09_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID09_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID10_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID10_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID10_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID10_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID10_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID10_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID10_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID10_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID10_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID10_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID10_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID10_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID10_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID10_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID10_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID11_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID11_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID11_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID11_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID11_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID11_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID11_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID11_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID11_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID11_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID11_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID11_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID11_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID11_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID11_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID12_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID12_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID12_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID12_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID12_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID12_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID12_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID12_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID12_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID12_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID12_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID12_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID12_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID12_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID12_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID13_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID13_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID13_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID13_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID13_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID13_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID13_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID13_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID13_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID13_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID13_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID13_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID13_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID13_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID13_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID14_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID14_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID14_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID14_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID14_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID14_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID14_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID14_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID14_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID14_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID14_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID14_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID14_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID14_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID14_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID15_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID15_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID15_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID15_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID15_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID15_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID15_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID15_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID15_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID15_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID15_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID15_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID15_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID15_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID15_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID16_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID16_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID16_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID16_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID16_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID16_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID16_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID16_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID16_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID16_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID16_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID16_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID16_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID16_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID16_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID17_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID17_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID17_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID17_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID17_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID17_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID17_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID17_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID17_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID17_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID17_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID17_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID17_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID17_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID17_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID18_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID18_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID18_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID18_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID18_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID18_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID18_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID18_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID18_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID18_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID18_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID18_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID18_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID18_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID18_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID19_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID19_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID19_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID19_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID19_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID19_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID19_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID19_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID19_MID_MASK                                          0x000003FFU
+#ifdef __cplusplus
+extern "C" {
+#endif
+ int psu_int (); 
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.html b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.html
new file mode 100644
index 000000000..69465de51
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.html
@@ -0,0 +1,38701 @@
+
+
+
+
+Zynq PS configuration detail
+
+
+
+

+

+
+
  • 
+
    Zynq PS Register Summary Viewer
+
    
+
    • 
+    
+
    
+
    
+
    
+
+
    Zynq PS7 Summary Report
+
    
+    
+
    User Configurations
+
    
+
    
+
+
    MIO Configurations
+
    
+    
+
    
+
+
    CLK Configurations
+
    
+    
+
    
+
+
    DDR Configurations
+
    
+    
+
    
+
+
    SMC Configurations
+
    
+    
+
    
+
    
+
    Select Version:
+
+
    
+
    
+
    Zynq Register View
+
    
+
    
+
+
    MIO Registers
+
    
+    
+
+
    PLL Registers
+
    
+    
+
+
    Clock Registers
+
    
+    
+
+
    DDR Registers
+
    
+    
+
+
    Peripherals Registers
+
    
+    
+
    
+
    This design is targeted for7vx485tboard (part number: )
+
+
    
+
    Zynq Design Summary
    
+
+
+
+
+
+
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+
+
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+
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+
    
+Device
+
+7vx485t
+
    
+SpeedGrade
+
+7vx485t
+
    
+Part
+
+
+
    
+Description
+
+Zynq PS Configuration Report with register details
+
    
+Vendor
+
+Xilinx
+
    
+
    MIO Table View
    
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+
    
+MIO Pin
+
+Peripheral
+
+Signal
+
+IO Type
+
+Speed
+
+Pullup
+
+Direction
+
    
+MIO 0
+
+Single Quad SPI (4bit)
+
+sclk_out
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 1
+
+Single Quad SPI (4bit)
+
+so_mo1
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 2
+
+Single Quad SPI (4bit)
+
+mo2
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 3
+
+Single Quad SPI (4bit)
+
+mo3
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 4
+
+Single Quad SPI (4bit)
+
+si_mi0
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 5
+
+Single Quad SPI (4bit)
+
+n_ss_out
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 6
+
+GPIO0 MIO
+
+gpio0[6]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 7
+
+GPIO0 MIO
+
+gpio0[7]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 8
+
+GPIO0 MIO
+
+gpio0[8]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 9
+
+GPIO0 MIO
+
+gpio0[9]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 10
+
+NAND
+
+nfc_rb_n[0]
+
+0
+
+0
+
+1
+
+in
+
    
+MIO 11
+
+NAND
+
+nfc_rb_n[1]
+
+0
+
+0
+
+1
+
+in
+
    
+MIO 12
+
+GPIO0 MIO
+
+gpio0[12]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 13
+
+NAND
+
+nfc_ce[0]
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 14
+
+NAND
+
+nfc_cle
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 15
+
+NAND
+
+nfc_ale
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 16
+
+NAND
+
+nfc_dq_out[0]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 17
+
+NAND
+
+nfc_dq_out[1]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 18
+
+NAND
+
+nfc_dq_out[2]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 19
+
+NAND
+
+nfc_dq_out[3]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 20
+
+NAND
+
+nfc_dq_out[4]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 21
+
+NAND
+
+nfc_dq_out[5]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 22
+
+NAND
+
+nfc_we_b
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 23
+
+NAND
+
+nfc_dq_out[6]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 24
+
+NAND
+
+nfc_dq_out[7]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 25
+
+NAND
+
+nfc_re_n
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 26
+
+NAND
+
+nfc_ce[1]
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 27
+
+GPIO1 MIO
+
+gpio1[27]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 28
+
+GPIO1 MIO
+
+gpio1[28]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 29
+
+SPI 0
+
+n_ss_out[0]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 30
+
+GPIO1 MIO
+
+gpio1[30]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 31
+
+GPIO1 MIO
+
+gpio1[31]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 32
+
+NAND
+
+nfc_dqs_out
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 33
+
+GPIO1 MIO
+
+gpio1[33]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 34
+
+GPIO1 MIO
+
+gpio1[34]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 35
+
+SPI 1
+
+n_ss_out[0]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 36
+
+GPIO1 MIO
+
+gpio1[36]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 37
+
+GPIO1 MIO
+
+gpio1[37]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 38
+
+GPIO1 MIO
+
+gpio1[38]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 39
+
+SD 1
+
+sdio1_data_out[4]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 40
+
+SD 1
+
+sdio1_data_out[5]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 41
+
+SD 1
+
+sdio1_data_out[6]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 42
+
+SD 1
+
+sdio1_data_out[7]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 43
+
+SD 1
+
+sdio1_bus_pow
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 44
+
+GPIO1 MIO
+
+gpio1[44]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 45
+
+GPIO1 MIO
+
+gpio1[45]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 46
+
+SD 1
+
+sdio1_data_out[0]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 47
+
+SD 1
+
+sdio1_data_out[1]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 48
+
+SD 1
+
+sdio1_data_out[2]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 49
+
+SD 1
+
+sdio1_data_out[3]
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 50
+
+SD 1
+
+sdio1_cmd_out
+
+0
+
+0
+
+1
+
+inout
+
    
+MIO 51
+
+SD 1
+
+sdio1_clk_out
+
+0
+
+0
+
+1
+
+out
+
    
+MIO 52
+
+USB 0
+
+ulpi_clk_in
+
+0
+
+0
+
+1
+
+in
+
    
+MIO 53
+
+USB 0
+
+ulpi_dir
+
+0
+
+0
+
+1
+
+in
+
    
+
    psu_pll_init_data
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+PSU_CRL_APB_RPLL_CTRL
+
+
+0XFF5E0030
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_RPLL_CTRL
+
+
+0XFF5E0030
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_RPLL_CTRL
+
+
+0XFF5E0030
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_RPLL_CTRL
+
+
+0XFF5E0030
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_RPLL_CTRL
+
+
+0XFF5E0030
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_RPLL_TO_FPD_CTRL
+
+
+0XFF5E0048
+
+32
+
+RW
+
+0x000000
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
+PSU_CRL_APB_IOPLL_CTRL
+
+
+0XFF5E0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_IOPLL_CTRL
+
+
+0XFF5E0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_IOPLL_CTRL
+
+
+0XFF5E0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_IOPLL_CTRL
+
+
+0XFF5E0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_IOPLL_CTRL
+
+
+0XFF5E0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRL_APB_IOPLL_TO_FPD_CTRL
+
+
+0XFF5E0044
+
+32
+
+RW
+
+0x000000
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
+PSU_CRF_APB_APLL_CTRL
+
+
+0XFD1A0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_APLL_CTRL
+
+
+0XFD1A0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_APLL_CTRL
+
+
+0XFD1A0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_APLL_CTRL
+
+
+0XFD1A0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_APLL_CTRL
+
+
+0XFD1A0020
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_APLL_TO_LPD_CTRL
+
+
+0XFD1A0048
+
+32
+
+RW
+
+0x000000
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
+PSU_CRF_APB_DPLL_CTRL
+
+
+0XFD1A002C
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_DPLL_CTRL
+
+
+0XFD1A002C
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_DPLL_CTRL
+
+
+0XFD1A002C
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_DPLL_CTRL
+
+
+0XFD1A002C
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_DPLL_CTRL
+
+
+0XFD1A002C
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_DPLL_TO_LPD_CTRL
+
+
+0XFD1A004C
+
+32
+
+RW
+
+0x000000
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
+PSU_CRF_APB_VPLL_CTRL
+
+
+0XFD1A0038
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_VPLL_CTRL
+
+
+0XFD1A0038
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_VPLL_CTRL
+
+
+0XFD1A0038
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_VPLL_CTRL
+
+
+0XFD1A0038
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_VPLL_CTRL
+
+
+0XFD1A0038
+
+32
+
+RW
+
+0x000000
+
+PLL Basic Control
+
    
+
+PSU_CRF_APB_VPLL_TO_LPD_CTRL
+
+
+0XFD1A0050
+
+32
+
+RW
+
+0x000000
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
    
+
    psu_pll_init_data
    
+
+
+
+
+
+
+
+
+
+
    RPLL INIT
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )RPLL_CTRL
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RPLL_CTRL
+
+0XFF5E0030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RPLL_CTRL_FBDIV
+
+14:8
+
+7f00
+
+30
+
+3000
+
+The integer portion of the feedback divider to the PLL
+
    
+PSU_CRL_APB_RPLL_CTRL_DIV2
+
+16:16
+
+10000
+
+1
+
+10000
+
+This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+
    
+PSU_CRL_APB_RPLL_CTRL@0XFF5E0030
+
+31:0
+
+17f00
+
+
+
+13000
+
+PLL Basic Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )RPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RPLL_CTRL
+
+0XFF5E0030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RPLL_CTRL_BYPASS
+
+3:3
+
+8
+
+1
+
+8
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_RPLL_CTRL@0XFF5E0030
+
+31:0
+
+8
+
+
+
+8
+
+PLL Basic Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )RPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RPLL_CTRL
+
+0XFF5E0030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RPLL_CTRL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Asserts Reset to the PLL
+
    
+PSU_CRL_APB_RPLL_CTRL@0XFF5E0030
+
+31:0
+
+1
+
+
+
+1
+
+PLL Basic Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )RPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RPLL_CTRL
+
+0XFF5E0030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RPLL_CTRL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Asserts Reset to the PLL
+
    
+PSU_CRL_APB_RPLL_CTRL@0XFF5E0030
+
+31:0
+
+1
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XFF5E0040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_PLL_STATUS_RPLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+RPLL is locked
+
    
+PSU_CRL_APB_PLL_STATUS@0XFF5E0040
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )RPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RPLL_CTRL
+
+0XFF5E0030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RPLL_CTRL_BYPASS
+
+3:3
+
+8
+
+0
+
+0
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_RPLL_CTRL@0XFF5E0030
+
+31:0
+
+8
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    Register ( slcr )RPLL_TO_FPD_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RPLL_TO_FPD_CTRL
+
+0XFF5E0048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3
+
+300
+
+Divisor value for this clock.
+
    
+PSU_CRL_APB_RPLL_TO_FPD_CTRL@0XFF5E0048
+
+31:0
+
+3f00
+
+
+
+300
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
    
+
    RPLL FRAC CFG
    
+
    IOPLL INIT
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IOPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IOPLL_CTRL
+
+0XFF5E0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_IOPLL_CTRL_FBDIV
+
+14:8
+
+7f00
+
+3c
+
+3c00
+
+The integer portion of the feedback divider to the PLL
+
    
+PSU_CRL_APB_IOPLL_CTRL_DIV2
+
+16:16
+
+10000
+
+1
+
+10000
+
+This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+
    
+PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020
+
+31:0
+
+17f00
+
+
+
+13c00
+
+PLL Basic Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IOPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IOPLL_CTRL
+
+0XFF5E0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_IOPLL_CTRL_BYPASS
+
+3:3
+
+8
+
+1
+
+8
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020
+
+31:0
+
+8
+
+
+
+8
+
+PLL Basic Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IOPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IOPLL_CTRL
+
+0XFF5E0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_IOPLL_CTRL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Asserts Reset to the PLL
+
    
+PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020
+
+31:0
+
+1
+
+
+
+1
+
+PLL Basic Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IOPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IOPLL_CTRL
+
+0XFF5E0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_IOPLL_CTRL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Asserts Reset to the PLL
+
    
+PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020
+
+31:0
+
+1
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XFF5E0040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+IOPLL is locked
+
    
+PSU_CRL_APB_PLL_STATUS@0XFF5E0040
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IOPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IOPLL_CTRL
+
+0XFF5E0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_IOPLL_CTRL_BYPASS
+
+3:3
+
+8
+
+0
+
+0
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020
+
+31:0
+
+8
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    Register ( slcr )IOPLL_TO_FPD_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IOPLL_TO_FPD_CTRL
+
+0XFF5E0044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+4
+
+400
+
+Divisor value for this clock.
+
    
+PSU_CRL_APB_IOPLL_TO_FPD_CTRL@0XFF5E0044
+
+31:0
+
+3f00
+
+
+
+400
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
    
+
    IOPLL FRAC CFG
    
+
    APU_PLL INIT
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )APLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APLL_CTRL
+
+0XFD1A0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_APLL_CTRL_FBDIV
+
+14:8
+
+7f00
+
+3c
+
+3c00
+
+The integer portion of the feedback divider to the PLL
+
    
+PSU_CRF_APB_APLL_CTRL_DIV2
+
+16:16
+
+10000
+
+1
+
+10000
+
+This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+
    
+PSU_CRF_APB_APLL_CTRL@0XFD1A0020
+
+31:0
+
+17f00
+
+
+
+13c00
+
+PLL Basic Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )APLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APLL_CTRL
+
+0XFD1A0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_APLL_CTRL_BYPASS
+
+3:3
+
+8
+
+1
+
+8
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_APLL_CTRL@0XFD1A0020
+
+31:0
+
+8
+
+
+
+8
+
+PLL Basic Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )APLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APLL_CTRL
+
+0XFD1A0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_APLL_CTRL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Asserts Reset to the PLL
+
    
+PSU_CRF_APB_APLL_CTRL@0XFD1A0020
+
+31:0
+
+1
+
+
+
+1
+
+PLL Basic Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )APLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APLL_CTRL
+
+0XFD1A0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_APLL_CTRL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Asserts Reset to the PLL
+
    
+PSU_CRF_APB_APLL_CTRL@0XFD1A0020
+
+31:0
+
+1
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XFD1A0044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_PLL_STATUS_APLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+APLL is locked
+
    
+PSU_CRF_APB_PLL_STATUS@0XFD1A0044
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )APLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APLL_CTRL
+
+0XFD1A0020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_APLL_CTRL_BYPASS
+
+3:3
+
+8
+
+0
+
+0
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_APLL_CTRL@0XFD1A0020
+
+31:0
+
+8
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    Register ( slcr )APLL_TO_LPD_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APLL_TO_LPD_CTRL
+
+0XFD1A0048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+4
+
+400
+
+Divisor value for this clock.
+
    
+PSU_CRF_APB_APLL_TO_LPD_CTRL@0XFD1A0048
+
+31:0
+
+3f00
+
+
+
+400
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
    
+
    APLL FRAC CFG
    
+
    DDR_PLL INIT
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DPLL_CTRL
+
+0XFD1A002C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DPLL_CTRL_FBDIV
+
+14:8
+
+7f00
+
+3c
+
+3c00
+
+The integer portion of the feedback divider to the PLL
+
    
+PSU_CRF_APB_DPLL_CTRL_DIV2
+
+16:16
+
+10000
+
+1
+
+10000
+
+This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+
    
+PSU_CRF_APB_DPLL_CTRL@0XFD1A002C
+
+31:0
+
+17f00
+
+
+
+13c00
+
+PLL Basic Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DPLL_CTRL
+
+0XFD1A002C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DPLL_CTRL_BYPASS
+
+3:3
+
+8
+
+1
+
+8
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DPLL_CTRL@0XFD1A002C
+
+31:0
+
+8
+
+
+
+8
+
+PLL Basic Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DPLL_CTRL
+
+0XFD1A002C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DPLL_CTRL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Asserts Reset to the PLL
+
    
+PSU_CRF_APB_DPLL_CTRL@0XFD1A002C
+
+31:0
+
+1
+
+
+
+1
+
+PLL Basic Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DPLL_CTRL
+
+0XFD1A002C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DPLL_CTRL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Asserts Reset to the PLL
+
    
+PSU_CRF_APB_DPLL_CTRL@0XFD1A002C
+
+31:0
+
+1
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XFD1A0044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_PLL_STATUS_DPLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DPLL is locked
+
    
+PSU_CRF_APB_PLL_STATUS@0XFD1A0044
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DPLL_CTRL
+
+0XFD1A002C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DPLL_CTRL_BYPASS
+
+3:3
+
+8
+
+0
+
+0
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DPLL_CTRL@0XFD1A002C
+
+31:0
+
+8
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    Register ( slcr )DPLL_TO_LPD_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DPLL_TO_LPD_CTRL
+
+0XFD1A004C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+4
+
+400
+
+Divisor value for this clock.
+
    
+PSU_CRF_APB_DPLL_TO_LPD_CTRL@0XFD1A004C
+
+31:0
+
+3f00
+
+
+
+400
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
    
+
    DPLL FRAC CFG
    
+
    VIDEO_PLL INIT
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )VPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+VPLL_CTRL
+
+0XFD1A0038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_VPLL_CTRL_FBDIV
+
+14:8
+
+7f00
+
+3f
+
+3f00
+
+The integer portion of the feedback divider to the PLL
+
    
+PSU_CRF_APB_VPLL_CTRL_DIV2
+
+16:16
+
+10000
+
+1
+
+10000
+
+This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+
    
+PSU_CRF_APB_VPLL_CTRL@0XFD1A0038
+
+31:0
+
+17f00
+
+
+
+13f00
+
+PLL Basic Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )VPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+VPLL_CTRL
+
+0XFD1A0038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_VPLL_CTRL_BYPASS
+
+3:3
+
+8
+
+1
+
+8
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_VPLL_CTRL@0XFD1A0038
+
+31:0
+
+8
+
+
+
+8
+
+PLL Basic Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )VPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+VPLL_CTRL
+
+0XFD1A0038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_VPLL_CTRL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Asserts Reset to the PLL
+
    
+PSU_CRF_APB_VPLL_CTRL@0XFD1A0038
+
+31:0
+
+1
+
+
+
+1
+
+PLL Basic Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )VPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+VPLL_CTRL
+
+0XFD1A0038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_VPLL_CTRL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Asserts Reset to the PLL
+
    
+PSU_CRF_APB_VPLL_CTRL@0XFD1A0038
+
+31:0
+
+1
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XFD1A0044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_PLL_STATUS_VPLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+VPLL is locked
+
    
+PSU_CRF_APB_PLL_STATUS@0XFD1A0044
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )VPLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+VPLL_CTRL
+
+0XFD1A0038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_VPLL_CTRL_BYPASS
+
+3:3
+
+8
+
+0
+
+0
+
+Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_VPLL_CTRL@0XFD1A0038
+
+31:0
+
+8
+
+
+
+0
+
+PLL Basic Control
+
    
+
    
+
    Register ( slcr )VPLL_TO_LPD_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+VPLL_TO_LPD_CTRL
+
+0XFD1A0050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+4
+
+400
+
+Divisor value for this clock.
+
    
+PSU_CRF_APB_VPLL_TO_LPD_CTRL@0XFD1A0050
+
+31:0
+
+3f00
+
+
+
+400
+
+Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+
    
+
    
+
    VIDEO FRAC CFG
    
+
+
    
+
    psu_clock_init_data
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+PSU_CRL_APB_GEM0_REF_CTRL
+
+
+0XFF5E0050
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_GEM1_REF_CTRL
+
+
+0XFF5E0054
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_GEM2_REF_CTRL
+
+
+0XFF5E0058
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_GEM3_REF_CTRL
+
+
+0XFF5E005C
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_USB0_BUS_REF_CTRL
+
+
+0XFF5E0060
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_USB3_DUAL_REF_CTRL
+
+
+0XFF5E004C
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_QSPI_REF_CTRL
+
+
+0XFF5E0068
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_SDIO0_REF_CTRL
+
+
+0XFF5E006C
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_SDIO1_REF_CTRL
+
+
+0XFF5E0070
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_UART0_REF_CTRL
+
+
+0XFF5E0074
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_UART1_REF_CTRL
+
+
+0XFF5E0078
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_I2C0_REF_CTRL
+
+
+0XFF5E0120
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_I2C1_REF_CTRL
+
+
+0XFF5E0124
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_SPI0_REF_CTRL
+
+
+0XFF5E007C
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_SPI1_REF_CTRL
+
+
+0XFF5E0080
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_CAN0_REF_CTRL
+
+
+0XFF5E0084
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_CAN1_REF_CTRL
+
+
+0XFF5E0088
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_CPU_R5_CTRL
+
+
+0XFF5E0090
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_IOU_SWITCH_CTRL
+
+
+0XFF5E009C
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_PCAP_CTRL
+
+
+0XFF5E00A4
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_LPD_SWITCH_CTRL
+
+
+0XFF5E00A8
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_LPD_LSBUS_CTRL
+
+
+0XFF5E00AC
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_DBG_LPD_CTRL
+
+
+0XFF5E00B0
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_NAND_REF_CTRL
+
+
+0XFF5E00B4
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_ADMA_REF_CTRL
+
+
+0XFF5E00B8
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_AMS_REF_CTRL
+
+
+0XFF5E0108
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_DLL_REF_CTRL
+
+
+0XFF5E0104
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRL_APB_TIMESTAMP_REF_CTRL
+
+
+0XFF5E0128
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_PCIE_REF_CTRL
+
+
+0XFD1A00B4
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_DP_VIDEO_REF_CTRL
+
+
+0XFD1A0070
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_DP_AUDIO_REF_CTRL
+
+
+0XFD1A0074
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_DP_STC_REF_CTRL
+
+
+0XFD1A007C
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_ACPU_CTRL
+
+
+0XFD1A0060
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_DBG_TRACE_CTRL
+
+
+0XFD1A0064
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_DBG_FPD_CTRL
+
+
+0XFD1A0068
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_DDR_CTRL
+
+
+0XFD1A0080
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_GPU_REF_CTRL
+
+
+0XFD1A0084
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_GDMA_REF_CTRL
+
+
+0XFD1A00B8
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_DPDMA_REF_CTRL
+
+
+0XFD1A00BC
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_TOPSW_MAIN_CTRL
+
+
+0XFD1A00C0
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_TOPSW_LSBUS_CTRL
+
+
+0XFD1A00C4
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_GTGREF0_REF_CTRL
+
+
+0XFD1A00C8
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
+PSU_CRF_APB_DBG_TSTMP_CTRL
+
+
+0XFD1A00F8
+
+32
+
+RW
+
+0x000000
+
+This register controls this reference clock
+
    
+
    
+
    psu_clock_init_data
    
+
+
+
+
+
+
+
+
+
+
    CLOCK CONTROL SLCR REGISTER
    
+
    Register ( slcr )GEM0_REF_CTRL
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_REF_CTRL
+
+0XFF5E0050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+Clock active for the RX channel
+
    
+PSU_CRL_APB_GEM0_REF_CTRL_CLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_GEM0_REF_CTRL@0XFF5E0050
+
+31:0
+
+63f3f07
+
+
+
+6022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )GEM1_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM1_REF_CTRL
+
+0XFF5E0054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+Clock active for the RX channel
+
    
+PSU_CRL_APB_GEM1_REF_CTRL_CLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_GEM1_REF_CTRL@0XFF5E0054
+
+31:0
+
+63f3f07
+
+
+
+6022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )GEM2_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM2_REF_CTRL
+
+0XFF5E0058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+Clock active for the RX channel
+
    
+PSU_CRL_APB_GEM2_REF_CTRL_CLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_GEM2_REF_CTRL@0XFF5E0058
+
+31:0
+
+63f3f07
+
+
+
+6022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )GEM3_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM3_REF_CTRL
+
+0XFF5E005C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+Clock active for the RX channel
+
    
+PSU_CRL_APB_GEM3_REF_CTRL_CLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_GEM3_REF_CTRL@0XFF5E005C
+
+31:0
+
+63f3f07
+
+
+
+6022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )USB0_BUS_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+USB0_BUS_REF_CTRL
+
+0XFF5E0060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+1
+
+10000
+
+6 bit divider
+
    
+PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+32
+
+3200
+
+6 bit divider
+
    
+PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_USB0_BUS_REF_CTRL@0XFF5E0060
+
+31:0
+
+23f3f07
+
+
+
+2013200
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )USB3_DUAL_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+USB3_DUAL_REF_CTRL
+
+0XFF5E004C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+1
+
+10000
+
+6 bit divider
+
    
+PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+8
+
+800
+
+6 bit divider
+
    
+PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_USB3_DUAL_REF_CTRL@0XFF5E004C
+
+31:0
+
+23f3f07
+
+
+
+2010800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )QSPI_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+QSPI_REF_CTRL
+
+0XFF5E0068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_QSPI_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+32
+
+3200
+
+6 bit divider
+
    
+PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_QSPI_REF_CTRL@0XFF5E0068
+
+31:0
+
+13f3f07
+
+
+
+1023200
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )SDIO0_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO0_REF_CTRL
+
+0XFF5E006C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+32
+
+3200
+
+6 bit divider
+
    
+PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_SDIO0_REF_CTRL@0XFF5E006C
+
+31:0
+
+13f3f07
+
+
+
+1023200
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )SDIO1_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO1_REF_CTRL
+
+0XFF5E0070
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+32
+
+3200
+
+6 bit divider
+
    
+PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_SDIO1_REF_CTRL@0XFF5E0070
+
+31:0
+
+13f3f07
+
+
+
+1023200
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )UART0_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART0_REF_CTRL
+
+0XFF5E0074
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_UART0_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_UART0_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_UART0_REF_CTRL@0XFF5E0074
+
+31:0
+
+13f3f07
+
+
+
+1022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )UART1_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART1_REF_CTRL
+
+0XFF5E0078
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_UART1_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_UART1_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_UART1_REF_CTRL@0XFF5E0078
+
+31:0
+
+13f3f07
+
+
+
+1022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )I2C0_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+I2C0_REF_CTRL
+
+0XFF5E0120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_I2C0_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_I2C0_REF_CTRL@0XFF5E0120
+
+31:0
+
+13f3f07
+
+
+
+1022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )I2C1_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+I2C1_REF_CTRL
+
+0XFF5E0124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_I2C1_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+a
+
+a0000
+
+6 bit divider
+
    
+PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+32
+
+3200
+
+6 bit divider
+
    
+PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_I2C1_REF_CTRL@0XFF5E0124
+
+31:0
+
+13f3f07
+
+
+
+10a3200
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )SPI0_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SPI0_REF_CTRL
+
+0XFF5E007C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_SPI0_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_SPI0_REF_CTRL@0XFF5E007C
+
+31:0
+
+13f3f07
+
+
+
+1022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )SPI1_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SPI1_REF_CTRL
+
+0XFF5E0080
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_SPI1_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+a
+
+a0000
+
+6 bit divider
+
    
+PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+32
+
+3200
+
+6 bit divider
+
    
+PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_SPI1_REF_CTRL@0XFF5E0080
+
+31:0
+
+13f3f07
+
+
+
+10a3200
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )CAN0_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CAN0_REF_CTRL
+
+0XFF5E0084
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_CAN0_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_CAN0_REF_CTRL@0XFF5E0084
+
+31:0
+
+13f3f07
+
+
+
+1022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )CAN1_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CAN1_REF_CTRL
+
+0XFF5E0088
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_CAN1_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_CAN1_REF_CTRL@0XFF5E0088
+
+31:0
+
+13f3f07
+
+
+
+1022800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )CPU_R5_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CPU_R5_CTRL
+
+0XFF5E0090
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_CPU_R5_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3f
+
+3f00
+
+6 bit divider
+
    
+PSU_CRL_APB_CPU_R5_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_CPU_R5_CTRL@0XFF5E0090
+
+31:0
+
+1003f07
+
+
+
+1003f02
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )IOU_SWITCH_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IOU_SWITCH_CTRL
+
+0XFF5E009C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+6
+
+600
+
+6 bit divider
+
    
+PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_IOU_SWITCH_CTRL@0XFF5E009C
+
+31:0
+
+1003f07
+
+
+
+1000600
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )PCAP_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CTRL
+
+0XFF5E00A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_PCAP_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_PCAP_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+8
+
+800
+
+6 bit divider
+
    
+PSU_CRL_APB_PCAP_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_PCAP_CTRL@0XFF5E00A4
+
+31:0
+
+1003f07
+
+
+
+1000800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )LPD_SWITCH_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPD_SWITCH_CTRL
+
+0XFF5E00A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+4
+
+400
+
+6 bit divider
+
    
+PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_LPD_SWITCH_CTRL@0XFF5E00A8
+
+31:0
+
+1003f07
+
+
+
+1000402
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )LPD_LSBUS_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPD_LSBUS_CTRL
+
+0XFF5E00AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+6 bit divider
+
    
+PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_LPD_LSBUS_CTRL@0XFF5E00AC
+
+31:0
+
+1003f07
+
+
+
+1001402
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DBG_LPD_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DBG_LPD_CTRL
+
+0XFF5E00B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_DBG_LPD_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3f
+
+3f00
+
+6 bit divider
+
    
+PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_DBG_LPD_CTRL@0XFF5E00B0
+
+31:0
+
+1003f07
+
+
+
+1003f00
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )NAND_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+NAND_REF_CTRL
+
+0XFF5E00B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_NAND_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+32
+
+3200
+
+6 bit divider
+
    
+PSU_CRL_APB_NAND_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_NAND_REF_CTRL@0XFF5E00B4
+
+31:0
+
+13f3f07
+
+
+
+1023200
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )ADMA_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ADMA_REF_CTRL
+
+0XFF5E00B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_ADMA_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+4
+
+400
+
+6 bit divider
+
    
+PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_ADMA_REF_CTRL@0XFF5E00B8
+
+31:0
+
+1003f07
+
+
+
+1000402
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )AMS_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+AMS_REF_CTRL
+
+0XFF5E0108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+1
+
+10000
+
+6 bit divider
+
    
+PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+28
+
+2800
+
+6 bit divider
+
    
+PSU_CRL_APB_AMS_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_AMS_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_AMS_REF_CTRL@0XFF5E0108
+
+31:0
+
+13f3f07
+
+
+
+1012800
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DLL_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_REF_CTRL
+
+0XFF5E0104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_DLL_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_DLL_REF_CTRL@0XFF5E0104
+
+31:0
+
+7
+
+
+
+0
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )TIMESTAMP_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+TIMESTAMP_REF_CTRL
+
+0XFF5E0128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+6 bit divider
+
    
+PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRL_APB_TIMESTAMP_REF_CTRL@0XFF5E0128
+
+31:0
+
+1003f07
+
+
+
+1001402
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )PCIE_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCIE_REF_CTRL
+
+0XFD1A00B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_PCIE_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3f
+
+3f00
+
+6 bit divider
+
    
+PSU_CRF_APB_PCIE_REF_CTRL@0XFD1A00B4
+
+31:0
+
+1003f07
+
+
+
+1003f00
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DP_VIDEO_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DP_VIDEO_REF_CTRL
+
+0XFD1A0070
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+15
+
+150000
+
+6 bit divider
+
    
+PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+32
+
+3200
+
+6 bit divider
+
    
+PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_DP_VIDEO_REF_CTRL@0XFD1A0070
+
+31:0
+
+13f3f07
+
+
+
+1153200
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DP_AUDIO_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DP_AUDIO_REF_CTRL
+
+0XFD1A0074
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+2a
+
+2a00
+
+6 bit divider
+
    
+PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_DP_AUDIO_REF_CTRL@0XFD1A0074
+
+31:0
+
+13f3f07
+
+
+
+1022a00
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DP_STC_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DP_STC_REF_CTRL
+
+0XFD1A007C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1
+
+21:16
+
+3f0000
+
+2
+
+20000
+
+6 bit divider
+
    
+PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+2a
+
+2a00
+
+6 bit divider
+
    
+PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_DP_STC_REF_CTRL@0XFD1A007C
+
+31:0
+
+13f3f07
+
+
+
+1022a00
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )ACPU_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ACPU_CTRL
+
+0XFD1A0060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_ACPU_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3f
+
+3f00
+
+6 bit divider
+
    
+PSU_CRF_APB_ACPU_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
+
    
+PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed clock to the entire APU
+
    
+PSU_CRF_APB_ACPU_CTRL@0XFD1A0060
+
+31:0
+
+3003f07
+
+
+
+3003f00
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DBG_TRACE_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DBG_TRACE_CTRL
+
+0XFD1A0064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3f
+
+3f00
+
+6 bit divider
+
    
+PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_DBG_TRACE_CTRL@0XFD1A0064
+
+31:0
+
+1003f07
+
+
+
+1003f02
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DBG_FPD_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DBG_FPD_CTRL
+
+0XFD1A0068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3f
+
+3f00
+
+6 bit divider
+
    
+PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DBG_FPD_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_DBG_FPD_CTRL@0XFD1A0068
+
+31:0
+
+1003f07
+
+
+
+1003f02
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CTRL
+
+0XFD1A0080
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DDR_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+a
+
+a00
+
+6 bit divider
+
    
+PSU_CRF_APB_DDR_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DDR_CTRL@0XFD1A0080
+
+31:0
+
+3f07
+
+
+
+a00
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )GPU_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GPU_REF_CTRL
+
+0XFD1A0084
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3f
+
+3f00
+
+6 bit divider
+
    
+PSU_CRF_APB_GPU_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_GPU_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below
+
    
+PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active signal for Pixel Processor. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+Clock active signal for Pixel Processor. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_GPU_REF_CTRL@0XFD1A0084
+
+31:0
+
+7003f07
+
+
+
+7003f02
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )GDMA_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GDMA_REF_CTRL
+
+0XFD1A00B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3
+
+300
+
+6 bit divider
+
    
+PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+3
+
+3
+
+000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_GDMA_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_GDMA_REF_CTRL@0XFD1A00B8
+
+31:0
+
+1003f07
+
+
+
+1000303
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DPDMA_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DPDMA_REF_CTRL
+
+0XFD1A00BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3
+
+300
+
+6 bit divider
+
    
+PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+3
+
+3
+
+000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_DPDMA_REF_CTRL@0XFD1A00BC
+
+31:0
+
+1003f07
+
+
+
+1000303
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )TOPSW_MAIN_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+TOPSW_MAIN_CTRL
+
+0XFD1A00C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+3
+
+300
+
+6 bit divider
+
    
+PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL
+
+2:0
+
+7
+
+3
+
+3
+
+000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_TOPSW_MAIN_CTRL@0XFD1A00C0
+
+31:0
+
+1003f07
+
+
+
+1000303
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )TOPSW_LSBUS_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+TOPSW_LSBUS_CTRL
+
+0XFD1A00C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+6 bit divider
+
    
+PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL
+
+2:0
+
+7
+
+0
+
+0
+
+000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_TOPSW_LSBUS_CTRL@0XFD1A00C4
+
+31:0
+
+1003f07
+
+
+
+1001400
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )GTGREF0_REF_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GTGREF0_REF_CTRL
+
+0XFD1A00C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+11
+
+1100
+
+6 bit divider
+
    
+PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active signal. Switch to 0 to disable the clock
+
    
+PSU_CRF_APB_GTGREF0_REF_CTRL@0XFD1A00C8
+
+31:0
+
+1003f07
+
+
+
+1001102
+
+This register controls this reference clock
+
    
+
    
+
    Register ( slcr )DBG_TSTMP_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DBG_TSTMP_CTRL
+
+0XFD1A00F8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0
+
+13:8
+
+3f00
+
+8
+
+800
+
+6 bit divider
+
    
+PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL
+
+2:0
+
+7
+
+2
+
+2
+
+000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+
    
+PSU_CRF_APB_DBG_TSTMP_CTRL@0XFD1A00F8
+
+31:0
+
+3f07
+
+
+
+802
+
+This register controls this reference clock
+
    
+
    
+
+
    
+
    psu_ddr_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
    
+
    psu_ddr_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
    
+
    psu_mio_init_data
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+PSU_IOU_SLCR_MIO_PIN_0
+
+
+0XFF180000
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 0 peripheral interface mapping. S
+
    
+
+PSU_IOU_SLCR_MIO_PIN_1
+
+
+0XFF180004
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 1 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_2
+
+
+0XFF180008
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 2 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_3
+
+
+0XFF18000C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 3 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_4
+
+
+0XFF180010
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 4 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_5
+
+
+0XFF180014
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 5 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_6
+
+
+0XFF180018
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 6 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_7
+
+
+0XFF18001C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 7 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_8
+
+
+0XFF180020
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 8 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_9
+
+
+0XFF180024
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 9 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_10
+
+
+0XFF180028
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 10 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_11
+
+
+0XFF18002C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 11 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_12
+
+
+0XFF180030
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 12 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_13
+
+
+0XFF180034
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 13 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_14
+
+
+0XFF180038
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 14 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_15
+
+
+0XFF18003C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 15 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_16
+
+
+0XFF180040
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 16 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_17
+
+
+0XFF180044
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 17 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_18
+
+
+0XFF180048
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 18 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_19
+
+
+0XFF18004C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 19 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_20
+
+
+0XFF180050
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 20 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_21
+
+
+0XFF180054
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 21 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_22
+
+
+0XFF180058
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 22 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_23
+
+
+0XFF18005C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 23 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_24
+
+
+0XFF180060
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 24 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_25
+
+
+0XFF180064
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 25 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_26
+
+
+0XFF180068
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 26 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_27
+
+
+0XFF18006C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 27 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_28
+
+
+0XFF180070
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 28 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_29
+
+
+0XFF180074
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 29 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_30
+
+
+0XFF180078
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 30 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_31
+
+
+0XFF18007C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 31 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_32
+
+
+0XFF180080
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 32 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_33
+
+
+0XFF180084
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 33 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_34
+
+
+0XFF180088
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 34 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_35
+
+
+0XFF18008C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 35 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_36
+
+
+0XFF180090
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 36 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_37
+
+
+0XFF180094
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 37 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_38
+
+
+0XFF180098
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 38 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_39
+
+
+0XFF18009C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 39 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_40
+
+
+0XFF1800A0
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 40 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_41
+
+
+0XFF1800A4
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 41 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_42
+
+
+0XFF1800A8
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 42 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_43
+
+
+0XFF1800AC
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 43 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_44
+
+
+0XFF1800B0
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 44 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_45
+
+
+0XFF1800B4
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 45 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_46
+
+
+0XFF1800B8
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 46 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_47
+
+
+0XFF1800BC
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 47 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_48
+
+
+0XFF1800C0
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 48 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_49
+
+
+0XFF1800C4
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 49 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_50
+
+
+0XFF1800C8
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 50 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_51
+
+
+0XFF1800CC
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 51 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_52
+
+
+0XFF1800D0
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 52 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_53
+
+
+0XFF1800D4
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 53 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_54
+
+
+0XFF1800D8
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 54 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_55
+
+
+0XFF1800DC
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 55 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_56
+
+
+0XFF1800E0
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 56 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_57
+
+
+0XFF1800E4
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 57 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_58
+
+
+0XFF1800E8
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 58 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_59
+
+
+0XFF1800EC
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 59 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_60
+
+
+0XFF1800F0
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 60 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_61
+
+
+0XFF1800F4
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 61 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_62
+
+
+0XFF1800F8
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 62 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_63
+
+
+0XFF1800FC
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 63 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_64
+
+
+0XFF180100
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 64 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_65
+
+
+0XFF180104
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 65 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_66
+
+
+0XFF180108
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 66 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_67
+
+
+0XFF18010C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 67 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_68
+
+
+0XFF180110
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 68 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_69
+
+
+0XFF180114
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 69 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_70
+
+
+0XFF180118
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 70 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_71
+
+
+0XFF18011C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 71 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_72
+
+
+0XFF180120
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 72 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_73
+
+
+0XFF180124
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 73 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_74
+
+
+0XFF180128
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 74 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_75
+
+
+0XFF18012C
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 75 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_76
+
+
+0XFF180130
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 76 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_PIN_77
+
+
+0XFF180134
+
+32
+
+RW
+
+0x000000
+
+Configures MIO Pin 77 peripheral interface mapping
+
    
+
+PSU_IOU_SLCR_MIO_MST_TRI0
+
+
+0XFF180204
+
+32
+
+RW
+
+0x000000
+
+MIO pin Tri-state Enables, 31:0
+
    
+
+PSU_IOU_SLCR_MIO_MST_TRI1
+
+
+0XFF180208
+
+32
+
+RW
+
+0x000000
+
+MIO pin Tri-state Enables, 63:32
+
    
+
+PSU_IOU_SLCR_MIO_MST_TRI2
+
+
+0XFF18020C
+
+32
+
+RW
+
+0x000000
+
+MIO pin Tri-state Enables, 77:64
+
    
+
+PSU_IOU_SLCR_MIO_LOOPBACK
+
+
+0XFF180200
+
+32
+
+RW
+
+0x000000
+
+Loopback function within MIO
+
    
+
    
+
    psu_mio_init_data
    
+
+
+
+
+
+
+
+
+
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_0
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_0
+
+0XFF180000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_0_L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_0_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_0_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_0_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_clk- (Trace Port Clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_0@0XFF180000
+
+31:0
+
+fe
+
+
+
+2
+
+Configures MIO Pin 0 peripheral interface mapping. S
+
    
+
    
+
    Register ( slcr )MIO_PIN_1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_1
+
+0XFF180004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_1_L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_1_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_1_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_1_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control Signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_1@0XFF180004
+
+31:0
+
+fe
+
+
+
+2
+
+Configures MIO Pin 1 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_2
+
+0XFF180008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_2_L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_2_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_2_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_2_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_2@0XFF180008
+
+31:0
+
+fe
+
+
+
+2
+
+Configures MIO Pin 2 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_3
+
+0XFF18000C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_3_L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_3_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_3_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_3_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_3@0XFF18000C
+
+31:0
+
+fe
+
+
+
+2
+
+Configures MIO Pin 3 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_4
+
+0XFF180010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_4_L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_4_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_4_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_4_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[2]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_4@0XFF180010
+
+31:0
+
+fe
+
+
+
+2
+
+Configures MIO Pin 4 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_5
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_5
+
+0XFF180014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_5_L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
+
    
+PSU_IOU_SLCR_MIO_PIN_5_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_5_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_5_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[3]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_5@0XFF180014
+
+31:0
+
+fe
+
+
+
+2
+
+Configures MIO Pin 5 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_6
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_6
+
+0XFF180018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_6_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
+
    
+PSU_IOU_SLCR_MIO_PIN_6_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_6_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_6_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_6@0XFF180018
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 6 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_7
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_7
+
+0XFF18001C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_7_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
+
    
+PSU_IOU_SLCR_MIO_PIN_7_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_7_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_7_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_7@0XFF18001C
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 7 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_8
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_8
+
+0XFF180020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_8_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_8_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_8_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_8_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_8@0XFF180020
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 8 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_9
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_9
+
+0XFF180024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_9_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_9_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+
    
+PSU_IOU_SLCR_MIO_PIN_9_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_9_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_9@0XFF180024
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 9 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XFF180028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_10_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_10_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+
    
+PSU_IOU_SLCR_MIO_PIN_10_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[10]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_10_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_10@0XFF180028
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 10 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XFF18002C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_11_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_11_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+
    
+PSU_IOU_SLCR_MIO_PIN_11_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[11]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_11_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_11@0XFF18002C
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 11 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XFF180030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_12_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_12_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
+
    
+PSU_IOU_SLCR_MIO_PIN_12_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[12]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_12_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_12@0XFF180030
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 12 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XFF180034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_13_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_13_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
+
    
+PSU_IOU_SLCR_MIO_PIN_13_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_13_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_13@0XFF180034
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 13 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XFF180038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_14_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_14_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
+
    
+PSU_IOU_SLCR_MIO_PIN_14_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_14_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_14@0XFF180038
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 14 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XFF18003C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_15_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_15_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
+
    
+PSU_IOU_SLCR_MIO_PIN_15_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_15_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_15@0XFF18003C
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 15 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XFF180040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_16_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_16_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_16_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_16_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_16@0XFF180040
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 16 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XFF180044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_17_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_17_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_17_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_17_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_17@0XFF180044
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 17 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XFF180048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_18_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_18_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_18_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_18_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_18@0XFF180048
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 18 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XFF18004C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_19_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_19_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_19_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_19_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_19@0XFF18004C
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 19 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XFF180050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_20_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_20_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_20_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_20_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_20@0XFF180050
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 20 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XFF180054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_21_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_21_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_21_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_21_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_21@0XFF180054
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 21 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XFF180058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_22_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_22_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
+
    
+PSU_IOU_SLCR_MIO_PIN_22_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_22_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_22@0XFF180058
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 22 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XFF18005C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_23_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_23_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_23_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_23_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_23@0XFF18005C
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 23 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XFF180060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_24_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_24_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_24_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_24_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_24@0XFF180060
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 24 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XFF180064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_25_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_25_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
+
    
+PSU_IOU_SLCR_MIO_PIN_25_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_25_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_25@0XFF180064
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 25 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XFF180068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_26_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_26_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+
    
+PSU_IOU_SLCR_MIO_PIN_26_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_26_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_26@0XFF180068
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 26 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XFF18006C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_27_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_27_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+
    
+PSU_IOU_SLCR_MIO_PIN_27_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
+
    
+PSU_IOU_SLCR_MIO_PIN_27_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_27@0XFF18006C
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 27 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XFF180070
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_28_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_28_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+
    
+PSU_IOU_SLCR_MIO_PIN_28_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+
    
+PSU_IOU_SLCR_MIO_PIN_28_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_28@0XFF180070
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 28 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XFF180074
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_29_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_29_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_29_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
+
    
+PSU_IOU_SLCR_MIO_PIN_29_L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_29@0XFF180074
+
+31:0
+
+fe
+
+
+
+80
+
+Configures MIO Pin 29 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XFF180078
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_30_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_30_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_30_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+
    
+PSU_IOU_SLCR_MIO_PIN_30_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_30@0XFF180078
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 30 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XFF18007C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_31_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
+
    
+PSU_IOU_SLCR_MIO_PIN_31_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_31_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_31_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_31@0XFF18007C
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 31 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XFF180080
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_32_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_32_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
+
    
+PSU_IOU_SLCR_MIO_PIN_32_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_32_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_32@0XFF180080
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 32 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XFF180084
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_33_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_33_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_33_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+
    
+PSU_IOU_SLCR_MIO_PIN_33_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_33@0XFF180084
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 33 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XFF180088
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_34_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_34_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_34_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
+
    
+PSU_IOU_SLCR_MIO_PIN_34_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_34@0XFF180088
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 34 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XFF18008C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_35_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_35_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_35_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+
    
+PSU_IOU_SLCR_MIO_PIN_35_L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_35@0XFF18008C
+
+31:0
+
+fe
+
+
+
+80
+
+Configures MIO Pin 35 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XFF180090
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_36_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_36_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_36_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
+
    
+PSU_IOU_SLCR_MIO_PIN_36_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_36@0XFF180090
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 36 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XFF180094
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_37_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
+
    
+PSU_IOU_SLCR_MIO_PIN_37_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_37_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+
    
+PSU_IOU_SLCR_MIO_PIN_37_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_37@0XFF180094
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 37 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XFF180098
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_38_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_38_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_38_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_38_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- (Trace Port Clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_38@0XFF180098
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 38 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XFF18009C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_39_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_39_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_39_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_39_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port Control Signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_39@0XFF18009C
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 39 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XFF1800A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_40_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_40_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_40_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_40_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_40@0XFF1800A0
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 40 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XFF1800A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_41_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_41_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_41_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_41_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_41@0XFF1800A4
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 41 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XFF1800A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_42_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_42_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_42_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_42_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[2]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_42@0XFF1800A8
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 42 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XFF1800AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_43_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
+
    
+PSU_IOU_SLCR_MIO_PIN_43_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_43_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_43_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[3]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_43@0XFF1800AC
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 43 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XFF1800B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_44_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_44_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_44_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_44_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_44@0XFF1800B0
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 44 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XFF1800B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_45_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_45_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_45_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_45_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_45@0XFF1800B4
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 45 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XFF1800B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_46_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_46_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_46_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_46_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_46@0XFF1800B8
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 46 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XFF1800BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_47_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_47_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_47_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_47_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_47@0XFF1800BC
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 47 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XFF1800C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_48_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_48_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_48_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_48_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_48@0XFF1800C0
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 48 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XFF1800C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_49_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
+
    
+PSU_IOU_SLCR_MIO_PIN_49_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_49_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_49_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_49@0XFF1800C4
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 49 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XFF1800C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_50_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_50_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_50_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_50_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_50@0XFF1800C8
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 50 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XFF1800CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_51_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_51_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_51_L2_SEL
+
+4:3
+
+18
+
+2
+
+10
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_51_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_51@0XFF1800CC
+
+31:0
+
+fe
+
+
+
+10
+
+Configures MIO Pin 51 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XFF1800D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_52_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_52_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_52_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_52_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_clk- (Trace Port Clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_52@0XFF1800D0
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 52 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XFF1800D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_53_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_53_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
+
    
+PSU_IOU_SLCR_MIO_PIN_53_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_53_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control Signal)
+
    
+PSU_IOU_SLCR_MIO_PIN_53@0XFF1800D4
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 53 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_54
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_54
+
+0XFF1800D8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_54_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_54_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_54_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_54_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_54@0XFF1800D8
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 54 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_55
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_55
+
+0XFF1800DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_55_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_55_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
+
    
+PSU_IOU_SLCR_MIO_PIN_55_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_55_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_55@0XFF1800DC
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 55 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_56
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_56
+
+0XFF1800E0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_56_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_56_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_56_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_56_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[2]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_56@0XFF1800E0
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 56 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_57
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_57
+
+0XFF1800E4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_57_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
+
    
+PSU_IOU_SLCR_MIO_PIN_57_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_57_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_57_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[3]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_57@0XFF1800E4
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 57 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_58
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_58
+
+0XFF1800E8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_58_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_58_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
+
    
+PSU_IOU_SLCR_MIO_PIN_58_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_58_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_58@0XFF1800E8
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 58 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_59
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_59
+
+0XFF1800EC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_59_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_59_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_59_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_59_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_59@0XFF1800EC
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 59 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_60
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_60
+
+0XFF1800F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_60_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_60_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_60_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_60_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_60@0XFF1800F0
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 60 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_61
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_61
+
+0XFF1800F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_61_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_61_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_61_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_61_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_61@0XFF1800F4
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 61 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_62
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_62
+
+0XFF1800F8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_62_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_62_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_62_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_62_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_62@0XFF1800F8
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 62 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_63
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_63
+
+0XFF1800FC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_63_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
+
    
+PSU_IOU_SLCR_MIO_PIN_63_L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_63_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_63_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_63@0XFF1800FC
+
+31:0
+
+fe
+
+
+
+4
+
+Configures MIO Pin 63 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_64
+
+0XFF180100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_64_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_64_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_64_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_64_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_64@0XFF180100
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 64 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_65
+
+0XFF180104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_65_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_65_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
+
    
+PSU_IOU_SLCR_MIO_PIN_65_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_65_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_65@0XFF180104
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 65 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_66
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_66
+
+0XFF180108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_66_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_66_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_66_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_66_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_66@0XFF180108
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 66 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_67
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_67
+
+0XFF18010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_67_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_67_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
+
    
+PSU_IOU_SLCR_MIO_PIN_67_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_67_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_67@0XFF18010C
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 67 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_68
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_68
+
+0XFF180110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_68_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_68_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_68_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= Not Used 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_68_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_68@0XFF180110
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 68 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_69
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_69
+
+0XFF180114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_69_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
+
    
+PSU_IOU_SLCR_MIO_PIN_69_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_69_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_69_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)
+
    
+PSU_IOU_SLCR_MIO_PIN_69@0XFF180114
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 69 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_70
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_70
+
+0XFF180118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_70_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
+
    
+PSU_IOU_SLCR_MIO_PIN_70_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
+
    
+PSU_IOU_SLCR_MIO_PIN_70_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_70_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_70@0XFF180118
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 70 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_71
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_71
+
+0XFF18011C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_71_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_71_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_71_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_71_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_71@0XFF18011C
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 71 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_72
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_72
+
+0XFF180120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_72_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_72_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_72_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_72_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_72@0XFF180120
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 72 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_73
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_73
+
+0XFF180124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_73_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_73_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_73_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_73_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_73@0XFF180124
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 73 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_74
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_74
+
+0XFF180128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_74_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
+
    
+PSU_IOU_SLCR_MIO_PIN_74_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_74_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_74_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_74@0XFF180128
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 74 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_75
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_75
+
+0XFF18012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_75_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
+
    
+PSU_IOU_SLCR_MIO_PIN_75_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)
+
    
+PSU_IOU_SLCR_MIO_PIN_75_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_75_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_75@0XFF18012C
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 75 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_76
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_76
+
+0XFF180130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_76_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_76_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_76_L2_SEL
+
+4:3
+
+18
+
+1
+
+8
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_76_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_76@0XFF180130
+
+31:0
+
+fe
+
+
+
+8
+
+Configures MIO Pin 76 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_PIN_77
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_77
+
+0XFF180134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_PIN_77_L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_77_L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_77_L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_77_L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_out- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
+
    
+PSU_IOU_SLCR_MIO_PIN_77@0XFF180134
+
+31:0
+
+fe
+
+
+
+0
+
+Configures MIO Pin 77 peripheral interface mapping
+
    
+
    
+
    Register ( slcr )MIO_MST_TRI0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_MST_TRI0
+
+0XFF180204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI
+
+0:0
+
+1
+
+0
+
+0
+
+Master Tri-state Enable for pin 0, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI
+
+1:1
+
+2
+
+0
+
+0
+
+Master Tri-state Enable for pin 1, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+Master Tri-state Enable for pin 2, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+Master Tri-state Enable for pin 3, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI
+
+4:4
+
+10
+
+0
+
+0
+
+Master Tri-state Enable for pin 4, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI
+
+5:5
+
+20
+
+0
+
+0
+
+Master Tri-state Enable for pin 5, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI
+
+6:6
+
+40
+
+0
+
+0
+
+Master Tri-state Enable for pin 6, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI
+
+7:7
+
+80
+
+0
+
+0
+
+Master Tri-state Enable for pin 7, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI
+
+8:8
+
+100
+
+0
+
+0
+
+Master Tri-state Enable for pin 8, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI
+
+9:9
+
+200
+
+0
+
+0
+
+Master Tri-state Enable for pin 9, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI
+
+10:10
+
+400
+
+1
+
+400
+
+Master Tri-state Enable for pin 10, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI
+
+11:11
+
+800
+
+1
+
+800
+
+Master Tri-state Enable for pin 11, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI
+
+12:12
+
+1000
+
+0
+
+0
+
+Master Tri-state Enable for pin 12, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI
+
+13:13
+
+2000
+
+0
+
+0
+
+Master Tri-state Enable for pin 13, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI
+
+14:14
+
+4000
+
+0
+
+0
+
+Master Tri-state Enable for pin 14, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI
+
+15:15
+
+8000
+
+0
+
+0
+
+Master Tri-state Enable for pin 15, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI
+
+16:16
+
+10000
+
+0
+
+0
+
+Master Tri-state Enable for pin 16, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI
+
+17:17
+
+20000
+
+0
+
+0
+
+Master Tri-state Enable for pin 17, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI
+
+18:18
+
+40000
+
+0
+
+0
+
+Master Tri-state Enable for pin 18, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI
+
+19:19
+
+80000
+
+0
+
+0
+
+Master Tri-state Enable for pin 19, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI
+
+20:20
+
+100000
+
+0
+
+0
+
+Master Tri-state Enable for pin 20, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI
+
+21:21
+
+200000
+
+0
+
+0
+
+Master Tri-state Enable for pin 21, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI
+
+22:22
+
+400000
+
+0
+
+0
+
+Master Tri-state Enable for pin 22, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI
+
+23:23
+
+800000
+
+0
+
+0
+
+Master Tri-state Enable for pin 23, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI
+
+24:24
+
+1000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 24, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI
+
+25:25
+
+2000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 25, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI
+
+26:26
+
+4000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 26, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI
+
+27:27
+
+8000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 27, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI
+
+28:28
+
+10000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 28, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI
+
+29:29
+
+20000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 29, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI
+
+30:30
+
+40000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 30, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI
+
+31:31
+
+80000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 31, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI0@0XFF180204
+
+31:0
+
+ffffffff
+
+
+
+c00
+
+MIO pin Tri-state Enables, 31:0
+
    
+
    
+
    Register ( slcr )MIO_MST_TRI1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_MST_TRI1
+
+0XFF180208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI
+
+0:0
+
+1
+
+0
+
+0
+
+Master Tri-state Enable for pin 32, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI
+
+1:1
+
+2
+
+0
+
+0
+
+Master Tri-state Enable for pin 33, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+Master Tri-state Enable for pin 34, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+Master Tri-state Enable for pin 35, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI
+
+4:4
+
+10
+
+0
+
+0
+
+Master Tri-state Enable for pin 36, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI
+
+5:5
+
+20
+
+0
+
+0
+
+Master Tri-state Enable for pin 37, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI
+
+6:6
+
+40
+
+0
+
+0
+
+Master Tri-state Enable for pin 38, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI
+
+7:7
+
+80
+
+0
+
+0
+
+Master Tri-state Enable for pin 39, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI
+
+8:8
+
+100
+
+0
+
+0
+
+Master Tri-state Enable for pin 40, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI
+
+9:9
+
+200
+
+0
+
+0
+
+Master Tri-state Enable for pin 41, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI
+
+10:10
+
+400
+
+0
+
+0
+
+Master Tri-state Enable for pin 42, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI
+
+11:11
+
+800
+
+0
+
+0
+
+Master Tri-state Enable for pin 43, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI
+
+12:12
+
+1000
+
+0
+
+0
+
+Master Tri-state Enable for pin 44, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI
+
+13:13
+
+2000
+
+0
+
+0
+
+Master Tri-state Enable for pin 45, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI
+
+14:14
+
+4000
+
+0
+
+0
+
+Master Tri-state Enable for pin 46, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI
+
+15:15
+
+8000
+
+0
+
+0
+
+Master Tri-state Enable for pin 47, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI
+
+16:16
+
+10000
+
+0
+
+0
+
+Master Tri-state Enable for pin 48, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI
+
+17:17
+
+20000
+
+0
+
+0
+
+Master Tri-state Enable for pin 49, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI
+
+18:18
+
+40000
+
+0
+
+0
+
+Master Tri-state Enable for pin 50, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI
+
+19:19
+
+80000
+
+0
+
+0
+
+Master Tri-state Enable for pin 51, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI
+
+20:20
+
+100000
+
+1
+
+100000
+
+Master Tri-state Enable for pin 52, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI
+
+21:21
+
+200000
+
+1
+
+200000
+
+Master Tri-state Enable for pin 53, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI
+
+22:22
+
+400000
+
+0
+
+0
+
+Master Tri-state Enable for pin 54, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI
+
+23:23
+
+800000
+
+1
+
+800000
+
+Master Tri-state Enable for pin 55, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI
+
+24:24
+
+1000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 56, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI
+
+25:25
+
+2000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 57, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI
+
+26:26
+
+4000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 58, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI
+
+27:27
+
+8000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 59, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI
+
+28:28
+
+10000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 60, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI
+
+29:29
+
+20000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 61, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI
+
+30:30
+
+40000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 62, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI
+
+31:31
+
+80000000
+
+0
+
+0
+
+Master Tri-state Enable for pin 63, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI1@0XFF180208
+
+31:0
+
+ffffffff
+
+
+
+b00000
+
+MIO pin Tri-state Enables, 63:32
+
    
+
    
+
    Register ( slcr )MIO_MST_TRI2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_MST_TRI2
+
+0XFF18020C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI
+
+0:0
+
+1
+
+0
+
+0
+
+Master Tri-state Enable for pin 64, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI
+
+1:1
+
+2
+
+1
+
+2
+
+Master Tri-state Enable for pin 65, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+Master Tri-state Enable for pin 66, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+Master Tri-state Enable for pin 67, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI
+
+4:4
+
+10
+
+0
+
+0
+
+Master Tri-state Enable for pin 68, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI
+
+5:5
+
+20
+
+0
+
+0
+
+Master Tri-state Enable for pin 69, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI
+
+6:6
+
+40
+
+0
+
+0
+
+Master Tri-state Enable for pin 70, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI
+
+7:7
+
+80
+
+0
+
+0
+
+Master Tri-state Enable for pin 71, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI
+
+8:8
+
+100
+
+0
+
+0
+
+Master Tri-state Enable for pin 72, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI
+
+9:9
+
+200
+
+0
+
+0
+
+Master Tri-state Enable for pin 73, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI
+
+10:10
+
+400
+
+0
+
+0
+
+Master Tri-state Enable for pin 74, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI
+
+11:11
+
+800
+
+0
+
+0
+
+Master Tri-state Enable for pin 75, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI
+
+12:12
+
+1000
+
+1
+
+1000
+
+Master Tri-state Enable for pin 76, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI
+
+13:13
+
+2000
+
+0
+
+0
+
+Master Tri-state Enable for pin 77, active high
+
    
+PSU_IOU_SLCR_MIO_MST_TRI2@0XFF18020C
+
+31:0
+
+3fff
+
+
+
+1002
+
+MIO pin Tri-state Enables, 77:64
+
    
+
    
+
    LOOPBACK
    
+
    Register ( slcr )MIO_LOOPBACK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_LOOPBACK
+
+0XFF180200
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1
+
+3:3
+
+8
+
+0
+
+0
+
+I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs.
+
    
+PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1
+
+2:2
+
+4
+
+0
+
+0
+
+CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.
+
    
+PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1
+
+1:1
+
+2
+
+0
+
+0
+
+UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
+
    
+PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1
+
+0:0
+
+1
+
+0
+
+0
+
+SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
+
    
+PSU_IOU_SLCR_MIO_LOOPBACK@0XFF180200
+
+31:0
+
+f
+
+
+
+0
+
+Loopback function within MIO
+
    
+
    
+
+
    
+
    psu_peripherals_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+PSU_CRL_APB_RST_LPD_IOU0
+
+
+0XFF5E0230
+
+32
+
+RW
+
+0x000000
+
+Software controlled reset for the GEMs
+
    
+
+PSU_CRL_APB_RST_LPD_IOU2
+
+
+0XFF5E0238
+
+32
+
+RW
+
+0x000000
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
+PSU_CRL_APB_RST_LPD_IOU2
+
+
+0XFF5E0238
+
+32
+
+RW
+
+0x000000
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
+PSU_CRL_APB_RST_LPD_TOP
+
+
+0XFF5E023C
+
+32
+
+RW
+
+0x000000
+
+Software control register for the LPD block.
+
    
+
+PSU_CRL_APB_RST_LPD_IOU2
+
+
+0XFF5E0238
+
+32
+
+RW
+
+0x000000
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
+PSU_IOU_SLCR_CTRL_REG_SD
+
+
+0XFF180310
+
+32
+
+RW
+
+0x000000
+
+SD eMMC selection
+
    
+
+PSU_IOU_SLCR_SD_CONFIG_REG2
+
+
+0XFF180320
+
+32
+
+RW
+
+0x000000
+
+SD Config Register 2
+
    
+
+PSU_CRL_APB_RST_LPD_IOU2
+
+
+0XFF5E0238
+
+32
+
+RW
+
+0x000000
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
+PSU_CRL_APB_RST_LPD_IOU2
+
+
+0XFF5E0238
+
+32
+
+RW
+
+0x000000
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
+PSU_CRL_APB_RST_LPD_IOU2
+
+
+0XFF5E0238
+
+32
+
+RW
+
+0x000000
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
+PSU_CRL_APB_RST_LPD_IOU2
+
+
+0XFF5E0238
+
+32
+
+RW
+
+0x000000
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
+PSU_CRL_APB_RST_LPD_IOU2
+
+
+0XFF5E0238
+
+32
+
+RW
+
+0x000000
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
+PSU_UART0_BAUD_RATE_DIVIDER_REG0
+
+
+0XFF000034
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Divider Register
+
    
+
+PSU_UART0_BAUD_RATE_GEN_REG0
+
+
+0XFF000018
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Generator Register.
+
    
+
+PSU_UART0_CONTROL_REG0
+
+
+0XFF000000
+
+32
+
+RW
+
+0x000000
+
+UART Control Register
+
    
+
+PSU_UART0_MODE_REG0
+
+
+0XFF000004
+
+32
+
+RW
+
+0x000000
+
+UART Mode Register
+
    
+
+PSU_UART1_BAUD_RATE_DIVIDER_REG0
+
+
+0XFF010034
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Divider Register
+
    
+
+PSU_UART1_BAUD_RATE_GEN_REG0
+
+
+0XFF010018
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Generator Register.
+
    
+
+PSU_UART1_CONTROL_REG0
+
+
+0XFF010000
+
+32
+
+RW
+
+0x000000
+
+UART Control Register
+
    
+
+PSU_UART1_MODE_REG0
+
+
+0XFF010004
+
+32
+
+RW
+
+0x000000
+
+UART Mode Register
+
    
+
+PSU_LPD_SLCR_SECURE_SLCR_ADMA
+
+
+0XFF4B0024
+
+32
+
+RW
+
+0x000000
+
+RPU TrustZone settings
+
    
+
+PSU_CSU_TAMPER_STATUS
+
+
+0XFFCA5000
+
+32
+
+RW
+
+0x000000
+
+Tamper Response Status
+
    
+
    
+
    psu_peripherals_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    ENET
    
+
    Register ( slcr )RST_LPD_IOU0
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_IOU0
+
+0XFF5E0230
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_IOU0_GEM0_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+GEM 0 reset
+
    
+PSU_CRL_APB_RST_LPD_IOU0_GEM1_RESET
+
+1:1
+
+2
+
+0
+
+0
+
+GEM 1 reset
+
    
+PSU_CRL_APB_RST_LPD_IOU0_GEM2_RESET
+
+2:2
+
+4
+
+0
+
+0
+
+GEM 2 reset
+
    
+PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET
+
+3:3
+
+8
+
+0
+
+0
+
+GEM 3 reset
+
    
+PSU_CRL_APB_RST_LPD_IOU0@0XFF5E0230
+
+31:0
+
+f
+
+
+
+0
+
+Software controlled reset for the GEMs
+
    
+
    
+
    QSPI
    
+
    Register ( slcr )RST_LPD_IOU2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_IOU2
+
+0XFF5E0238
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238
+
+31:0
+
+1
+
+
+
+0
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
    
+
    NAND
    
+
    Register ( slcr )RST_LPD_IOU2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_IOU2
+
+0XFF5E0238
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_IOU2_NAND_RESET
+
+16:16
+
+10000
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238
+
+31:0
+
+10000
+
+
+
+0
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
    
+
    USB
    
+
    Register ( slcr )RST_LPD_TOP
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_TOP
+
+0XFF5E023C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET
+
+10:10
+
+400
+
+0
+
+0
+
+USB 0 reset for control registers
+
    
+PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET
+
+8:8
+
+100
+
+0
+
+0
+
+USB 0 sleep circuit reset
+
    
+PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET
+
+6:6
+
+40
+
+0
+
+0
+
+USB 0 reset
+
    
+PSU_CRL_APB_RST_LPD_TOP@0XFF5E023C
+
+31:0
+
+540
+
+
+
+0
+
+Software control register for the LPD block.
+
    
+
    
+
    SD
    
+
    Register ( slcr )RST_LPD_IOU2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_IOU2
+
+0XFF5E0238
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_IOU2_SDIO0_RESET
+
+5:5
+
+20
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET
+
+6:6
+
+40
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238
+
+31:0
+
+60
+
+
+
+0
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
    
+
    Register ( slcr )CTRL_REG_SD
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL_REG_SD
+
+0XFF180310
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL
+
+0:0
+
+1
+
+0
+
+0
+
+SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled
+
    
+PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL
+
+15:15
+
+8000
+
+0
+
+0
+
+SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
+
    
+PSU_IOU_SLCR_CTRL_REG_SD@0XFF180310
+
+31:0
+
+8001
+
+
+
+0
+
+SD eMMC selection
+
    
+
    
+
    Register ( slcr )SD_CONFIG_REG2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD_CONFIG_REG2
+
+0XFF180320
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE
+
+13:12
+
+3000
+
+0
+
+0
+
+Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
+
    
+PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE
+
+29:28
+
+30000000
+
+0
+
+0
+
+Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
+
    
+PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V
+
+9:9
+
+200
+
+1
+
+200
+
+1.8V Support 1: 1.8V supported 0: 1.8V not supported support
+
    
+PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V
+
+8:8
+
+100
+
+0
+
+0
+
+3.0V Support 1: 3.0V supported 0: 3.0V not supported support
+
    
+PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V
+
+7:7
+
+80
+
+1
+
+80
+
+3.3V Support 1: 3.3V supported 0: 3.3V not supported support
+
    
+PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+1.8V Support 1: 1.8V supported 0: 1.8V not supported support
+
    
+PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V
+
+24:24
+
+1000000
+
+0
+
+0
+
+3.0V Support 1: 3.0V supported 0: 3.0V not supported support
+
    
+PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V
+
+23:23
+
+800000
+
+1
+
+800000
+
+3.3V Support 1: 3.3V supported 0: 3.3V not supported support
+
    
+PSU_IOU_SLCR_SD_CONFIG_REG2@0XFF180320
+
+31:0
+
+33803380
+
+
+
+2800280
+
+SD Config Register 2
+
    
+
    
+
    CAN
    
+
    Register ( slcr )RST_LPD_IOU2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_IOU2
+
+0XFF5E0238
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_IOU2_CAN0_RESET
+
+7:7
+
+80
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET
+
+8:8
+
+100
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238
+
+31:0
+
+180
+
+
+
+0
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
    
+
    I2C
    
+
    Register ( slcr )RST_LPD_IOU2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_IOU2
+
+0XFF5E0238
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET
+
+9:9
+
+200
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET
+
+10:10
+
+400
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238
+
+31:0
+
+600
+
+
+
+0
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
    
+
    SWDT
    
+
    SPI
    
+
    Register ( slcr )RST_LPD_IOU2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_IOU2
+
+0XFF5E0238
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_IOU2_SPI0_RESET
+
+3:3
+
+8
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2_SPI1_RESET
+
+4:4
+
+10
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238
+
+31:0
+
+18
+
+
+
+0
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
    
+
    TTC
    
+
    Register ( slcr )RST_LPD_IOU2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_IOU2
+
+0XFF5E0238
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET
+
+11:11
+
+800
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET
+
+12:12
+
+1000
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET
+
+13:13
+
+2000
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET
+
+14:14
+
+4000
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238
+
+31:0
+
+7800
+
+
+
+0
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
    
+
    UART
    
+
    Register ( slcr )RST_LPD_IOU2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+RST_LPD_IOU2
+
+0XFF5E0238
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET
+
+1:1
+
+2
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET
+
+2:2
+
+4
+
+0
+
+0
+
+Block level reset
+
    
+PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238
+
+31:0
+
+6
+
+
+
+0
+
+Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+
    
+
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XFF000034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV
+
+7:0
+
+ff
+
+0
+
+0
+
+Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+
    
+PSU_UART0_BAUD_RATE_DIVIDER_REG0@0XFF000034
+
+31:0
+
+ff
+
+
+
+0
+
+Baud Rate Divider Register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XFF000018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_UART0_BAUD_RATE_GEN_REG0_CD
+
+15:0
+
+ffff
+
+0
+
+0
+
+Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+
    
+PSU_UART0_BAUD_RATE_GEN_REG0@0XFF000018
+
+31:0
+
+ffff
+
+
+
+0
+
+Baud Rate Generator Register.
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XFF000000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_UART0_CONTROL_REG0_STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+
    
+PSU_UART0_CONTROL_REG0_STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+PSU_UART0_CONTROL_REG0_RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.
+
    
+PSU_UART0_CONTROL_REG0_TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable: 0: enable transmitter 1: disable transmitter
+
    
+PSU_UART0_CONTROL_REG0_TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+
    
+PSU_UART0_CONTROL_REG0_RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+
    
+PSU_UART0_CONTROL_REG0_RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+
    
+PSU_UART0_CONTROL_REG0_TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.
+
    
+PSU_UART0_CONTROL_REG0_RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.
+
    
+PSU_UART0_CONTROL_REG0@0XFF000000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control Register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XFF000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_UART0_MODE_REG0_CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+
    
+PSU_UART0_MODE_REG0_NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
+
    
+PSU_UART0_MODE_REG0_PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+
    
+PSU_UART0_MODE_REG0_CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+
    
+PSU_UART0_MODE_REG0_CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8
+
    
+PSU_UART0_MODE_REG0@0XFF000004
+
+31:0
+
+3ff
+
+
+
+20
+
+UART Mode Register
+
    
+
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XFF010034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV
+
+7:0
+
+ff
+
+0
+
+0
+
+Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+
    
+PSU_UART1_BAUD_RATE_DIVIDER_REG0@0XFF010034
+
+31:0
+
+ff
+
+
+
+0
+
+Baud Rate Divider Register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XFF010018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_UART1_BAUD_RATE_GEN_REG0_CD
+
+15:0
+
+ffff
+
+0
+
+0
+
+Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+
    
+PSU_UART1_BAUD_RATE_GEN_REG0@0XFF010018
+
+31:0
+
+ffff
+
+
+
+0
+
+Baud Rate Generator Register.
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XFF010000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_UART1_CONTROL_REG0_STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+
    
+PSU_UART1_CONTROL_REG0_STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+PSU_UART1_CONTROL_REG0_RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.
+
    
+PSU_UART1_CONTROL_REG0_TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable: 0: enable transmitter 1: disable transmitter
+
    
+PSU_UART1_CONTROL_REG0_TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+
    
+PSU_UART1_CONTROL_REG0_RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+
    
+PSU_UART1_CONTROL_REG0_RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+
    
+PSU_UART1_CONTROL_REG0_TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.
+
    
+PSU_UART1_CONTROL_REG0_RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.
+
    
+PSU_UART1_CONTROL_REG0@0XFF010000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control Register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XFF010004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_UART1_MODE_REG0_CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+
    
+PSU_UART1_MODE_REG0_NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
+
    
+PSU_UART1_MODE_REG0_PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+
    
+PSU_UART1_MODE_REG0_CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+
    
+PSU_UART1_MODE_REG0_CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8
+
    
+PSU_UART1_MODE_REG0@0XFF010004
+
+31:0
+
+3ff
+
+
+
+20
+
+UART Mode Register
+
    
+
    
+
    GPIO
    
+
    ADMA TZ
    
+
    Register ( slcr )slcr_adma
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+slcr_adma
+
+0XFF4B0024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ
+
+7:0
+
+ff
+
+ff
+
+ff
+
+TrustZone Classification for ADMA
+
    
+PSU_LPD_SLCR_SECURE_SLCR_ADMA@0XFF4B0024
+
+31:0
+
+ff
+
+
+
+ff
+
+RPU TrustZone settings
+
    
+
    
+
    CSU TAMPERING
    
+
    CSU TAMPER STATUS
    
+
    Register ( slcr )tamper_status
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+tamper_status
+
+0XFFCA5000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_0
+
+0:0
+
+1
+
+0
+
+0
+
+CSU regsiter
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_1
+
+1:1
+
+2
+
+0
+
+0
+
+External MIO
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_2
+
+2:2
+
+4
+
+0
+
+0
+
+JTAG toggle detect
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_3
+
+3:3
+
+8
+
+0
+
+0
+
+PL SEU error
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_4
+
+4:4
+
+10
+
+0
+
+0
+
+AMS over temperature alarm for LPD
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_5
+
+5:5
+
+20
+
+0
+
+0
+
+AMS over temperature alarm for APU
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_6
+
+6:6
+
+40
+
+0
+
+0
+
+AMS voltage alarm for VCCPINT_FPD
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_7
+
+7:7
+
+80
+
+0
+
+0
+
+AMS voltage alarm for VCCPINT_LPD
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_8
+
+8:8
+
+100
+
+0
+
+0
+
+AMS voltage alarm for VCCPAUX
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_9
+
+9:9
+
+200
+
+0
+
+0
+
+AMS voltage alarm for DDRPHY
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_10
+
+10:10
+
+400
+
+0
+
+0
+
+AMS voltage alarm for PSIO bank 0/1/2
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_11
+
+11:11
+
+800
+
+0
+
+0
+
+AMS voltage alarm for PSIO bank 3 (dedicated pins)
+
    
+PSU_CSU_TAMPER_STATUS_TAMPER_12
+
+12:12
+
+1000
+
+0
+
+0
+
+AMS voltaage alarm for GT
+
    
+PSU_CSU_TAMPER_STATUS@0XFFCA5000
+
+31:0
+
+1fff
+
+
+
+0
+
+Tamper Response Status
+
    
+
    
+
    CSU TAMPER RESPONSE
    
+
+
    
+
    psu_post_config
    
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
    
+
    psu_post_config
    
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
    
+
    psu_peripherals_powerdwn_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
    
+
    psu_peripherals_powerdwn_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    POWER DOWN REQUEST INTERRUPT ENABLE
    
+
    POWER DOWN TRIGGER
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
    
+
    psu_security_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID00
+
+
+0XFF980100
+
+32
+
+RW
+
+0x000000
+
+Master ID 00 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID01
+
+
+0XFF980104
+
+32
+
+RW
+
+0x000000
+
+Master ID 01 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID02
+
+
+0XFF980108
+
+32
+
+RW
+
+0x000000
+
+Master ID 02 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID03
+
+
+0XFF98010C
+
+32
+
+RW
+
+0x000000
+
+Master ID 03 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID04
+
+
+0XFF980110
+
+32
+
+RW
+
+0x000000
+
+Master ID 04 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID05
+
+
+0XFF980114
+
+32
+
+RW
+
+0x000000
+
+Master ID 05 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID06
+
+
+0XFF980118
+
+32
+
+RW
+
+0x000000
+
+Master ID 06 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID07
+
+
+0XFF98011C
+
+32
+
+RW
+
+0x000000
+
+Master ID 07 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID08
+
+
+0XFF980120
+
+32
+
+RW
+
+0x000000
+
+Master ID 08 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID09
+
+
+0XFF980124
+
+32
+
+RW
+
+0x000000
+
+Master ID 09 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID10
+
+
+0XFF980128
+
+32
+
+RW
+
+0x000000
+
+Master ID 10 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID11
+
+
+0XFF98012C
+
+32
+
+RW
+
+0x000000
+
+Master ID 11 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID12
+
+
+0XFF980130
+
+32
+
+RW
+
+0x000000
+
+Master ID 12 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID13
+
+
+0XFF980134
+
+32
+
+RW
+
+0x000000
+
+Master ID 13 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID14
+
+
+0XFF980138
+
+32
+
+RW
+
+0x000000
+
+Master ID 14 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID15
+
+
+0XFF98013C
+
+32
+
+RW
+
+0x000000
+
+Master ID 15 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID16
+
+
+0XFF980140
+
+32
+
+RW
+
+0x000000
+
+Master ID 16 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID17
+
+
+0XFF980144
+
+32
+
+RW
+
+0x000000
+
+Master ID 17 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID18
+
+
+0XFF980148
+
+32
+
+RW
+
+0x000000
+
+Master ID 18 Register
+
    
+
+PSU_LPD_XPPU_CFG_MASTER_ID19
+
+
+0XFF98014C
+
+32
+
+RW
+
+0x000000
+
+Master ID 19 Register
+
    
+
    
+
    psu_security_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    DDR XMPU0
    
+
    DDR XMPU1
    
+
    DDR XMPU2
    
+
    DDR XMPU3
    
+
    DDR XMPU4
    
+
    DDR XMPU5
    
+
    FPD XMPU
    
+
    OCM XMPU
    
+
    XPPU
    
+
    MASTER ID LIST
    
+
    Register ( slcr )MASTER_ID00
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID00
+
+0XFF980100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID00_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID00_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID00_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID00_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Predefined Master ID for PMU
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID00@0XFF980100
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 00 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID01
+
+0XFF980104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID01_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID01_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID01_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID01_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Predefined Master ID for RPU0
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID01@0XFF980104
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 01 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID02
+
+0XFF980108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID02_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID02_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID02_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID02_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Predefined Master ID for RPU1
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID02@0XFF980108
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 02 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID03
+
+0XFF98010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID03_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID03_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID03_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID03_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Predefined Master ID for APU
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID03@0XFF98010C
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 03 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID04
+
+0XFF980110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID04_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID04_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID04_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID04_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Predefined Master ID for A53 Core 0
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID04@0XFF980110
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 04 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID05
+
+0XFF980114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID05_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID05_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID05_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID05_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Predefined Master ID for A53 Core 1
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID05@0XFF980114
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 05 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID06
+
+0XFF980118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID06_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID06_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID06_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID06_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Predefined Master ID for A53 Core 2
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID06@0XFF980118
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 06 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID07
+
+0XFF98011C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID07_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID07_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID07_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID07_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Predefined Master ID for A53 Core 3
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID07@0XFF98011C
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 07 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID08
+
+0XFF980120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID08_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID08_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID08_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID08_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID08@0XFF980120
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 08 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID09
+
+0XFF980124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID09_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID09_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID09_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID09_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID09@0XFF980124
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 09 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID10
+
+0XFF980128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID10_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID10_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID10_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID10_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID10@0XFF980128
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 10 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID11
+
+0XFF98012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID11_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID11_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID11_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID11_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID11@0XFF98012C
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 11 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID12
+
+0XFF980130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID12_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID12_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID12_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID12_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID12@0XFF980130
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 12 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID13
+
+0XFF980134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID13_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID13_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID13_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID13_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID13@0XFF980134
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 13 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID14
+
+0XFF980138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID14_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID14_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID14_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID14_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID14@0XFF980138
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 14 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID15
+
+0XFF98013C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID15_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID15_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID15_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID15_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID15@0XFF98013C
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 15 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID16
+
+0XFF980140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID16_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID16_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID16_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID16_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID16@0XFF980140
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 16 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID17
+
+0XFF980144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID17_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID17_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID17_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID17_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID17@0XFF980144
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 17 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID18
+
+0XFF980148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID18_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID18_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID18_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID18_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID18@0XFF980148
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 18 Register
+
    
+
    
+
    Register ( slcr )MASTER_ID19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASTER_ID19
+
+0XFF98014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID19_MIDP
+
+31:31
+
+80000000
+
+0
+
+0
+
+Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID19_MIDR
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set, only read transactions are allowed for the masters matching this register
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID19_MIDM
+
+25:16
+
+3ff0000
+
+0
+
+0
+
+Mask to be applied before comparing
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID19_MID
+
+9:0
+
+3ff
+
+0
+
+0
+
+Programmable Master ID
+
    
+PSU_LPD_XPPU_CFG_MASTER_ID19@0XFF98014C
+
+31:0
+
+c3ff03ff
+
+
+
+0
+
+Master ID 19 Register
+
    
+
    
+
    APERTURE PERMISIION LIST
    
+
+
    
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.tcl b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.tcl
new file mode 100644
index 000000000..a16285fea
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.tcl
@@ -0,0 +1,349 @@
+proc psu_pll_init_data {} {
+    mask_write 0XFF5E0030 0x00017F00 0x00013000
+    mask_write 0XFF5E0030 0x00000008 0x00000008
+    mask_write 0XFF5E0030 0x00000001 0x00000001
+    mask_write 0XFF5E0030 0x00000001 0x00000000
+    mask_poll 0XFF5E0040 0x00000002
+    mask_write 0XFF5E0030 0x00000008 0x00000000
+    mask_write 0XFF5E0048 0x00003F00 0x00000300
+    mask_write 0XFF5E0020 0x00017F00 0x00013C00
+    mask_write 0XFF5E0020 0x00000008 0x00000008
+    mask_write 0XFF5E0020 0x00000001 0x00000001
+    mask_write 0XFF5E0020 0x00000001 0x00000000
+    mask_poll 0XFF5E0040 0x00000001
+    mask_write 0XFF5E0020 0x00000008 0x00000000
+    mask_write 0XFF5E0044 0x00003F00 0x00000400
+    mask_write 0XFD1A0020 0x00017F00 0x00013C00
+    mask_write 0XFD1A0020 0x00000008 0x00000008
+    mask_write 0XFD1A0020 0x00000001 0x00000001
+    mask_write 0XFD1A0020 0x00000001 0x00000000
+    mask_poll 0XFD1A0044 0x00000001
+    mask_write 0XFD1A0020 0x00000008 0x00000000
+    mask_write 0XFD1A0048 0x00003F00 0x00000400
+    mask_write 0XFD1A002C 0x00017F00 0x00013C00
+    mask_write 0XFD1A002C 0x00000008 0x00000008
+    mask_write 0XFD1A002C 0x00000001 0x00000001
+    mask_write 0XFD1A002C 0x00000001 0x00000000
+    mask_poll 0XFD1A0044 0x00000002
+    mask_write 0XFD1A002C 0x00000008 0x00000000
+    mask_write 0XFD1A004C 0x00003F00 0x00000400
+    mask_write 0XFD1A0038 0x00017F00 0x00013F00
+    mask_write 0XFD1A0038 0x00000008 0x00000008
+    mask_write 0XFD1A0038 0x00000001 0x00000001
+    mask_write 0XFD1A0038 0x00000001 0x00000000
+    mask_poll 0XFD1A0044 0x00000004
+    mask_write 0XFD1A0038 0x00000008 0x00000000
+    mask_write 0XFD1A0050 0x00003F00 0x00000400
+}
+proc psu_clock_init_data {} {
+    mask_write 0XFF5E0050 0x063F3F07 0x06022800
+    mask_write 0XFF5E0054 0x063F3F07 0x06022800
+    mask_write 0XFF5E0058 0x063F3F07 0x06022800
+    mask_write 0XFF5E005C 0x063F3F07 0x06022800
+    mask_write 0XFF5E0060 0x023F3F07 0x02013200
+    mask_write 0XFF5E004C 0x023F3F07 0x02010800
+    mask_write 0XFF5E0068 0x013F3F07 0x01023200
+    mask_write 0XFF5E006C 0x013F3F07 0x01023200
+    mask_write 0XFF5E0070 0x013F3F07 0x01023200
+    mask_write 0XFF5E0074 0x013F3F07 0x01022800
+    mask_write 0XFF5E0078 0x013F3F07 0x01022800
+    mask_write 0XFF5E0120 0x013F3F07 0x01022800
+    mask_write 0XFF5E0124 0x013F3F07 0x010A3200
+    mask_write 0XFF5E007C 0x013F3F07 0x01022800
+    mask_write 0XFF5E0080 0x013F3F07 0x010A3200
+    mask_write 0XFF5E0084 0x013F3F07 0x01022800
+    mask_write 0XFF5E0088 0x013F3F07 0x01022800
+    mask_write 0XFF5E0090 0x01003F07 0x01003F02
+    mask_write 0XFF5E009C 0x01003F07 0x01000600
+    mask_write 0XFF5E00A4 0x01003F07 0x01000800
+    mask_write 0XFF5E00A8 0x01003F07 0x01000402
+    mask_write 0XFF5E00AC 0x01003F07 0x01001402
+    mask_write 0XFF5E00B0 0x01003F07 0x01003F00
+    mask_write 0XFF5E00B4 0x013F3F07 0x01023200
+    mask_write 0XFF5E00B8 0x01003F07 0x01000402
+    mask_write 0XFF5E0108 0x013F3F07 0x01012800
+    mask_write 0XFF5E0104 0x00000007 0x00000000
+    mask_write 0XFF5E0128 0x01003F07 0x01001402
+    mask_write 0XFD1A00B4 0x01003F07 0x01003F00
+    mask_write 0XFD1A0070 0x013F3F07 0x01153200
+    mask_write 0XFD1A0074 0x013F3F07 0x01022A00
+    mask_write 0XFD1A007C 0x013F3F07 0x01022A00
+    mask_write 0XFD1A0060 0x03003F07 0x03003F00
+    mask_write 0XFD1A0064 0x01003F07 0x01003F02
+    mask_write 0XFD1A0068 0x01003F07 0x01003F02
+    mask_write 0XFD1A0080 0x00003F07 0x00000A00
+    mask_write 0XFD1A0084 0x07003F07 0x07003F02
+    mask_write 0XFD1A00B8 0x01003F07 0x01000303
+    mask_write 0XFD1A00BC 0x01003F07 0x01000303
+    mask_write 0XFD1A00C0 0x01003F07 0x01000303
+    mask_write 0XFD1A00C4 0x01003F07 0x01001400
+    mask_write 0XFD1A00C8 0x01003F07 0x01001102
+    mask_write 0XFD1A00F8 0x00003F07 0x00000802
+}
+proc psu_ddr_init_data_3_0 {} {
+}
+proc psu_mio_init_data {} {
+#    mask_write 0XFF180000 0x000000FE 0x00000002
+#    mask_write 0XFF180004 0x000000FE 0x00000002
+#    mask_write 0XFF180008 0x000000FE 0x00000002
+#    mask_write 0XFF18000C 0x000000FE 0x00000002
+#    mask_write 0XFF180010 0x000000FE 0x00000002
+#    mask_write 0XFF180014 0x000000FE 0x00000002
+#    mask_write 0XFF180018 0x000000FE 0x00000000
+#    mask_write 0XFF18001C 0x000000FE 0x00000000
+#    mask_write 0XFF180020 0x000000FE 0x00000000
+#    mask_write 0XFF180024 0x000000FE 0x00000000
+#    mask_write 0XFF180028 0x000000FE 0x00000004
+#    mask_write 0XFF18002C 0x000000FE 0x00000004
+#    mask_write 0XFF180030 0x000000FE 0x00000000
+#    mask_write 0XFF180034 0x000000FE 0x00000004
+#    mask_write 0XFF180038 0x000000FE 0x00000004
+#    mask_write 0XFF18003C 0x000000FE 0x00000004
+#    mask_write 0XFF180040 0x000000FE 0x00000004
+#    mask_write 0XFF180044 0x000000FE 0x00000004
+#    mask_write 0XFF180048 0x000000FE 0x00000004
+#    mask_write 0XFF18004C 0x000000FE 0x00000004
+#    mask_write 0XFF180050 0x000000FE 0x00000004
+#    mask_write 0XFF180054 0x000000FE 0x00000004
+#    mask_write 0XFF180058 0x000000FE 0x00000004
+#    mask_write 0XFF18005C 0x000000FE 0x00000004
+#    mask_write 0XFF180060 0x000000FE 0x00000004
+#    mask_write 0XFF180064 0x000000FE 0x00000004
+#    mask_write 0XFF180068 0x000000FE 0x00000004
+#    mask_write 0XFF18006C 0x000000FE 0x00000000
+#    mask_write 0XFF180070 0x000000FE 0x00000000
+#    mask_write 0XFF180074 0x000000FE 0x00000080
+#    mask_write 0XFF180078 0x000000FE 0x00000000
+#    mask_write 0XFF18007C 0x000000FE 0x00000000
+#    mask_write 0XFF180080 0x000000FE 0x00000004
+#    mask_write 0XFF180084 0x000000FE 0x00000000
+#    mask_write 0XFF180088 0x000000FE 0x00000000
+#    mask_write 0XFF18008C 0x000000FE 0x00000080
+#    mask_write 0XFF180090 0x000000FE 0x00000000
+#    mask_write 0XFF180094 0x000000FE 0x00000000
+#    mask_write 0XFF180098 0x000000FE 0x00000000
+#    mask_write 0XFF18009C 0x000000FE 0x00000010
+#    mask_write 0XFF1800A0 0x000000FE 0x00000010
+#    mask_write 0XFF1800A4 0x000000FE 0x00000010
+#    mask_write 0XFF1800A8 0x000000FE 0x00000010
+#    mask_write 0XFF1800AC 0x000000FE 0x00000010
+#    mask_write 0XFF1800B0 0x000000FE 0x00000000
+#    mask_write 0XFF1800B4 0x000000FE 0x00000000
+#    mask_write 0XFF1800B8 0x000000FE 0x00000010
+#    mask_write 0XFF1800BC 0x000000FE 0x00000010
+#    mask_write 0XFF1800C0 0x000000FE 0x00000010
+#    mask_write 0XFF1800C4 0x000000FE 0x00000010
+#    mask_write 0XFF1800C8 0x000000FE 0x00000010
+#    mask_write 0XFF1800CC 0x000000FE 0x00000010
+#    mask_write 0XFF1800D0 0x000000FE 0x00000004
+#    mask_write 0XFF1800D4 0x000000FE 0x00000004
+#    mask_write 0XFF1800D8 0x000000FE 0x00000004
+#    mask_write 0XFF1800DC 0x000000FE 0x00000004
+#    mask_write 0XFF1800E0 0x000000FE 0x00000004
+#    mask_write 0XFF1800E4 0x000000FE 0x00000004
+#    mask_write 0XFF1800E8 0x000000FE 0x00000004
+#    mask_write 0XFF1800EC 0x000000FE 0x00000004
+#    mask_write 0XFF1800F0 0x000000FE 0x00000004
+#    mask_write 0XFF1800F4 0x000000FE 0x00000004
+#    mask_write 0XFF1800F8 0x000000FE 0x00000004
+#    mask_write 0XFF1800FC 0x000000FE 0x00000004
+#    mask_write 0XFF180100 0x000000FE 0x00000008
+#    mask_write 0XFF180104 0x000000FE 0x00000008
+#    mask_write 0XFF180108 0x000000FE 0x00000008
+#    mask_write 0XFF18010C 0x000000FE 0x00000008
+#    mask_write 0XFF180110 0x000000FE 0x00000008
+#    mask_write 0XFF180114 0x000000FE 0x00000008
+#    mask_write 0XFF180118 0x000000FE 0x00000008
+#    mask_write 0XFF18011C 0x000000FE 0x00000008
+#    mask_write 0XFF180120 0x000000FE 0x00000008
+#    mask_write 0XFF180124 0x000000FE 0x00000008
+#    mask_write 0XFF180128 0x000000FE 0x00000008
+#    mask_write 0XFF18012C 0x000000FE 0x00000008
+#    mask_write 0XFF180130 0x000000FE 0x00000008
+#    mask_write 0XFF180134 0x000000FE 0x00000000
+#    mask_write 0XFF180204 0xFFFFFFFF 0x00000C00
+#    mask_write 0XFF180208 0xFFFFFFFF 0x00B00000
+#    mask_write 0XFF18020C 0x00003FFF 0x00001002
+#    mask_write 0XFF180200 0x0000000F 0x00000000
+}
+proc psu_peripherals_init_data_3_0 {} {
+    mask_write 0XFF5E0230 0x0000000F 0x00000000
+    mask_write 0XFF5E0238 0x00000001 0x00000000
+    mask_write 0XFF5E0238 0x00010000 0x00000000
+    mask_write 0XFF5E023C 0x00000540 0x00000000
+    mask_write 0XFF5E0238 0x00000060 0x00000000
+    mask_write 0XFF180310 0x00008001 0x00000000
+    mask_write 0XFF180320 0x33803380 0x02800280
+    mask_write 0XFF5E0238 0x00000180 0x00000000
+    mask_write 0XFF5E0238 0x00000600 0x00000000
+    mask_write 0XFF5E0238 0x00000018 0x00000000
+    mask_write 0XFF5E0238 0x00007800 0x00000000
+    mask_write 0XFF5E0238 0x00000006 0x00000000
+    mask_write 0XFF000034 0x000000FF 0x00000000
+    mask_write 0XFF000018 0x0000FFFF 0x00000000
+    mask_write 0XFF000000 0x000001FF 0x00000017
+    mask_write 0XFF000004 0x000003FF 0x00000020
+    mask_write 0XFF010034 0x000000FF 0x00000000
+    mask_write 0XFF010018 0x0000FFFF 0x00000000
+    mask_write 0XFF010000 0x000001FF 0x00000017
+    mask_write 0XFF010004 0x000003FF 0x00000020
+    mask_write 0XFF4B0024 0x000000FF 0x000000FF
+    mask_write 0XFFCA5000 0x00001FFF 0x00000000
+}
+proc psu_post_config {} {
+}
+proc psu_peripherals_powerdwn_data_3_0 {} {
+}
+proc psu_security_data_3_0 {} {
+    mask_write 0XFF980100 0xC3FF03FF 0x00000000
+    mask_write 0XFF980104 0xC3FF03FF 0x00000000
+    mask_write 0XFF980108 0xC3FF03FF 0x00000000
+    mask_write 0XFF98010C 0xC3FF03FF 0x00000000
+    mask_write 0XFF980110 0xC3FF03FF 0x00000000
+    mask_write 0XFF980114 0xC3FF03FF 0x00000000
+    mask_write 0XFF980118 0xC3FF03FF 0x00000000
+    mask_write 0XFF98011C 0xC3FF03FF 0x00000000
+    mask_write 0XFF980120 0xC3FF03FF 0x00000000
+    mask_write 0XFF980124 0xC3FF03FF 0x00000000
+    mask_write 0XFF980128 0xC3FF03FF 0x00000000
+    mask_write 0XFF98012C 0xC3FF03FF 0x00000000
+    mask_write 0XFF980130 0xC3FF03FF 0x00000000
+    mask_write 0XFF980134 0xC3FF03FF 0x00000000
+    mask_write 0XFF980138 0xC3FF03FF 0x00000000
+    mask_write 0XFF98013C 0xC3FF03FF 0x00000000
+    mask_write 0XFF980140 0xC3FF03FF 0x00000000
+    mask_write 0XFF980144 0xC3FF03FF 0x00000000
+    mask_write 0XFF980148 0xC3FF03FF 0x00000000
+    mask_write 0XFF98014C 0xC3FF03FF 0x00000000
+}
+proc init_ddrc {} {
+
+  mask_write 0XFD1A0108 0xFFFFFFFF 0x0000000F
+
+  mask_write 0xFD070000 0xFFFFFFFF 0x41040001
+  mask_write 0xFD070034 0xFFFFFFFF 0x00404310
+  mask_write 0xFD070064 0xFFFFFFFF 0x0040001E
+  mask_write 0xFD070070 0xFFFFFFFF 0x00000010
+  mask_write 0xFD070074 0xFFFFFFFF 0x00000000
+  mask_write 0xFD0700C4 0xFFFFFFFF 0x10000200
+  mask_write 0xFD0700C8 0xFFFFFFFF 0x0030051F
+  mask_write 0xFD0700D0 0xFFFFFFFF 0x40020004
+  mask_write 0xFD0700D4 0xFFFFFFFF 0x00010000
+  mask_write 0xFD0700D8 0xFFFFFFFF 0x00001205
+  mask_write 0xFD0700DC 0xFFFFFFFF 0x09300000
+  mask_write 0xFD0700E0 0xFFFFFFFF 0x02080000
+  mask_write 0xFD0700E4 0xFFFFFFFF 0x00110004
+  mask_write 0xFD070100 0xFFFFFFFF 0x090E110A
+  mask_write 0xFD070104 0xFFFFFFFF 0x0007020E
+  mask_write 0xFD070108 0xFFFFFFFF 0x03040407
+  mask_write 0xFD07010C 0xFFFFFFFF 0x00502006
+  mask_write 0xFD070110 0xFFFFFFFF 0x04020205
+  mask_write 0xFD070114 0xFFFFFFFF 0x03030202
+  mask_write 0xFD070118 0xFFFFFFFF 0x01010003
+  mask_write 0xFD07011C 0xFFFFFFFF 0x00000101
+  mask_write 0xFD070120 0xFFFFFFFF 0x03030903
+  mask_write 0xFD070130 0xFFFFFFFF 0x00020608
+  mask_write 0xFD070180 0xFFFFFFFF 0x00800020
+  mask_write 0xFD070184 0xFFFFFFFF 0x0200CB52
+  mask_write 0xFD070190 0xFFFFFFFF 0x02838204
+  mask_write 0xFD070194 0xFFFFFFFF 0x00020404
+  mask_write 0xFD0701A4 0xFFFFFFFF 0x00010087
+  mask_write 0xFD0701B0 0xFFFFFFFF 0x00000001
+  mask_write 0xFD0701B4 0xFFFFFFFF 0x00000202
+  mask_write 0xFD0701C0 0xFFFFFFFF 0x00000000
+  mask_write 0xFD070200 0xFFFFFFFF 0x0000001F
+  mask_write 0xFD070204 0xFFFFFFFF 0x00080808
+  mask_write 0xFD070208 0xFFFFFFFF 0x00000000
+  mask_write 0xFD07020C 0xFFFFFFFF 0x00000000
+  mask_write 0xFD070210 0xFFFFFFFF 0x00000F0F
+  mask_write 0xFD070214 0xFFFFFFFF 0x07070707
+  mask_write 0xFD070218 0xFFFFFFFF 0x07070707
+  mask_write 0xFD07021C 0xFFFFFFFF 0x00000F0F
+  mask_write 0xFD070220 0xFFFFFFFF 0x00000000
+  mask_write 0xFD070240 0xFFFFFFFF 0x06000604
+  mask_write 0xFD070244 0xFFFFFFFF 0x00000001
+  mask_write 0xFD070250 0xFFFFFFFF 0x01002001
+  mask_write 0xFD070264 0xFFFFFFFF 0x08000040
+  mask_write 0xFD07026C 0xFFFFFFFF 0x08000040
+  mask_write 0xFD070294 0xFFFFFFFF 0x00000001
+  mask_write 0xFD07030C 0xFFFFFFFF 0x00000000
+  mask_write 0xFD070320 0xFFFFFFFF 0x00000000
+  mask_write 0xFD070400 0xFFFFFFFF 0x00000001
+  mask_write 0xFD070404 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD070408 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD070490 0xFFFFFFFF 0x00000001
+  mask_write 0xFD070494 0xFFFFFFFF 0x0021000B
+  mask_write 0xFD070498 0xFFFFFFFF 0x004F004F
+  mask_write 0xFD0704B4 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD0704B8 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD070540 0xFFFFFFFF 0x00000001
+  mask_write 0xFD070544 0xFFFFFFFF 0x02000B03
+  mask_write 0xFD070548 0xFFFFFFFF 0x00010040
+  mask_write 0xFD070564 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD070568 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD0705F0 0xFFFFFFFF 0x00000001
+  mask_write 0xFD0705F4 0xFFFFFFFF 0x02000B03
+  mask_write 0xFD0705F8 0xFFFFFFFF 0x00010040
+  mask_write 0xFD070614 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD070618 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD0706A0 0xFFFFFFFF 0x00000001
+  mask_write 0xFD0706A4 0xFFFFFFFF 0x00100003
+  mask_write 0xFD0706A8 0xFFFFFFFF 0x002F004F
+  mask_write 0xFD0706AC 0xFFFFFFFF 0x00100007
+  mask_write 0xFD0706B0 0xFFFFFFFF 0x0000004F
+  mask_write 0xFD0706C4 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD0706C8 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD070750 0xFFFFFFFF 0x00000001
+  mask_write 0xFD070754 0xFFFFFFFF 0x00100003
+  mask_write 0xFD070758 0xFFFFFFFF 0x002F004F
+  mask_write 0xFD07075C 0xFFFFFFFF 0x00100007
+  mask_write 0xFD070760 0xFFFFFFFF 0x0000004F
+  mask_write 0xFD070774 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD070778 0xFFFFFFFF 0x0000600F
+  mask_write 0xFD070800 0xFFFFFFFF 0x00000001
+  mask_write 0xFD070804 0xFFFFFFFF 0x00100003
+  mask_write 0xFD070808 0xFFFFFFFF 0x002F004F
+  mask_write 0xFD07080C 0xFFFFFFFF 0x00100007
+  mask_write 0xFD070810 0xFFFFFFFF 0x0000004F
+  mask_write 0xFD070F04 0xFFFFFFFF 0x00000000
+  mask_write 0xFD070F08 0xFFFFFFFF 0x00000000
+  mask_write 0xFD070F0C 0xFFFFFFFF 0x00000010
+  mask_write 0xFD070F10 0xFFFFFFFF 0x0000000F
+  set RegValue [mrd -force -value 0XFD1A0108]
+  mask_write 0XFD1A0108  0xFFFFFFFF 0x00000000
+  set RegValue [mrd -force -value  0XFD1A0108]
+}
+
+
+proc init_peripheral {}  {
+	# Turn on IOU Clock
+	mask_write 0xFF5E009C 0xFFFFFFFF 0x01001500
+
+	# Release all resets in the IOU
+	mask_write 0xFF5E0230 0xFFFFFFFF 0x00000000
+	mask_write 0xFF5E0234 0xFFFFFFFF 0x00000000
+	mask_write 0xFF5E0238 0xFFFFFFFF 0x00000000
+
+	# Activate GPU clocks
+	mask_write 0xFD1A0084 0xFFFFFFFF 0x07001500
+
+	# Take LPD out of reset except R5
+	set RegValue [mrd -force -value 0xFF5E023C]
+	set RegValue [expr $RegValue & 0x3]
+	mask_write 0xFF5E023C 0xFFFFFFFF $RegValue
+
+	# Take most of FPD out of reset
+	mask_write 0XFD1A0100 0xFFFFFFFF 0x00000000
+}
+
+proc psu_init {} {
+    psu_mio_init_data
+    psu_pll_init_data
+    psu_clock_init_data
+    psu_ddr_init_data_3_0
+	init_ddrc
+	init_peripheral
+    psu_peripherals_init_data_3_0
+    psu_peripherals_powerdwn_data_3_0
+	psu_security_data_3_0
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.c
new file mode 100644
index 000000000..171e4f290
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.c
@@ -0,0 +1,6344 @@
+/******************************************************************************
+/****************************************************************************** 
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* 
+* Permission is hereby granted, free of charge, to any person obtaining a copy 
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights 
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 
+* copies of the Software, and to permit persons to whom the Software is 
+* furnished to do so, subject to the following conditions: 
+* 
+* The above copyright notice and this permission notice shall be included in 
+* all copies or substantial portions of the Software. 
+* 
+* Use of the Software is limited solely to applications: 
+* (a) running on a Xilinx device, or 
+* (b) that interact with a Xilinx device through a bus or interconnect. 
+* 
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
+* SOFTWARE.
+* 
+* Except as contained in this notice, the name of the Xilinx shall not be used 
+* in advertising or otherwise to promote the sale, use or other dealings in 
+* this Software without prior written authorization from Xilinx. 
+* 
+******************************************************************************/ 
+
+#include "psu_init_gpl.h"
+
+static unsigned int RegMask = 0x0;
+
+static unsigned int RegVal = 0x0;
+
+unsigned long psu_pll_init_data() {
+		// : RPLL INIT
+		// : UPDATE FB_DIV
+		/*Register : RPLL_CTRL @ 0XFF5E0030
    
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRL_APB_RPLL_CTRL_FBDIV                                                     0x30
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRL_APB_RPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00017F00U ,0x00013000U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000030U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : RPLL_CTRL @ 0XFF5E0030
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : RPLL_CTRL @ 0XFF5E0030
    
+
+		Asserts Reset to the PLL
+		PSU_CRL_APB_RPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : RPLL_CTRL @ 0XFF5E0030
    
+
+		Asserts Reset to the PLL
+		PSU_CRL_APB_RPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFF5E0040
    
+
+		RPLL is locked
+		PSU_CRL_APB_PLL_STATUS_RPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000002U ,0x00000002U)  */
+		while(!(Xil_In32 ( CRL_APB_PLL_STATUS_OFFSET) & 0x00000002U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : RPLL_CTRL @ 0XFF5E0030
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048
    
+
+		Divisor value for this clock.
+		PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFF5E0048, 0x00003F00U ,0x00000300U)  */
+		RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RPLL_TO_FPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : RPLL FRAC CFG
+		// : IOPLL INIT
+		// : UPDATE FB_DIV
+		/*Register : IOPLL_CTRL @ 0XFF5E0020
    
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRL_APB_IOPLL_CTRL_FBDIV                                                    0x3c
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRL_APB_IOPLL_CTRL_DIV2                                                     0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00017F00U ,0x00013C00U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000003CU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : IOPLL_CTRL @ 0XFF5E0020
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : IOPLL_CTRL @ 0XFF5E0020
    
+
+		Asserts Reset to the PLL
+		PSU_CRL_APB_IOPLL_CTRL_RESET                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : IOPLL_CTRL @ 0XFF5E0020
    
+
+		Asserts Reset to the PLL
+		PSU_CRL_APB_IOPLL_CTRL_RESET                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFF5E0040
    
+
+		IOPLL is locked
+		PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK                                               1
+		(OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000001U ,0x00000001U)  */
+		while(!(Xil_In32 ( CRL_APB_PLL_STATUS_OFFSET) & 0x00000001U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : IOPLL_CTRL @ 0XFF5E0020
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044
    
+
+		Divisor value for this clock.
+		PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0                                          0x4
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFF5E0044, 0x00003F00U ,0x00000400U)  */
+		RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000004U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : IOPLL FRAC CFG
+		// : APU_PLL INIT
+		// : UPDATE FB_DIV
+		/*Register : APLL_CTRL @ 0XFD1A0020
    
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_APLL_CTRL_FBDIV                                                     0x3c
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_APLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00017F00U ,0x00013C00U)  */
+		RegMask = (CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000003CU << CRF_APB_APLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : APLL_CTRL @ 0XFD1A0020
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_APLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : APLL_CTRL @ 0XFD1A0020
    
+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_APLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : APLL_CTRL @ 0XFD1A0020
    
+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_APLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044
    
+
+		APLL is locked
+		PSU_CRF_APB_PLL_STATUS_APLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000001U ,0x00000001U)  */
+		while(!(Xil_In32 ( CRF_APB_PLL_STATUS_OFFSET) & 0x00000001U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : APLL_CTRL @ 0XFD1A0020
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_APLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048
    
+
+		Divisor value for this clock.
+		PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0                                           0x4
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A0048, 0x00003F00U ,0x00000400U)  */
+		RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_APLL_TO_LPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000004U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_APLL_TO_LPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : APLL FRAC CFG
+		// : DDR_PLL INIT
+		// : UPDATE FB_DIV
+		/*Register : DPLL_CTRL @ 0XFD1A002C
    
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_DPLL_CTRL_FBDIV                                                     0x3c
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_DPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00017F00U ,0x00013C00U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000003CU << CRF_APB_DPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : DPLL_CTRL @ 0XFD1A002C
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : DPLL_CTRL @ 0XFD1A002C
    
+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_DPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : DPLL_CTRL @ 0XFD1A002C
    
+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_DPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044
    
+
+		DPLL is locked
+		PSU_CRF_APB_PLL_STATUS_DPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000002U ,0x00000002U)  */
+		while(!(Xil_In32 ( CRF_APB_PLL_STATUS_OFFSET) & 0x00000002U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : DPLL_CTRL @ 0XFD1A002C
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C
    
+
+		Divisor value for this clock.
+		PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0                                           0x4
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A004C, 0x00003F00U ,0x00000400U)  */
+		RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000004U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPLL_TO_LPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DPLL FRAC CFG
+		// : VIDEO_PLL INIT
+		// : UPDATE FB_DIV
+		/*Register : VPLL_CTRL @ 0XFD1A0038
    
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_VPLL_CTRL_FBDIV                                                     0x3f
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_VPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00017F00U ,0x00013F00U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000003FU << CRF_APB_VPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : VPLL_CTRL @ 0XFD1A0038
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000008U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : VPLL_CTRL @ 0XFD1A0038
    
+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_VPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000001U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : VPLL_CTRL @ 0XFD1A0038
    
+
+		Asserts Reset to the PLL
+		PSU_CRF_APB_VPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044
    
+
+		VPLL is locked
+		PSU_CRF_APB_PLL_STATUS_VPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000004U ,0x00000004U)  */
+		while(!(Xil_In32 ( CRF_APB_PLL_STATUS_OFFSET) & 0x00000004U));
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : VPLL_CTRL @ 0XFD1A0038
    
+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000000U)  */
+		RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050
    
+
+		Divisor value for this clock.
+		PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0                                           0x4
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A0050, 0x00003F00U ,0x00000400U)  */
+		RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000004U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_VPLL_TO_LPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : VIDEO FRAC CFG
+
+}
+unsigned long psu_clock_init_data() {
+		// : CLOCK CONTROL SLCR REGISTER
+		/*Register : GEM0_REF_CTRL @ 0XFF5E0050
    
+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0050, 0x063F3F07U ,0x06022800U)  */
+		RegMask = (CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_GEM0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_GEM0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GEM1_REF_CTRL @ 0XFF5E0054
    
+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0054, 0x063F3F07U ,0x06022800U)  */
+		RegMask = (CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_GEM1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_GEM1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GEM2_REF_CTRL @ 0XFF5E0058
    
+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM2_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0058, 0x063F3F07U ,0x06022800U)  */
+		RegMask = (CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_GEM2_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_GEM2_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GEM3_REF_CTRL @ 0XFF5E005C
    
+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM3_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E005C, 0x063F3F07U ,0x06022800U)  */
+		RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_GEM3_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_GEM3_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT                                            0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0                                          0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL                                            0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0060, 0x023F3F07U ,0x02013200U)  */
+		RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_USB0_BUS_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_USB0_BUS_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT                                           0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1                                         0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0                                         0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL                                           0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E004C, 0x023F3F07U ,0x02010800U)  */
+		RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000008U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_USB3_DUAL_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : QSPI_REF_CTRL @ 0XFF5E0068
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_QSPI_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01023200U)  */
+		RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_QSPI_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_QSPI_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SDIO0_REF_CTRL @ 0XFF5E006C
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0                                             0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E006C, 0x013F3F07U ,0x01023200U)  */
+		RegMask = (CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_SDIO0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_SDIO0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SDIO1_REF_CTRL @ 0XFF5E0070
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                                             0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01023200U)  */
+		RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_SDIO1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_SDIO1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : UART0_REF_CTRL @ 0XFF5E0074
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_UART0_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0                                             0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_UART0_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0074, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_UART0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_UART0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : UART1_REF_CTRL @ 0XFF5E0078
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_UART1_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0                                             0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_UART1_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0078, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_UART1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_UART1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : I2C0_REF_CTRL @ 0XFF5E0120
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_I2C0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0120, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_I2C0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_I2C0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : I2C1_REF_CTRL @ 0XFF5E0124
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_I2C1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1                                              0xa
+
+		6 bit divider
+		PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0                                              0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0124, 0x013F3F07U ,0x010A3200U)  */
+		RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_I2C1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
+			| 0x0000000AU << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_I2C1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SPI0_REF_CTRL @ 0XFF5E007C
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SPI0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E007C, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_SPI0_REF_CTRL_CLKACT_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_SPI0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_SPI0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SPI1_REF_CTRL @ 0XFF5E0080
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SPI1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1                                              0xa
+
+		6 bit divider
+		PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0                                              0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0080, 0x013F3F07U ,0x010A3200U)  */
+		RegMask = (CRL_APB_SPI1_REF_CTRL_CLKACT_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_SPI1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
+			| 0x0000000AU << CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_SPI1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : CAN0_REF_CTRL @ 0XFF5E0084
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CAN0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0084, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_CAN0_REF_CTRL_CLKACT_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_CAN0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_CAN0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : CAN1_REF_CTRL @ 0XFF5E0088
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CAN1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0                                              0x28
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0088, 0x013F3F07U ,0x01022800U)  */
+		RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_CAN1_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_CAN1_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : CPU_R5_CTRL @ 0XFF5E0090
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CPU_R5_CTRL_CLKACT                                                  0x1
+
+		6 bit divider
+		PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0                                                0x1f4
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CPU_R5_CTRL_SRCSEL                                                  0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0090, 0x01003F07U ,0x01003F02U)  */
+		RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_CPU_R5_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
+			| 0x000001F4U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_CPU_R5_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : IOU_SWITCH_CTRL @ 0XFF5E009C
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0                                            0x6
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL                                              0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E009C, 0x01003F07U ,0x01000600U)  */
+		RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_IOU_SWITCH_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
+			| 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_IOU_SWITCH_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : PCAP_CTRL @ 0XFF5E00A4
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PCAP_CTRL_CLKACT                                                    0x1
+
+		6 bit divider
+		PSU_CRL_APB_PCAP_CTRL_DIVISOR0                                                  0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PCAP_CTRL_SRCSEL                                                    0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000800U)  */
+		RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_PCAP_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT
+			| 0x00000008U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_PCAP_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0                                            0x4
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A8, 0x01003F07U ,0x01000402U)  */
+		RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_LPD_SWITCH_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
+			| 0x00000004U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_LPD_SWITCH_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0                                             0x14
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00AC, 0x01003F07U ,0x01001402U)  */
+		RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_LPD_LSBUS_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
+			| 0x00000014U << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_LPD_LSBUS_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DBG_LPD_CTRL @ 0XFF5E00B0
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_DBG_LPD_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0                                               0x190
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL                                                 0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B0, 0x01003F07U ,0x01003F00U)  */
+		RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_DBG_LPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
+			| 0x00000190U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_DBG_LPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : NAND_REF_CTRL @ 0XFF5E00B4
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_NAND_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1                                              0x2
+
+		6 bit divider
+		PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0                                              0x32
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_NAND_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B4, 0x013F3F07U ,0x01023200U)  */
+		RegMask = (CRL_APB_NAND_REF_CTRL_CLKACT_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK | CRL_APB_NAND_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_NAND_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_NAND_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : ADMA_REF_CTRL @ 0XFF5E00B8
    
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_ADMA_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0                                              0x4
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL                                                0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B8, 0x01003F07U ,0x01000402U)  */
+		RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_ADMA_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
+			| 0x00000004U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_ADMA_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : AMS_REF_CTRL @ 0XFF5E0108
    
+
+		6 bit divider
+		PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0                                               0x28
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_AMS_REF_CTRL_SRCSEL                                                 0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_AMS_REF_CTRL_CLKACT                                                 0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0108, 0x013F3F07U ,0x01012800U)  */
+		RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_AMS_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000028U << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_AMS_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DLL_REF_CTRL @ 0XFF5E0104
    
+
+		000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
+		is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_DLL_REF_CTRL_SRCSEL                                                 0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0104, 0x00000007U ,0x00000000U)  */
+		RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_DLL_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_DLL_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128
    
+
+		6 bit divider
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                                         0x14
+
+		1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 
+		 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                                           0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                                           0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01001402U)  */
+		RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000014U << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_TIMESTAMP_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : PCIE_REF_CTRL @ 0XFD1A00B4
    
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL                                                0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_PCIE_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0                                              0x7d
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00B4, 0x01003F07U ,0x01003F00U)  */
+		RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_PCIE_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
+			| 0x0000007DU << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_PCIE_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070
    
+
+		6 bit divider
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                                          0x15
+
+		6 bit divider
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                                          0x32
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
+		k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                                            0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                                            0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01153200U)  */
+		RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000015U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000032U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DP_VIDEO_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074
    
+
+		6 bit divider
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                                          0x2
+
+		6 bit divider
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                                          0x2a
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
+		k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                                            0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                                            0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01022A00U)  */
+		RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000002U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000002AU << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DP_AUDIO_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DP_STC_REF_CTRL @ 0XFD1A007C
    
+
+		6 bit divider
+		PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                                            0x2
+
+		6 bit divider
+		PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                                            0x2a
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL                                              0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                                              0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01022A00U)  */
+		RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DP_STC_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000002U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000002AU << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DP_STC_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : ACPU_CTRL @ 0XFD1A0060
    
+
+		6 bit divider
+		PSU_CRF_APB_ACPU_CTRL_DIVISOR0                                                  0xfa
+
+		000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_ACPU_CTRL_SRCSEL                                                    0x0
+
+		Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
+		PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF                                               0x1
+
+		Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
+		 to the entire APU
+		PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0060, 0x03003F07U ,0x03003F00U)  */
+		RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_ACPU_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x000000FAU << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
+			| 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_ACPU_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DBG_TRACE_CTRL @ 0XFD1A0064
    
+
+		6 bit divider
+		PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0                                             0x1f4
+
+		000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL                                               0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0064, 0x01003F07U ,0x01003F02U)  */
+		RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DBG_TRACE_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x000001F4U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DBG_TRACE_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DBG_FPD_CTRL @ 0XFD1A0068
    
+
+		6 bit divider
+		PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0                                               0x1f4
+
+		000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL                                                 0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DBG_FPD_CTRL_CLKACT                                                 0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0068, 0x01003F07U ,0x01003F02U)  */
+		RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DBG_FPD_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x000001F4U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DBG_FPD_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DDR_CTRL @ 0XFD1A0080
    
+
+		6 bit divider
+		PSU_CRF_APB_DDR_CTRL_DIVISOR0                                                   0xa
+
+		000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 
+		s not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DDR_CTRL_SRCSEL                                                     0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0080, 0x00003F07U ,0x00000A00U)  */
+		RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DDR_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000000AU << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DDR_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GPU_REF_CTRL @ 0XFD1A0084
    
+
+		6 bit divider
+		PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0                                               0x20d
+
+		000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GPU_REF_CTRL_SRCSEL                                                 0x2
+
+		Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below
+		PSU_CRF_APB_GPU_REF_CTRL_CLKACT                                                 0x1
+
+		Clock active signal for Pixel Processor. Switch to 0 to disable the clock
+		PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT                                             0x1
+
+		Clock active signal for Pixel Processor. Switch to 0 to disable the clock
+		PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0084, 0x07003F07U ,0x07003F02U)  */
+		RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_GPU_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x0000020DU << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_GPU_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GDMA_REF_CTRL @ 0XFD1A00B8
    
+
+		6 bit divider
+		PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0                                              0x3
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL                                                0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_GDMA_REF_CTRL_CLKACT                                                0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00B8, 0x01003F07U ,0x01000303U)  */
+		RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_GDMA_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000003U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_GDMA_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DPDMA_REF_CTRL @ 0XFD1A00BC
    
+
+		6 bit divider
+		PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0                                             0x3
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL                                               0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00BC, 0x01003F07U ,0x01000303U)  */
+		RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DPDMA_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000003U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DPDMA_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0
    
+
+		6 bit divider
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0                                            0x3
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                                              0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                                              0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000303U)  */
+		RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_TOPSW_MAIN_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000003U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_TOPSW_MAIN_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4
    
+
+		6 bit divider
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0                                           0x14
+
+		000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL                                             0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C4, 0x01003F07U ,0x01001400U)  */
+		RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000014U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_TOPSW_LSBUS_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : GTGREF0_REF_CTRL @ 0XFD1A00C8
    
+
+		6 bit divider
+		PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0                                           0x11
+
+		000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL                                             0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C8, 0x01003F07U ,0x01001102U)  */
+		RegMask = (CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK | CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK | CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_GTGREF0_REF_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000011U << CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_GTGREF0_REF_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8
    
+
+		6 bit divider
+		PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0                                             0x8
+
+		000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00F8, 0x00003F07U ,0x00000802U)  */
+		RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = Xil_In32 (CRF_APB_DBG_TSTMP_CTRL_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000008U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRF_APB_DBG_TSTMP_CTRL_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+
+}
+unsigned long psu_ddr_init_data_3_0() {
+
+}
+unsigned long psu_mio_init_data() {
+		// : MIO PROGRAMMING
+		/*Register : MIO_PIN_0 @ 0XFF180000
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_0_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_0_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[0]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_0_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_0_L3_SEL                                                   0
+
+		Configures MIO Pin 0 peripheral interface mapping. S
+		(OFFSET, MASK, VALUE)      (0XFF180000, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_1 @ 0XFF180004
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
+		us)
+		PSU_IOU_SLCR_MIO_PIN_1_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_1_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[1]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_1_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)
+		PSU_IOU_SLCR_MIO_PIN_1_L3_SEL                                                   0
+
+		Configures MIO Pin 1 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180004, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_1_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_1_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_2 @ 0XFF180008
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
+		PSU_IOU_SLCR_MIO_PIN_2_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_2_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[2]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_2_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_2_L3_SEL                                                   0
+
+		Configures MIO Pin 2 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180008, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_3 @ 0XFF18000C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
+		PSU_IOU_SLCR_MIO_PIN_3_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_3_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[3]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_3_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_3_L3_SEL                                                   0
+
+		Configures MIO Pin 3 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18000C, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_3_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_3_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_4 @ 0XFF180010
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
+		us)
+		PSU_IOU_SLCR_MIO_PIN_4_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_4_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[4]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_4_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_4_L3_SEL                                                   0
+
+		Configures MIO Pin 4 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180010, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_4_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_4_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_5 @ 0XFF180014
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
+		PSU_IOU_SLCR_MIO_PIN_5_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_5_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[5]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_5_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_5_L3_SEL                                                   0
+
+		Configures MIO Pin 5 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180014, 0x000000FEU ,0x00000002U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_5_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_5_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_6 @ 0XFF180018
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
+		PSU_IOU_SLCR_MIO_PIN_6_L0_SEL                                                   0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_6_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[6]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_6_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
+		sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
+		Output, tracedq[4]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_6_L3_SEL                                                   0
+
+		Configures MIO Pin 6 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180018, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_6_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_6_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_7 @ 0XFF18001C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
+		PSU_IOU_SLCR_MIO_PIN_7_L0_SEL                                                   0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_7_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[7]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_7_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 
+		tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 
+		racedq[5]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_7_L3_SEL                                                   0
+
+		Configures MIO Pin 7 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18001C, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_7_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_7_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_8 @ 0XFF180020
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[0]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_8_L0_SEL                                                   0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_8_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[8]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_8_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
+		, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
+		ce Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_8_L3_SEL                                                   0
+
+		Configures MIO Pin 8 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180020, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_8_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_8_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_9 @ 0XFF180024
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[1]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_9_L0_SEL                                                   0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_9_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[9]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_9_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 
+		utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
+		RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_9_L3_SEL                                                   0
+
+		Configures MIO Pin 9 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180024, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_9_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_9_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_10 @ 0XFF180028
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[2]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_10_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_10_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[10]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_10_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_10_L3_SEL                                                  0
+
+		Configures MIO Pin 10 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180028, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_10_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_10_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_11 @ 0XFF18002C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[3]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_11_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_11_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[11]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_11_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_11_L3_SEL                                                  0
+
+		Configures MIO Pin 11 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18002C, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_11_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_11_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_12 @ 0XFF180030
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
+		PSU_IOU_SLCR_MIO_PIN_12_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		
+		PSU_IOU_SLCR_MIO_PIN_12_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[12]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_12_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
+		ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
+		dq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_12_L3_SEL                                                  0
+
+		Configures MIO Pin 12 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180030, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_12_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_12_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_13 @ 0XFF180034
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_13_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_13_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_13_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
+		out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
+		bus)
+		PSU_IOU_SLCR_MIO_PIN_13_L3_SEL                                                  0
+
+		Configures MIO Pin 13 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180034, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_13_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_13_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_14 @ 0XFF180038
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_14_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
+		PSU_IOU_SLCR_MIO_PIN_14_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_14_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
+		n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_14_L3_SEL                                                  0
+
+		Configures MIO Pin 14 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180038, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_14_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_14_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_15 @ 0XFF18003C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_15_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
+		PSU_IOU_SLCR_MIO_PIN_15_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_15_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
+		0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
+		l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_15_L3_SEL                                                  0
+
+		Configures MIO Pin 15 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18003C, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_15_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_15_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_16 @ 0XFF180040
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_16_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_16_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_16_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_16_L3_SEL                                                  0
+
+		Configures MIO Pin 16 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180040, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_16_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_16_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_17 @ 0XFF180044
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_17_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_17_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_17_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_17_L3_SEL                                                  0
+
+		Configures MIO Pin 17 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180044, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_17_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_17_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_18 @ 0XFF180048
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_18_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_18_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_18_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_18_L3_SEL                                                  0
+
+		Configures MIO Pin 18 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180048, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_18_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_18_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_19 @ 0XFF18004C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_19_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_19_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_19_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_19_L3_SEL                                                  0
+
+		Configures MIO Pin 19 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18004C, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_19_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_19_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_20 @ 0XFF180050
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_20_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_20_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_20_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
+		c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_20_L3_SEL                                                  0
+
+		Configures MIO Pin 20 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180050, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_20_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_20_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_21 @ 0XFF180054
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_21_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_21_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 
+		= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_21_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 
+		UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_21_L3_SEL                                                  0
+
+		Configures MIO Pin 21 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180054, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_21_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_21_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_22 @ 0XFF180058
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_22_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
+		PSU_IOU_SLCR_MIO_PIN_22_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
+		(Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_22_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed
+		PSU_IOU_SLCR_MIO_PIN_22_L3_SEL                                                  0
+
+		Configures MIO Pin 22 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180058, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_22_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_22_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_23 @ 0XFF18005C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_23_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_23_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
+		23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
+		
+		PSU_IOU_SLCR_MIO_PIN_23_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_23_L3_SEL                                                  0
+
+		Configures MIO Pin 23 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18005C, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_23_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_23_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_24 @ 0XFF180060
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_24_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_24_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
+		scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
+		 Tamper)
+		PSU_IOU_SLCR_MIO_PIN_24_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
+		Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_24_L3_SEL                                                  0
+
+		Configures MIO Pin 24 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180060, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_24_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_24_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_25 @ 0XFF180064
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_25_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
+		PSU_IOU_SLCR_MIO_PIN_25_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
+		test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
+		U Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_25_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 
+		lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_25_L3_SEL                                                  0
+
+		Configures MIO Pin 25 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180064, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_25_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_25_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_26 @ 0XFF180068
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_26_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_26_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_26_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_26_L3_SEL                                                  0
+
+		Configures MIO Pin 26 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180068, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_26_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_26_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_27 @ 0XFF18006C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_27_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_27_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_27_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)
+		PSU_IOU_SLCR_MIO_PIN_27_L3_SEL                                                  0
+
+		Configures MIO Pin 27 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18006C, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_27_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_27_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_28 @ 0XFF180070
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_28_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_28_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_28_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_28_L3_SEL                                                  0
+
+		Configures MIO Pin 28 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180070, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_28_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_28_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_29 @ 0XFF180074
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_29_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_29_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_29_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_29_L3_SEL                                                  4
+
+		Configures MIO Pin 29 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180074, 0x000000FEU ,0x00000080U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_29_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
+			| 0x00000004U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_29_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_30 @ 0XFF180078
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_30_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_30_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_30_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
+		 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
+		 tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_30_L3_SEL                                                  0
+
+		Configures MIO Pin 30 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180078, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_30_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_30_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_31 @ 0XFF18007C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_31_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_31_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_31_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
+		_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
+		ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_31_L3_SEL                                                  0
+
+		Configures MIO Pin 31 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18007C, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_31_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_31_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_32 @ 0XFF180080
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_32_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		
+		PSU_IOU_SLCR_MIO_PIN_32_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_32_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
+		_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 
+		race, Output, tracedq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_32_L3_SEL                                                  0
+
+		Configures MIO Pin 32 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180080, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_32_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_32_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_33 @ 0XFF180084
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_33_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_33_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_33_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
+		c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
+		[11]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_33_L3_SEL                                                  0
+
+		Configures MIO Pin 33 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180084, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_33_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_33_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_34 @ 0XFF180088
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_34_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_34_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_34_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
+		 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
+		rt Databus)
+		PSU_IOU_SLCR_MIO_PIN_34_L3_SEL                                                  0
+
+		Configures MIO Pin 34 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180088, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_34_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_34_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_35 @ 0XFF18008C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_35_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_35_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_35_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
+		Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 
+		UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_35_L3_SEL                                                  4
+
+		Configures MIO Pin 35 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18008C, 0x000000FEU ,0x00000080U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_35_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
+			| 0x00000004U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_35_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_36 @ 0XFF180090
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_36_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_36_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_36_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_36_L3_SEL                                                  0
+
+		Configures MIO Pin 36 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180090, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_36_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_36_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_37 @ 0XFF180094
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_37_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_37_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_37_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_37_L3_SEL                                                  0
+
+		Configures MIO Pin 37 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180094, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_37_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_37_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_38 @ 0XFF180098
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_38_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_38_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_38_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
+		k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
+		(Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_38_L3_SEL                                                  0
+
+		Configures MIO Pin 38 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180098, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_38_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_38_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_39 @ 0XFF18009C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_39_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_39_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
+		[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_39_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
+		_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
+		Control Signal)
+		PSU_IOU_SLCR_MIO_PIN_39_L3_SEL                                                  0
+
+		Configures MIO Pin 39 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18009C, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_39_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_39_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_40 @ 0XFF1800A0
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_40_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_40_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_40_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
+		in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_40_L3_SEL                                                  0
+
+		Configures MIO Pin 40 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A0, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_40_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_40_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_41 @ 0XFF1800A4
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_41_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_41_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_41_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
+		]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
+		ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_41_L3_SEL                                                  0
+
+		Configures MIO Pin 41 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A4, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_41_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_41_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_42 @ 0XFF1800A8
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_42_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_42_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_42_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_42_L3_SEL                                                  0
+
+		Configures MIO Pin 42 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A8, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_42_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_42_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_43 @ 0XFF1800AC
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_43_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_43_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_43_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
+		i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_43_L3_SEL                                                  0
+
+		Configures MIO Pin 43 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800AC, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_43_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_43_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_44 @ 0XFF1800B0
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_44_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
+		i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L3_SEL                                                  0
+
+		Configures MIO Pin 44 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B0, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_44_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_44_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_45 @ 0XFF1800B4
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_45_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L3_SEL                                                  0
+
+		Configures MIO Pin 45 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B4, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_45_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_45_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_46 @ 0XFF1800B8
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_46_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
+		0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L3_SEL                                                  0
+
+		Configures MIO Pin 46 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B8, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_46_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_46_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_47 @ 0XFF1800BC
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_47_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L3_SEL                                                  0
+
+		Configures MIO Pin 47 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800BC, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_47_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_47_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_48 @ 0XFF1800C0
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_48_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_48_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_48_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
+		ed
+		PSU_IOU_SLCR_MIO_PIN_48_L3_SEL                                                  0
+
+		Configures MIO Pin 48 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C0, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_48_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_48_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_49 @ 0XFF1800C4
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_49_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
+		bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L3_SEL                                                  0
+
+		Configures MIO Pin 49 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C4, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_49_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_49_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_50 @ 0XFF1800C8
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		PSU_IOU_SLCR_MIO_PIN_50_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
+		d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
+		clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L3_SEL                                                  0
+
+		Configures MIO Pin 50 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C8, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_50_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_50_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_51 @ 0XFF1800CC
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		PSU_IOU_SLCR_MIO_PIN_51_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
+		t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
+		serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L3_SEL                                                  0
+
+		Configures MIO Pin 51 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800CC, 0x000000FEU ,0x00000010U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_51_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_51_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_52 @ 0XFF1800D0
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_52_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L3_SEL                                                  0
+
+		Configures MIO Pin 52 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D0, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_52_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_52_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_53 @ 0XFF1800D4
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_53_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
+		PSU_IOU_SLCR_MIO_PIN_53_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_53_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)
+		PSU_IOU_SLCR_MIO_PIN_53_L3_SEL                                                  0
+
+		Configures MIO Pin 53 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D4, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_53_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_53_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_54 @ 0XFF1800D8
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_54_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[2]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_54_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_54_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_54_L3_SEL                                                  0
+
+		Configures MIO Pin 54 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D8, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_54_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_54_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_55 @ 0XFF1800DC
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_55_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
+		PSU_IOU_SLCR_MIO_PIN_55_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_55_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_55_L3_SEL                                                  0
+
+		Configures MIO Pin 55 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800DC, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_55_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_55_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_56 @ 0XFF1800E0
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_56_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[0]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_56_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_56_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_56_L3_SEL                                                  0
+
+		Configures MIO Pin 56 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E0, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_56_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_56_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_57 @ 0XFF1800E4
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_57_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[1]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_57_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_57_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_57_L3_SEL                                                  0
+
+		Configures MIO Pin 57 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E4, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_57_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_57_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_58 @ 0XFF1800E8
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_58_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
+		PSU_IOU_SLCR_MIO_PIN_58_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_58_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_58_L3_SEL                                                  0
+
+		Configures MIO Pin 58 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E8, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_58_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_58_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_59 @ 0XFF1800EC
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_59_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[3]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_59_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_59_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)
+		PSU_IOU_SLCR_MIO_PIN_59_L3_SEL                                                  0
+
+		Configures MIO Pin 59 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800EC, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_59_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_59_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_60 @ 0XFF1800F0
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_60_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[4]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_60_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_60_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_60_L3_SEL                                                  0
+
+		Configures MIO Pin 60 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F0, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_60_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_60_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_61 @ 0XFF1800F4
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_61_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[5]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_61_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_61_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_61_L3_SEL                                                  0
+
+		Configures MIO Pin 61 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F4, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_61_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_61_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_62 @ 0XFF1800F8
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_62_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[6]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_62_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_62_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_62_L3_SEL                                                  0
+
+		Configures MIO Pin 62 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F8, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_62_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_62_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_63 @ 0XFF1800FC
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_63_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[7]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_63_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_63_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_63_L3_SEL                                                  0
+
+		Configures MIO Pin 63 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800FC, 0x000000FEU ,0x00000004U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_63_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_63_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_64 @ 0XFF180100
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_64_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_64_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_64_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
+		i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 trace, Output, tracedq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_64_L3_SEL                                                  0
+
+		Configures MIO Pin 64 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180100, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_64_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_64_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_65 @ 0XFF180104
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_65_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
+		PSU_IOU_SLCR_MIO_PIN_65_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_65_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
+		dq[11]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_65_L3_SEL                                                  0
+
+		Configures MIO Pin 65 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180104, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_65_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_65_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_66 @ 0XFF180108
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_66_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[2]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_66_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_66_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
+		2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
+		Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_66_L3_SEL                                                  0
+
+		Configures MIO Pin 66 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180108, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_66_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_66_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_67 @ 0XFF18010C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_67_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
+		PSU_IOU_SLCR_MIO_PIN_67_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_67_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_67_L3_SEL                                                  0
+
+		Configures MIO Pin 67 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18010C, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_67_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_67_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_68 @ 0XFF180110
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_68_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[0]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_68_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_68_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_68_L3_SEL                                                  0
+
+		Configures MIO Pin 68 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180110, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_68_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_68_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_69 @ 0XFF180114
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_69_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[1]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_69_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_69_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_69_L3_SEL                                                  0
+
+		Configures MIO Pin 69 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180114, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_69_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_69_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_70 @ 0XFF180118
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_70_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
+		PSU_IOU_SLCR_MIO_PIN_70_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_70_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed
+		PSU_IOU_SLCR_MIO_PIN_70_L3_SEL                                                  0
+
+		Configures MIO Pin 70 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180118, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_70_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_70_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_71 @ 0XFF18011C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_71_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[3]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_71_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_71_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_71_L3_SEL                                                  0
+
+		Configures MIO Pin 71 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18011C, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_71_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_71_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_72 @ 0XFF180120
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_72_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[4]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_72_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_72_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
+		t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_72_L3_SEL                                                  0
+
+		Configures MIO Pin 72 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180120, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_72_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_72_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_73 @ 0XFF180124
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_73_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[5]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_73_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_73_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_73_L3_SEL                                                  0
+
+		Configures MIO Pin 73 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180124, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_73_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_73_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_74 @ 0XFF180128
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_74_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[6]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_74_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_74_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_74_L3_SEL                                                  0
+
+		Configures MIO Pin 74 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180128, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_74_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_74_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_75 @ 0XFF18012C
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_75_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[7]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_75_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
+		d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_75_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_75_L3_SEL                                                  0
+
+		Configures MIO Pin 75 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18012C, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_75_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_75_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_76 @ 0XFF180130
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
+		_clk_out- (SDSDIO clock) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
+		 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L3_SEL                                                  0
+
+		Configures MIO Pin 76 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180130, 0x000000FEU ,0x00000008U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_76_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_76_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_77 @ 0XFF180134
    
+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
+		O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
+		t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L3_SEL                                                  0
+
+		Configures MIO Pin 77 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180134, 0x000000FEU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_77_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_PIN_77_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI0 @ 0XFF180204
    
+
+		Master Tri-state Enable for pin 0, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI                                            0
+
+		Master Tri-state Enable for pin 1, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI                                            0
+
+		Master Tri-state Enable for pin 2, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI                                            0
+
+		Master Tri-state Enable for pin 3, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI                                            0
+
+		Master Tri-state Enable for pin 4, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI                                            0
+
+		Master Tri-state Enable for pin 5, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI                                            0
+
+		Master Tri-state Enable for pin 6, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI                                            0
+
+		Master Tri-state Enable for pin 7, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI                                            0
+
+		Master Tri-state Enable for pin 8, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI                                            0
+
+		Master Tri-state Enable for pin 9, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI                                            0
+
+		Master Tri-state Enable for pin 10, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI                                            1
+
+		Master Tri-state Enable for pin 11, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI                                            1
+
+		Master Tri-state Enable for pin 12, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI                                            0
+
+		Master Tri-state Enable for pin 13, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI                                            0
+
+		Master Tri-state Enable for pin 14, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI                                            0
+
+		Master Tri-state Enable for pin 15, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI                                            0
+
+		Master Tri-state Enable for pin 16, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI                                            0
+
+		Master Tri-state Enable for pin 17, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI                                            0
+
+		Master Tri-state Enable for pin 18, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI                                            0
+
+		Master Tri-state Enable for pin 19, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI                                            0
+
+		Master Tri-state Enable for pin 20, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI                                            0
+
+		Master Tri-state Enable for pin 21, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI                                            0
+
+		Master Tri-state Enable for pin 22, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI                                            0
+
+		Master Tri-state Enable for pin 23, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI                                            0
+
+		Master Tri-state Enable for pin 24, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI                                            0
+
+		Master Tri-state Enable for pin 25, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI                                            0
+
+		Master Tri-state Enable for pin 26, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI                                            0
+
+		Master Tri-state Enable for pin 27, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI                                            0
+
+		Master Tri-state Enable for pin 28, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI                                            0
+
+		Master Tri-state Enable for pin 29, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI                                            0
+
+		Master Tri-state Enable for pin 30, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI                                            0
+
+		Master Tri-state Enable for pin 31, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI                                            0
+
+		MIO pin Tri-state Enables, 31:0
+		(OFFSET, MASK, VALUE)      (0XFF180204, 0xFFFFFFFFU ,0x00000C00U)  */
+		RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_MST_TRI0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_MST_TRI0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI1 @ 0XFF180208
    
+
+		Master Tri-state Enable for pin 32, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI                                            0
+
+		Master Tri-state Enable for pin 33, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI                                            0
+
+		Master Tri-state Enable for pin 34, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI                                            0
+
+		Master Tri-state Enable for pin 35, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI                                            0
+
+		Master Tri-state Enable for pin 36, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI                                            0
+
+		Master Tri-state Enable for pin 37, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI                                            0
+
+		Master Tri-state Enable for pin 38, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI                                            0
+
+		Master Tri-state Enable for pin 39, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI                                            0
+
+		Master Tri-state Enable for pin 40, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI                                            0
+
+		Master Tri-state Enable for pin 41, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI                                            0
+
+		Master Tri-state Enable for pin 42, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI                                            0
+
+		Master Tri-state Enable for pin 43, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI                                            0
+
+		Master Tri-state Enable for pin 44, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI                                            0
+
+		Master Tri-state Enable for pin 45, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI                                            0
+
+		Master Tri-state Enable for pin 46, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI                                            0
+
+		Master Tri-state Enable for pin 47, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI                                            0
+
+		Master Tri-state Enable for pin 48, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI                                            0
+
+		Master Tri-state Enable for pin 49, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI                                            0
+
+		Master Tri-state Enable for pin 50, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI                                            0
+
+		Master Tri-state Enable for pin 51, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI                                            0
+
+		Master Tri-state Enable for pin 52, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI                                            1
+
+		Master Tri-state Enable for pin 53, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI                                            1
+
+		Master Tri-state Enable for pin 54, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI                                            0
+
+		Master Tri-state Enable for pin 55, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI                                            1
+
+		Master Tri-state Enable for pin 56, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI                                            0
+
+		Master Tri-state Enable for pin 57, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI                                            0
+
+		Master Tri-state Enable for pin 58, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI                                            0
+
+		Master Tri-state Enable for pin 59, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI                                            0
+
+		Master Tri-state Enable for pin 60, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI                                            0
+
+		Master Tri-state Enable for pin 61, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI                                            0
+
+		Master Tri-state Enable for pin 62, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI                                            0
+
+		Master Tri-state Enable for pin 63, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI                                            0
+
+		MIO pin Tri-state Enables, 63:32
+		(OFFSET, MASK, VALUE)      (0XFF180208, 0xFFFFFFFFU ,0x00B00000U)  */
+		RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_MST_TRI1_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_MST_TRI1_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI2 @ 0XFF18020C
    
+
+		Master Tri-state Enable for pin 64, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI                                            0
+
+		Master Tri-state Enable for pin 65, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI                                            1
+
+		Master Tri-state Enable for pin 66, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI                                            0
+
+		Master Tri-state Enable for pin 67, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI                                            0
+
+		Master Tri-state Enable for pin 68, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI                                            0
+
+		Master Tri-state Enable for pin 69, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI                                            0
+
+		Master Tri-state Enable for pin 70, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI                                            0
+
+		Master Tri-state Enable for pin 71, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI                                            0
+
+		Master Tri-state Enable for pin 72, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI                                            0
+
+		Master Tri-state Enable for pin 73, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI                                            0
+
+		Master Tri-state Enable for pin 74, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI                                            0
+
+		Master Tri-state Enable for pin 75, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI                                            0
+
+		Master Tri-state Enable for pin 76, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI                                            1
+
+		Master Tri-state Enable for pin 77, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI                                            0
+
+		MIO pin Tri-state Enables, 77:64
+		(OFFSET, MASK, VALUE)      (0XFF18020C, 0x00003FFFU ,0x00001002U)  */
+		RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_MST_TRI2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_MST_TRI2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : LOOPBACK
+		/*Register : MIO_LOOPBACK @ 0XFF180200
    
+
+		I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
+		ts to I2C 0 inputs.
+		PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1                                        0
+
+		CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
+		.
+		PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1                                        0
+
+		UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
+		outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
+		PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1                                          0
+
+		SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
+		ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
+		PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1                                        0
+
+		Loopback function within MIO
+		(OFFSET, MASK, VALUE)      (0XFF180200, 0x0000000FU ,0x00000000U)  */
+		RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_MIO_LOOPBACK_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_MIO_LOOPBACK_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+
+}
+unsigned long psu_peripherals_init_data_3_0() {
+		// : ENET
+		/*Register : RST_LPD_IOU0 @ 0XFF5E0230
    
+
+		GEM 0 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM0_RESET                                             0
+
+		GEM 1 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM1_RESET                                             0
+
+		GEM 2 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM2_RESET                                             0
+
+		GEM 3 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0
+
+		Software controlled reset for the GEMs
+		(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x0000000FU ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK | CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK | CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK | CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : QSPI
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238
    
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000001U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : NAND
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238
    
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_NAND_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00010000U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : USB
+		/*Register : RST_LPD_TOP @ 0XFF5E023C
    
+
+		USB 0 reset for control registers
+		PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0
+
+		USB 0 sleep circuit reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0
+
+		USB 0 reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_TOP_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_TOP_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : SD
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238
    
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SDIO0_RESET                                            0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET                                            0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000060U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK | CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : CTRL_REG_SD @ 0XFF180310
    
+
+		SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled
+		PSU_IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL                                           0
+
+		SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
+		PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL                                           0
+
+		SD eMMC selection
+		(OFFSET, MASK, VALUE)      (0XFF180310, 0x00008001U ,0x00000000U)  */
+		RegMask = (IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_MASK | IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_CTRL_REG_SD_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_CTRL_REG_SD_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : SD_CONFIG_REG2 @ 0XFF180320
    
+
+		Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE                                        0
+
+		Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE                                        0
+
+		1.8V Support 1: 1.8V supported 0: 1.8V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V                                            1
+
+		3.0V Support 1: 3.0V supported 0: 3.0V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V                                            0
+
+		3.3V Support 1: 3.3V supported 0: 3.3V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V                                            1
+
+		1.8V Support 1: 1.8V supported 0: 1.8V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V                                            1
+
+		3.0V Support 1: 3.0V supported 0: 3.0V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V                                            0
+
+		3.3V Support 1: 3.3V supported 0: 3.3V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V                                            1
+
+		SD Config Register 2
+		(OFFSET, MASK, VALUE)      (0XFF180320, 0x33803380U ,0x02800280U)  */
+		RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK |  0 );
+
+		RegVal = Xil_In32 (IOU_SLCR_SD_CONFIG_REG2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( IOU_SLCR_SD_CONFIG_REG2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CAN
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238
    
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_CAN0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000180U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK | CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : I2C
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238
    
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000600U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : SWDT
+		// : SPI
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238
    
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SPI0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SPI1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000018U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK | CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : TTC
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238
    
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00007800U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : UART
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238
    
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET                                            0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET                                            0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000006U ,0x00000000U)  */
+		RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK |  0 );
+
+		RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_divider_reg0 @ 0XFF000034
    
+
+		Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x0
+
+		Baud Rate Divider Register
+		(OFFSET, MASK, VALUE)      (0XFF000034, 0x000000FFU ,0x00000000U)  */
+		RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
+
+		RegVal = Xil_In32 (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART0_BAUD_RATE_DIVIDER_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_gen_reg0 @ 0XFF000018
    
+
+		Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		PSU_UART0_BAUD_RATE_GEN_REG0_CD                                                 0x0
+
+		Baud Rate Generator Register.
+		(OFFSET, MASK, VALUE)      (0XFF000018, 0x0000FFFFU ,0x00000000U)  */
+		RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
+
+		RegVal = Xil_In32 (UART0_BAUD_RATE_GEN_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART0_BAUD_RATE_GEN_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Control_reg0 @ 0XFF000000
    
+
+		Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		PSU_UART0_CONTROL_REG0_STPBRK                                                   0x0
+
+		Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		PSU_UART0_CONTROL_REG0_STTBRK                                                   0x0
+
+		Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.
+		PSU_UART0_CONTROL_REG0_RSTTO                                                    0x0
+
+		Transmit disable: 0: enable transmitter 1: disable transmitter
+		PSU_UART0_CONTROL_REG0_TXDIS                                                    0x0
+
+		Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		PSU_UART0_CONTROL_REG0_TXEN                                                     0x1
+
+		Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		PSU_UART0_CONTROL_REG0_RXDIS                                                    0x0
+
+		Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		PSU_UART0_CONTROL_REG0_RXEN                                                     0x1
+
+		Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.
+		PSU_UART0_CONTROL_REG0_TXRES                                                    0x1
+
+		Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.
+		PSU_UART0_CONTROL_REG0_RXRES                                                    0x1
+
+		UART Control Register
+		(OFFSET, MASK, VALUE)      (0XFF000000, 0x000001FFU ,0x00000017U)  */
+		RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK |  0 );
+
+		RegVal = Xil_In32 (UART0_CONTROL_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART0_CONTROL_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : mode_reg0 @ 0XFF000004
    
+
+		Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		PSU_UART0_MODE_REG0_CHMODE                                                      0x0
+
+		Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved
+		PSU_UART0_MODE_REG0_NBSTOP                                                      0x0
+
+		Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		PSU_UART0_MODE_REG0_PAR                                                         0x4
+
+		Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		PSU_UART0_MODE_REG0_CHRL                                                        0x0
+
+		Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		PSU_UART0_MODE_REG0_CLKS                                                        0x0
+
+		UART Mode Register
+		(OFFSET, MASK, VALUE)      (0XFF000004, 0x000003FFU ,0x00000020U)  */
+		RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK |  0 );
+
+		RegVal = Xil_In32 (UART0_MODE_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT
+			| 0x00000004U << UART0_MODE_REG0_PAR_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART0_MODE_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_divider_reg0 @ 0XFF010034
    
+
+		Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x0
+
+		Baud Rate Divider Register
+		(OFFSET, MASK, VALUE)      (0XFF010034, 0x000000FFU ,0x00000000U)  */
+		RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
+
+		RegVal = Xil_In32 (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART1_BAUD_RATE_DIVIDER_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_gen_reg0 @ 0XFF010018
    
+
+		Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		PSU_UART1_BAUD_RATE_GEN_REG0_CD                                                 0x0
+
+		Baud Rate Generator Register.
+		(OFFSET, MASK, VALUE)      (0XFF010018, 0x0000FFFFU ,0x00000000U)  */
+		RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
+
+		RegVal = Xil_In32 (UART1_BAUD_RATE_GEN_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART1_BAUD_RATE_GEN_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : Control_reg0 @ 0XFF010000
    
+
+		Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		PSU_UART1_CONTROL_REG0_STPBRK                                                   0x0
+
+		Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		PSU_UART1_CONTROL_REG0_STTBRK                                                   0x0
+
+		Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.
+		PSU_UART1_CONTROL_REG0_RSTTO                                                    0x0
+
+		Transmit disable: 0: enable transmitter 1: disable transmitter
+		PSU_UART1_CONTROL_REG0_TXDIS                                                    0x0
+
+		Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		PSU_UART1_CONTROL_REG0_TXEN                                                     0x1
+
+		Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		PSU_UART1_CONTROL_REG0_RXDIS                                                    0x0
+
+		Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		PSU_UART1_CONTROL_REG0_RXEN                                                     0x1
+
+		Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.
+		PSU_UART1_CONTROL_REG0_TXRES                                                    0x1
+
+		Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.
+		PSU_UART1_CONTROL_REG0_RXRES                                                    0x1
+
+		UART Control Register
+		(OFFSET, MASK, VALUE)      (0XFF010000, 0x000001FFU ,0x00000017U)  */
+		RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK |  0 );
+
+		RegVal = Xil_In32 (UART1_CONTROL_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART1_CONTROL_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : mode_reg0 @ 0XFF010004
    
+
+		Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		PSU_UART1_MODE_REG0_CHMODE                                                      0x0
+
+		Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved
+		PSU_UART1_MODE_REG0_NBSTOP                                                      0x0
+
+		Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		PSU_UART1_MODE_REG0_PAR                                                         0x4
+
+		Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		PSU_UART1_MODE_REG0_CHRL                                                        0x0
+
+		Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		PSU_UART1_MODE_REG0_CLKS                                                        0x0
+
+		UART Mode Register
+		(OFFSET, MASK, VALUE)      (0XFF010004, 0x000003FFU ,0x00000020U)  */
+		RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK |  0 );
+
+		RegVal = Xil_In32 (UART1_MODE_REG0_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT
+			| 0x00000004U << UART1_MODE_REG0_PAR_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( UART1_MODE_REG0_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : GPIO
+		// : ADMA TZ
+		/*Register : slcr_adma @ 0XFF4B0024
    
+
+		TrustZone Classification for ADMA
+		PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ                                                0XFF
+
+		RPU TrustZone settings
+		(OFFSET, MASK, VALUE)      (0XFF4B0024, 0x000000FFU ,0x000000FFU)  */
+		RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_SLCR_SECURE_SLCR_ADMA_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CSU TAMPERING
+		// : CSU TAMPER STATUS
+		/*Register : tamper_status @ 0XFFCA5000
    
+
+		CSU regsiter
+		PSU_CSU_TAMPER_STATUS_TAMPER_0                                                  0
+
+		External MIO
+		PSU_CSU_TAMPER_STATUS_TAMPER_1                                                  0
+
+		JTAG toggle detect
+		PSU_CSU_TAMPER_STATUS_TAMPER_2                                                  0
+
+		PL SEU error
+		PSU_CSU_TAMPER_STATUS_TAMPER_3                                                  0
+
+		AMS over temperature alarm for LPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_4                                                  0
+
+		AMS over temperature alarm for APU
+		PSU_CSU_TAMPER_STATUS_TAMPER_5                                                  0
+
+		AMS voltage alarm for VCCPINT_FPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_6                                                  0
+
+		AMS voltage alarm for VCCPINT_LPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_7                                                  0
+
+		AMS voltage alarm for VCCPAUX
+		PSU_CSU_TAMPER_STATUS_TAMPER_8                                                  0
+
+		AMS voltage alarm for DDRPHY
+		PSU_CSU_TAMPER_STATUS_TAMPER_9                                                  0
+
+		AMS voltage alarm for PSIO bank 0/1/2
+		PSU_CSU_TAMPER_STATUS_TAMPER_10                                                 0
+
+		AMS voltage alarm for PSIO bank 3 (dedicated pins)
+		PSU_CSU_TAMPER_STATUS_TAMPER_11                                                 0
+
+		AMS voltaage alarm for GT
+		PSU_CSU_TAMPER_STATUS_TAMPER_12                                                 0
+
+		Tamper Response Status
+		(OFFSET, MASK, VALUE)      (0XFFCA5000, 0x00001FFFU ,0x00000000U)  */
+		RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK |  0 );
+
+		RegVal = Xil_In32 (CSU_TAMPER_STATUS_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( CSU_TAMPER_STATUS_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : CSU TAMPER RESPONSE
+
+}
+unsigned long psu_post_config() {
+
+}
+unsigned long psu_peripherals_powerdwn_data_3_0() {
+		// : POWER DOWN REQUEST INTERRUPT ENABLE
+		// : POWER DOWN TRIGGER
+
+}
+unsigned long psu_security_data_3_0() {
+		// : DDR XMPU0
+		// : DDR XMPU1
+		// : DDR XMPU2
+		// : DDR XMPU3
+		// : DDR XMPU4
+		// : DDR XMPU5
+		// : FPD XMPU
+		// : OCM XMPU
+		// : XPPU
+		// : MASTER ID LIST
+		/*Register : MASTER_ID00 @ 0XFF980100
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID00_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID00_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID00_MIDM                                               0
+
+		Predefined Master ID for PMU
+		PSU_LPD_XPPU_CFG_MASTER_ID00_MID                                                0
+
+		Master ID 00 Register
+		(OFFSET, MASK, VALUE)      (0XFF980100, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID00_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID00_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID00_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID00_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID01 @ 0XFF980104
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID01_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID01_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID01_MIDM                                               0
+
+		Predefined Master ID for RPU0
+		PSU_LPD_XPPU_CFG_MASTER_ID01_MID                                                0
+
+		Master ID 01 Register
+		(OFFSET, MASK, VALUE)      (0XFF980104, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID01_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID01_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID01_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID01_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID02 @ 0XFF980108
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID02_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID02_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID02_MIDM                                               0
+
+		Predefined Master ID for RPU1
+		PSU_LPD_XPPU_CFG_MASTER_ID02_MID                                                0
+
+		Master ID 02 Register
+		(OFFSET, MASK, VALUE)      (0XFF980108, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID02_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID02_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID02_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID02_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID03 @ 0XFF98010C
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID03_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID03_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID03_MIDM                                               0
+
+		Predefined Master ID for APU
+		PSU_LPD_XPPU_CFG_MASTER_ID03_MID                                                0
+
+		Master ID 03 Register
+		(OFFSET, MASK, VALUE)      (0XFF98010C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID03_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID03_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID03_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID03_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID04 @ 0XFF980110
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID04_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID04_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID04_MIDM                                               0
+
+		Predefined Master ID for A53 Core 0
+		PSU_LPD_XPPU_CFG_MASTER_ID04_MID                                                0
+
+		Master ID 04 Register
+		(OFFSET, MASK, VALUE)      (0XFF980110, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID04_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID04_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID04_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID04_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID05 @ 0XFF980114
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID05_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID05_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID05_MIDM                                               0
+
+		Predefined Master ID for A53 Core 1
+		PSU_LPD_XPPU_CFG_MASTER_ID05_MID                                                0
+
+		Master ID 05 Register
+		(OFFSET, MASK, VALUE)      (0XFF980114, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID05_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID05_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID05_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID05_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID06 @ 0XFF980118
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID06_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID06_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID06_MIDM                                               0
+
+		Predefined Master ID for A53 Core 2
+		PSU_LPD_XPPU_CFG_MASTER_ID06_MID                                                0
+
+		Master ID 06 Register
+		(OFFSET, MASK, VALUE)      (0XFF980118, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID06_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID06_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID06_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID06_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID07 @ 0XFF98011C
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID07_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID07_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID07_MIDM                                               0
+
+		Predefined Master ID for A53 Core 3
+		PSU_LPD_XPPU_CFG_MASTER_ID07_MID                                                0
+
+		Master ID 07 Register
+		(OFFSET, MASK, VALUE)      (0XFF98011C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID07_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID07_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID07_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID07_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID08 @ 0XFF980120
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID08_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID08_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID08_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID08_MID                                                0
+
+		Master ID 08 Register
+		(OFFSET, MASK, VALUE)      (0XFF980120, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID08_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID08_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID08_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID08_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID08_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID08_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID09 @ 0XFF980124
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID09_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID09_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID09_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID09_MID                                                0
+
+		Master ID 09 Register
+		(OFFSET, MASK, VALUE)      (0XFF980124, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID09_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID09_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID09_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID09_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID09_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID09_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID10 @ 0XFF980128
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID10_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID10_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID10_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID10_MID                                                0
+
+		Master ID 10 Register
+		(OFFSET, MASK, VALUE)      (0XFF980128, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID10_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID10_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID10_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID10_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID10_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID10_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID11 @ 0XFF98012C
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID11_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID11_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID11_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID11_MID                                                0
+
+		Master ID 11 Register
+		(OFFSET, MASK, VALUE)      (0XFF98012C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID11_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID11_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID11_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID11_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID11_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID11_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID12 @ 0XFF980130
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID12_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID12_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID12_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID12_MID                                                0
+
+		Master ID 12 Register
+		(OFFSET, MASK, VALUE)      (0XFF980130, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID12_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID12_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID12_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID12_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID12_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID12_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID13 @ 0XFF980134
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID13_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID13_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID13_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID13_MID                                                0
+
+		Master ID 13 Register
+		(OFFSET, MASK, VALUE)      (0XFF980134, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID13_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID13_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID13_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID13_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID13_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID13_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID14 @ 0XFF980138
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID14_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID14_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID14_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID14_MID                                                0
+
+		Master ID 14 Register
+		(OFFSET, MASK, VALUE)      (0XFF980138, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID14_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID14_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID14_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID14_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID14_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID14_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID15 @ 0XFF98013C
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID15_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID15_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID15_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID15_MID                                                0
+
+		Master ID 15 Register
+		(OFFSET, MASK, VALUE)      (0XFF98013C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID15_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID15_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID15_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID15_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID15_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID15_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID16 @ 0XFF980140
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID16_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID16_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID16_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID16_MID                                                0
+
+		Master ID 16 Register
+		(OFFSET, MASK, VALUE)      (0XFF980140, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID16_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID16_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID16_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID16_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID16_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID16_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID17 @ 0XFF980144
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID17_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID17_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID17_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID17_MID                                                0
+
+		Master ID 17 Register
+		(OFFSET, MASK, VALUE)      (0XFF980144, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID17_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID17_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID17_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID17_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID17_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID17_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID18 @ 0XFF980148
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID18_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID18_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID18_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID18_MID                                                0
+
+		Master ID 18 Register
+		(OFFSET, MASK, VALUE)      (0XFF980148, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID18_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID18_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID18_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID18_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID18_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID18_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		/*Register : MASTER_ID19 @ 0XFF98014C
    
+
+		Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
+		PSU_LPD_XPPU_CFG_MASTER_ID19_MIDP                                               0
+
+		If set, only read transactions are allowed for the masters matching this register
+		PSU_LPD_XPPU_CFG_MASTER_ID19_MIDR                                               0
+
+		Mask to be applied before comparing
+		PSU_LPD_XPPU_CFG_MASTER_ID19_MIDM                                               0
+
+		Programmable Master ID
+		PSU_LPD_XPPU_CFG_MASTER_ID19_MID                                                0
+
+		Master ID 19 Register
+		(OFFSET, MASK, VALUE)      (0XFF98014C, 0xC3FF03FFU ,0x00000000U)  */
+		RegMask = (LPD_XPPU_CFG_MASTER_ID19_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID19_MID_MASK |  0 );
+
+		RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID19_OFFSET);
+		RegVal &= ~(RegMask);
+		RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDP_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT
+			| 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT
+			|  0 ) & RegMask);
+		Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID19_OFFSET , RegVal);
+
+	/*############################################################################################################################ */
+
+		// : APERTURE PERMISIION LIST
+
+}
+/**
+ * CRL_APB Base Address
+ */
+#define CRL_APB_BASEADDR      0XFF5E0000U
+#define CRL_APB_RST_LPD_IOU0    ( ( CRL_APB_BASEADDR ) + 0X00000230U )
+#define CRL_APB_RST_LPD_IOU1    ( ( CRL_APB_BASEADDR ) + 0X00000234U )
+#define CRL_APB_RST_LPD_IOU2    ( ( CRL_APB_BASEADDR ) + 0X00000238U )
+#define CRL_APB_RST_LPD_TOP    ( ( CRL_APB_BASEADDR ) + 0X0000023CU )
+#define CRL_APB_IOU_SWITCH_CTRL    ( ( CRL_APB_BASEADDR ) + 0X0000009CU )
+
+/**
+ * CRF_APB Base Address
+ */
+#define CRF_APB_BASEADDR      0XFD1A0000U
+
+#define CRF_APB_RST_FPD_TOP    ( ( CRF_APB_BASEADDR ) + 0X00000100U )
+#define CRF_APB_GPU_REF_CTRL    ( ( CRF_APB_BASEADDR ) + 0X00000084U )
+#define CRF_APB_RST_DDR_SS    ( ( CRF_APB_BASEADDR ) + 0X00000108U )
+
+void init_ddrc()
+{
+
+	Xil_Out32(  0XFD1A0108, 0x0000000F)  ; //#RST_DDR_SS 0xFE500108
+		Xil_Out32(  0xFD070000, 0x41040001)  ; //#MSTR
+		Xil_Out32(  0xFD070034, 0x00404310)  ; //#PWRTMG
+		Xil_Out32(  0xFD070064, 0x0040001E)  ; //#RFSHTMG 
+		Xil_Out32(  0xFD070070, 0x00000010)  ; //#ECCCFG0
+		Xil_Out32(  0xFD070074, 0x00000000)  ; //#ECCCFG1
+		Xil_Out32(  0xFD0700C4, 0x10000200)  ; //#CRCPARCTL1
+		Xil_Out32(  0xFD0700C8, 0x0030051F)  ; //#CRCPARCTL2
+		Xil_Out32(  0xFD0700D0, 0x40020004)  ; //#INIT0  
+		Xil_Out32(  0xFD0700D4, 0x00010000)  ; //#INIT1 
+		Xil_Out32(  0xFD0700D8, 0x00001205)  ; //#INIT2
+		Xil_Out32(  0xFD0700DC, 0x09300000)  ; //#INIT3
+		Xil_Out32(  0xFD0700E0, 0x02080000)  ; //#INIT4
+		Xil_Out32(  0xFD0700E4, 0x00110004)  ; //#INIT5
+		Xil_Out32(  0xFD070100, 0x090E110A)  ; //#DRAMTMG0
+		Xil_Out32(  0xFD070104, 0x0007020E)  ; //#DRAMTMG1
+		Xil_Out32(  0xFD070108, 0x03040407)  ; //#DRAMTMG2
+		Xil_Out32(  0xFD07010C, 0x00502006)  ; //#DRAMTMG3
+		Xil_Out32(  0xFD070110, 0x04020205)  ; //#DRAMTMG4
+		Xil_Out32(  0xFD070114, 0x03030202)  ; //#DRAMTMG5
+		Xil_Out32(  0xFD070118, 0x01010003)  ; //#DRAMTMG6
+		Xil_Out32(  0xFD07011C, 0x00000101)  ; //#DRAMTMG7
+		Xil_Out32(  0xFD070120, 0x03030903)  ; //#DRAMTMG8
+		Xil_Out32(  0xFD070130, 0x00020608)  ; //#DRAMTMG12
+		Xil_Out32(  0xFD070180, 0x00800020)  ; //#ZQCTL0
+		Xil_Out32(  0xFD070184, 0x0200CB52)  ; //#ZQCTL1
+		Xil_Out32(  0xFD070190, 0x02838204)  ; //#DFITMG0 
+		Xil_Out32(  0xFD070194, 0x00020404)  ; //#DFITMG1 
+		Xil_Out32(  0xFD0701A4, 0x00010087)  ; //#DFIUPD1
+		Xil_Out32(  0xFD0701B0, 0x00000001)  ; //#DFIMISC #change-reset value
+		Xil_Out32(  0xFD0701B4, 0x00000202)  ; //#DFITMG2
+		Xil_Out32(  0xFD0701C0, 0x00000000)  ; //#DBICTL
+		Xil_Out32(  0xFD070200, 0x0000001F)  ; //#ADDRMAP0
+		Xil_Out32(  0xFD070204, 0x00080808)  ; //#ADDRMAP1
+		Xil_Out32(  0xFD070208, 0x00000000)  ; //#ADDRMAP2
+		Xil_Out32(  0xFD07020C, 0x00000000)  ; //#ADDRMAP3
+		Xil_Out32(  0xFD070210, 0x00000F0F)  ; //#ADDRMAP4
+		Xil_Out32(  0xFD070214, 0x07070707)  ; //#ADDRMAP5 
+		Xil_Out32(  0xFD070218, 0x07070707)  ; //#ADDRMAP6
+		Xil_Out32(  0xFD07021C, 0x00000F0F)  ; //#ADDRMAP7
+		Xil_Out32(  0xFD070220, 0x00000000)  ; //#ADDRMAP8
+		Xil_Out32(  0xFD070240, 0x06000604)  ; //#ODTCFG
+		Xil_Out32(  0xFD070244, 0x00000001)  ; //#ODTMAP
+		Xil_Out32(  0xFD070250, 0x01002001)  ; //#SCHED
+		Xil_Out32(  0xFD070264, 0x08000040)  ; //#PERFLPR1
+		Xil_Out32(  0xFD07026C, 0x08000040)  ; //#PERFWR1
+		Xil_Out32(  0xFD070294, 0x00000001)  ; //#DQMAP5
+		Xil_Out32(  0xFD07030C, 0x00000000)  ; //#DBGCMD
+		Xil_Out32(  0xFD070320, 0x00000000)  ; //#SWCTL
+		Xil_Out32(  0xFD070400, 0x00000001)  ; //#PCCFG
+		Xil_Out32(  0xFD070404, 0x0000600F)  ; //#PCFGR_0
+		Xil_Out32(  0xFD070408, 0x0000600F)  ; //#PCFGW_0
+		Xil_Out32(  0xFD070490, 0x00000001)  ; //#PCTRL_0
+		Xil_Out32(  0xFD070494, 0x0021000B)  ; //#PCFGQOS0_0
+		Xil_Out32(  0xFD070498, 0x004F004F)  ; //#PCFGQOS1_0
+		Xil_Out32(  0xFD0704B4, 0x0000600F)  ; //#PCFGR_1
+		Xil_Out32(  0xFD0704B8, 0x0000600F)  ; //#PCFGW_1
+		Xil_Out32(  0xFD070540, 0x00000001)  ; //#PCTRL_1
+		Xil_Out32(  0xFD070544, 0x02000B03)  ; //#PCFGQOS0_1
+		Xil_Out32(  0xFD070548, 0x00010040)  ; //#PCFGQOS1_1
+		Xil_Out32(  0xFD070564, 0x0000600F)  ; //#PCFGR_2
+		Xil_Out32(  0xFD070568, 0x0000600F)  ; //#PCFGW_2
+		Xil_Out32(  0xFD0705F0, 0x00000001)  ; //#PCTRL_2
+		Xil_Out32(  0xFD0705F4, 0x02000B03)  ; //#PCFGQOS0_2
+		Xil_Out32(  0xFD0705F8, 0x00010040)  ; //#PCFGQOS1_2
+		Xil_Out32(  0xFD070614, 0x0000600F)  ; //#PCFGR_3
+		Xil_Out32(  0xFD070618, 0x0000600F)  ; //#PCFGW_3
+		Xil_Out32(  0xFD0706A0, 0x00000001)  ; //#PCTRL_3
+		Xil_Out32(  0xFD0706A4, 0x00100003)  ; //#PCFGQOS0_3
+		Xil_Out32(  0xFD0706A8, 0x002F004F)  ; //#PCFGQOS1_3
+		Xil_Out32(  0xFD0706AC, 0x00100007)  ; //#PCFGWQOS0_3
+		Xil_Out32(  0xFD0706B0, 0x0000004F)  ; //#PCFGWQOS1_3
+		Xil_Out32(  0xFD0706C4, 0x0000600F)  ; //#PCFGR_4
+		Xil_Out32(  0xFD0706C8, 0x0000600F)  ; //#PCFGW_4
+		Xil_Out32(  0xFD070750, 0x00000001)  ; //#PCTRL_4
+		Xil_Out32(  0xFD070754, 0x00100003)  ; //#PCFGQOS0_4
+		Xil_Out32(  0xFD070758, 0x002F004F)  ; //#PCFGQOS1_4
+		Xil_Out32(  0xFD07075C, 0x00100007)  ; //#PCFGWQOS0_4
+		Xil_Out32(  0xFD070760, 0x0000004F)  ; //#PCFGWQOS1_4
+		Xil_Out32(  0xFD070774, 0x0000600F)  ; //#PCFGR_5
+		Xil_Out32(  0xFD070778, 0x0000600F)  ; //#PCFGW_5
+		Xil_Out32(  0xFD070800, 0x00000001)  ; //#PCTRL_5
+		Xil_Out32(  0xFD070804, 0x00100003)  ; //#PCFGQOS0_5
+		Xil_Out32(  0xFD070808, 0x002F004F)  ; //#PCFGQOS1_5
+		Xil_Out32(  0xFD07080C, 0x00100007)  ; //#PCFGWQOS0_5
+		Xil_Out32(  0xFD070810, 0x0000004F)  ; //#PCFGWQOS1_5
+		Xil_Out32(  0xFD070F04, 0x00000000)  ; //#SARBASE0
+		Xil_Out32(  0xFD070F08, 0x00000000)  ; //#SARSIZE0
+		Xil_Out32(  0xFD070F0C, 0x00000010)  ; //#SARBASE1
+		Xil_Out32(  0xFD070F10, 0x0000000F)  ; //#SARSIZE1
+		      
+		Xil_In32( 0XFD1A0108)  ; //#RST_DDR_SS 0xFE500108
+		Xil_Out32(  0XFD1A0108, 0x00000000)  ; //#RST_DDR_SS 0xFE500108 0
+		Xil_In32( 0XFD1A0108           )  ; //#RST_DDR_SS 0xFE500108  
+
+	/* Take DDR out of reset */
+	Xil_Out32( CRF_APB_RST_DDR_SS, 0x00000000);
+}
+
+void init_peripheral()
+{
+	unsigned int RegValue;
+
+	/* Turn on IOU Clock */
+	Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500);
+
+	/* Release all resets in the IOU */
+	Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000);
+	Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000);
+	Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000);
+
+	/* Activate GPU clocks */
+	Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500);
+
+	/* Take LPD out of reset except R5 */
+	RegValue = Xil_In32(CRL_APB_RST_LPD_TOP);
+	RegValue &= 0x3;
+	Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue);
+
+	/* Take most of FPD out of reset */
+	Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000);
+}
+int
+psu_init() 
+{
+    psu_mio_init_data ();
+    psu_pll_init_data ();
+    psu_clock_init_data ();
+    psu_ddr_init_data_3_0 ();
+    init_ddrc();
+    init_peripheral ();
+    psu_peripherals_init_data_3_0 ();
+    psu_peripherals_powerdwn_data_3_0 ();
+    psu_security_data_3_0();
+    return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.h
new file mode 100644
index 000000000..1903eb60f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.h
@@ -0,0 +1,6859 @@
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET                                            0XFF5E0048
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET                                           0XFF5E0044
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0048
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A004C
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0050
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_RPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRL_APB_RPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_RPLL_CTRL_DIV2_MASK 
+#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL                                              0x00012C09
+#define CRL_APB_RPLL_CTRL_DIV2_SHIFT                                               16
+#define CRL_APB_RPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*RPLL is locked*/
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL                                        0x00000018
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT                                         1
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK                                          0x00000002U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT                                             8
+#define CRL_APB_IOPLL_CTRL_FBDIV_MASK                                              0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_DIV2_MASK 
+#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL                                             0x00012C09
+#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT                                              16
+#define CRL_APB_IOPLL_CTRL_DIV2_MASK                                               0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
+
+/*IOPLL is locked*/
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL                                       0x00000018
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT                                        0
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK                                         0x00000001U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                  0x00000400
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_APLL_CTRL_FBDIV_MASK 
+#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_APLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_APLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_APLL_CTRL_DIV2_MASK 
+#define CRF_APB_APLL_CTRL_DIV2_DEFVAL                                              0x00012C09
+#define CRF_APB_APLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_APLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*APLL is locked*/
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT                                         0
+#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK                                          0x00000001U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_DPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_DPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_DPLL_CTRL_DIV2_MASK 
+#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL                                              0x00002C09
+#define CRF_APB_DPLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_DPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*DPLL is locked*/
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT                                         1
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK                                          0x00000002U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_VPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_VPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_VPLL_CTRL_DIV2_MASK 
+#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL                                              0x00012809
+#define CRF_APB_VPLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_VPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*VPLL is locked*/
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT                                         2
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK                                          0x00000004U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+#undef CRL_APB_GEM0_REF_CTRL_OFFSET 
+#define CRL_APB_GEM0_REF_CTRL_OFFSET                                               0XFF5E0050
+#undef CRL_APB_GEM1_REF_CTRL_OFFSET 
+#define CRL_APB_GEM1_REF_CTRL_OFFSET                                               0XFF5E0054
+#undef CRL_APB_GEM2_REF_CTRL_OFFSET 
+#define CRL_APB_GEM2_REF_CTRL_OFFSET                                               0XFF5E0058
+#undef CRL_APB_GEM3_REF_CTRL_OFFSET 
+#define CRL_APB_GEM3_REF_CTRL_OFFSET                                               0XFF5E005C
+#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET 
+#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET                                           0XFF5E0060
+#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 
+#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET                                          0XFF5E004C
+#undef CRL_APB_QSPI_REF_CTRL_OFFSET 
+#define CRL_APB_QSPI_REF_CTRL_OFFSET                                               0XFF5E0068
+#undef CRL_APB_SDIO0_REF_CTRL_OFFSET 
+#define CRL_APB_SDIO0_REF_CTRL_OFFSET                                              0XFF5E006C
+#undef CRL_APB_SDIO1_REF_CTRL_OFFSET 
+#define CRL_APB_SDIO1_REF_CTRL_OFFSET                                              0XFF5E0070
+#undef CRL_APB_UART0_REF_CTRL_OFFSET 
+#define CRL_APB_UART0_REF_CTRL_OFFSET                                              0XFF5E0074
+#undef CRL_APB_UART1_REF_CTRL_OFFSET 
+#define CRL_APB_UART1_REF_CTRL_OFFSET                                              0XFF5E0078
+#undef CRL_APB_I2C0_REF_CTRL_OFFSET 
+#define CRL_APB_I2C0_REF_CTRL_OFFSET                                               0XFF5E0120
+#undef CRL_APB_I2C1_REF_CTRL_OFFSET 
+#define CRL_APB_I2C1_REF_CTRL_OFFSET                                               0XFF5E0124
+#undef CRL_APB_SPI0_REF_CTRL_OFFSET 
+#define CRL_APB_SPI0_REF_CTRL_OFFSET                                               0XFF5E007C
+#undef CRL_APB_SPI1_REF_CTRL_OFFSET 
+#define CRL_APB_SPI1_REF_CTRL_OFFSET                                               0XFF5E0080
+#undef CRL_APB_CAN0_REF_CTRL_OFFSET 
+#define CRL_APB_CAN0_REF_CTRL_OFFSET                                               0XFF5E0084
+#undef CRL_APB_CAN1_REF_CTRL_OFFSET 
+#define CRL_APB_CAN1_REF_CTRL_OFFSET                                               0XFF5E0088
+#undef CRL_APB_CPU_R5_CTRL_OFFSET 
+#define CRL_APB_CPU_R5_CTRL_OFFSET                                                 0XFF5E0090
+#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET 
+#define CRL_APB_IOU_SWITCH_CTRL_OFFSET                                             0XFF5E009C
+#undef CRL_APB_PCAP_CTRL_OFFSET 
+#define CRL_APB_PCAP_CTRL_OFFSET                                                   0XFF5E00A4
+#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET 
+#define CRL_APB_LPD_SWITCH_CTRL_OFFSET                                             0XFF5E00A8
+#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET 
+#define CRL_APB_LPD_LSBUS_CTRL_OFFSET                                              0XFF5E00AC
+#undef CRL_APB_DBG_LPD_CTRL_OFFSET 
+#define CRL_APB_DBG_LPD_CTRL_OFFSET                                                0XFF5E00B0
+#undef CRL_APB_NAND_REF_CTRL_OFFSET 
+#define CRL_APB_NAND_REF_CTRL_OFFSET                                               0XFF5E00B4
+#undef CRL_APB_ADMA_REF_CTRL_OFFSET 
+#define CRL_APB_ADMA_REF_CTRL_OFFSET                                               0XFF5E00B8
+#undef CRL_APB_AMS_REF_CTRL_OFFSET 
+#define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
+#undef CRL_APB_DLL_REF_CTRL_OFFSET 
+#define CRL_APB_DLL_REF_CTRL_OFFSET                                                0XFF5E0104
+#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 
+#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET                                          0XFF5E0128
+#undef CRF_APB_PCIE_REF_CTRL_OFFSET 
+#define CRF_APB_PCIE_REF_CTRL_OFFSET                                               0XFD1A00B4
+#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET                                           0XFD1A0070
+#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET                                           0XFD1A0074
+#undef CRF_APB_DP_STC_REF_CTRL_OFFSET 
+#define CRF_APB_DP_STC_REF_CTRL_OFFSET                                             0XFD1A007C
+#undef CRF_APB_ACPU_CTRL_OFFSET 
+#define CRF_APB_ACPU_CTRL_OFFSET                                                   0XFD1A0060
+#undef CRF_APB_DBG_TRACE_CTRL_OFFSET 
+#define CRF_APB_DBG_TRACE_CTRL_OFFSET                                              0XFD1A0064
+#undef CRF_APB_DBG_FPD_CTRL_OFFSET 
+#define CRF_APB_DBG_FPD_CTRL_OFFSET                                                0XFD1A0068
+#undef CRF_APB_DDR_CTRL_OFFSET 
+#define CRF_APB_DDR_CTRL_OFFSET                                                    0XFD1A0080
+#undef CRF_APB_GPU_REF_CTRL_OFFSET 
+#define CRF_APB_GPU_REF_CTRL_OFFSET                                                0XFD1A0084
+#undef CRF_APB_GDMA_REF_CTRL_OFFSET 
+#define CRF_APB_GDMA_REF_CTRL_OFFSET                                               0XFD1A00B8
+#undef CRF_APB_DPDMA_REF_CTRL_OFFSET 
+#define CRF_APB_DPDMA_REF_CTRL_OFFSET                                              0XFD1A00BC
+#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET 
+#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET                                             0XFD1A00C0
+#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 
+#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET                                            0XFD1A00C4
+#undef CRF_APB_GTGREF0_REF_CTRL_OFFSET 
+#define CRF_APB_GTGREF0_REF_CTRL_OFFSET                                            0XFD1A00C8
+#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET 
+#define CRF_APB_DBG_TSTMP_CTRL_OFFSET                                              0XFD1A00F8
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL                                    0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT                                     25
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK                                      0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL                                  0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL                                  0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL                                    0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL                                   0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT                                    25
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK                                     0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL                                 0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT                                  16
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK                                   0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL                                 0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT                                  8
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL                                   0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT                                    0
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK                                     0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL                                        0x01000800
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL                                        0x01000800
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK 
+#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL                                          0x03000600
+#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT                                           24
+#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK                                            0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL                                        0x03000600
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT                                         8
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK                                          0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL                                          0x03000600
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT                                           0
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK                                            0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL                                      0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT                                       24
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT                                       0
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PCAP_CTRL_CLKACT_MASK 
+#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL                                            0x00001500
+#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT                                             24
+#define CRL_APB_PCAP_CTRL_CLKACT_MASK                                              0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL                                          0x00001500
+#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT                                           8
+#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK                                            0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK 
+#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL                                            0x00001500
+#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT                                             0
+#define CRL_APB_PCAP_CTRL_SRCSEL_MASK                                              0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL                                      0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT                                       24
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT                                       0
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL                                         0x01002000
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL                                       0x01002000
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL                                         0x01002000
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL                                        0x00052000
+#define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_NAND_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL                                      0x00052000
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL                                      0x00052000
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL                                        0x00052000
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL                                        0x00002000
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002000
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL                                        0x00002000
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                                       0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                                       0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                                         0x01001800
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                                         0x01001800
+#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
+		is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL                                         0x00000000
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL                                 0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT                                  8
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
+
+/*1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 
+		 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL                                   0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT                                    0
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK                                     0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL                                   0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT                                    24
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK                                     0x01000000U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL                                        0x00001500
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL                                        0x00001500
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL                                      0x00001500
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
+		k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL                                    0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL                                    0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT                                     24
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK                                      0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
+		k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL                                    0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL                                    0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT                                     24
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK                                      0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL                                    0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT                                     16
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK                                      0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL                                    0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT                                     8
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL                                      0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT                                       0
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL                                      0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT                                       24
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK 
+#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL                                          0x03000400
+#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT                                           8
+#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK                                            0x00003F00U
+
+/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK 
+#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL                                            0x03000400
+#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT                                             0
+#define CRF_APB_ACPU_CTRL_SRCSEL_MASK                                              0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL                                       0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT                                        25
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK                                         0x02000000U
+
+/*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
+		 to the entire APU*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL                                       0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT                                        24
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL                                     0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL                                       0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL                                       0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT                                        24
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL                                       0x01002500
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT                                        8
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL                                         0x01002500
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT                                          0
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL                                         0x01002500
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT                                          24
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL                                           0x01000500
+#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT                                            8
+#define CRF_APB_DDR_CTRL_DIVISOR0_MASK                                             0x00003F00U
+
+/*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 
+		s not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DDR_CTRL_SRCSEL_MASK 
+#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL                                             0x01000500
+#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT                                              0
+#define CRF_APB_DDR_CTRL_SRCSEL_MASK                                               0x00000007U
+
+/*6 bit divider*/
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL                                       0x00001500
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL                                         0x00001500
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below*/
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL                                         0x00001500
+#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock*/
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL                                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT                                      25
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK                                       0x02000000U
+
+/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock*/
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL                                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT                                      26
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK                                       0x04000000U
+
+/*6 bit divider*/
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL                                       0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL                                       0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL                                    0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT                                     8
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL                                      0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT                                       0
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL                                      0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT                                       24
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL                                   0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL                                     0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT                                      0
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL                                     0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT                                      24
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL                                   0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL                                     0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT                                      0
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL                                     0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT                                      24
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL                                     0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL                                       0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK                                         0x00000007U
+#undef IOU_SLCR_MIO_PIN_0_OFFSET 
+#define IOU_SLCR_MIO_PIN_0_OFFSET                                                  0XFF180000
+#undef IOU_SLCR_MIO_PIN_1_OFFSET 
+#define IOU_SLCR_MIO_PIN_1_OFFSET                                                  0XFF180004
+#undef IOU_SLCR_MIO_PIN_2_OFFSET 
+#define IOU_SLCR_MIO_PIN_2_OFFSET                                                  0XFF180008
+#undef IOU_SLCR_MIO_PIN_3_OFFSET 
+#define IOU_SLCR_MIO_PIN_3_OFFSET                                                  0XFF18000C
+#undef IOU_SLCR_MIO_PIN_4_OFFSET 
+#define IOU_SLCR_MIO_PIN_4_OFFSET                                                  0XFF180010
+#undef IOU_SLCR_MIO_PIN_5_OFFSET 
+#define IOU_SLCR_MIO_PIN_5_OFFSET                                                  0XFF180014
+#undef IOU_SLCR_MIO_PIN_6_OFFSET 
+#define IOU_SLCR_MIO_PIN_6_OFFSET                                                  0XFF180018
+#undef IOU_SLCR_MIO_PIN_7_OFFSET 
+#define IOU_SLCR_MIO_PIN_7_OFFSET                                                  0XFF18001C
+#undef IOU_SLCR_MIO_PIN_8_OFFSET 
+#define IOU_SLCR_MIO_PIN_8_OFFSET                                                  0XFF180020
+#undef IOU_SLCR_MIO_PIN_9_OFFSET 
+#define IOU_SLCR_MIO_PIN_9_OFFSET                                                  0XFF180024
+#undef IOU_SLCR_MIO_PIN_10_OFFSET 
+#define IOU_SLCR_MIO_PIN_10_OFFSET                                                 0XFF180028
+#undef IOU_SLCR_MIO_PIN_11_OFFSET 
+#define IOU_SLCR_MIO_PIN_11_OFFSET                                                 0XFF18002C
+#undef IOU_SLCR_MIO_PIN_12_OFFSET 
+#define IOU_SLCR_MIO_PIN_12_OFFSET                                                 0XFF180030
+#undef IOU_SLCR_MIO_PIN_13_OFFSET 
+#define IOU_SLCR_MIO_PIN_13_OFFSET                                                 0XFF180034
+#undef IOU_SLCR_MIO_PIN_14_OFFSET 
+#define IOU_SLCR_MIO_PIN_14_OFFSET                                                 0XFF180038
+#undef IOU_SLCR_MIO_PIN_15_OFFSET 
+#define IOU_SLCR_MIO_PIN_15_OFFSET                                                 0XFF18003C
+#undef IOU_SLCR_MIO_PIN_16_OFFSET 
+#define IOU_SLCR_MIO_PIN_16_OFFSET                                                 0XFF180040
+#undef IOU_SLCR_MIO_PIN_17_OFFSET 
+#define IOU_SLCR_MIO_PIN_17_OFFSET                                                 0XFF180044
+#undef IOU_SLCR_MIO_PIN_18_OFFSET 
+#define IOU_SLCR_MIO_PIN_18_OFFSET                                                 0XFF180048
+#undef IOU_SLCR_MIO_PIN_19_OFFSET 
+#define IOU_SLCR_MIO_PIN_19_OFFSET                                                 0XFF18004C
+#undef IOU_SLCR_MIO_PIN_20_OFFSET 
+#define IOU_SLCR_MIO_PIN_20_OFFSET                                                 0XFF180050
+#undef IOU_SLCR_MIO_PIN_21_OFFSET 
+#define IOU_SLCR_MIO_PIN_21_OFFSET                                                 0XFF180054
+#undef IOU_SLCR_MIO_PIN_22_OFFSET 
+#define IOU_SLCR_MIO_PIN_22_OFFSET                                                 0XFF180058
+#undef IOU_SLCR_MIO_PIN_23_OFFSET 
+#define IOU_SLCR_MIO_PIN_23_OFFSET                                                 0XFF18005C
+#undef IOU_SLCR_MIO_PIN_24_OFFSET 
+#define IOU_SLCR_MIO_PIN_24_OFFSET                                                 0XFF180060
+#undef IOU_SLCR_MIO_PIN_25_OFFSET 
+#define IOU_SLCR_MIO_PIN_25_OFFSET                                                 0XFF180064
+#undef IOU_SLCR_MIO_PIN_26_OFFSET 
+#define IOU_SLCR_MIO_PIN_26_OFFSET                                                 0XFF180068
+#undef IOU_SLCR_MIO_PIN_27_OFFSET 
+#define IOU_SLCR_MIO_PIN_27_OFFSET                                                 0XFF18006C
+#undef IOU_SLCR_MIO_PIN_28_OFFSET 
+#define IOU_SLCR_MIO_PIN_28_OFFSET                                                 0XFF180070
+#undef IOU_SLCR_MIO_PIN_29_OFFSET 
+#define IOU_SLCR_MIO_PIN_29_OFFSET                                                 0XFF180074
+#undef IOU_SLCR_MIO_PIN_30_OFFSET 
+#define IOU_SLCR_MIO_PIN_30_OFFSET                                                 0XFF180078
+#undef IOU_SLCR_MIO_PIN_31_OFFSET 
+#define IOU_SLCR_MIO_PIN_31_OFFSET                                                 0XFF18007C
+#undef IOU_SLCR_MIO_PIN_32_OFFSET 
+#define IOU_SLCR_MIO_PIN_32_OFFSET                                                 0XFF180080
+#undef IOU_SLCR_MIO_PIN_33_OFFSET 
+#define IOU_SLCR_MIO_PIN_33_OFFSET                                                 0XFF180084
+#undef IOU_SLCR_MIO_PIN_34_OFFSET 
+#define IOU_SLCR_MIO_PIN_34_OFFSET                                                 0XFF180088
+#undef IOU_SLCR_MIO_PIN_35_OFFSET 
+#define IOU_SLCR_MIO_PIN_35_OFFSET                                                 0XFF18008C
+#undef IOU_SLCR_MIO_PIN_36_OFFSET 
+#define IOU_SLCR_MIO_PIN_36_OFFSET                                                 0XFF180090
+#undef IOU_SLCR_MIO_PIN_37_OFFSET 
+#define IOU_SLCR_MIO_PIN_37_OFFSET                                                 0XFF180094
+#undef IOU_SLCR_MIO_PIN_38_OFFSET 
+#define IOU_SLCR_MIO_PIN_38_OFFSET                                                 0XFF180098
+#undef IOU_SLCR_MIO_PIN_39_OFFSET 
+#define IOU_SLCR_MIO_PIN_39_OFFSET                                                 0XFF18009C
+#undef IOU_SLCR_MIO_PIN_40_OFFSET 
+#define IOU_SLCR_MIO_PIN_40_OFFSET                                                 0XFF1800A0
+#undef IOU_SLCR_MIO_PIN_41_OFFSET 
+#define IOU_SLCR_MIO_PIN_41_OFFSET                                                 0XFF1800A4
+#undef IOU_SLCR_MIO_PIN_42_OFFSET 
+#define IOU_SLCR_MIO_PIN_42_OFFSET                                                 0XFF1800A8
+#undef IOU_SLCR_MIO_PIN_43_OFFSET 
+#define IOU_SLCR_MIO_PIN_43_OFFSET                                                 0XFF1800AC
+#undef IOU_SLCR_MIO_PIN_44_OFFSET 
+#define IOU_SLCR_MIO_PIN_44_OFFSET                                                 0XFF1800B0
+#undef IOU_SLCR_MIO_PIN_45_OFFSET 
+#define IOU_SLCR_MIO_PIN_45_OFFSET                                                 0XFF1800B4
+#undef IOU_SLCR_MIO_PIN_46_OFFSET 
+#define IOU_SLCR_MIO_PIN_46_OFFSET                                                 0XFF1800B8
+#undef IOU_SLCR_MIO_PIN_47_OFFSET 
+#define IOU_SLCR_MIO_PIN_47_OFFSET                                                 0XFF1800BC
+#undef IOU_SLCR_MIO_PIN_48_OFFSET 
+#define IOU_SLCR_MIO_PIN_48_OFFSET                                                 0XFF1800C0
+#undef IOU_SLCR_MIO_PIN_49_OFFSET 
+#define IOU_SLCR_MIO_PIN_49_OFFSET                                                 0XFF1800C4
+#undef IOU_SLCR_MIO_PIN_50_OFFSET 
+#define IOU_SLCR_MIO_PIN_50_OFFSET                                                 0XFF1800C8
+#undef IOU_SLCR_MIO_PIN_51_OFFSET 
+#define IOU_SLCR_MIO_PIN_51_OFFSET                                                 0XFF1800CC
+#undef IOU_SLCR_MIO_PIN_52_OFFSET 
+#define IOU_SLCR_MIO_PIN_52_OFFSET                                                 0XFF1800D0
+#undef IOU_SLCR_MIO_PIN_53_OFFSET 
+#define IOU_SLCR_MIO_PIN_53_OFFSET                                                 0XFF1800D4
+#undef IOU_SLCR_MIO_PIN_54_OFFSET 
+#define IOU_SLCR_MIO_PIN_54_OFFSET                                                 0XFF1800D8
+#undef IOU_SLCR_MIO_PIN_55_OFFSET 
+#define IOU_SLCR_MIO_PIN_55_OFFSET                                                 0XFF1800DC
+#undef IOU_SLCR_MIO_PIN_56_OFFSET 
+#define IOU_SLCR_MIO_PIN_56_OFFSET                                                 0XFF1800E0
+#undef IOU_SLCR_MIO_PIN_57_OFFSET 
+#define IOU_SLCR_MIO_PIN_57_OFFSET                                                 0XFF1800E4
+#undef IOU_SLCR_MIO_PIN_58_OFFSET 
+#define IOU_SLCR_MIO_PIN_58_OFFSET                                                 0XFF1800E8
+#undef IOU_SLCR_MIO_PIN_59_OFFSET 
+#define IOU_SLCR_MIO_PIN_59_OFFSET                                                 0XFF1800EC
+#undef IOU_SLCR_MIO_PIN_60_OFFSET 
+#define IOU_SLCR_MIO_PIN_60_OFFSET                                                 0XFF1800F0
+#undef IOU_SLCR_MIO_PIN_61_OFFSET 
+#define IOU_SLCR_MIO_PIN_61_OFFSET                                                 0XFF1800F4
+#undef IOU_SLCR_MIO_PIN_62_OFFSET 
+#define IOU_SLCR_MIO_PIN_62_OFFSET                                                 0XFF1800F8
+#undef IOU_SLCR_MIO_PIN_63_OFFSET 
+#define IOU_SLCR_MIO_PIN_63_OFFSET                                                 0XFF1800FC
+#undef IOU_SLCR_MIO_PIN_64_OFFSET 
+#define IOU_SLCR_MIO_PIN_64_OFFSET                                                 0XFF180100
+#undef IOU_SLCR_MIO_PIN_65_OFFSET 
+#define IOU_SLCR_MIO_PIN_65_OFFSET                                                 0XFF180104
+#undef IOU_SLCR_MIO_PIN_66_OFFSET 
+#define IOU_SLCR_MIO_PIN_66_OFFSET                                                 0XFF180108
+#undef IOU_SLCR_MIO_PIN_67_OFFSET 
+#define IOU_SLCR_MIO_PIN_67_OFFSET                                                 0XFF18010C
+#undef IOU_SLCR_MIO_PIN_68_OFFSET 
+#define IOU_SLCR_MIO_PIN_68_OFFSET                                                 0XFF180110
+#undef IOU_SLCR_MIO_PIN_69_OFFSET 
+#define IOU_SLCR_MIO_PIN_69_OFFSET                                                 0XFF180114
+#undef IOU_SLCR_MIO_PIN_70_OFFSET 
+#define IOU_SLCR_MIO_PIN_70_OFFSET                                                 0XFF180118
+#undef IOU_SLCR_MIO_PIN_71_OFFSET 
+#define IOU_SLCR_MIO_PIN_71_OFFSET                                                 0XFF18011C
+#undef IOU_SLCR_MIO_PIN_72_OFFSET 
+#define IOU_SLCR_MIO_PIN_72_OFFSET                                                 0XFF180120
+#undef IOU_SLCR_MIO_PIN_73_OFFSET 
+#define IOU_SLCR_MIO_PIN_73_OFFSET                                                 0XFF180124
+#undef IOU_SLCR_MIO_PIN_74_OFFSET 
+#define IOU_SLCR_MIO_PIN_74_OFFSET                                                 0XFF180128
+#undef IOU_SLCR_MIO_PIN_75_OFFSET 
+#define IOU_SLCR_MIO_PIN_75_OFFSET                                                 0XFF18012C
+#undef IOU_SLCR_MIO_PIN_76_OFFSET 
+#define IOU_SLCR_MIO_PIN_76_OFFSET                                                 0XFF180130
+#undef IOU_SLCR_MIO_PIN_77_OFFSET 
+#define IOU_SLCR_MIO_PIN_77_OFFSET                                                 0XFF180134
+#undef IOU_SLCR_MIO_MST_TRI0_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI0_OFFSET                                               0XFF180204
+#undef IOU_SLCR_MIO_MST_TRI1_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI1_OFFSET                                               0XFF180208
+#undef IOU_SLCR_MIO_MST_TRI2_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI2_OFFSET                                               0XFF18020C
+#undef IOU_SLCR_MIO_LOOPBACK_OFFSET 
+#define IOU_SLCR_MIO_LOOPBACK_OFFSET                                               0XFF180200
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
+		us)*/
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)*/
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
+		us)*/
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
+		sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
+		Output, tracedq[4]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 
+		tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 
+		racedq[5]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[0]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
+		, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
+		ce Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[1]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 
+		utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
+		RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[2]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[3]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		*/
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
+		ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
+		dq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
+		out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
+		bus)*/
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
+		n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
+		0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
+		l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
+		c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 
+		= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 
+		UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
+		(Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed*/
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
+		23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
+		*/
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
+		scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
+		 Tamper)*/
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
+		Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
+		test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
+		U Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 
+		lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)*/
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
+		 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
+		 tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
+		_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
+		ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		*/
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
+		_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 
+		race, Output, tracedq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
+		c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
+		[11]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
+		 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
+		rt Databus)*/
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
+		Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 
+		UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
+		k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
+		(Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
+		[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
+		_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
+		Control Signal)*/
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
+		in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
+		]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
+		ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
+		i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
+		i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
+		0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
+		ed*/
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
+		bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
+		d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
+		clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
+		t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
+		serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)*/
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[2]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[0]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[1]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[3]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)*/
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[4]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[5]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[6]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[7]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
+		i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 trace, Output, tracedq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
+		dq[11]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[2]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
+		2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
+		Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[0]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[1]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed*/
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[3]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[4]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
+		t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[5]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[6]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[7]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
+		d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
+		_clk_out- (SDSDIO clock) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
+		 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
+		O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
+		t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK                                            0x000000E0U
+
+/*Master Tri-state Enable for pin 0, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 1, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 2, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 3, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 4, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 5, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 6, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 7, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 8, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 9, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 10, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 11, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 12, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 13, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK                                      0x00002000U
+
+/*Master Tri-state Enable for pin 14, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT                                     14
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK                                      0x00004000U
+
+/*Master Tri-state Enable for pin 15, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT                                     15
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK                                      0x00008000U
+
+/*Master Tri-state Enable for pin 16, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT                                     16
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK                                      0x00010000U
+
+/*Master Tri-state Enable for pin 17, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT                                     17
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK                                      0x00020000U
+
+/*Master Tri-state Enable for pin 18, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT                                     18
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK                                      0x00040000U
+
+/*Master Tri-state Enable for pin 19, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT                                     19
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK                                      0x00080000U
+
+/*Master Tri-state Enable for pin 20, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT                                     20
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK                                      0x00100000U
+
+/*Master Tri-state Enable for pin 21, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT                                     21
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK                                      0x00200000U
+
+/*Master Tri-state Enable for pin 22, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT                                     22
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK                                      0x00400000U
+
+/*Master Tri-state Enable for pin 23, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT                                     23
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK                                      0x00800000U
+
+/*Master Tri-state Enable for pin 24, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT                                     24
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK                                      0x01000000U
+
+/*Master Tri-state Enable for pin 25, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT                                     25
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK                                      0x02000000U
+
+/*Master Tri-state Enable for pin 26, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT                                     26
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK                                      0x04000000U
+
+/*Master Tri-state Enable for pin 27, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT                                     27
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK                                      0x08000000U
+
+/*Master Tri-state Enable for pin 28, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT                                     28
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK                                      0x10000000U
+
+/*Master Tri-state Enable for pin 29, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT                                     29
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK                                      0x20000000U
+
+/*Master Tri-state Enable for pin 30, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT                                     30
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK                                      0x40000000U
+
+/*Master Tri-state Enable for pin 31, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT                                     31
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK                                      0x80000000U
+
+/*Master Tri-state Enable for pin 32, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 33, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 34, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 35, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 36, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 37, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 38, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 39, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 40, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 41, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 42, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 43, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 44, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 45, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK                                      0x00002000U
+
+/*Master Tri-state Enable for pin 46, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT                                     14
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK                                      0x00004000U
+
+/*Master Tri-state Enable for pin 47, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT                                     15
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK                                      0x00008000U
+
+/*Master Tri-state Enable for pin 48, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT                                     16
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK                                      0x00010000U
+
+/*Master Tri-state Enable for pin 49, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT                                     17
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK                                      0x00020000U
+
+/*Master Tri-state Enable for pin 50, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT                                     18
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK                                      0x00040000U
+
+/*Master Tri-state Enable for pin 51, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT                                     19
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK                                      0x00080000U
+
+/*Master Tri-state Enable for pin 52, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT                                     20
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK                                      0x00100000U
+
+/*Master Tri-state Enable for pin 53, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT                                     21
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK                                      0x00200000U
+
+/*Master Tri-state Enable for pin 54, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT                                     22
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK                                      0x00400000U
+
+/*Master Tri-state Enable for pin 55, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT                                     23
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK                                      0x00800000U
+
+/*Master Tri-state Enable for pin 56, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT                                     24
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK                                      0x01000000U
+
+/*Master Tri-state Enable for pin 57, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT                                     25
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK                                      0x02000000U
+
+/*Master Tri-state Enable for pin 58, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT                                     26
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK                                      0x04000000U
+
+/*Master Tri-state Enable for pin 59, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT                                     27
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK                                      0x08000000U
+
+/*Master Tri-state Enable for pin 60, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT                                     28
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK                                      0x10000000U
+
+/*Master Tri-state Enable for pin 61, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT                                     29
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK                                      0x20000000U
+
+/*Master Tri-state Enable for pin 62, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT                                     30
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK                                      0x40000000U
+
+/*Master Tri-state Enable for pin 63, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT                                     31
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK                                      0x80000000U
+
+/*Master Tri-state Enable for pin 64, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 65, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 66, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 67, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 68, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 69, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 70, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 71, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 72, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 73, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 74, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 75, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 76, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 77, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK                                      0x00002000U
+
+/*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
+		ts to I2C 0 inputs.*/
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT                                 3
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK                                  0x00000008U
+
+/*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
+		.*/
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT                                 2
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK                                  0x00000004U
+
+/*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
+		outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL                                  0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT                                   1
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK                                    0x00000002U
+
+/*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
+		ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT                                 0
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK                                  0x00000001U
+#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef IOU_SLCR_CTRL_REG_SD_OFFSET 
+#define IOU_SLCR_CTRL_REG_SD_OFFSET                                                0XFF180310
+#undef IOU_SLCR_SD_CONFIG_REG2_OFFSET 
+#define IOU_SLCR_SD_CONFIG_REG2_OFFSET                                             0XFF180320
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF000034
+#undef UART0_BAUD_RATE_GEN_REG0_OFFSET 
+#define UART0_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF000018
+#undef UART0_CONTROL_REG0_OFFSET 
+#define UART0_CONTROL_REG0_OFFSET                                                  0XFF000000
+#undef UART0_MODE_REG0_OFFSET 
+#define UART0_MODE_REG0_OFFSET                                                     0XFF000004
+#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF010034
+#undef UART1_BAUD_RATE_GEN_REG0_OFFSET 
+#define UART1_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF010018
+#undef UART1_CONTROL_REG0_OFFSET 
+#define UART1_CONTROL_REG0_OFFSET                                                  0XFF010000
+#undef UART1_MODE_REG0_OFFSET 
+#define UART1_MODE_REG0_OFFSET                                                     0XFF010004
+#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 
+#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
+#undef CSU_TAMPER_STATUS_OFFSET 
+#define CSU_TAMPER_STATUS_OFFSET                                                   0XFFCA5000
+
+/*GEM 0 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT                                      0
+#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK                                       0x00000001U
+
+/*GEM 1 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT                                      1
+#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK                                       0x00000002U
+
+/*GEM 2 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT                                      2
+#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK                                       0x00000004U
+
+/*GEM 3 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT                                      0
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK                                       0x00000001U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_NAND_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_NAND_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT                                      16
+#define CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK                                       0x00010000U
+
+/*USB 0 reset for control registers*/
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
+
+/*USB 0 sleep circuit reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
+
+/*USB 0 reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SDIO0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT                                     5
+#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK                                      0x00000020U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT                                     6
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK                                      0x00000040U
+
+/*SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled*/
+#undef IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_DEFVAL 
+#undef IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_SHIFT 
+#undef IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_MASK 
+#define IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_SHIFT                                    0
+#define IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_MASK                                     0x00000001U
+
+/*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT                                    15
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK                                     0x00008000U
+
+/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_DEFVAL                                0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT                                 12
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_MASK                                  0x00003000U
+
+/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL                                0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT                                 28
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK                                  0x30000000U
+
+/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_SHIFT                                     9
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_MASK                                      0x00000200U
+
+/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_SHIFT                                     8
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_MASK                                      0x00000100U
+
+/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_SHIFT                                     7
+#define IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_MASK                                      0x00000080U
+
+/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT                                     25
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK                                      0x02000000U
+
+/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT                                     24
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK                                      0x01000000U
+
+/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT                                     23
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK                                      0x00800000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT                                      7
+#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK                                       0x00000080U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT                                      8
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK                                       0x00000100U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT                                      9
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK                                       0x00000200U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT                                      10
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK                                       0x00000400U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK                                       0x00000008U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT                                      4
+#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK                                       0x00000010U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT                                      11
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK                                       0x00000800U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT                                      12
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK                                       0x00001000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT                                      13
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK                                       0x00002000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT                                      14
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK                                       0x00004000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT                                     1
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK                                      0x00000002U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT                                     2
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK                                      0x00000004U
+
+/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
+
+/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
+#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 
+#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 
+#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK 
+#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
+#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
+#define UART0_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
+
+/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
+#undef UART0_CONTROL_REG0_STPBRK_DEFVAL 
+#undef UART0_CONTROL_REG0_STPBRK_SHIFT 
+#undef UART0_CONTROL_REG0_STPBRK_MASK 
+#define UART0_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
+#define UART0_CONTROL_REG0_STPBRK_SHIFT                                            8
+#define UART0_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
+
+/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
+#undef UART0_CONTROL_REG0_STTBRK_DEFVAL 
+#undef UART0_CONTROL_REG0_STTBRK_SHIFT 
+#undef UART0_CONTROL_REG0_STTBRK_MASK 
+#define UART0_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
+#define UART0_CONTROL_REG0_STTBRK_SHIFT                                            7
+#define UART0_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
+
+/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.*/
+#undef UART0_CONTROL_REG0_RSTTO_DEFVAL 
+#undef UART0_CONTROL_REG0_RSTTO_SHIFT 
+#undef UART0_CONTROL_REG0_RSTTO_MASK 
+#define UART0_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RSTTO_SHIFT                                             6
+#define UART0_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
+
+/*Transmit disable: 0: enable transmitter 1: disable transmitter*/
+#undef UART0_CONTROL_REG0_TXDIS_DEFVAL 
+#undef UART0_CONTROL_REG0_TXDIS_SHIFT 
+#undef UART0_CONTROL_REG0_TXDIS_MASK 
+#define UART0_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_TXDIS_SHIFT                                             5
+#define UART0_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
+
+/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
+#undef UART0_CONTROL_REG0_TXEN_DEFVAL 
+#undef UART0_CONTROL_REG0_TXEN_SHIFT 
+#undef UART0_CONTROL_REG0_TXEN_MASK 
+#define UART0_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
+#define UART0_CONTROL_REG0_TXEN_SHIFT                                              4
+#define UART0_CONTROL_REG0_TXEN_MASK                                               0x00000010U
+
+/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
+#undef UART0_CONTROL_REG0_RXDIS_DEFVAL 
+#undef UART0_CONTROL_REG0_RXDIS_SHIFT 
+#undef UART0_CONTROL_REG0_RXDIS_MASK 
+#define UART0_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RXDIS_SHIFT                                             3
+#define UART0_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
+
+/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
+#undef UART0_CONTROL_REG0_RXEN_DEFVAL 
+#undef UART0_CONTROL_REG0_RXEN_SHIFT 
+#undef UART0_CONTROL_REG0_RXEN_MASK 
+#define UART0_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
+#define UART0_CONTROL_REG0_RXEN_SHIFT                                              2
+#define UART0_CONTROL_REG0_RXEN_MASK                                               0x00000004U
+
+/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.*/
+#undef UART0_CONTROL_REG0_TXRES_DEFVAL 
+#undef UART0_CONTROL_REG0_TXRES_SHIFT 
+#undef UART0_CONTROL_REG0_TXRES_MASK 
+#define UART0_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_TXRES_SHIFT                                             1
+#define UART0_CONTROL_REG0_TXRES_MASK                                              0x00000002U
+
+/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.*/
+#undef UART0_CONTROL_REG0_RXRES_DEFVAL 
+#undef UART0_CONTROL_REG0_RXRES_SHIFT 
+#undef UART0_CONTROL_REG0_RXRES_MASK 
+#define UART0_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RXRES_SHIFT                                             0
+#define UART0_CONTROL_REG0_RXRES_MASK                                              0x00000001U
+
+/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
+#undef UART0_MODE_REG0_CHMODE_DEFVAL 
+#undef UART0_MODE_REG0_CHMODE_SHIFT 
+#undef UART0_MODE_REG0_CHMODE_MASK 
+#define UART0_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
+#define UART0_MODE_REG0_CHMODE_SHIFT                                               8
+#define UART0_MODE_REG0_CHMODE_MASK                                                0x00000300U
+
+/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved*/
+#undef UART0_MODE_REG0_NBSTOP_DEFVAL 
+#undef UART0_MODE_REG0_NBSTOP_SHIFT 
+#undef UART0_MODE_REG0_NBSTOP_MASK 
+#define UART0_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
+#define UART0_MODE_REG0_NBSTOP_SHIFT                                               6
+#define UART0_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
+
+/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
+#undef UART0_MODE_REG0_PAR_DEFVAL 
+#undef UART0_MODE_REG0_PAR_SHIFT 
+#undef UART0_MODE_REG0_PAR_MASK 
+#define UART0_MODE_REG0_PAR_DEFVAL                                                 0x00000000
+#define UART0_MODE_REG0_PAR_SHIFT                                                  3
+#define UART0_MODE_REG0_PAR_MASK                                                   0x00000038U
+
+/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
+#undef UART0_MODE_REG0_CHRL_DEFVAL 
+#undef UART0_MODE_REG0_CHRL_SHIFT 
+#undef UART0_MODE_REG0_CHRL_MASK 
+#define UART0_MODE_REG0_CHRL_DEFVAL                                                0x00000000
+#define UART0_MODE_REG0_CHRL_SHIFT                                                 1
+#define UART0_MODE_REG0_CHRL_MASK                                                  0x00000006U
+
+/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
+#undef UART0_MODE_REG0_CLKS_DEFVAL 
+#undef UART0_MODE_REG0_CLKS_SHIFT 
+#undef UART0_MODE_REG0_CLKS_MASK 
+#define UART0_MODE_REG0_CLKS_DEFVAL                                                0x00000000
+#define UART0_MODE_REG0_CLKS_SHIFT                                                 0
+#define UART0_MODE_REG0_CLKS_MASK                                                  0x00000001U
+
+/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
+
+/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
+#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 
+#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 
+#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK 
+#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
+#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
+#define UART1_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
+
+/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
+#undef UART1_CONTROL_REG0_STPBRK_DEFVAL 
+#undef UART1_CONTROL_REG0_STPBRK_SHIFT 
+#undef UART1_CONTROL_REG0_STPBRK_MASK 
+#define UART1_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
+#define UART1_CONTROL_REG0_STPBRK_SHIFT                                            8
+#define UART1_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
+
+/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
+#undef UART1_CONTROL_REG0_STTBRK_DEFVAL 
+#undef UART1_CONTROL_REG0_STTBRK_SHIFT 
+#undef UART1_CONTROL_REG0_STTBRK_MASK 
+#define UART1_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
+#define UART1_CONTROL_REG0_STTBRK_SHIFT                                            7
+#define UART1_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
+
+/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.*/
+#undef UART1_CONTROL_REG0_RSTTO_DEFVAL 
+#undef UART1_CONTROL_REG0_RSTTO_SHIFT 
+#undef UART1_CONTROL_REG0_RSTTO_MASK 
+#define UART1_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RSTTO_SHIFT                                             6
+#define UART1_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
+
+/*Transmit disable: 0: enable transmitter 1: disable transmitter*/
+#undef UART1_CONTROL_REG0_TXDIS_DEFVAL 
+#undef UART1_CONTROL_REG0_TXDIS_SHIFT 
+#undef UART1_CONTROL_REG0_TXDIS_MASK 
+#define UART1_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_TXDIS_SHIFT                                             5
+#define UART1_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
+
+/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
+#undef UART1_CONTROL_REG0_TXEN_DEFVAL 
+#undef UART1_CONTROL_REG0_TXEN_SHIFT 
+#undef UART1_CONTROL_REG0_TXEN_MASK 
+#define UART1_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
+#define UART1_CONTROL_REG0_TXEN_SHIFT                                              4
+#define UART1_CONTROL_REG0_TXEN_MASK                                               0x00000010U
+
+/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
+#undef UART1_CONTROL_REG0_RXDIS_DEFVAL 
+#undef UART1_CONTROL_REG0_RXDIS_SHIFT 
+#undef UART1_CONTROL_REG0_RXDIS_MASK 
+#define UART1_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RXDIS_SHIFT                                             3
+#define UART1_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
+
+/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
+#undef UART1_CONTROL_REG0_RXEN_DEFVAL 
+#undef UART1_CONTROL_REG0_RXEN_SHIFT 
+#undef UART1_CONTROL_REG0_RXEN_MASK 
+#define UART1_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
+#define UART1_CONTROL_REG0_RXEN_SHIFT                                              2
+#define UART1_CONTROL_REG0_RXEN_MASK                                               0x00000004U
+
+/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.*/
+#undef UART1_CONTROL_REG0_TXRES_DEFVAL 
+#undef UART1_CONTROL_REG0_TXRES_SHIFT 
+#undef UART1_CONTROL_REG0_TXRES_MASK 
+#define UART1_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_TXRES_SHIFT                                             1
+#define UART1_CONTROL_REG0_TXRES_MASK                                              0x00000002U
+
+/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.*/
+#undef UART1_CONTROL_REG0_RXRES_DEFVAL 
+#undef UART1_CONTROL_REG0_RXRES_SHIFT 
+#undef UART1_CONTROL_REG0_RXRES_MASK 
+#define UART1_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RXRES_SHIFT                                             0
+#define UART1_CONTROL_REG0_RXRES_MASK                                              0x00000001U
+
+/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
+#undef UART1_MODE_REG0_CHMODE_DEFVAL 
+#undef UART1_MODE_REG0_CHMODE_SHIFT 
+#undef UART1_MODE_REG0_CHMODE_MASK 
+#define UART1_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
+#define UART1_MODE_REG0_CHMODE_SHIFT                                               8
+#define UART1_MODE_REG0_CHMODE_MASK                                                0x00000300U
+
+/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved*/
+#undef UART1_MODE_REG0_NBSTOP_DEFVAL 
+#undef UART1_MODE_REG0_NBSTOP_SHIFT 
+#undef UART1_MODE_REG0_NBSTOP_MASK 
+#define UART1_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
+#define UART1_MODE_REG0_NBSTOP_SHIFT                                               6
+#define UART1_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
+
+/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
+#undef UART1_MODE_REG0_PAR_DEFVAL 
+#undef UART1_MODE_REG0_PAR_SHIFT 
+#undef UART1_MODE_REG0_PAR_MASK 
+#define UART1_MODE_REG0_PAR_DEFVAL                                                 0x00000000
+#define UART1_MODE_REG0_PAR_SHIFT                                                  3
+#define UART1_MODE_REG0_PAR_MASK                                                   0x00000038U
+
+/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
+#undef UART1_MODE_REG0_CHRL_DEFVAL 
+#undef UART1_MODE_REG0_CHRL_SHIFT 
+#undef UART1_MODE_REG0_CHRL_MASK 
+#define UART1_MODE_REG0_CHRL_DEFVAL                                                0x00000000
+#define UART1_MODE_REG0_CHRL_SHIFT                                                 1
+#define UART1_MODE_REG0_CHRL_MASK                                                  0x00000006U
+
+/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
+#undef UART1_MODE_REG0_CLKS_DEFVAL 
+#undef UART1_MODE_REG0_CLKS_SHIFT 
+#undef UART1_MODE_REG0_CLKS_MASK 
+#define UART1_MODE_REG0_CLKS_DEFVAL                                                0x00000000
+#define UART1_MODE_REG0_CLKS_SHIFT                                                 0
+#define UART1_MODE_REG0_CLKS_MASK                                                  0x00000001U
+
+/*TrustZone Classification for ADMA*/
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL                                        
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                                         0
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                                          0x000000FFU
+
+/*CSU regsiter*/
+#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_0_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT                                           0
+#define CSU_TAMPER_STATUS_TAMPER_0_MASK                                            0x00000001U
+
+/*External MIO*/
+#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_1_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT                                           1
+#define CSU_TAMPER_STATUS_TAMPER_1_MASK                                            0x00000002U
+
+/*JTAG toggle detect*/
+#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_2_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT                                           2
+#define CSU_TAMPER_STATUS_TAMPER_2_MASK                                            0x00000004U
+
+/*PL SEU error*/
+#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_3_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT                                           3
+#define CSU_TAMPER_STATUS_TAMPER_3_MASK                                            0x00000008U
+
+/*AMS over temperature alarm for LPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_4_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT                                           4
+#define CSU_TAMPER_STATUS_TAMPER_4_MASK                                            0x00000010U
+
+/*AMS over temperature alarm for APU*/
+#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_5_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT                                           5
+#define CSU_TAMPER_STATUS_TAMPER_5_MASK                                            0x00000020U
+
+/*AMS voltage alarm for VCCPINT_FPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_6_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT                                           6
+#define CSU_TAMPER_STATUS_TAMPER_6_MASK                                            0x00000040U
+
+/*AMS voltage alarm for VCCPINT_LPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_7_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT                                           7
+#define CSU_TAMPER_STATUS_TAMPER_7_MASK                                            0x00000080U
+
+/*AMS voltage alarm for VCCPAUX*/
+#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_8_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT                                           8
+#define CSU_TAMPER_STATUS_TAMPER_8_MASK                                            0x00000100U
+
+/*AMS voltage alarm for DDRPHY*/
+#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_9_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT                                           9
+#define CSU_TAMPER_STATUS_TAMPER_9_MASK                                            0x00000200U
+
+/*AMS voltage alarm for PSIO bank 0/1/2*/
+#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_10_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT                                          10
+#define CSU_TAMPER_STATUS_TAMPER_10_MASK                                           0x00000400U
+
+/*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/
+#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_11_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT                                          11
+#define CSU_TAMPER_STATUS_TAMPER_11_MASK                                           0x00000800U
+
+/*AMS voltaage alarm for GT*/
+#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_12_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT                                          12
+#define CSU_TAMPER_STATUS_TAMPER_12_MASK                                           0x00001000U
+#undef LPD_XPPU_CFG_MASTER_ID00_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID00_OFFSET                                            0XFF980100
+#undef LPD_XPPU_CFG_MASTER_ID01_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID01_OFFSET                                            0XFF980104
+#undef LPD_XPPU_CFG_MASTER_ID02_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID02_OFFSET                                            0XFF980108
+#undef LPD_XPPU_CFG_MASTER_ID03_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID03_OFFSET                                            0XFF98010C
+#undef LPD_XPPU_CFG_MASTER_ID04_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID04_OFFSET                                            0XFF980110
+#undef LPD_XPPU_CFG_MASTER_ID05_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID05_OFFSET                                            0XFF980114
+#undef LPD_XPPU_CFG_MASTER_ID06_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID06_OFFSET                                            0XFF980118
+#undef LPD_XPPU_CFG_MASTER_ID07_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID07_OFFSET                                            0XFF98011C
+#undef LPD_XPPU_CFG_MASTER_ID08_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID08_OFFSET                                            0XFF980120
+#undef LPD_XPPU_CFG_MASTER_ID09_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID09_OFFSET                                            0XFF980124
+#undef LPD_XPPU_CFG_MASTER_ID10_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID10_OFFSET                                            0XFF980128
+#undef LPD_XPPU_CFG_MASTER_ID11_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID11_OFFSET                                            0XFF98012C
+#undef LPD_XPPU_CFG_MASTER_ID12_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID12_OFFSET                                            0XFF980130
+#undef LPD_XPPU_CFG_MASTER_ID13_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID13_OFFSET                                            0XFF980134
+#undef LPD_XPPU_CFG_MASTER_ID14_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID14_OFFSET                                            0XFF980138
+#undef LPD_XPPU_CFG_MASTER_ID15_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID15_OFFSET                                            0XFF98013C
+#undef LPD_XPPU_CFG_MASTER_ID16_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID16_OFFSET                                            0XFF980140
+#undef LPD_XPPU_CFG_MASTER_ID17_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID17_OFFSET                                            0XFF980144
+#undef LPD_XPPU_CFG_MASTER_ID18_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID18_OFFSET                                            0XFF980148
+#undef LPD_XPPU_CFG_MASTER_ID19_OFFSET 
+#define LPD_XPPU_CFG_MASTER_ID19_OFFSET                                            0XFF98014C
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID00_MIDP_DEFVAL                                       0x83FF0040
+#define LPD_XPPU_CFG_MASTER_ID00_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID00_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID00_MIDR_DEFVAL                                       0x83FF0040
+#define LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID00_MIDM_DEFVAL                                       0x83FF0040
+#define LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for PMU*/
+#undef LPD_XPPU_CFG_MASTER_ID00_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID00_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID00_MID_DEFVAL                                        0x83FF0040
+#define LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID00_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID01_MIDP_DEFVAL                                       0x03F00000
+#define LPD_XPPU_CFG_MASTER_ID01_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID01_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID01_MIDR_DEFVAL                                       0x03F00000
+#define LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID01_MIDM_DEFVAL                                       0x03F00000
+#define LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for RPU0*/
+#undef LPD_XPPU_CFG_MASTER_ID01_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID01_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID01_MID_DEFVAL                                        0x03F00000
+#define LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID01_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID02_MIDP_DEFVAL                                       0x83F00010
+#define LPD_XPPU_CFG_MASTER_ID02_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID02_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID02_MIDR_DEFVAL                                       0x83F00010
+#define LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID02_MIDM_DEFVAL                                       0x83F00010
+#define LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for RPU1*/
+#undef LPD_XPPU_CFG_MASTER_ID02_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID02_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID02_MID_DEFVAL                                        0x83F00010
+#define LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID02_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID03_MIDP_DEFVAL                                       0x83C00080
+#define LPD_XPPU_CFG_MASTER_ID03_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID03_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID03_MIDR_DEFVAL                                       0x83C00080
+#define LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID03_MIDM_DEFVAL                                       0x83C00080
+#define LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for APU*/
+#undef LPD_XPPU_CFG_MASTER_ID03_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID03_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID03_MID_DEFVAL                                        0x83C00080
+#define LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID03_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID04_MIDP_DEFVAL                                       0x83C30080
+#define LPD_XPPU_CFG_MASTER_ID04_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID04_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID04_MIDR_DEFVAL                                       0x83C30080
+#define LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID04_MIDM_DEFVAL                                       0x83C30080
+#define LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for A53 Core 0*/
+#undef LPD_XPPU_CFG_MASTER_ID04_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID04_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID04_MID_DEFVAL                                        0x83C30080
+#define LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID04_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID05_MIDP_DEFVAL                                       0x03C30081
+#define LPD_XPPU_CFG_MASTER_ID05_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID05_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID05_MIDR_DEFVAL                                       0x03C30081
+#define LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID05_MIDM_DEFVAL                                       0x03C30081
+#define LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for A53 Core 1*/
+#undef LPD_XPPU_CFG_MASTER_ID05_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID05_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID05_MID_DEFVAL                                        0x03C30081
+#define LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID05_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID06_MIDP_DEFVAL                                       0x03C30082
+#define LPD_XPPU_CFG_MASTER_ID06_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID06_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID06_MIDR_DEFVAL                                       0x03C30082
+#define LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID06_MIDM_DEFVAL                                       0x03C30082
+#define LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for A53 Core 2*/
+#undef LPD_XPPU_CFG_MASTER_ID06_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID06_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID06_MID_DEFVAL                                        0x03C30082
+#define LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID06_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID07_MIDP_DEFVAL                                       0x83C30083
+#define LPD_XPPU_CFG_MASTER_ID07_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID07_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID07_MIDR_DEFVAL                                       0x83C30083
+#define LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID07_MIDM_DEFVAL                                       0x83C30083
+#define LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK                                         0x03FF0000U
+
+/*Predefined Master ID for A53 Core 3*/
+#undef LPD_XPPU_CFG_MASTER_ID07_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID07_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID07_MID_DEFVAL                                        0x83C30083
+#define LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID07_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID08_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID08_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID08_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID08_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID08_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID08_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID08_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID08_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID08_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID08_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID08_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID08_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID08_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID08_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID08_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID08_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID09_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID09_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID09_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID09_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID09_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID09_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID09_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID09_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID09_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID09_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID09_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID09_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID09_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID09_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID09_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID09_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID10_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID10_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID10_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID10_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID10_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID10_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID10_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID10_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID10_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID10_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID10_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID10_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID10_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID10_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID10_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID10_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID11_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID11_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID11_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID11_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID11_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID11_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID11_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID11_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID11_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID11_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID11_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID11_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID11_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID11_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID11_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID11_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID12_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID12_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID12_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID12_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID12_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID12_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID12_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID12_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID12_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID12_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID12_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID12_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID12_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID12_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID12_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID12_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID13_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID13_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID13_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID13_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID13_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID13_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID13_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID13_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID13_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID13_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID13_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID13_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID13_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID13_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID13_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID13_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID14_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID14_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID14_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID14_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID14_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID14_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID14_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID14_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID14_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID14_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID14_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID14_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID14_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID14_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID14_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID14_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID15_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID15_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID15_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID15_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID15_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID15_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID15_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID15_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID15_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID15_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID15_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID15_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID15_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID15_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID15_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID15_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID16_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID16_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID16_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID16_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID16_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID16_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID16_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID16_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID16_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID16_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID16_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID16_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID16_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID16_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID16_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID16_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID17_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID17_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID17_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID17_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID17_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID17_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID17_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID17_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID17_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID17_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID17_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID17_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID17_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID17_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID17_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID17_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID18_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID18_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID18_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID18_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID18_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID18_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID18_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID18_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID18_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID18_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID18_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID18_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID18_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID18_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID18_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID18_MID_MASK                                          0x000003FFU
+
+/*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDP_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDP_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDP_MASK 
+#define LPD_XPPU_CFG_MASTER_ID19_MIDP_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID19_MIDP_SHIFT                                        31
+#define LPD_XPPU_CFG_MASTER_ID19_MIDP_MASK                                         0x80000000U
+
+/*If set, only read transactions are allowed for the masters matching this register*/
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDR_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK 
+#define LPD_XPPU_CFG_MASTER_ID19_MIDR_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT                                        30
+#define LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK                                         0x40000000U
+
+/*Mask to be applied before comparing*/
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDM_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK 
+#define LPD_XPPU_CFG_MASTER_ID19_MIDM_DEFVAL                                       0x00000000
+#define LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT                                        16
+#define LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK                                         0x03FF0000U
+
+/*Programmable Master ID*/
+#undef LPD_XPPU_CFG_MASTER_ID19_MID_DEFVAL 
+#undef LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT 
+#undef LPD_XPPU_CFG_MASTER_ID19_MID_MASK 
+#define LPD_XPPU_CFG_MASTER_ID19_MID_DEFVAL                                        0x00000000
+#define LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT                                         0
+#define LPD_XPPU_CFG_MASTER_ID19_MID_MASK                                          0x000003FFU
+#ifdef __cplusplus
+extern "C" {
+#endif
+ int psu_int (); 
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_pmucfg.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_pmucfg.c
new file mode 100644
index 000000000..faf3252ed
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_pmucfg.c
@@ -0,0 +1,158 @@
+/******************************************************************************
+ *
+ * (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+ *
+ * This file contains confidential and proprietary information  of Xilinx, Inc.
+ * and is protected under U.S. and  international copyright and other
+ * intellectual property  laws.
+ *
+ * DISCLAIMER
+ * This disclaimer is not a license and does not grant any  rights to the
+ * materials distributed herewith. Except as  otherwise provided in a valid
+ * license issued to you by  Xilinx, and to the maximum extent permitted by
+ * applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL
+ * FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS,
+ * IMPLIED, OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NON-  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+ * and
+ * (2) Xilinx shall not be liable (whether in contract or tort,  including
+ * negligence, or under any other theory of liability) for any loss or damage
+ * of any kind or nature  related to, arising under or in connection with these
+ * materials, including for any direct, or any indirect,  special, incidental,
+ * or consequential loss or damage  (including loss of data, profits,
+ * goodwill, or any type of  loss or damage suffered as a result of any
+ * action brought  by a third party) even if such damage or loss was
+ * reasonably foreseeable or Xilinx had been advised of the  possibility
+ * of the same.
+ *
+ * CRITICAL APPLICATIONS
+ * Xilinx products are not designed or intended to be fail-  safe, or for use
+ * in any application requiring fail-safe  performance, such as life-support
+ * or safety devices or  systems, Class III medical devices, nuclear
+ * facilities,  applications related to the deployment of airbags, or any
+ * other applications that could lead to death, personal  injury, or severe
+ * property or environmental damage  (individually and collectively,
+ * "Critical  Applications"). Customer assumes the sole risk and  liability
+ * of any use of Xilinx products in Critical  Applications, subject only to
+ * applicable laws and  regulations governing limitations on product liability.
+ *
+ * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS  PART
+ * OF THIS FILE AT ALL TIMES.
+ *
+ ******************************************************************************/
+/*
+  PMU - PCW handoff file
+  Auto generated file from PCW-Vivado tools to be consumed in PMU firmware  
+*/
+
+#define XPFW_CFG_MASTER_PMU                   0 
+#define XPFW_CFG_MASTER_CSU                   1
+#define XPFW_CFG_MASTER_APU                   2
+#define XPFW_CFG_MASTER_RPU_0                 3
+#define XPFW_CFG_MASTER_RPU_1                 4
+#define XPFW_CFG_MASTER_USB0                  5
+#define XPFW_CFG_MASTER_USB1                  6
+#define XPFW_CFG_MASTER_ENET0                 7
+#define XPFW_CFG_MASTER_ENET1                 8
+#define XPFW_CFG_MASTER_ENET2                 9
+#define XPFW_CFG_MASTER_ENET3                 10
+#define XPFW_CFG_MASTER_DAP                   11
+#define XPFW_CFG_MASTER_ADMA                  12
+#define XPFW_CFG_MASTER_SD0                   13
+#define XPFW_CFG_MASTER_SD1                   14
+#define XPFW_CFG_MASTER_NAND                  15
+#define XPFW_CFG_MASTER_QSPI                  16
+#define XPFW_CFG_MASTER_SATA                  17
+#define XPFW_CFG_MASTER_GPU                   18
+#define XPFW_CFG_MASTER_CORESIGHT             19
+#define XPFW_CFG_MASTER_PCIE                  20 
+#define XPFW_CFG_MASTER_DP                    21 
+#define XPFW_CFG_MASTER_GDMA                  22 
+#define XPFW_CFG_MASTER_AF0                   23 
+#define XPFW_CFG_MASTER_AF1                   24 
+#define XPFW_CFG_MASTER_AF2                   25 
+#define XPFW_CFG_MASTER_AF3                   26 
+#define XPFW_CFG_MASTER_AF4                   27 
+#define XPFW_CFG_MASTER_AF5                   28 
+#define XPFW_CFG_MASTER_AFILPD                29
+#define XPFW_CFG_MASTER_MAX                   30 
+
+#define XPFW_CFG_SLAVE_UART0                  0 
+#define XPFW_CFG_SLAVE_UART1                  1 
+#define XPFW_CFG_SLAVE_I2C0                   2 
+#define XPFW_CFG_SLAVE_I2C1                   3 
+#define XPFW_CFG_SLAVE_SPI0                   4 
+#define XPFW_CFG_SLAVE_SPI1                   5 
+#define XPFW_CFG_SLAVE_CAN0                   6 
+#define XPFW_CFG_SLAVE_CAN1                   7 
+#define XPFW_CFG_SLAVE_GPIO0                  8 
+#define XPFW_CFG_SLAVE_ENET0                  9 
+#define XPFW_CFG_SLAVE_ENET1                  10 
+#define XPFW_CFG_SLAVE_ENET2                  11 
+#define XPFW_CFG_SLAVE_ENET3                  12 
+#define XPFW_CFG_SLAVE_NAND0                  13 
+#define XPFW_CFG_SLAVE_TTC0                   14 
+#define XPFW_CFG_SLAVE_TTC1                   15 
+#define XPFW_CFG_SLAVE_TTC2                   16 
+#define XPFW_CFG_SLAVE_TTC3                   17 
+#define XPFW_CFG_SLAVE_WDT0                   18 
+#define XPFW_CFG_SLAVE_SD0                    19 
+#define XPFW_CFG_SLAVE_SD1                    10 
+#define XPFW_CFG_SLAVE_USB0                   11 
+#define XPFW_CFG_SLAVE_USB1                   12 
+#define XPFW_CFG_SLAVE_IOUSLCR0               13 
+#define XPFW_CFG_SLAVE_CSU0                   14 
+#define XPFW_CFG_SLAVE_LPD_SLCR               15 
+#define XPFW_CFG_SLAVE_LPD_GPV                16 
+#define XPFW_CFG_SLAVE_USB3_0                 17 
+#define XPFW_CFG_SLAVE_USB3_1                 18 
+#define XPFW_CFG_SLAVE_QSPI0                  19 
+#define XPFW_CFG_SLAVE_DDR                    20 
+#define XPFW_CFG_SLAVE_OCM                    21 
+#define XPFW_CFG_SLAVE_PMU_GLREG              22 
+#define XPFW_CFG_SLAVE_MAX                    23 
+ 
+ 
+/* MASTER LIST
+ Shared resources like DDR will be powered off by the PMUFW, if no active user for such a resource is present. In order to be able to determine whether no user is present, 
+ PMUFW needs to be aware of all possible users. These include:
+ 1.  APU  / Independent A53s
+ 2.  RPU lockstep/independent
+ 3.  PL Soft-Cores
+ So a list of all active Masters in the System should be exported to PMU FW */
+ unsigned int XPFW_ConfigActMasters[XPFW_CFG_MASTER_MAX] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; 
+
+/* SLAVE LIST
+ It is expected that unused resources are statically turned off by the FSBL during boot. Everything else that is used during run-time needs to be known to the
+ PMUFW in order to execute PM-related functionality on it. So a list of all active slaves on the system should be exported to the PMU FW */
+ unsigned int XPFW_ConfigActSlaves[XPFW_CFG_SLAVE_MAX] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; 
+
+/* Ownership Information
+ PMU_Master_Slave_Isolation[C_MASTER_PSS_CORTEX_APU][PSS_DDR_0] = 1 */
+unsigned int XPFW_ConfigTable[XPFW_CFG_MASTER_MAX][XPFW_CFG_SLAVE_MAX] = {
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,   // E.g APU   - > DDR, SD0, ENET0 
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,   // E.g RPU_0 - > DDR, SD0, ENET0 
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,   // E.g RPU_1 - > DDR, ENET0 
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                         
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                        
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                       
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                      
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                     
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,                    
+                                                                             1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1                    
+                                                                           };
+
+/* Safety Monitor test case to be done */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/system.hdf b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/system.hdf
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diff --git a/FreeRTOS/Demo/Common/Minimal/QueueSet.c b/FreeRTOS/Demo/Common/Minimal/QueueSet.c
index 4c17fa5ca..1f74bdcc4 100644
--- a/FreeRTOS/Demo/Common/Minimal/QueueSet.c
+++ b/FreeRTOS/Demo/Common/Minimal/QueueSet.c
@@ -187,8 +187,8 @@ static void prvChangeRelativePriorities( void );
  * Local pseudo random number seed and return functions.  Used to avoid calls
  * to the standard library.
  */
-static uint32_t prvRand( void );
-static void prvSRand( uint32_t ulSeed );
+static size_t prvRand( void );
+static void prvSRand( size_t uxSeed );
 
 /*-----------------------------------------------------------*/
 
@@ -223,7 +223,7 @@ expected. */
 static volatile uint32_t ulISRTxValue = queuesetINITIAL_ISR_TX_VALUE;
 
 /* Used by the pseudo random number generator. */
-static uint32_t ulNextRand = 0;
+static size_t uxNextRand = 0;
 
 /* The task handles are stored so their priorities can be changed. */
 TaskHandle_t xQueueSetSendingTask, xQueueSetReceivingTask;
@@ -295,24 +295,25 @@ BaseType_t xReturn = pdPASS, x;
 
 static void prvQueueSetSendingTask( void *pvParameters )
 {
-uint32_t ulTaskTxValue = 0, ulQueueToWriteTo;
+uint32_t ulTaskTxValue = 0;
+size_t uxQueueToWriteTo;
 QueueHandle_t xQueueInUse;
 
 	/* Remove compiler warning about the unused parameter. */
 	( void ) pvParameters;
 
 	/* Seed mini pseudo random number generator. */
-	prvSRand( ( uint32_t ) &ulTaskTxValue );
+	prvSRand( ( size_t ) &ulTaskTxValue );
 
 	for( ;; )
 	{
 		/* Generate the index for the queue to which a value is to be sent. */
-		ulQueueToWriteTo = prvRand() % queuesetNUM_QUEUES_IN_SET;
-		xQueueInUse = xQueues[ ulQueueToWriteTo ];
+		uxQueueToWriteTo = prvRand() % queuesetNUM_QUEUES_IN_SET;
+		xQueueInUse = xQueues[ uxQueueToWriteTo ];
 
 		/* Note which index is being written to to ensure all the queues are
 		used. */
-		( ulQueueUsedCounter[ ulQueueToWriteTo ] )++;
+		( ulQueueUsedCounter[ uxQueueToWriteTo ] )++;
 
 		/* Send to the queue to unblock the task that is waiting for data to
 		arrive on a queue within the queue set to which this queue belongs. */
@@ -719,15 +720,15 @@ uint32_t ulValueToSend = 0;
 }
 /*-----------------------------------------------------------*/
 
-static uint32_t prvRand( void )
+static size_t prvRand( void )
 {
-	ulNextRand = ( ulNextRand * 1103515245UL ) + 12345UL;
-    return ( ulNextRand / 65536UL ) % 32768UL;
+	uxNextRand = ( uxNextRand * ( size_t ) 1103515245 ) + ( size_t ) 12345;
+	return ( uxNextRand / ( size_t ) 65536 ) % ( size_t ) 32768;
 }
 /*-----------------------------------------------------------*/
 
-static void prvSRand( uint32_t ulSeed )
+static void prvSRand( size_t uxSeed )
 {
-    ulNextRand = ulSeed;
+	uxNextRand = uxSeed;
 }
 
diff --git a/FreeRTOS/Demo/Common/Minimal/TaskNotify.c b/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
index 2a65b86c1..83a5fbce0 100644
--- a/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
+++ b/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
@@ -84,7 +84,7 @@
 #include "TaskNotify.h"
 
 #define notifyTASK_PRIORITY		( tskIDLE_PRIORITY )
-
+#define notifyUINT32_MAX	( ( uint32_t ) 0xffffffff )
 /*-----------------------------------------------------------*/
 
 /*
@@ -128,7 +128,7 @@ static uint32_t ulTimerNotificationsReceived = 0UL, ulTimerNotificationsSent = 0
 static TimerHandle_t xTimer = NULL;
 
 /* Used by the pseudo random number generating function. */
-static uint32_t ulNextRand = 0;
+static size_t uxNextRand = 0;
 
 /*-----------------------------------------------------------*/
 
@@ -139,7 +139,7 @@ void vStartTaskNotifyTask( void  )
 	xTaskCreate( prvNotifiedTask, "Notified", configMINIMAL_STACK_SIZE, NULL, notifyTASK_PRIORITY, &xTaskToNotify );
 
 	/* Pseudo seed the random number generator. */
-	ulNextRand = ( uint32_t ) prvRand;
+	uxNextRand = ( size_t ) prvRand;
 }
 /*-----------------------------------------------------------*/
 
@@ -155,7 +155,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 	/* -------------------------------------------------------------------------
 	Check blocking when there are no notifications. */
 	xTimeOnEntering = xTaskGetTickCount();
-	xReturned = xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, xTicksToWait );
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
 
 	/* Should have blocked for the entire block time. */
 	if( ( xTaskGetTickCount() - xTimeOnEntering ) < xTicksToWait )
@@ -183,7 +183,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 
 	/* The task should now have a notification pending, and so not time out. */
 	xTimeOnEntering = xTaskGetTickCount();
-	xReturned = xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, xTicksToWait );
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
 
 	if( ( xTaskGetTickCount() - xTimeOnEntering ) >= xTicksToWait )
 	{
@@ -215,7 +215,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 
 	/* Waiting for the notification should now return immediately so a block
 	time of zero is used. */
-	xReturned = xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, 0 );
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
 
 	configASSERT( xReturned == pdPASS );
 	configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
@@ -233,7 +233,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 	configASSERT( xReturned == pdPASS );
 	xReturned = xTaskNotify( xTaskToNotify, ulSecondNotifiedValueConst, eSetValueWithOverwrite );
 	configASSERT( xReturned == pdPASS );
-	xReturned = xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, 0 );
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
 	configASSERT( xReturned == pdPASS );
 	configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
 
@@ -246,7 +246,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 	remain at ulSecondNotifiedConst. */
 	xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eNoAction );
 	configASSERT( xReturned == pdPASS );
-	xReturned = xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, 0 );
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
 	configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
 
 
@@ -262,7 +262,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 		configASSERT( xReturned == pdPASS );
 	}
 
-	xReturned = xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, 0 );
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
 	configASSERT( xReturned == pdPASS );
 	configASSERT( ulNotifiedValue == ( ulSecondNotifiedValueConst + ulMaxLoops ) );
 
@@ -282,7 +282,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 	ulLoop = 0;
 
 	/* Start with all bits clear. */
-	xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, 0 );
+	xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
 
 	do
 	{
@@ -300,7 +300,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 		/* Use the next bit on the next iteration around this loop. */
 		ulNotifyingValue <<= 1UL;
 
-	} while ( ulNotifiedValue != ULONG_MAX );
+	} while ( ulNotifiedValue != notifyUINT32_MAX );
 
 	/* As a 32-bit value was used the loop should have executed 32 times before
 	all the bits were set. */
@@ -320,15 +320,15 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 	configASSERT( xReturned == pdFAIL );
 
 	/* Notify the task with no action so as not to update the bits even though
-	ULONG_MAX is used as the notification value. */
-	xTaskNotify( xTaskToNotify, ULONG_MAX, eNoAction );
+	notifyUINT32_MAX is used as the notification value. */
+	xTaskNotify( xTaskToNotify, notifyUINT32_MAX, eNoAction );
 
 	/* Reading back the value should should find bit 0 is clear, as this was
 	cleared on entry, but bit 1 is not clear as it will not have been cleared on
 	exit as no notification was received. */
 	xReturned = xTaskNotifyWait( 0x00UL, 0x00UL, &ulNotifiedValue, 0 );
 	configASSERT( xReturned == pdPASS );
-	configASSERT( ulNotifiedValue == ( ULONG_MAX & ~ulBit0 ) );
+	configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
 
 
 
@@ -343,25 +343,25 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 	/* However as the bit is cleared on exit, after the returned notification
 	value is set, the returned notification value should not have the bit
 	cleared... */
-	configASSERT( ulNotifiedValue == ( ULONG_MAX & ~ulBit0 ) );
+	configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
 
 	/* ...but reading the value back again should find that the bit was indeed
 	cleared internally.  The returned value should be pdFAIL however as nothing
 	has notified the task in the mean time. */
 	xReturned = xTaskNotifyWait( 0x00, 0x00, &ulNotifiedValue, 0 );
 	configASSERT( xReturned == pdFAIL );
-	configASSERT( ulNotifiedValue == ( ULONG_MAX & ~( ulBit0 | ulBit1 ) ) );
+	configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
 
 
 
 
 	/*--------------------------------------------------------------------------
-	Now try querying the previous value while notifying a task. */
+	Now try querying the previus value while notifying a task. */
 	xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
-	configASSERT( ulNotifiedValue == ( ULONG_MAX & ~( ulBit0 | ulBit1 ) ) );
+	configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
 
 	/* Clear all bits. */
-	xTaskNotifyWait( 0x00, ULONG_MAX, &ulNotifiedValue, 0 );
+	xTaskNotifyWait( 0x00, notifyUINT32_MAX, &ulNotifiedValue, 0 );
 	xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
 	configASSERT( ulPreviousValue == 0 );
 
@@ -380,7 +380,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 
 	/* -------------------------------------------------------------------------
 	Clear the previous notifications. */
-	xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, 0 );
+	xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
 
 	/* The task should not have any notifications pending, so an attempt to clear
 	the notification state should fail. */
@@ -402,7 +402,7 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 	ulNotifyCycleCount++;
 
 	/* Leave all bits cleared. */
-	xTaskNotifyWait( ULONG_MAX, 0, NULL, 0 );
+	xTaskNotifyWait( notifyUINT32_MAX, 0, NULL, 0 );
 }
 /*-----------------------------------------------------------*/
 
@@ -594,10 +594,10 @@ const uint32_t ulMaxSendReceiveDeviation = 5UL;
 
 static UBaseType_t prvRand( void )
 {
-const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL;
+const size_t uxMultiplier = ( size_t ) 0x015a4e35, uxIncrement = ( size_t ) 1;
 
 	/* Utility function to generate a pseudo random number. */
-	ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;
-	return( ( ulNextRand >> 16UL ) & 0x7fffUL );
+	uxNextRand = ( uxMultiplier * uxNextRand ) + uxIncrement;
+	return( ( uxNextRand >> 16 ) & ( ( size_t ) 0x7fff ) );
 }
 /*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/Common/Minimal/TimerDemo.c b/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
index f40b90618..d79f1c354 100644
--- a/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
+++ b/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
@@ -1044,12 +1044,12 @@ static TickType_t uxTick = ( TickType_t ) -1;
 
 static void prvAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer )
 {
-uint32_t ulTimerID;
+size_t uxTimerID;
 
-	ulTimerID = ( uint32_t ) pvTimerGetTimerID( pxExpiredTimer );
-	if( ulTimerID <= ( configTIMER_QUEUE_LENGTH + 1 ) )
+	uxTimerID = ( size_t ) pvTimerGetTimerID( pxExpiredTimer );
+	if( uxTimerID <= ( configTIMER_QUEUE_LENGTH + 1 ) )
 	{
-		( ucAutoReloadTimerCounters[ ulTimerID ] )++;
+		( ucAutoReloadTimerCounters[ uxTimerID ] )++;
 	}
 	else
 	{
@@ -1065,19 +1065,19 @@ static void prvOneShotTimerCallback( TimerHandle_t pxExpiredTimer )
 /* A count is kept of the number of times this callback function is executed.
 The count is stored as the timer's ID.  This is only done to test the
 vTimerSetTimerID() function. */
-static uint32_t ulCallCount = 0;
-uint32_t ulLastCallCount;
+static size_t uxCallCount = 0;
+size_t uxLastCallCount;
 
 	/* Obtain the timer's ID, which should be a count of the number of times
 	this callback function has been executed. */
-	ulLastCallCount = ( uint32_t ) pvTimerGetTimerID( pxExpiredTimer );
-	configASSERT( ulLastCallCount == ulCallCount );
+	uxLastCallCount = ( size_t ) pvTimerGetTimerID( pxExpiredTimer );
+	configASSERT( uxLastCallCount == uxCallCount );
 
 	/* Increment the call count, then save it back as the timer's ID.  This is
 	only done to test the vTimerSetTimerID() API function. */
-	ulLastCallCount++;
-	vTimerSetTimerID( pxExpiredTimer, ( void * ) ulLastCallCount );
-	ulCallCount++;	
+	uxLastCallCount++;
+	vTimerSetTimerID( pxExpiredTimer, ( void * ) uxLastCallCount );
+	uxCallCount++;
 
 	ucOneShotTimerCounter++;
 }
diff --git a/FreeRTOS/Demo/Common/Minimal/dynamic.c b/FreeRTOS/Demo/Common/Minimal/dynamic.c
index 1b705be36..8b80ca93d 100644
--- a/FreeRTOS/Demo/Common/Minimal/dynamic.c
+++ b/FreeRTOS/Demo/Common/Minimal/dynamic.c
@@ -148,7 +148,7 @@ static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters );
 
 /* Demo task specific constants. */
 #define priSTACK_SIZE				( configMINIMAL_STACK_SIZE )
-#define priSLEEP_TIME				( ( TickType_t ) 128 / portTICK_PERIOD_MS )
+#define priSLEEP_TIME				pdMS_TO_TICKS( 128 )
 #define priLOOPS					( 5 )
 #define priMAX_COUNT				( ( uint32_t ) 0xff )
 #define priNO_BLOCK					( ( TickType_t ) 0 )
diff --git a/FreeRTOS/Source/include/list.h b/FreeRTOS/Source/include/list.h
index 75d391d4c..2a6a74811 100644
--- a/FreeRTOS/Source/include/list.h
+++ b/FreeRTOS/Source/include/list.h
@@ -414,12 +414,12 @@ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIV
  * such that it will be the last item within the list returned by multiple
  * calls to listGET_OWNER_OF_NEXT_ENTRY.
  *
- * The list member pvIndex is used to walk through a list.  Calling
- * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
  * Placing an item in a list using vListInsertEnd effectively places the item
- * in the list position pointed to by pvIndex.  This means that every other
+ * in the list position pointed to by pxIndex.  This means that every other
  * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
- * the pvIndex parameter again points to the item being inserted.
+ * the pxIndex parameter again points to the item being inserted.
  *
  * @param pxList The list into which the item is to be inserted.
  *
-- 
2.39.2